LT8336

LT8342 AD | Alldatasheet

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Technical content

analog.com Rev. 0 2 of 36 TABLE OF CONTENTS

analog.com Rev. 0 3 of 36

REVISION HISTORY

0 6/24 Initial release —

Table 1. Electrical Characteristics

analog.com Rev. 0 5 of 36 (Specifications are for TJ = 25°C, VIN = SNS = EN/UVLO = 5V unless otherwise noted1.) PARAMETER CONDITIONS COMMENTS MIN TYP MAX UNITS Error Amplifier Transconductance (gmEA) 160 µS Error Amplifier Voltage Gain

600 V/V

(gmp) 14.7 S Error Amplifier Source/Sink Current 36 µA Soft-Start Pin Current SS = 0.5V −40°C ≤ TJ ≤ 150°C 9.1 10 10.5 µA VOUT Accuracy with Internal Feedback OSCILLATOR AND SPREAD SPECTRUM FREQUENCY MODULATION (SSFM) Switching Frequency Range −40°C ≤ TJ ≤ 150°C 0.3 3.0 MHz Switching Frequency (fOSC) RT = 110kΩ −40°C ≤ TJ ≤ 150°C 270 300 330 kHz RT = 31.6kΩ −40°C ≤ TJ ≤ 150°C 0.95 1 1.05 MHz RT = 15kΩ −40°C ≤ TJ ≤ 150°C 1.9 2 2.1 MHz SSFM Mode Frequency Deviation Δf/fOSC × 100% RT = 15kΩ 13 20 % SYNC/MODE SYNC Logic Level SYNC Logic High −40°C ≤ T J ≤ 150°C 1.7 V SYNC Logic Low −40°C ≤ T J ≤ 150°C 0.4 V fSYNC/fOSC allowed ratio 0.9 1 1.25 INTERNAL NMOS POWER SWITCHES Bottom Switch On-Resistance ISW = 2A 25 mΩ Bottom Switch Peak Current Limit −40°C ≤ TJ ≤ 150°C 9 10.3 11 A Bottom Switch Minimum Off-Time −40°C ≤ TJ ≤ 150°C 20 35 50 ns

analog.com Rev. 0 6 of 36 (Specifications are for TJ = 25°C, VIN = SNS = EN/UVLO = 5V unless otherwise noted1.) PARAMETER CONDITIONS COMMENTS MIN TYP MAX UNITS Bottom Switch Minimum On-Time VIN = 9.5V, VOUT = 10V 60 ns Top Switch On-Resistance BST – SW = 4V, ISW = 2A 30 mΩ OUTPUT POWER GOOD AND OVERVOLTAGE LOCKOUT Power Not Good High (Outside this Window)2 FB Rising −40°C ≤ TJ ≤ 150°C 7 11 15 % Hysteresis 3 % Power Not Good Low (Outside this Window) FB Falling −40°C ≤ TJ ≤ 150°C -13 -9 -5 % Hysteresis 3 % PG Leakage Current PG = 20V 1 µA PG Pull-Down Voltage 1mA current (into the pin) 200 400 600 mV VOUT Over-Voltage Lockout (Rising) Normalized to target or 36V −40°C ≤ TJ ≤ 150°C 107 111 115 % INPUT DISCONNECT GATE Drive Voltage (GATE − VIN) VIN = 3V, 1µA out of GATE pin −40°C ≤ TJ ≤ 150°C 3.2 5 7 V VIN ≥ 5V, 1µA out of GATE pin −40°C ≤ TJ ≤ 150°C 4.5 6.5 8.5 V GATE to VIN Clamp Voltage GATE−VIN, 5mA into GATE pin 13 15 17 V GATE Turn-On Pull-Up Current GATE = 0V 5 9 13 µA Over-Current Trip Voltage (ΔVSNS) ΔVSNS = VIN − SNS −40°C ≤ TJ ≤ 150°C 37.5 45 52.5 mV Over-Current Event to GATE Turn-Off Propagation Delay 450 ns GATE Turn-Off Pull-Down Current GATE = 5V During Over-Current Condition 80 135 190 mA During Time-Out Period 20 mA GATE Retry Hiccup Time 40 ms

package thermal impedance, and other environmental factors. 2 If PreBoost is connected to INTVCC, PG only pulls down if outside the lower window. Table 2. Absolute Maximum Ratings impedance, and other environmental factors.

3 LT8342R includes over-temperature protection that is intended to protect the device during momentary

temperature may impair device reliability. extended periods may affect product reliability.

Thermal performance is directly linked to the Printed circuit board (PCB) design and the operating environment. Close attention to PCB thermal design is required. Table 3. Thermal Resistance The following ESD information is provided for handling of ESD-sensitive devices in an ESD protected area only. Table 4. LT8342, 24-Lead (4mm × 4mm) LQFN

Figure 3. Pin Configuration Table 5. Pin Descriptions

1 GATE

Gate Driver Pin for External N-channel input-disconnect Field-effect transistor (FET). used, connect the GATE Pin to ground. 2 NC No internal connection. ceramic capacitor between (and in close proximity to) BST and SW pins. metal trace area connected to this pin. Silent Switcher performance.

11 VOUT

divider connected to VSET2/FB Pin (regulated to 1V).

13 VSET2/FB

the desired VOUT voltage. The LT8342 regulates the VSET2/FB pin to 1V (typical). Table 6. Target VOUT Configurations

14 VSET1

Table 6. If external feedback is used, connect this pin to INTVCC through a 100kΩ

15 PREBOOST

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16 SYNC/MODE

This pin allows five selectable modes for optimization of performance. SYNC / MODE Pin Input Capable Mode(s) of Operation GND or < 0.1V Burst External Clock Pulse-skip/Sync 100k Resistor to GND Burst/SSFM Float (pin open) Pulse-skip INTVCC Pulse-skip/SSFM Where the selectable modes of operation are: Burst = Low IQ, low output ripple operation at light loads. Pulse-skip = Skipped pulse(s) at light load (aligned to the clock). Sync = Switching frequency synchronized to an external clock. SSFM = Spread Spectrum Frequency Modulation for low EMI. 17 RT Timing Resistor Pin. Connect a resistor from this pin to GND to set the LT8342’s switching frequency internally. Do not float this pin. When clocking the IC externally with the SYNC pin, the external clock frequency can be no lower than 90% of the switching frequency programmed by the RT pin resistor. 18 VC Error Amplifier Compensation Pin. Place the external RC compensation network from the VC pin to GND to stabilize the voltage loop. 19 SS Soft-Start Pin. Place a soft-start capacitor CSS between this pin and GND to program the output soft-start time.

20 INTVCC

Internal 3.6V Regulator Bypass Pin. Connect a 2.2µF (or larger), low ESR, ceramic bypass capacitor from this pin to GND, placing the capacitor in close proximity to the pin. Do not drive this pin directly, nor load it with any other external circuitry. This pin powers the IC's internal switch drivers. INTVCC must exceed 2.75V to commence switching. 21 PG Output Power Good Indicator Pin. The PG Pin is the open-drain output of an internal comparator. The PG pin is pulled low by the LT8342 when VOUT is outside a ±10% window of its target voltage. An external pull-up resistor or current source pulls the PG pin high when the VOUT enters a ±7% window around its target voltage. For a PreBoost application, the PREBOOST Pin can be connected to INTVCC, so that the PG pin stays high at PassThru, and does not draw current.

22 EN/UVLO

Enable/Input Undervoltage Lockout Pin. The LT8342 is shut down when the EN/UVLO pin is driven below a 1.02V accurate threshold. The LT8342 is enabled when the EN/UVLO pin is driven above 1.08V. The EN/UVLO pin can be connected to a resistor divider network from VIN to GND to set a VIN undervoltage lockout threshold below which the IC is disabled/shut down. See the Applications Information section for further details. Connect the pin directly to VIN if the shutdown feature is not used.

23 VIN

Input Supply Pin. Connect a 2.2µF (or larger) low ESR ceramic bypass capacitor from this pin to GND, placing the capacitor near the pin. The VIN pin is also the positive input of the current sensing comparator for the input-disconnect FET.

24 SNS

this pin to VIN or float this pin if the input-disconnect FET is not used. Figure 4. Burst Mode Efficiency and Power Loss vs Figure 5. Pulse-Skip Mode Efficiency and Power Loss vs Figure 6. Burst Mode Efficiency vs Inductor Value. Figure 7. Efficiency vs Output Current at Different Switching Frequencies. See Figure 1.

Figure 41. Block Diagram

analog.com Rev. 0 20 of 36 THEORY OF OPERATION The LT8342 is a monolithic, synchronous step-up DC/DC converter that uses fixed frequency and peak current mode control to provide excellent line and load regulation. It contains a Silent Switcher architecture that enables a significant reduction in EMI and can be configured to control an optional external input-disconnect N-channel FET (MEXT) for output short-circuit protection and reduction of inrush current. See the Block Diagram for the following explanation of the LT8342’s operation. An optional resistor divider from the converter input to the EN/UVLO pin, with a 1.08V rising threshold and an accurate 1.02V falling threshold, allows the user to program turn on/off levels for the converter input. Alternatively, the EN/UVLO pin can be connected to the converter input or driven from an external logic-level signal. EN/UVLO pin voltage below 0.15V shuts down all internal circuitry and draws less than 1μA from the VIN pin. With the EN/UVLO pin voltage high enough and the VIN pin voltage at least 2.8V, the internal circuitry is activated. The LT8342 will check whether internal feedback (FBINT) or external feedback (VSET2/FB pin) will be used as the feedback node (FB0). If internal feedback is used, FB_SEL will automatically determine the correct internal feedback ratio accordingly. 10μA from the SS pin will gradually charge up the external soft-start capacitor (CSS), which slowly ramps up the regulation reference voltage. An oscillator (A1), with frequency set using a resistor from the RT pin to GND, turns on the internal bottom power switch (M1) at the beginning of each clock cycle. Current in the inductor then increases until the bottom switch current comparator (A2) trips and turns off the bottom power switch. The peak inductor current at which the bottom switch turns off is controlled by the voltage on the VC pin. The error amplifier (A3) servos the VC pin by comparing the voltage on the feedback node (FB0) with the internal 1V reference. The error amplifier drives the VC pin voltage to set the correct peak switch current level that keeps the output voltage in regulation. When the load current increases, it causes a reduction in the feedback node (FB0) voltage relative to the internal 1V reference. This causes the error amplifier to raise the VC pin voltage, to increase the peak inductor current until enough power is delivered to the output to maintain the output voltage in regulation. When the bottom power switch (M1) turns off, the synchronous power switch (M2) turns on until the next clock cycle begins or the inductor current falls to zero. For applications requiring a PreBoost regulator to maintain output voltage, for example, during the automotive cold crank or start-stop, the VIN and VOUT pins are constantly monitored to determine when VIN exceeds VOUT. If VIN exceeds VOUT and VOUT is above its programmed regulation voltage, the LT8342 enters PassThru Mode and turns on the top side synchronous switch to maximize efficiency. Optional output short-circuit protection, and inrush current reduction are available by adding an external sense resistor (RSNS) and an N-channel FET (MEXT) in series with the converter input. If MEXT is not used, connect the GATE pin to GND. The LT8342 can automatically detect whether MEXT is configured. At startup, an internal 9μA current source charges up the GATE pin (connected to the gate of MEXT) to 6.5V above VIN. During an output short circuit, when the converter input current rises high enough in the sense resistor RSNS to trip the 45mV threshold of comparator A4, the LT8342 pulls the GATE Pin to GND, turning off MEXT and limits the maximum short circuit inductor current. After MEXT is turned off, the LT8342 waits 40ms before charging up the GATE pin to turn on MEXT again. The LT8342's SYNC/MODE pin allows synchronization to an external clock. It can also be used to select between burst or pulse-skipping modes of operation to optimize the converter performance based on the application requirements. SSFM can be activated with either of the two modes to reduce the EMI further.

analog.com Rev. 0 21 of 36 The LT8342's protection features include output over-voltage and short-circuit protection, thermal shutdown, and under-voltage lockout. The IC also prevents inductor current runaway in conditions requiring extremely low converter duty cycles by adjusting switching frequency to maintain volt-second balance of the inductor. APPLICATIONS INFORMATION Programming VIN Turn-On and Turn-Off Thresholds with the EN/UVLO Pin System VIN turn-on/-off thresholds can be programmed by driving the EN/UVLO pin with a resistor divider connected from VIN to GND (See Block Diagram). The threshold voltages are determined by equations (1) and (2). 𝑉(𝐹𝐴𝐿𝐿𝐼𝑁𝐺,𝑇𝑈𝑅𝑁 𝑂𝐹𝐹) = 1.02𝑉 × 𝑅1 + 𝑅2 (1) 𝑉(𝑅𝐼𝑆𝐼𝑁𝐺,𝑇𝑈𝑅𝑁 𝑂𝑁) = 1.082𝑉 × 𝑅1 + 𝑅2 (2) When in Burst Mode operation with light load currents, the current through the resistor network R1 and R2 can easily be greater than the supply current consumed by the LT8342. Therefore, R1 and R2 should be large to minimize their effect on efficiency at low loads. The EN/UVLO pin can be connected to VIN if the shutdown feature is not used, or alternatively, the pin may be tied to a logic level if shutdown control is required. The IC draws a low VIN quiescent current of 0.35μA (typical) when EN/UVLO is below 0.15V. INTVCC Regulator An internal low dropout (LDO) regulator produces the 3.6V supply from VIN that powers the gate drivers and the internal bias circuitry. The INTVCC pin must be bypassed to GND with a minimum of 2.2μF ceramic capacitor. Good bypassing is necessary to supply the high transient currents required by the power MOSFET gate drivers. Applications with high input voltage and high switching frequency will increase die temperature because of the higher power dissipation across the LDO. Do not connect any external load to the INTVCC pin. Programming the Output Voltage LT8342 features an adjustable internal feedback divider which programs the regulated output voltage level. Configuring VSET1 and VSET2/FB pins as shown in Table 6 to select the preset level. The >10MΩ (typical) resistor divider guarantees that the quiescent current from the VOUT pin is much reduced compared with a conventional external potential divider. In some applications where external feedback is still desired, one can tie the VSET1 pin to INTVCC through a 100kΩ resistor, which programs the VSET2/FB pin as the conventional feedback pin. In this case, the output voltage is programmed with a resistor divider between the output and the VSET2/FB pin, as shown in Figure 1. Choose the resistor values according to the equation (3). 𝑅𝐹𝐵1 = 𝑅𝐹𝐵2 × (𝑉𝑂𝑈𝑇 1𝑉 − 1) (3) The resistance in equation (3) refer to reference designators in Figure 42. The 1% resistors are recommended to maintain output voltage accuracy. When using large feedback resistors, a 4.7pF to 22pF phase-lead capacitor may be required from VOUT to VSET2/FB. Note that when external feedback is used, if the fault occurs where VSET2/FB is short to ground, instead of producing an excessively high output voltage, as shown in Table 6, LT8342 will automatically switch to internal feedback with 19V output regulation.

Figure 42. Simplified LT8342 External Feedback Configuration mode increases, resulting in much higher light load efficiency than for typical converters. shown in Figure 41, the Block Diagram. Table 7 shows the value of RT for a given switching frequency. resistor should be chosen to program a switching frequency as close as possible to the SYNC pulse frequency.

Table 7. Switching Frequency (fsw) vs RT Value Oscillator Frequency with Spread Spectrum Modulation in the Typical Performance Characteristics section). power switch M1 is kept off continuously. The voltage across the boost capacitor (CBST) is constantly monitored. 3.2V and then turned off, maintaining enough gate drive voltage on M2.

analog.com Rev. 0 24 of 36 can connect the PREBOOST pin to INTVCC, so that PG no longer pulls low in PassThru operation when output voltage is above regulation. When the input voltage drops sharply (such as during stop-start or cold crank) to a level below the voltage stored on the output capacitor of the boost converter, reverse inductor current exceeding −1.8A (typical) will cause M2 to turn off. The output capacitor will naturally discharge due to load current. The LT8342 PassThru mode is maintained as long as VOUT remains above its programmed regulation level, regardless of the level of VIN. The LT8342 can only exit PassThru mode when VOUT drops below its programmed regulation level, which turns on M1 and turns off M2. The LT8342 will then quickly respond as a boost converter to maintain VOUT at its programmed level. To ensure the PassThru mode operation works properly, the LT8342’s VIN pin must be connected to the input of the boost converter. Switching Frequency Foldback when VIN Approaches VOUT In some boost applications, the input voltage may rise to a voltage very close to VOUT. In this condition, the switching regulator must operate at a very low duty cycle to keep output voltage in regulation. However, the minimum on-time limitation of the power switch may prevent the switcher from attaining a sufficiently low duty cycle at the programmed switching frequency. As a result, a typical boost converter may experience a large output ripple under these conditions. The LT8342 addresses this issue by adopting a switching frequency foldback function to decrease the switching frequency when its minimum on-time starts to limit the switcher from attaining a sufficiently low duty cycle. Output Short-Circuit Protection Optional output short-circuit protection is available by adding an external sense resistor (RSNS), and a N-channel FET (MEXT) in series with the converter input. A low-leakage p-n clamp diode (D3) is also required between the source and gate of MEXT (See Block Diagram). At startup, an internal 9μA current source charges up the GATE Pin (connected to the gate of MEXT) to 6.5V above VIN. During an output short circuit, when the converter input current rises high enough in the sense resistor RSNS to trip the 45mV threshold of the comparator A4, the LT8342 pulls the GATE pin to GND, immediately limiting the maximum short-circuit inductor current and eventually turns off MEXT. When the inductor current decreases below zero, the parasitic capacitances on the SW node will cause ringing, possibly creating a big negative gate-to-source voltage (VGS) that could damage the MEXT. The diode D3 protects MEXT by clamping the negative VGS of MEXT. After MEXT is turned off, the LT8342 waits 40ms before charging up the GATE pin to turn on MEXT again. The typical waveforms during output short circuits are shown in Figure 37 and Figure 38 in the Typical Performance Characteristics section. When selecting MEXT, the following factors should be taken into consideration:  The drain-to-source voltage and current ratings should be sufficient for the intended application. Typically, a 40V VDS_MAX and an IDS_MAX higher than the over-current limit (45mV/RSNS) are safe.  The gate-to-source voltage should be rated to 15V or above. Since the internal charge pump operates to drive the GATE pin 6.5V above VIN, VGS_MAX should be at least +15V. The negative maximum rating can be more relaxed because of the clamp diode from source to gate.  A gate threshold voltage (VGS_TH) of less than 1.8V is recommended.  The gate-to-drain charge (QGD) should be large enough to reduce in-rush current. During the start-up of MEXT, and when VGS just exceeds VGS_TH, all the 9μA charging current flows into the gate-to-drain capacitance

analog.com Rev. 0 25 of 36 (CRSS) while VGS remains roughly the same. The source voltage VS, which also acts as the input of the inductor, will ramp up quickly to the drain voltage VIN. Since VOUT is initially at ground, an in-rush current will occur and must be kept below the output short current programmed by RSNS. Note that a larger QGD might be needed as COUT or VIN increases.  Low on-resistance (RDSON) for optimum efficiency; For most applications, MEXT does not have a Safe Operating Area (SOA) violation problem as long as its IDS_MAX is well above the short-circuit current limit. This is because the LT8342 does not regulate MEXT's current and only turns it off once the limit is reached. In addition, the strong pull-down strength on the GATE pin ensures that excess current only lasts for a very short period, thus limiting the amount of stress on MEXT. The 40ms time-out period before retrying ensures heat is well dissipated. Start-Up To limit the peak switch current and VOUT overshoot during start-up, the LT8342 uses an SS pin to provide soft-start operation (see the error amplifier A3 in Block Diagram). During soft-start, a 10µA (typical) current source gradually charges the external soft-start capacitor CSS. When the SS pin voltage falls between the FB initial voltage and 1V, the IC regulates the FB pin voltage to the SS pin voltage instead of 1V. This way, the output capacitor is charged gradually toward its final value while limiting the start-up peak switch currents. The IC selects pulse-skipping mode with no spread spectrum frequency modulation during start-up, and the SYNC/MODE pin configuration is ignored. The IC reads the SYNC/MODE pin configuration after the SS pin voltage exceeds 1.2V (typical). When the external disconnect FET (MEXT) is used, at power up and EN/UVLO high, the hiccup timer will count 40ms (typical) before turning on MEXT and starting SS pin operation. In case the system is stuck in an under-voltage reset loop when a certain fault happens, this mechanism guarantees sufficient hiccup time between retries to protect MEXT from overheating, even when the IC keeps being reset. If MEXT is not used (GATE ties to ground), no hiccup delay is inserted between enable and start-up. See Figure 20 and Figure 21 in the Typical Performance Characteristics section for comparing start-up operations under different configurations. Loop Compensation Loop compensation determines stability and transient performance. The LT8342 uses peak current mode control to regulate the output, simplifying loop compensation. To compensate for the feedback loop of the LT8342, a series resistor-capacitor network is usually connected from the VC pin to GND. The Block Diagram shows the typical VC compensation network. For most applications, the capacitor should be in the range of 100pF to 10nF, and the resistor should be in the range of 5kΩ to 200kΩ. A small capacitor is often connected in parallel with the RC compensation network to attenuate the VC voltage ripple, which is induced from the output voltage ripple passing all the way through the feedback resistor network and the internal error amplifier. The parallel capacitor usually ranges in value from 2.2pF to 22pF. A practical approach to design the compensation network is to start with one of the circuits in this data sheet, which is close to your application, and tune the compensation network to optimize the performance. Stability should then be checked across all operating conditions, including load current, input voltage, and temperature. Refer to the Application Note 76 for more details. Thermal Considerations Care should be taken in the layout of the PCB to ensure good thermal management of the LT8342. The power ground plane should consist of large copper layers with thermal vias; these layers spread heat dissipated by the LT8342. Placing additional vias can further reduce thermal resistance. The maximum load current should be de-

analog.com Rev. 0 26 of 36 rated as the ambient temperature approaches the maximum junction temperature rating. Power dissipation within the LT8342 (PDISS) can be estimated by subtracting the power losses of the inductor and the sense resistor plus NMOS (if used) from the total power losses calculated in an efficiency measurement. The junction temperature of the LT8342 can then be estimated by equation (4). 𝑇𝐽𝑈𝑁𝐶𝑇𝐼𝑂𝑁 = 𝑇𝐴𝑀𝐵𝐼𝐸𝑁𝑇 + 𝜃𝐽𝐴 × 𝑃𝐷𝐼𝑆𝑆 (4) Thermal Lockout If the LT8342 die temperature reaches 177°C (typical), the part will stop switching and enter thermal lockout. When the die temperature drops below 170°C (typical), the part will resume switching with a soft-started inductor peak current. Inductor Selection When operating in continuous conduction mode (CCM), the duty cycle can be calculated based on the output voltage (VOUT) and the input voltage (VIN). The maximum duty cycle (DMAX) occurs when the converter has the minimum input voltage given by equation (5). 𝐷𝑀𝐴𝑋 = 𝑉𝑂𝑈𝑇 − 𝑉𝐼𝑁,𝑀𝐼𝑁 𝑉𝑂𝑈𝑇 (5) Discontinuous conduction mode (DCM) provides higher conversion ratios at a given frequency at the cost of reduced efficiencies and higher switching currents. The inductor ripple current ∆IL directly affects the choice of the inductor value, the converter’s maximum output current capability, and the light load efficiency in the Burst Mode operation. Choosing smaller values of ∆IL increases output current capability and light load efficiency in Burst Mode operation, but it requires a large inductance value and reduces the current loop gain. Accepting larger values of ∆IL provides a fast transient response and allows the use of low inductance values but results in higher input current ripple, greater core losses, lower light load efficiency in Burst Mode operation, and lower output current capability. Large values of ∆IL at high- duty cycle operation may result in sub-harmonic oscillation. Given an operating input voltage range and having chosen the operating frequency and ripple current in the inductor, the inductor value of the boost converter can be determined by equation (6). 𝐿 = 𝑉𝐼𝑁,𝑀𝐼𝑁 ∆𝐼𝐿 × 𝑓𝑆𝑊 × 𝐷𝑀𝐴𝑋 (6) The LT8342 limits the peak switching current to protect the switches and the system from overload faults. The bottom switch current limit is controlled to 10.3A (typical) regardless of the duty cycle. The peak inductor current is equal to the LT8342 bottom switch current limit. The user should choose an inductor with sufficient saturation and RMS current ratings to handle the inductor’s peak current. Input Capacitor Selection The input ripple current in a boost converter is relatively low (compared with the output ripple current) because this current is continuous. The voltage rating of the input capacitor, CIN, should comfortably exceed the maximum input voltage. Be sure to characterize the input voltage for any possible overvoltage transients that could apply excess stress to the input capacitors. The value of CIN is a function of the source impedance, and in general, the higher the source impedance, the higher the required input capacitance.

analog.com Rev. 0 27 of 36 The RMS CIN ripple current can be estimated by equation (7). 𝐼𝑅𝑀𝑆,𝐶𝐼𝑁 = 0.3 × ∆𝐼𝐿 (7) Output Capacitor Selection The output capacitor has two essential functions. First, it filters the LT8342’s discontinuous top switch current to produce the DC output. In this role, it determines the output ripple; thus, low impedance at the switching frequency is important. The second function is storing energy to satisfy the transient loads and stabilizing the LT8342’s control loop. The X5R or X7R type ceramic capacitors have very low equivalent series resistance (ESR), which provides low output voltage ripple as well as good transient response. Transient performance can be improved with larger output capacitance and the addition of a feedforward capacitor placed between VOUT and VSET2/FB (if external feedback is used). When a feedforward capacitor is used, or output capacitance is adjusted, a careful evaluation of system stability should be made to ensure adequate design margin. Increasing the output capacitance will also decrease the output voltage ripple. Lower value of output capacitance can be used to save space and cost, but transient performance will suffer, and loop instability may result. In addition to the bulk output capacitors, two small output ceramic capacitors, 0.1µF each, should be placed as close as possible to the IC to complete the Silent Switcher cancellation loops. See the Board Layout section for more details. Note that larger output capacitance is required when a lower switching frequency is used. If there is significant inductance to the load due to long wires or cables, additional bulk capacitance may be necessary, which can be implemented with an electrolytic capacitor. When choosing a capacitor, special attention should be given to the capacitor's datasheet to calculate the effective capacitance under the relevant operating conditions of voltage bias and temperature. A physically larger capacitor, or one with a higher voltage rating, may be required. For good starting values, see the Typical Applications section. Recommended PCB Layout Guidelines The LT8342 is specifically designed to minimize electromagnetic emissions and maximize efficiency when switching at high frequencies. Figure 43 shows a recommended PCB layout. For more details and PCB design files, refer to the demo board guide for the LT8342. For optimal performance, the LT8342 requires the use of multiple output bypass capacitors. It is recommended to connect one 0.1µF capacitor between VOUT at Pin 8 and GND at Pin 7 only, and a matching 0.1µF capacitor between VOUT at Pin 11 and GND at Pin 12 only, to complete the Silent Switcher EMI cancellation loops. These two capacitors must be placed as close as possible to the IC, and the loops formed by these two capacitors should be symmetrical and as small as possible to achieve an optimized EMI cancellation performance. Capacitors with small case sizes, such as 0402 or 0603, are optimal due to the low parasitic inductance. Additional bulk capacitors of 4.7µF or more should be placed close to the IC, with the positive terminals connected to the output, and negative terminals connected to ground plane. The bypass capacitors for VIN and INTVCC pins should also be connected to the ground plane. The output capacitors, along with the inductor and input capacitors, should be placed on the same side of the circuit board, and their connections should be made on that layer. Place a local, unbroken power ground plane under the application circuit on the layer closest to the surface layer. The SW and BST nodes should be as small as possible to minimize EMI. Keep the VSET2/FB (if external feedback is used) and RT nodes small so that the ground traces will shield them from the noise generated by the SW and BST nodes.

many thermal vias to additional power ground planes within the circuit board. Figure 43. Recommended PCB Layout for LT8342

Figure 44. Low IQ, low EMI, 24V Boost Converter with SSFM and Burst Mode.

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PACKAGE INFORMATION

A PACKAGE TOP VIEW PIN 1 CORNER Y X 24b PACKAGE BOTTOM VIEW E D DETAIL B SUBSTR ATE MOLD CA P Z DETAIL C SUGGESTED PCB LAYOUT TOP VIEW 0.0000 0.0000 0.7500 1.2500 0.2500 0.2500 0.7500 1.2500 1.2500 0.7500 0.2500 0.2500 1.2500 0.7500 DETAIL A PACKAGE OUTLINE 0.25 0.375 0.375 0.65 4.50 ±0.50 4.50 ±0.50 LQFN 24 0920 REV Ø TRAY PIN 1 BEVE L PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN 1 LTXXXXXX 24× SYMBO L A L b D E e aaa bbb ccc ddd eee fff MIN 0.85 0.30 0.22 NOM 0.95 0.40 0.25 4.00 4.00 2.70 2.30 0.50

0.25 REF

0.70 REF

1.05 0.03 0.50 0.28 0.10 0.10 0.10 0.10 0.15 0.08 NOTES SUBSTR ATE THK MOLD CA P HT DIMENSIONS Z DETAIL C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. PRIMA RY DATUM -Z- IS SE ATING PLANE METAL FEATURES UNDER THE SOLDER MASK OPENING NOT SHOWN SO AS NOT TO OBSCURE THESE TERMINALS AND HEAT FEATURES DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDIC ATED. THE PIN 1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FE ATURE

6 THE EXPOSED HEAT FEATURE MAY HAVE OPTIONAL CORNER RADII

7 CORNER SUPPORT PAD CHAMFER IS OPTIONA L

e L e/2 SEE NOTES b0.375 e e b DETAIL A SEE NOTES PIN 1 NOTCH 0.283 × 45° 19 24 12 7 0.25 0.45 2.30 2.70 0.25 0.45 2.30 2.70 2× aaa Z 2× aaa Z ddd Z // bbb Z M X YZeee M Zfff M X YZccc M X YZccc

Table 8. Ordering Guide *Temperature grades are identified by a label on the shipping container. **The LT8342 package has the same dimensions as a standard (4mm x 4mm) QFN package.

Table 9. Ordering Guide

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