LT8292

LT8292 Rev. 0

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 50

Technical content

analog.com Rev. 0 2 of 50 TABLE OF CONTENTS

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REVISION HISTORY

0 9/24 Initial release —

Table 1. Electrical Characteristics

analog.com Rev. 0 5 of 50 (Specifications are at TA = 25°C3. VIN = 12V, VEN/UVLO = 1.5V, RT = 147kΩ to GND, CINTVCC = 4.7μF to GND, unless otherwise noted. ) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS ISP Input Bias Current IISP VISP = VISN = 12V 20 µA VISP = VISN = 0V -10 VEN/UVLO = 0V, VISP = VISN = 12V or 0V -0.3 0 0.3 ISP/ISN Input Bias Current Mismatch IISP - IISN VISP = VISN = 12V, -40°C ≤ TJ ≤ 125°C -3 0 3 µA VISP = VISN = 0V, -40°C ≤ TJ ≤ 125°C -10 0 10 ISP/ISN Current Regulation Amplifier gm gM(ISP-ISN) 3600 μS FB Regulation Voltage VFB -40°C ≤ TJ ≤ 125°C 0.98 1.00 1.02 V FB Line Regulation ΔVFB(LINE) 4V < VIN < 60V, VOUT = 12V 0.2 0.5 % FB Voltage Regulation Amplifier gM(FB) 570 µS FB Input Bias Current IFB FB in regulation, Current out of Pin -20 0 20 nA VC Output Impedance RVC 0.9 MΩ Current Comparator Maximum Current Sense Threshold V(LSP-LSN) Buck, VFB = 0.8V -40°C ≤ TJ ≤ 125°C 41 50 59 mV Boost, VFB = 0.8V -40°C ≤ TJ ≤ 125°C 44 50 56 Fault FB Short Threshold VFB Falling 0.22 0.25 0.27 V FB Short Hysteresis VFB Hysteresis 40 50 60 mV PGOOD Upper Threshold Offset from VFB ΔVFB Rising 6 8 10 % PGOOD Lower Threshold Offset from VFB ΔVFB Falling -10 -8 -6 % PGOOD Pull-Down Resistance RPGOOD 100 200 Ω SS Strong Pull-Down Resistance RSS 50 Ω SS Pull-Up Current ISS VFB = 0.8V, VSS = 0V 10.5 13 16 µA SS Pull-Down Current ISS VFB = 1.0V, VSS = 2V 0.8 1.25 1.6 µA Oscillator Switching Frequency fSW RT = 523kΩ 95 100 105 kHz RT = 258kΩ 190 200 210 RT = 147kΩ 330 350 370 SYNC Frequency fSW fSYNC/MODE = fRT 100 650 kHz

analog.com Rev. 0 6 of 50 (Specifications are at TA = 25°C3. VIN = 12V, VEN/UVLO = 1.5V, RT = 147kΩ to GND, CINTVCC = 4.7μF to GND, unless otherwise noted. ) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS SYNC/MODE Threshold Voltage VSYNC/MODE 0.4 2.5 V Highest Spread Spectrum Above Oscillator Frequency 22 25 28 % NMOS Drivers TG1P, TG2P Gate Pull- Up Resistance RTG1, TG2 V(BST—SW) = 5V 2 Ω TG1N, TG2N Gate Pull- Down Resistance RTG1, TG2 V(BST—SW) = 5V 1 Ω BG1P, BG2P Gate Pull- Up Resistance RBG1, BG2 VINTVCC = 5V 2 Ω BG1N, BG2N Gate Pull- Down Resistance RBG1, BG2 VINTVCC = 5V 1 Ω TG Off to BG On Delay tDELAY(TG-BG) RDT1,2 = 0Ω to INTVCC 25 40 55 ns RDT1,2 = 130kΩ to GND 20 RDT1, DT2 = 82kΩ to GND 10 RDT1, DT2 = 51kΩ to GND 2 BG Off to TG On Delay tDELAY(BG-TG) RDT1, DT2 = 0Ω to INTVCC 25 40 55 ns RDT1, DT2 = 130kΩ to GND 20 RDT1, DT2 = 82kΩ to GND 10 RDT1, DT2 = 51kΩ to GND 2

Table 2. Absolute Maximum Ratings 1 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. operating conditions for extended periods may affect product reliability. 2 Do not apply a positive or negative voltage source to these pins, otherwise permanent damage may occur. degrade operating lifetimes. overload conditions. Junction temperature will exceed 150°C when overtemperature protection is active.

Figure 3. Pin Configuration Table 3. Pin Descriptions Channel MOSFET with a voltage swing from ground to INTVCC. N-Channel MOSFET with a voltage swing from ground to INTVCC.

4 BST1

connected to the SW1 pin. The BST1 pin swings from INTVCC to (VIN + INTVCC). MOSFET with a voltage swing from SW1 to BST1. Channel MOSFET with a voltage swing from SW1 to BST1. current sense with Kelvin connection. current sense with Kelvin connection.

1. EXPOSED PAD (PIN 39) IS GND, MUST BE

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11 VIN

Input Supply. The VIN pin must be connected to the power input to determine the buck, boost, or buck-boost operation regions. Locally bypass this pin to ground with a ceramic capacitor.

12 EN/UVLO

Enable and Undervoltage Lockout. Force the pin to the ground to shut down the part and reduce the VIN quiescent current below 0.3μA. Force the pin above 1.239V for normal operation. The accurate 1.18V falling threshold can be used to program an undervoltage lockout (UVLO) threshold with a resistor divider from VIN to the ground.

13 INTVCC

Internal 5V Linear Regulator Output. The INTVCC linear regulator is intelligently powered from either VIN or VOUT pins. The split gate drivers and control circuits are powered from this voltage. Bypass this pin to the ground with a minimum 4.7μF ceramic capacitor.

15 VOUT

Output Supply. The VOUT pin must be tied to the power output to determine the buck, boost, or buck-boost operation regions. Locally bypass this pin to ground with a ceramic capacitor. 16 ISP Positive Terminal of the ISP/ISN Current Sense Resistor (RIS). Ensure accurate current sense with Kelvin connection. 17 ISN Negative Terminal of the ISP/ISN Current Sense Resistor (RIS). Ensure accurate current sense with Kelvin connection.

19 IGND

Local Ground for Leader-less Current Sharing. When paralleling, kelvin all IGND pins to a common ground. See the Paralleling Multiple Regulators in the Applications Information section for more details. When not in use, connect the pin to the ground.

20 ISHARE

Leaderless Current Sharing Input for Paralleling. Together with the IGND pin, this pin allows equal output current sharing among multiple LT8292s in parallel, enabling higher output current, and better heat management. Each LT8292 independently regulates the average output current, eliminating the need for a leader controller. For parallel applications, tie the ISHARE pins of all the LT8292s together. See the Paralleling Multiple Regulators in the Applications Information section for more details. When not in use, leave the pin floating.

21 ICTRL

Control Input for ISP/ISN Current Sense Threshold. The ICTRL pin generates a 10μA current and is used to program the ISP/ISN current limit: 𝐼𝐼𝑆(𝑀𝐴𝑋) = 𝑚𝑖𝑛(𝑉𝐼𝐶𝑇𝑅𝐿 − 0.25𝑉, 1𝑉) 20 ⋅ 𝑅𝐼𝑆 The VICTRL can be set by a voltage drop of an external resistor (RICTRL) from the ICTRL pin to ground: VICTRL= 10μA ⋅ RICTRL For 0.35V ≤ VICTRL ≤ 1.15V, the current sense threshold linearly goes up from 5mV to 45mV. For VICTRL ≥ 1.35V, the current sense threshold is constant at 50mV full-scale value. For 1.15V ≤ VICTRL ≤ 1.35V, the current sense threshold smoothly transitions from the linear function of VICTRL to the 50mV constant value. Connect ICTRL to INTVCC for the 50mV full-scale threshold or when not in use. 22 VC Error Amplifier Output to Set Inductor Current Comparator Threshold. The VC pin is used to compensate the control loop with an external RC network.

analog.com Rev. 0 10 of 50 23 FB Voltage Loop Feedback Input. The FB pin is used for constant-voltage regulation and output fault protection. The internal error amplifier with output VC regulates VFB to 1.0V through the DC/DC converter. During the output short circuit (VFB < 0.25V) condition, the part runs in low-duty cycle auto-retry mode. During an overvoltage (VFB > 1.8V) condition, the part stops switching. 24 SS Soft-Start Timer Setting. The SS pin is used to set the soft-start timer by connecting a capacitor to the ground. An internal 13μA pull-up current charging the external SS capacitor gradually ramps up the FB regulation voltage. A 0.1μF capacitor is recommended on this pin. Any UVLO or thermal shutdown immediately pulls the SS pin to the ground and stops switching.

25 PGOOD

Power Good Open Drain Output. The PGOOD pin is pulled high externally when the FB pin is within ±8% of the final regulation voltage. To function, the pin requires an external pull-up resistor. 26 RDT1 Buck Side Switching Dead Time Setting. Connect a resistor from this pin to the ground to select one of four dead time settings. 27 RDT2 Boost Side Switching Dead Time Setting. Connect a resistor from this pin to the ground to select one of four dead time settings. 28 RT Switching Frequency Setting. Connect a resistor from this pin to the ground to set the internal oscillator frequency from 100kHz to 650kHz.

29 SYNC/MODE

External Frequency Synchronization and Operation Mode Selection. This pin allows the following selectable modes for optimization of performance:  External clock: For external frequency synchronization and forced continuous mode at light load.  INTVCC: For spread spectrum around internal oscillator frequency and forced continuous mode at light load.  Float: For internal oscillator frequency and forced continuous mode at light load.  100kΩ to GND: For internal oscillator frequency and pulse skipping mode at light load.  GND: For internal oscillator frequency and low ripple burst mode at light load.

30 CLKOUT

Digital Clock Output. Use this pin to synchronize one or more LT8292 ICs in parallel. The CLKOUT pin provides 180° out-of-phase and 50% duty cycle clock signal at the switching frequency set by the internal oscillator or the external frequency synchronization using the SYNC/MODE pin. 32 SW2 Boost Side Switch Node. The SW2 pin swings from a Schottky diode voltage drop below ground to VOUT. 33 TG2N Boost Side Top Gate Driver Pull-Down Output. Drives the gate of buck side top N- Channel MOSFET with a voltage swing from SW2 to BST2. 34 TG2P Boost Side Top Gate Driver Pull-Up Output. Drives the gate of buck side top N-Channel MOSFET with a voltage swing from SW2 to BST2.

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35 BST2

Buck Side Bootstrap Floating Driver Supply. The BST2 pin has an integrated bootstrap Schottky diode from the INTVCC pin and requires an external bootstrap capacitor to be connected to the SW1 pin. The BST2 pin swings from INTVCC to (VIN + INTVCC). 37 BG2N Boost Side Bottom Gate Driver Pull-Down Output. Drives the gate of buck side bottom N-Channel MOSFET with a voltage swing from ground to INTVCC. 38 BG2P Boost Side Bottom Gate Driver Pull-Up Output. Drives the gate of buck side bottom N- Channel MOSFET with a voltage swing from ground to INTVCC. GND (Exposed Pad) Ground. Solder the exposed pad directly to the ground plane.

Figure 34. INTVCC Voltage vs Temperature

Figure 35. Block Diagram

analog.com Rev. 0 19 of 50 THEORY OF OPERATION The LT8292 is a 60V current mode synchronous DC/DC controller that can regulate output voltage, input or output current from input voltage above, below, or equal to the output voltage. The new generation ADI proprietary buck - boost dual edge peak current mode control scheme uses a direct inductor current sense resistor and guarantees the lowest inductor current ripple for improved power efficiency while enabling a smooth transition between buck region, buck-boost region, and boost region. The synchronous power switch controller with split pull-up and pull-down gate pins allows applications to use a wide range of pull-up gate resistance to improve EMI performance without compromising the pull -down strength of the driver. Moreover, the LT8292’s split gate driver architecture can monitor the true gate voltage of the power switches and thus provide more robust and accurate dead times, which can also be programmable from 2ns to 40ns. The internal control circuitry and gate drivers in LT8292 are powered by the dual input INTVCC linear regulator (LDO). Intelligently selecting the input source from either the VIN pin or VOUT pin further optimizes efficiency across all loads and enables the controller to provide enough gate drive capability. To optimize efficiency at light load, the LT8292 operates in low ripple Burst Mode operation in light load situations. Between bursts, all circuitry associated with controlling the output switch is shut down, reducing the input supply current to 32μA. In a typical application, less than 60μA will be consumed from the input supply when regulating 12V output with no load. The LT8292’s low -ripple Burst Mode operation guarantees only a single burst pulse switching while maintaining a tight output regulation per formance with minimum ripple even under deep or no -load burst conditions. The SYNC/MODE is tied low to use Burst Mode operation and can be tied with 100kΩ to GND or float to use pulse-skipping mode or force continuous mode (FCM), respectively. If a clock is applied to the SYNC/MODE pin, the part will synchronize to an external clock frequency and operate in FCM. When in FCM, the oscillator operates continuously, and positive SW transitions are aligned to the clock. A negative inductor current is allowed. In this mode, the LT8292 can sink current from the output and return this charge to the input, improving load-step transient response. If the EN/UVLO pin is low, the LT8292 is shut down and consumes only 0.3µA (typical) from the input. When the EN/UV pin is above 1.239V, the switching controller will become active. To improve EMI, the LT8292 can operate in spread spectrum mode. This feature varies the clock with a triangular frequency modulation of +25%. For example, if the LT8292 frequency is programmed to switch at 400kHz, spread spectrum mode will modulate the oscillator between 400kHz and 500kHz. The SYNC/MODE pin is to be tied high to INTVCC to use spread spectrum modulation with FCM. To expand the buck -boost controller into a kilowatt power level, the LT8292 features a leaderless current sharing scheme using the ISHARE and the IGND pins, allowing higher load current and better heat management. A CLKOUT pin enables synchronizing other regulators with the LT8292. Comparators monitoring the FB pin voltage will pull the PGOOD pin low if the output voltage varies more than ±8% (typical) from the set point, or if a fault condition is present. See the Block Diagram for the best understanding of LT8292’s operation.

by the voltage on the VC pin, which is the diode-OR of error amplifiers EA1 and EA2. Figure 43. SW Frequency vs Load Current in Burst Mode Operation SYNC/MODE pin low to the ground. time the LT8292 is in sleep mode increases, resulting in much higher light load efficiency than for typical converters. leakage currents from the output should also be minimized as they all add to the equivalent output load.

Table 4. Comparison Between Burst Mode, Pulse-Skipping Mode, and Forced Continuous Mode Operations The LT8292 can operate in FCM for fast transient response and full -frequency operation over the entire load range. is required to sink current. To enable FCM, float the SYNC/MODE pin. the negative inductor current is not allowed, and the LT8292 operates in pulse-skipping mode. Figure 44. Load Step Transient Response with and without FCM

analog.com Rev. 0 25 of 50 Internal Charge Path Each of the two top MOSFET drivers is biased from its floating bootstrap capacitor, which is normally re-charged by INTVCC through the integrated bootstrap diode D1 or D2 when the top MOSFET is turned off. When the LT8292 operates exclusively in the buck or boost regions, one of the top MOSFETs is constantly on. An internal charge path, from VOUT and BST2 to BST1 or from VIN and BST1 to BST2, charges the bootstrap capacitor to 4.6V so that the top MOSFET can be kept on. Shutdown and Power-on-Reset The LT8292 enters shutdown mode and drains less than 2μA quiescent current when the EN/UVLO pin is below its shutdown threshold (0.6V typical). Once the EN/UVLO pin is above its shutdown threshold, the LT8292 wakes up startup circuitry, generates bandgap reference, and powers up the internal INTVCC LDO. The INTVCC LDO supplies the internal control circuitry and gate drivers. Now, the LT8292 enters UVLO mode. When in UVLO mode, the part is in a power-on-reset (POR) state, waking up the entire internal control circuitry and settling to the right initial conditions. When the following conditions are met, the LT8292 is ready to exit the POR state and will enter the INIT state: 1) SS < 0.2V 2) INTVCC pin is charged above its rising UVLO threshold (3.6V typical) for approximately 100us. 3) EN/UVLO pin passes its rising enable threshold (1.239V typical). 4) Junction temperature is less than its thermal shutdown (170°C typical). The LT8292 has an accurate enable threshold (typically 1.239V rising and 1.18V falling) on the EN/UVLO pin to enable the part. The accurate enable threshold allows the user to program an UVLO threshold with a resistor divider from the input supply V IN to the ground. When operating in Burst Mode, the current flowing through the resistor divider can easily exceed the quiescent current consumed by the part. Therefore, the resistor divider values should be large enough to minimize its effect on the efficiency at light load conditions.

analog.com Rev. 0 27 of 50 1.75V, the control logic forbids synchronizing from the external clock and disables the Burst Mode operation, FCM, and spread spectrum frequency modulation. After the SS pin rises above 1.75V, both external frequency synchronization and operation mode selection are controlled by the SYNC/MODE pin setting. Once the SS pin is charged above 1.75V, the LT8292 enters the OK/RUN state, where the output short detection is activated. The output short means VFB < 0.25V. When the output short happens, the LT8292 enters the FAULT/STOP state, where the switching is immediately disabled, and a 1.25μA pull -down current slowly discharges the SS pin. Once the SS pin is discharged below 1.7V, the LT8292 enters the DOWN/ STOP state, where the short detection is deactivated with the previous fault latched. During this period, the part forbids the Burst Mode operation, FCM, and spread spectrum frequency modulation. Once the SS pin is discharged below 0.2V, the LT8292 goes back to the UP/RUN state. In an output short condition, the LT8292 is set to hiccup fault protection mode, where the LT8292 will hiccup between 0.2V and 1.75V and go around the UP/RUN, OK/RUN, FAULT/STOP, and DOWN/STOP states until the fault condition is cleared. Once the FB pin voltage exceeds 8% (typical) above its 1V regulation voltage, the output overvoltage fault will be triggered, which disables the switching immediately. After the FB pin voltage drops below the overvoltage threshold, the switching will be enabled again. No soft start-up will be re-initiated in this fault case.

assume continuous conduction mode unless otherwise specified. applications, consider operating at higher frequencies to minimize the total solution size. system, the switching frequency is usually selected to keep the switching noise out of a sensitive frequency band. RT resistor values for common switching frequencies. Table 5. Switching Frequency vs RT Value (1% Resistor) internal oscillator frequency. beginning of a switching cycle, turning on switches A and C or switches A and D.

analog.com Rev. 0 29 of 50 Inductor Selection The switching frequency and inductor selection are interrelated in that higher switching frequencies allow the use of smaller inductor and capacitor values. The inductor value has a direct effect on the ripple current. The highest current ripple ΔIL% happens in the buck region at V IN(MAX), and the lowest current ripple ΔI L% happens in the boost region at VIN(MIN). For any given ripple allowance set by customers, the minimum inductance can be calculated as: LBUCK > VOUT • (VIN(MAX) – VOUT) f • IOUT(MAX) • ∆IL% • VIN(MAX) LBOOST > VIN(MIN) 2 • (VOUT – VIN(MIN)) f • IOUT(MAX) • ∆IL% • VOUT where: IL% > ∆IL IL(AVG) f is the switching frequency. VIN(MIN) is the minimum input voltage. VIN(MAX) is the maximum input voltage. VOUT is the output voltage. IOUT(MAX) is the maximum output current. Slope compensation provides stability in constant frequency current mode control by preventing subharmonic oscillations at certain duty cycles. The minimum inductance required for stability when duty cycles are larger than 50% can be calculated as: L > 10 • VOUT • RSENSE f For high efficiency, choose an inductor with low core loss, such as ferrite. Also, the inductor should have low DC resistance to reduce the I 2R losses and must be able to handle the peak inductor current without saturating. To minimize radiated noise, use a shielded inductor.

analog.com Rev. 0 30 of 50 RSENSE Selection and Maximum Output Current The inductor current sense resistor (R SENSE) is chosen based on the required output current. The duty cycle independent maximum current sense thresholds (50mV in peak -buck and 50mV in peak -boost) set the maximum inductor peak current in buck region, buck-boost region, and boost region. In the boost region, the lowest maximum average load current happens at VIN(MIN) and can be calculated as: IOUT(MAX_BOOST) = ( 50mV RSENSE − ∆IL(BOOST) 2 ) • VIN(MIN) VOUT where ΔIL(BOOST) is the peak-to-peak inductor ripple current in the boost region and can be calculated as: IL(BOOST) = VIN(MIN) • (VOUT – VIN(MIN)) f • L • VOUT In buck region, the lowest maximum average load current happens at VIN(MAX) and can be calculated as: IOUT(MAX_BUCK) = ( 50mV RSENSE − ∆IL(BUCK) 2 ) where ΔIL(BUCK) is peak-to-peak inductor ripple current in buck region and can be calculated as: IL(BUCK) = VOUT • (VIN(MAX)-VOUT) f • L • VIN(MAX) The maximum current sense RSENSE in the boost region is: RSENSE(BOOST) = 2 • 50mV • VIN(MIN) 2 • IOUT(MAX) • VOUT + ∆IL(BOOST) • VIN(MIN) The maximum current sense RSENSE in the buck region is: RSENSE(BUCK) = 2 50mV 2 • IOUT(MAX) + ∆IL(BUCK) The final RSENSE value should be lower than the calculated RSENSE in both buck and boost regions. A 20% to 30% margin is usually recommended. Always choose a low ESL current sense resistor. Power MOSFET Selection The LT8292 requires four external N-channel power MOSFETs, two for the top switches (switches A and D, shown in Figure 36) and two for the bottom switches (switches B and C, shown in Figure 36). Important parameters for the power MOSFETs are the breakdown voltage V BR(DSS), threshold voltage V GS(TH), on-resistance RDS(ON), reverse transfer capacitance CRSS, and maximum current IDS(MAX). The drive voltage is set by the 5V INTVCC supply. Consequently, logic-level threshold MOSFETs must be used in LT8292 applications. To select the power MOSFETs, the power dissipated by the device must be known. For switch A, the maximum power dissipation happens in the boost region, when it remains on all the time. Its maximum power dissipation at maximum output current is given by: PA(BOOST) = (IOUT(MAX) • VOUT VIN )

• ρT • RDS(ON)

Figure 46. Normalized RDS(ON) vs Temperature the reverse recovery current, is inversely proportional to the gate drive current and has an empirical value of 1.7. For switch D, the maximum power dissipation happens in the boost region, when its duty cycle is higher than 50%.

• IOUT(MAX) 2 • ρT• RDS(ON) For the same output voltage and current, switch A has the highest power dissipation, and switch B has the lowest power dissipation unless a short occurs at the output. JUNCTION TEMPERATURE (°C) –50 ρT NORMALIZED ON-RESISTANCE (Ω) 1.0 1.5 150 0.5 0 50 100 2.0 046

analog.com Rev. 0 32 of 50 From a known power dissipated in the power MOSFET, its junction temperature can be obtained using the following formula: TJ = TJ + P • RTH(JA) The junction-to-ambient thermal resistance R TH(JA) includes the junction -to-case thermal resistance R TH(JC) and the case-to-ambient thermal resistance RTH(CA). This value of TJ can then be compared to the original, assumed value used in the iterative calculation process. Optional Schottky Diode (DB, DD) Selection The optional Schottky diodes D B (in parallel with switch B) and D D (in parallel with switch D) are conducted during the dead time between the conduction of the power MOSFET switches. They are intended to prevent the body diode of synchronous switches B and D from turning on and storing charge during the dead time. In par ticular, D B significantly reduces the reverse recovery current between switch B turn -off and switch A turn -on, and D D significantly reduces the reverse recovery current between switch D turn -off and switch C turn -on. They improve converter efficiency and reduce switch voltage stress. For the diode to be effective, the inductance between it and the synchronous switch must be as small as possible, mandating that these components be placed adjacently. CIN and COUT Selection Input and output capacitance are necessary to suppress voltage ripple caused by discontinuous current moving in and out of the regulator. A parallel combination of capacitors is typically used to achieve high capacitance and low equivalent series resistance (ESR). Dry tantalum, special polymer, aluminum electrolytic, and ceramic capacitors are all available in surface -mount packages. Capacitors with low ESR and high ripple current ratings, such as OS -CON and POSCAP, are also available. Ceramic capacitors should be placed near the regulator input and output to suppress high -frequency switching spikes. Ceramic capacitors of at least 1μF should also be placed from V IN to GND and V OUT to GND as close to the LT8292 pins as possible. Due to their excellent low ESR characteristics, ceramic capacitors can significantly reduce input ripple voltage and help reduce power loss in the higher ESR bulk capacitors. X5R or X7R dielectrics are preferred, as these materials retain their capacitance over wide voltag e and temperature ranges. Many ceramic capacitors, particularly 0805 or 0603 case sizes, have greatly reduced capacitance at the desired operating voltage. Input Capacitance (CIN) Discontinuous input current is highest in the buck region due to switch A toggling on and off. Ensure that the C IN capacitor network has low enough ESR and is sized to handle the maximum RMS current. In buck region, the input RMS current is given by: IRMS ≈ IOUT(MAX) • VOUT VIN • √ VIN VOUT − 1 The formula has a maximum at VIN = 2VOUT, where IRMS = IOUT(MAX)/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Output Capacitance (COUT) Discontinuous current shifts from the input to the output in the boost region. Ensure that the COUT capacitor network is capable of reducing the output voltage ripple. The effects of ESR and bulk capacitance must be considered when choosing the right capacitor for a given output ripple voltage.

analog.com Rev. 0 33 of 50 The maximum steady state ripple due to charging and discharging the bulk capacitance is given by: ΔVCAP(BOOST) = IOUT(MAX) • (VOUT – VIN(MIN)) COUT • VOUT • f ΔVCAP(BUCK) = VOUT • (1 − VOUT VIN(MAX) 8 • L • f2 • COUT The maximum steady ripple due to the voltage drop across the ESR is given by: ΔVESR(BOOST) = VOUT • IOUT(MAX) VIN(MIN)  ESR ΔVESR(BUCK) = VOUT • (1 − VOUT VIN(MAX) L  f  ESR Dual Input INTVCC Regulator An internal P-channel low dropout (LDO) regulator produces 5V at the INTV CC pin from either the V IN supply or VOUT pins powering internal circuitry and gate drivers in the LT8292. The INTV CC regulator can supply a peak current of 170mA and must be bypassed to ground with a minimum of 4.7μF ceramic capacitor. A good local bypass is necessary to supply the high transient current required by MOSFET gate drivers. Note: The INTVCC LDO is designed only to supply the internal circuitry of LT8292 and can not be used as a bias supply for other external circuits. Overload or short circuit on the INTVCC LDO may cause permanent damage and failure. To enable a wider VIN range and more efficient operation, the internal LDO can intelligently draw current from either the VIN supply pin or the VOUT pin. When VIN is below 5.5V, the internal LDO draws current from the higher of the two voltage pins so that the LT8292 can provide enough gate drive capability. When the V OUT is regulated above 5V, the LT8292 can still securely operate with the minimum VIN as low as 3V. When VIN and VOUT are both above 5.5V, the internal LDO draws current from the lower of the two voltage pins so that the LT8292 can optimize efficiency across all loads. If the VIN is above 5.5V but the VOUT is below 5.5V, the internal LDO will then draw current from the V IN, ensuring gate drive capability. Table 6 summarizes this input selection logic of the LT8292’s dual input LDO. Higher input voltage applications with large MOSFETs being driven at higher switching frequencies may cause the maximum junction temperature rating for the LT8292 to be exceeded. The system supply current is normally dominated by the gate charge current. The total LT8292 power dissipation, in this case, is VSOURCE  IINTVCC, where VSOURCE is either V IN or VOUT, depending on the conditions described above. The junction temperature can be estimated by using the equation: TJ = TA + PD • θJA where θJA (in °C/W) is the package thermal resistance. To prevent the maximum junction temperature from being exceeded, the input supply current must be checked, operating in continuous mode at maximum VSOURCE.

Table 6. Dual Input LDO’s Supply Combination Logic D. In most applications, a 0.1μF to 0.47μF, X5R or X7R dielectric capacitor is adequate. of the gate and weaken the pull-down strength of the driver, causing degraded efficiency and system reliability. Figure 47. Split-Gate Driver of the LT8292 (Buck-Side)

pull-down strength is not needed, the split pins can be shorted and used as a single-gate drive. The LT8292 eliminates these side effects by offering adaptive and selectable dead times from 40ns to 2ns (typical). accurate and robust dead time control. proper PCB layout and power MOSFET selection should be carefully considered. Table 7. Dead Time Period vs RDT value

should be tied to a voltage higher than 1.35V to get the full-scale 50mV (typical) threshold across the sense resistor. varies. The typical VISP-VISN threshold vs VICTRL is listed in Table 8. Table 8. VISP – VISN Threshold vs VICTRL the ISP and ISN pins should be shorted to VIN, VOUT, or ground. Figure 50. Programming Input Current Limit

together, and kelvin all IGND pins to a common ground as shown in Figure 54. Figure 54. ISHARE and IGND Connection for LT8292s in Parallel where, IOUTN is the output current of the Nth phase.

A low-pass filter formed by RF and CF (Figure 54) is recommended to optimize the current loop response and stability. demonstrates a good parallel design example. lower tolerance resistor is not available. A resistor value of less than 50Ω is mostly recommended. The LT8292 provides a digital clock output pin CLKOUT that enables synchronizing one or more LT8292 ICs in parallel. example in the Typical application diagram (Figure 57). Figure 55. Feedback Resistor Connection

analog.com Rev. 0 41 of 50 To provide the output short-circuit detection and protection, the output short threshold can be calculated as: VOUT(SHORT) = 0.25V • R3 + R4 Power Good (PGOOD) Pin The LT8292 provides an open-drain status pin, PGOOD, which is pulled low when VFB exceeds ±8% of the 1V regulation voltage. The PGOOD pin can be pulled up by an external resistor to INTVCC or an external voltage source of up to 6V. Soft-Start and Short-Circuit Protection As shown in Figure 45 and explained in the Theory of Operation section, the SS pin can be used to program the output voltage soft -start by connecting an external capacitor from the SS pin to the ground. The internal 13μA pull -up current charges up the capacitor, creating a voltage ramp on the SS pin. As the SS pin voltage rises linearly from 0.25V to 1V (and beyond), the output voltage rises smoothly into its final voltage regulation. The soft -start time can be calculated as: tSS = 1V • CSS 13µA Ensure that the C SS is at least five to ten times larger than the compensation capacitor on the V C pin for a well - controlled output voltage soft-start. A 0.1μF ceramic capacitor is a good starting point. The SS pin is also used as a fault timer. Once an output short -circuit fault is detected, the LT8292 enters a low-duty cycle auto-retry (hiccup) operation. In this scenario, the switching is immediately disabled, and a 1.25μA pull-down current source is activated to discharge the SS pin. After the SS pin is discharged below 0.2V, the 13μA pull-up current charges the SS pin up again. If the output short -circuit condition has not been removed when the SS pin reaches 1.75V, the 1.25μA pull-down current turns on again, initiating a new hiccup cycle. This will continue until the fault is removed. Once the output short -circuit condition is removed, the output will have a smooth short -circuit recovery due to a soft-start. Loop Compensation The LT8292 uses an internal transconductance error amplifier, the output of which, VC, compensates the control loop. The external inductor, output capacitor, and compensation resistor and capacitor determine the loop stability. The inductor and output capacitor are chosen based on performance, size, and cost. The compensation resistor and capacitor on the V C pin are set to optimize control loop response and stability. For a typical voltage regulator application, a 10nF compensation capacitor on the VC pin is adequate, and a series resistor should always be used to increase the slew rate on the VC pin to maintain tighter output voltage regulation during fast transients on the input supply of the converter.

analog.com Rev. 0 42 of 50 Efficiency Considerations The power efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what limits efficiency and which change would produce the most improvement. Although all dissipative elements in circuits produce losses, four main sources account for most of the losses in LT8292 circuits: 1. DC I 2R losses. These arise from the resistances of the MOSFETs, sensing resistor, inductor, and PC board traces and cause the efficiency to drop at high output currents. 2. Transition loss. This loss arises from the brief amount of time switch A or switch C spends in the saturated region during switch node transitions. It depends upon the input voltage, load current, driver strength, and MOSFET capacitance, among other factors. 3. INTVCC current. This is the sum of the MOSFET driver and control currents. 4. CIN and C OUT loss. The input capacitor has the difficult job of filtering the large RMS input current to the regulator in the buck region, and the output capacitor has the difficult job of filtering the large RMS output current in the boost region. Both C IN and COUT must have low ESR to minimize the AC I 2R loss and sufficient capacitance to prevent the RMS current from causing additional upstream losses in fuses or batteries. 5. Other losses. Body diodes of switch B and switch D, or optional Schottky diodes D B and DD, are responsible for conduction losses during dead time and light load conduction periods. Inductor core loss occurs predominantly at light loads. Switch A causes reverse recovery current loss in the buck region, and switch C causes reverse recovery current loss in the boost region. 6. When making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. If you make a change and the input current decreases, then the efficiency has increased. If there is no change in the input current, then there is no change in efficiency. PC Board Layout Checklist The basic PC board layout requires a dedicated ground plane layer. For high currents, a multilayer board provides heat sinking for power components.  The ground plane layer should not have traces and should be as close as possible to the layer with power MOSFETs.  Place CIN, switch A, switch B, and D B in one compact area. Place C OUT, switch C, switch D, and D D in one compact area.  Connect the components to the ground plane using immediate vias. Use several large vias for each power component.  Use planes for VIN and VOUT to maintain good voltage filtering and to keep power losses low.  Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. Connect the copper areas to any DC net (VIN or GND).  Separate the signal and power grounds. All small-signal components should return to the exposed GND pad from the bottom, which is then tied to the power GND close to the sources of switch B and switch C.  Place all power switches close to the controller. Keep the power GND, BG, TG, and SW traces short.  Keep the high dV/dT SW1, SW2, BST1, BST2, TG1 and TG2 nodes away from sensitive small-signal nodes.  The path formed by switch A, switch B, D B, and the CIN capacitor should have short leads and PCB trace lengths. The path formed by switch C, switch D, D D, and the C OUT capacitor should also have short leads and PCB trace lengths.

analog.com Rev. 0 43 of 50  The output capacitor ( –) terminals should be connected as close as possible to the ( –) terminals of the input capacitor.  Connect the top driver boost capacitor C BST1 closely to the BST1 and SW1 pins. Connect the top driver boost capacitor CBST2 closely to the BST2 and SW2 pins.  Connect the input capacitors CIN and output capacitors COUT closely to the power MOSFETs. These capacitors carry the MOSFET AC current.  Route LSP and LSN trace together with minimum PCB trace spacing. Avoid sense lines passing through noisy areas, such as switch nodes. The filter capacitor between LSP and LSN should be as close as possible to the IC. Ensure accurate, current sensing with K elvin connections at the R SENSE resistor. A low ESL sense resistor is recommended. LSP trace and SW1 trace should be two separate traces. Do not share traces.  Connect the VC pin compensation network close to the IC, between the V C and the signal ground. The capacitor helps to filter the effects of PCB noise and output ripple voltage from the compensation loop.  Connect the INTV CC bypass capacitor, C INTVCC, close to the IC, between the INTV CC and the power ground. This capacitor carries the MOSFET drivers’ current peaks. An additional 1μF ceramic capacitor placed immediately next to the INTVCC pin and power ground can help improve noise performance substantially.

analog.com Rev. 0 44 of 50 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT8390/LT8390A 60V Synchronous 4-Switch Buck-Boost Controller with Spread Spectrum VIN: 4V to 60V, VOUT: 1V to 60V, ±1.5% Voltage Accuracy, ±3% Current Accuracy, TSSOP-28, and 4mm × 5mm QFN-28 LT8392 60V Synchronous 4-Switch Buck-Boost Controller with Spread Spectrum VIN: 3V to 60V, VOUT: 1V to 60V, ±1.5% Voltage Accuracy, ±4% Current Accuracy, TSSOP-28, and 4mm × 5mm QFN-28 LT3790 60V Synchronous 4-Switch Buck-Boost Controller VIN: 4.7V to 60V, VOUT: 1.2V to 60V, ±2% Voltage Accuracy, ±6% Current Accuracy, and TSSOP-38 LT8705 80V Synchronous 4-Switch Buck-Boost Controller VIN: 2.8V to 80V, VOUT: 1.3V to 80V, Regulates VOUT, IOUT, VIN, IIN, 5mm × 7mm QFN-38 and Modified TSSOP-38 for High Voltage LTC3789 38V Synchronous 4-Switch Buck-Boost Controller VIN: 4V to 38V, VOUT: 0.8V to 38V, Regulates VOUT, IOUT, or IIN, 5mm × 5mm QFN-32 and SSOP-24 LTC3780 36V Synchronous 4-Switch Buck-Boost Controller VIN: 4V to 36V, VOUT: 0.8V to 30V, Regulates VOUT, 4mm × 5mm QFN-28 and SSOP-28

Figure 56. 300W (12V, 25A) Parallelable Buck-Boost Voltage Regulator

Figure 57. 600W (12V, 50A) 2-Phase Parallel Buck-Boost Voltage Regulator System with 180° Phase Shift using CLKOUT

Figure 58. 1.2kW (12V, 100A) 4-Phase Parallel Buck-Boost Voltage Regulator System with 90° Phase Shift using LTC6902

analog.com Rev. 0 48 of 50 OUTLINE DIMENSIONS

Table 9. Ordering Guide Contact the factory for parts specified with wider operating temperature ranges. specific product ordering information and to obtain the specific Automotive Reliability report for this model.

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