LT8277 AD | Alldatasheet
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Technical content
analog.com Rev 0 2 of 31 TABLE OF CONTENTS
REVISION HISTORY
10/2023 - Rev. 0
Table 1. Electrical Characteristics
analog.com Rev 0 4 of 31 (Specifications are at TA = 25°C, VIN = 12V, VENABLE = 12V, unless otherwise noted) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS VSENSE Matching PH1 to PH2 Maximum Current Sense Threshold Mismatch -5 5 mV SNSP1, SNSP2 Pin Current VC = 1.25V 100 µA SNSN1, SNSN2 Pin Current VC = 1.25V 1 4 µA Error Amplifier Error Amplifier Transconductance gMEA Using SPI Code for 60V 100 µS Error Amplifier Output Resistance REA Using SPI Code for 60V 4 MΩ VC Current Mode Gain (∆VVC/∆VSENSE) GVC 2-Phase Operation (VC = 1V) 8 V/V Internal VC Upper Limit Clamp Voltage VC_CLAMP 1.38 1.42 1.46 V VC Phase 2 Shed Threshold (Falling) VC_SHED 675 mV VC Phase 2 Add Threshold (Rising) VC_ADD 750 mV VC Source Current IVC_SOURCE –30 µA VC Sink Current IVC_SINK 30 µA VOUT Range VOUT 9 60 V VOUT Regulation Accuracy VOUT = 9V Typical This specification is valid over the full operating temperature range 8.8 9 9.2 V VOUT = 60V Typical This specification is valid over the full operating temperature range 58 60 62
analog.com Rev 0 5 of 31 (Specifications are at TA = 25°C, VIN = 12V, VENABLE = 12V, unless otherwise noted) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS Oscillator Switching Frequency fSW RT = 523kΩ This specification is valid over the full operating temperature range 90 100 110 kHz RT = 11kΩ 1.8 2 2.2 MHz Minimum Off Time tGATE_OFF_MIN This specification is valid over the full operating temperature range 35 55 77 ns Minimum On Time tGATE_ON_MIN 70 ns SYNC Input Low VSYNC_IL 0.4 V SYNC Input High VSYNC_IH 1.6 V Spread Spectrum Frequency Range 100 122 %fSW Spread Spectrum Modulation Frequency 1.0 kHz Logic PGOOD Output Low VPGOOD_OL IPGOOD = 1mA 300 mV PGOOD Upper Limit Fraction of Programmed VOUT 105 % PGOOD Lower Limit Fraction of Programmed VOUT 95 % Gate Driver Driver Pull-UP RDS(ON) RGATE_UP 1 Ω Driver Pull-DOWN RDS(ON) RGATE_DN 1 Ω SPI Interface CS, SCK, SDI Input Low Voltage VSPI_IL 0.8 V CS, SCK, SDI Input High Voltage VSPI_IH 1.7 V tCSI, CS Idle Time tCSI 500 ns tSC, CS Setup Time tSC 300 ns
Figure 3. Timing Diagram
TA = 25°C unless otherwise specified. Table 2. Absolute Maximum Ratings these pins or the RT pin externally to a power supply. junction temperatures greater than 125°C. temperature may impair device reliability. for extended periods may affect product reliability.
Figure 4. Pin Diagram Table 3. Pin Descriptions
2 ENABLE
Applications Information section. Applications Information section. 7 SDI Data Input Pin for SPI port.
14 MODE
15 PGOOD
16 VOUT
18 GATE1
19 GND
20 INTVCC
- EXPOSED PIN. EXPOSED PIN = GND. THE EXPOSED PAD (PIN 21)
GROUND PIN FOR ROUTING CONVENIENCE ONLY.
analog.com Rev 0 9 of 31 8 CS Chip Select Pin for SPI port. 9 SCK Serial Clock Input Pin for SPI port. All serial data transfers are sampled on rising edges of this clock.
10 CLKOUT
Buffered Version of Internal Clock. The buffered version is either 45° or 90° out-of- phase with the switching clock of phase 1. This pin can be set to high-Z mode if it is not needed.
11 SYNC/
The SYNC/SPRD Pin can be used to synchronize the internal oscillator to an external logic level signal. Tie to INTVCC to enable internal spread spectrum frequency modulation, and tie to the ground or leave open if unused. 12 RT Switching Frequency Adjustment Pin. Set the frequency using a resistor to GND. Do not leave this pin open. 13 VC Transconductance Error Amplifier Output Pin used to stabilize the loop with an RC network. Read more in the Applications Information section for details about compensation. Wake-up and Watchdog Timer Mode Selection Pin. Tie this pin to INTVCC to wake up with VOUT programmed to 60V and return to 60V on watchdog timer expiration. Tie this pin to INTVCC/2 or leave it open to wake up with VOUT set to 36V and return to 36V on watchdog timer expiration. Tie this pin to the ground to disable the watchdog timer and delay wake-up after ENABLE goes high until a valid SPI command has programmed the output voltage target. 15 PGOOD Power Good Indicator Pin. Open-drain logic output is pulled to GND when the output voltage is more than around ±5% away from the programmed regulation target. Output Voltage Sense Pin. Also, it supplies power to INTVCC when the input voltage drops below 5V. The output regulation target is programmed via the SPI port. A minimum 0.1μF local bypass capacitor must be placed close to this pin. 17, 18 GATE2, GATE1 N-Channel MOSFET Gate Driver Output Pin. Switches between INTVCC and GND. Driven to GND when the IC is in thermal shutdown or when INTVCC is below its undervoltage lockout, or the part is shut down by the ENABLE pin. Internal Low-Dropout Regulator Output Pin. INTVCC is regulated to 5V and requires a 4.7μF bypass capacitor. This regulator supplies power to internal circuitry, and connecting certain external loads may interfere with the operation of the part. 19, 21 GND Ground Pin. The exposed pad (pin 21) must be soldered to PCB ground. Pin 19 is included as a ground pin for routing convenience only.
Figure 28. Block Diagram enable 4- or 8-phase configurations. To best understand the following discussion, see Figure 28. behavior. A multiphase, multichip operation uses the CLKOUT pin of one part to drive the SYNC/SPRD pin of the next.
the part allows for a wide range of voltage and power levels with minimal off-chip components. toggling phase 2 dropout at light load, organized as a 12-bit command word. Table 4. SPI Operation Configuration Table 5. MODE Pin Settings
inductance requirements will change based on switching frequency, programmed current limit, and input voltage. Use Equation 1 to estimate the inductance needed for each phase. Additional margin is recommended. series resistance. A table of manufacturers appears in Table 6. Table 6. Recommended Inductor Vendors the part will see. For a boost or SEPIC converter, the input capacitor can often be smaller than the output capacitor. above guidance. Here, n represents the number of phases. Additional margin is recommended. capacitor. A normalized plot of peak-to-peak current flowing in the input capacitor appears in Figure 29.
A table of manufacturers appears in Table 7. Table 7. Recommended Capacitors Vendors SNSN pins monitor the voltage at this resistor. The inductor current limit using this method is shown in Figure 31. Keep the power dissipation capability of the resistor in mind for high-current applications. Figure 31. Input Current Limit Programmed by Sense Resistor
Figure 32. LT8277 DCR Current Sensing This relationship is underspecified, so pick a reasonable pair of R and C values. in mind for high-power applications. A table of manufacturers appears in Table 8. Table 8. Recommended Power NMOS Vendors than the programmed inductor current limit. A table of manufacturers appears in Table 9. Table 9. Recommended Schottky Vendors
the VC pin and ground. For many low-frequency applications, a 4.7nF capacitor and 10k resistor will suffice. input and output voltage ripple and reduce inductor current ripple, but it can also decrease efficiency. programmed switching frequency is within ±15% of the external clock frequency. tie the SYNC/SPRD pin to INTVCC. Table 10. Selected RT values and Switching Frequency bit to speed up soft-start, decreasing its duration to 25% of the default soft-start time set by RT. recommended to prevent errant assertions of the PGOOD signal while the part is unpowered. cooldown period, the part will attempt to restart as if power had just been applied.
ENABLE pin in the off state to enable programmable hysteresis, as shown in Figure 33. Figure 33. Resistor Network for Accurate UVLO limits, contribute the same current to the load. can improve phase-to-phase peak current matching. Multiphase operation can degrade light-load efficiency and lead to pulse skipping earlier than the single-phase case. prevent pulse skipping at a very light load for either phase.
example layout represents a two-layer PCB; however, a four-layer PCB is recommended. thermal performance. Users must consider the tradeoffs carefully. Figure 34. Example of 8-Phase Operation using the Same Interface as the Single-Chip Configuration connects the VOUT pin to the output capacitor.
Figure 35. Reference Layout for the LT8277
Figure 36. 180W Automotive Pre-Boost Converter with SPI
Figure 39. Efficiency vs. Load Current Curve of 12V 60W 2MHz Boost Voltage Regulator
Figure 42. Efficiency vs. Load Current Curve of 4-Phase 60V 360W 250kHz Boost Voltage Regulator
analog.com Rev 0 29 of 31 OUTLINE DIMENSIONS 3.00 ±0.05 1.50 REF 4.00 ±0.05 NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (NOTE 6) 0.40 ±0.10 19 20 BOTTOM VIEW—EXPOSED PAD
2.50 REF
1.00 BSC
0.75 ±0.05 R = 0.115 TYP PIN 1 CHAMFER C = 0.35 0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05 (UDCM20) QFN 0722 REV A RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 0.25 ±0.05 3.10 ±0.05 4.50 ±0.05
1.50 REF
2.10 ±0.05 3.50 ±0.05 PACKAGE OUTLINE 1.65 ±0.10 2.65 ±0.10 1.65 ±0.05 2.65 ±0.05 0.75 ±0.050.200 REF 0.00 – 0.05
0.203 REF
0.40 ± 0.10
0.05 REF
0.10 MIN
0.275 REF
Table 11. Ordering Guide
ALL INFORMATION CONTAINED HEREIN IS PROVIDED “AS IS” WITHOUT REPRESENTATION OR WARRANTY. NO RESPONSIBILITY IS ASSUMED BY ANALOG DEVICES FOR ITS USE, NOR FOR ANY INFRINGEMENTS OF PATENTS OR OTHER RIGHTS OF THIRD PARTIES THAT MAY RESULT FROM ITS USE. SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. NO LICENCE, EITHER EXPRESSED OR IMPLIED, IS GRANTED UNDER ANY ADI PATENT RIGHT, COPYRIGHT, MASK WORK RIGHT, OR ANY OTHER ADI INTELLECTUAL PROPERTY RIGHT RELATING TO ANY COMBINATION, MACHINE, OR PROCESS WHICH ADI PRODUCTS OR SERVICES ARE USED. TRADEMARKS AND REGISTERED TRADEMARKS ARE THE PROPERTY OF THEIR RESPECTIVE OWNERS. analog.com Rev 0 31 of 31