LT8253

LT8253/LT8253A (Rev. A)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 20

Technical content

Rev. AFor more information www.analog.com Document Feedback TYPICAL APPLICATION FEATURES DESCRIPTION 40V USB Type-C Power Delivery Buck-Boost Controller The LT®8253/LT8253A are synchronous 4-switch buck- boost controllers optimized for automotive USB-C power delivery. The LT8253/53A are fully compliant to the USB Power Delivery (PD) specification when used in conjunc- tion with a USB Type-C or PD port controller . The output voltage slew rate can be controlled through the FB pin. The LT8253 can deliver up to 100W output power with 98% peak efficiency when running below the AM band. The LT8253A can deliver up to 60W output power with 95% peak efficiency when running above the AM band. The LT8253/8253A support single buck-boost output for 1 Type-C port with power good flag. Over-current, over- voltage, and short-circuit protections are also available. Automotive 60W USB-C Power Delivery Charger (400kHz)

APPLICATIONS

n Proprietary Low-EMI Buck-Boost Architecture n Wide Input Range: 4V to 40V n Synchronous Switching: Up to 98% Efficiency n ±1.5% Output Voltage Regulation n Single Output supports 1 Type-C Port up to 100W n Output Channel Enable Function n Programmable Switching Frequency with External Synchronization and Spread Spectrum n Over-Current, Over-Voltage, Short-Circuit Protection n Available in 28-Lead Side Solderable QFN Package n AEC-Q100 Qualified for Automotive Applications n Automotive USB-C Power Delivery n General Purpose Voltage Regulator All registered trademarks and trademarks are the property of their respective owners. 6.8µH 0.1µF 0.1µF 200k 100k 100nF 5m/uni03A9 RS1 0.47µF 100k 3.3µH VIN VOUT EN/UVLO FB SSFM ON NO SSFM/SYNC SYNC D1: DIODES INC BZT52C12TQ-7-F FBIN: 2x MURATA BLM31KN471SZ1L FBOUT : 2x TDK MPZ2012S102ATD25 L1: COILCRAFT XAL8080-682ME L2: COILCRAFT XEL5050-332ME M1-M4: INFINEON IPZ40N04S5L-4R8 M5: DIODES INC DMP3010LPSQ RS1: SUSUMU KRL3216D-M-R005 RS2: SUSUMU KRL2012 L T8253 SW2 SW1 INTVCC PGOOD SYNC/SPRD VC RT SS f = 400kHz LSP LSN BST1 BST BG1 TG1 BG2 TG2 1µF 50V 1µF 25V VREF VOUTEN TEST GND 10µF 50V 10µF 25V 47µF 50V 4.7µF 30k 2.2nF 200k 50k 270µF 25V 4.7µF 25V VBUS CC1 CC2 GND D+2 D-1 D+1 D-2 USB TYPE-C P1.0 P0.0 P0.1 P2.1 P_CTRL C_CTRL DP1 DM1 C_MON CC1 CC2 DP0 DM0 GND VCCD VDDD COMP FB CSP VBUS_IN CYPD3196 VTARG GND NC SCLK SDAT 221k 10k PVIN 59k 0.1µF 470/uni03A9 10nF RS2 5m/uni03A9 6.04k DP0 390pF 390pF SHEILD 100k 2.2nF 2kV PVIN 1µF 0.1µF 1µF 0.1µF 1µF 0.1µF VOUTEN VOUTEN EXT SYNC VIN 10µF 0.1µF FBIN 10µF 50V 50V 10µF 0.1µF FBOUT 25V 2/uni03A9 5.1/uni03A9 2/uni03A9 5.1/uni03A9 100k 10nF 10k INTVCC NTC 100k 10nF 10k INTVCC NTC 8253A TA01

Rev. A For more information www.analog.com PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS Operating Junction Temperature Range (Notes 2, 3) (Note 1) 9 10 TOP VIEW UFDM PACKAGE 28-LEAD (4mm × 5mm) PLASTIC SIDE SOLDERABLE QFN θJA = 43°C/W, θJC = 3.4°C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB 11 12 13 28 27 26 25 24 1TG1 LSP LSN VIN INTVCC EN/UVLO TEST VOUTEN TG2 VOUT NC SYNC/SPRD RT VC FB SS SW1 BST1 BG1 BG2 BST2 SW2 VREF NC NC NC NC PGOOD 8 15 GND ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT8253EUFDM#PBF LT8253EUFDM#TRPBF 8253 28-Lead (4mm x 5mm) Plastic Side Solderable QFN –40°C to 125°C LT8253JUFDM#PBF LT8253JUFDM#TRPBF 8253 28-Lead (4mm x 5mm) Plastic Side Solderable QFN –40°C to 150°C LT8253HUFDM#PBF LT8253HUFDM#TRPBF 8253 28-Lead (4mm x 5mm) Plastic Side Solderable QFN –40°C to 150°C LT8253AEUFDM#PBF LT8253AEUFDM#TRPBF 8253A 28-Lead (4mm x 5mm) Plastic Side Solderable QFN –40°C to 125°C LT8253AJUFDM#PBF LT8253AJUFDM#TRPBF 8253A 28-Lead (4mm x 5mm) Plastic Side Solderable QFN –40°C to 150°C LT8253AHUFDM#PBF LT8253AHUFDM#TRPBF 8253A 28-Lead (4mm x 5mm) Plastic Side Solderable QFN –40°C to 150°C AUTOMOTIVE PRODUCTS** LT8253JUFDM#WPBF LT8253JUFDM#WTRPBF 8253 28-Lead (4mm x 5mm) Plastic Side Solderable QFN –40°C to 150°C LT8253HUFDM#WPBF LT8253HUFDM#WTRPBF 8253 28-Lead (4mm x 5mm) Plastic Side Solderable QFN –40°C to 150°C LT8253AJUFDM#WPBF LT8253AJUFDM#WTRPBF 8253A 28-Lead (4mm x 5mm) Plastic Side Solderable QFN –40°C to 150°C LT8253AHUFDM#WPBF LT8253AHUFDM#WTRPBF 8253A 28-Lead (4mm x 5mm) Plastic Side Solderable QFN –40°C to 150°C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by aLabel on the shipping container . Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. **Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact yourLocal Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.

Rev. AFor more information www.analog.com

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Supply VIN Operating Voltage Range l 4 40 V VIN Quiescent Current VEN/UVLO = 0.3V VEN/UVLO = 1.5V 2.1 µA mA VOUT Voltage Range l 1 25 V Linear Regulators INTVCC Regulation Voltage IINTVCC = 20mA 4.8 5 5.2 V INTVCC Current Limit VINTVCC = 4.5V (LT8253) VINTVCC = 4.5V (LT8253A) 110 110 145 160 190 mA mA INTVCC Undervoltage Lockout Threshold Falling 3.44 3.54 3.64 V INTVCC Undervoltage Lockout Hysteresis 0.24 V VREF Regulation Voltage IVREF = 100uA 1.96 2 2.04 V VREF Current Limit VREF = 1.8V 2 2.5 3.2 mA Control Inputs EN/UVLO Shutdown Threshold 0.3 0.6 1 V EN/UVLO Enable Threshold Falling 1.196 1.22 1.244 V EN/UVLO Enable Hysteresis 13 mV EN/UVLO Hysteresis Current VEN/UVLO = 1.1V VEN/UVLO = 1.3V –0.1 2.5 0.1 µA µA VOUTEN Threshold 1 1.6 V Error Amplifier FB Regulation Voltage l 0.985 1 1.015 V FB Voltage Regulation Amplifier gm 660 µS Current Comparator Maximum Current Sense Threshold V(LSP-LSN) Buck, VFB = 0.8V Boost, VFB = 0.8V mV mV Fault FB Short Threshold Falling 0.2 0.25 0.3 V FB Short Hysteresis 30 50 70 mV PGOOD Upper Threshold from VFB Rising 8 10 12 % PGOOD Lower Threshold from VFB Falling –12 –10 –8 % PGOOD Pull-Down Resistance 100 200 Ω SS Hard Pull-Down Resistance VEN/UVLO = 1.1V 100 200 Ω SS Pull-Up Current VFB = 0.4V, VSS = 0V 12.5 µA SS Pull-Down Current VFB = 0.1V, VSS = 2V 1.25 µA SS Fault High Threshold 1.7 V SS Fault Low Threshold 0.2 V Oscillator Oscillator Frequency VSYNC/SPRD = 0V, RT = 100kΩ (LT8253) VSYNC/SPRD = 0V, RT = 59.0kΩ (LT8253A) l l 380 1900 400 2000 420 2100 kHz kHz SYNC/SPRD Clock SYNC Frequency (LT8253) (LT8253A) 150 600 650 2000 kHz kHz The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VEN/UVLO = 1.5V unless otherwise noted.

Rev. A For more information www.analog.com Note 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2. The LT8253E/LT8253AE are guaranteed to meet performance specifications from 0°C to 125°C operating junction temperature. Specifications over the −40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT8253J/LT8253AJ and LT8253H/ SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SYNC/SPRD Clock SYNC Threshold 0.4 1.5 V NMOS Drivers TG1, TG2 Gate Driver On-Resistance Gate Pull-Up Gate Pull-Down V(BST-SW) = 5V 2.6 1.7 Ω Ω BG1, BG2 Gate Driver On-Resistance Gate Pull-Up Gate Pull-Down VINTVCC = 5V 1.2 Ω Ω TG Off to BG On Delay Time LT8253 LT8253A ns ns BG Off to TG On Delay Time LT8253 LT8253A ns ns ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VEN/UVLO = 1.5V unless otherwise noted. LT8253AH are guaranteed over the −40°C to 150°C operating junction temperature range. High junction temperatures degrade operating lifetimes. Operating lifetime is derated at junction temperatures greater than 125°C. Note 3. The LT8253/LT8253A include overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 150°C when overtemperature protection is active. Continuous operation above the specified absolute maximum operating junction temperature may impair device reliability.

Rev. AFor more information www.analog.com PIN FUNCTIONS BG1: Buck Side Bottom Gate Drive. Drives the gate of buck side bottom N-Channel MOSFET with a voltage swing from ground to INTVCC. BG2: Boost Side Bottom Gate Drive. Drives the gate of boost side bottom N-Channel MOSFET with a voltage swing from ground to INTVCC. BST1: Buck Side Bootstrap Floating Driver Supply. The BST1 pin has an integrated bootstrap diode from the INTVCC pin and requires an external bootstrap capacitor to the SW1 pin. BST2: Boost Side Bootstrap Floating Driver Supply. The BST2 pin has an integrated bootstrap diode from the INTVCC pin and requires an external bootstrap capacitor to the SW2 pin. EN/UVLO: Enable and Undervoltage Lockout. Force the pin below 0.3V to shut down the part and force the pin above 1.23V for normal operation. The 1.22V falling threshold and 2.5μA pull-down current can be used to program VIN UVLO with hysteresis. If neither function is used, tie this pin directly to VIN. FB: Voltage Loop Feedback Input. The FB pin is used for output voltage regulation and output fault protection. GND (Exposed Pad) : Ground. Solder the exposed pad directly to the ground plane. INTVCC: Internal 5V Linear Regulator Output. The INTVCC linear regulator is supplied from the V IN pin and pow - ers the internal control circuitry and gate drivers. Locally bypass this pin to ground with a minimum 4.7µF ceramic capacitor . LSN: Negative Terminal of the Buck Side Inductor Current Sense Resistor . Ensure accurate current sense with Kelvin connection. LSP: Positive Terminal of the Buck Side Inductor Current Sense Resistor . Ensure accurate current sense with Kelvin connection. PGOOD: Power Good Open Drain Output. The PGOOD pin is pulled low when the FB pin is within ±10% of its regu- lation voltage. To function, the pin requires an external pull-up resistor . RT: Switching Frequency Setting. Connect a resistor from this pin to ground to set the internal oscillator frequency. SS: Soft-Start Timer Setting. The SS pin is used to set soft-start timer by connecting a capacitor to ground. An internal 12.5μA pull-up current charging the external SS capacitor gradually ramps up FB regulation voltage. SW1: Buck Side Switch Node. SW2: Boost Side Switch Node. SYNC/SPRD: External Clock Frequency Synchronization or Spread Spectrum. Ground this pin for switching at internal oscillator frequency. Apply a clock signal for external frequency synchronization. Tie to INTV CC for spread spectrum frequency modulation. TEST: Factory Test. This pin is for factory testing purpose only and must be directly connected to ground for proper operation. TG1: Buck Side Top Gate Drive. Drives the gate of buck side top N-Channel MOSFET with a voltage swing from SW1 to BST1. TG2: Boost Side Top Gate Drive. Drives the gate of boost side top N-Channel MOSFET with a voltage swing from SW2 to BST2. VC: Error Amplifier Output. The VC pin is used to com - pensate the control loop with an external RC network. VIN: Input Supply. The VIN pin must be tied to the power input to determine its operation regions. Locally bypass this pin to ground with a minimum 0.1μF ceramic capacitor . VOUT: Output Pin. The V OUT pin must be tied to the power output to determine its operation regions. Locally bypass this pin to ground with a minimum 0.1μF ceramic capacitor . VOUTEN: Output Enable. The VOUTEN pin is used to enable buck-boost switching and deliver output power . VREF: Voltage Reference Output. The VREF pin provides an accurate 2V reference capable of supplying 1mA current. Locally bypass this pin to ground with a 0.47μF ceramic capacitor .

Rev. AFor more information www.analog.com OPERATION Main Control Loop The LT8253/LT8253A are fixed frequency current mode controllers. The inductor current is sensed through the inductor sense resistor between the LSP and LSN pins. The current sense voltage is gained up by amplifier A1 and added to a slope compensation ramp signal from the internal oscillator . The summing signal is then fed into the positive terminals of the buck current comparator A3 and boost current comparator A4. The negative terminals of A3 and A4 are controlled by the voltage on the V C pin, which is the output of error amplifier EA1. Depending on the state of the peak-buck peak-boost cur- rent mode control, either the buck logic or the boost logic is controlling the four power switches so that the FB volt- age is regulated to 1V. Light Load Current Operation At light load, the LT8253/LT8253A typically run at discon- tinuous conduction mode, to maintain the regulation and improve the efficiency. Shutdown and Power-On-Reset The LT8253/LT8253A enter shutdown mode and drain less than 2µA quiescent current when the EN/UVLO pin is below its shutdown threshold ( 0.3V minimum). Once the EN/UVLO pin is above its shutdown threshold ( 1V maximum), the LT8253/LT8253A wake up startup cir - cuitry, generate bandgap reference, and power up the internal INTVCC LDO. The INTVCC LDO supplies the inter- nal control circuitry and gate drivers. Then the LT8253/ LT8253A enter undervoltage lockout (UVLO) mode with a hysteresis current ( 2.5µA typical) pulled into the EN/ UVLO pin. When the INTVCC pin is charged above its ris- ing UVLO threshold ( 3.78V typical), the EN/UVLO pin passes its rising enable threshold ( 1.233V typical), and the junction temperature is less than its thermal shutdown (165°C typical), the LT8253/LT8253A enter enable mode, in which the EN/UVLO hysteresis current is turned off and the voltage reference VREF is being charged up from ground. From the time of entering enable mode to the time of VREF passing its rising UVLO threshold (1.89V typical), the LT8253/LT8253A are going through a power-on-reset (POR), waking up the entire internal control circuitry and settling to the right initial conditions. After the POR, the LT8253/LT8253A start switching.

mize the total solution size. the switching noise out of a sensitive frequency band. LT8253 and LT8253A, respectively. Table 1. LT8253 Switching Frequency vs RT Value (1% Resistor) Table 2. LT8253A Switching Frequency vs RT Value (1% frequency 25% above the internal oscillator frequency. chronized to an external clock using the SYNC/SPRD pin.

Rev. A For more information www.analog.com APPLICATIONS INFORMATION Slope compensation provides stability in constant fre - quency current mode control by preventing subharmonic oscillations at certain duty cycles. The minimum induc - tance required for stability when duty cycles are larger than 50% can be calculated as: L >10 • VOUT •RSENSE f For high efficiency, choose an inductor with low core loss, such as ferrite. Also, the inductor should have low DC resistance to reduce the I2R losses, and must be able to handle the peak inductor current without saturating. To minimize radiated noise, use a shielded inductor . RSENSE Selection and Maximum Output Current RSENSE is chosen based on the required output current. The duty cycle independent maximum current sense thresholds (50mV in peak-buck and 50mV in peak-boost) set the maximum inductor peak current in buck region, buck-boost region, and boost region. In boost region, the lowest maximum average load cur - rent happens at VIN(MIN) and can be calculated as: IOUT(MAX _BOOST) = 50mV RSENSE ΔIL(BOOST) ⎠⎟ • VIN(MIN) VOUT where ∆IL(BOOST) is peak-to-peak inductor ripple current in boost region and can be calculated as: ΔIL(BOOST) = VIN(MIN) • VOUT −VIN(MIN)( ) f •L •VOUT In buck region, the lowest maximum average load current happens at VIN(MAX) and can be calculated as: IOUT(MAX _BUCK) = 50mV RSENSE ΔIL(BUCK) where ∆IL(BUCK) is peak-to-peak inductor ripple current in buck region and can be calculated as: ΔIL(BUCK) = VOUT • VIN(MAX) −VOUT( ) f •L •VIN(MAX) The maximum current sense RSENSE in boost region is: RSENSE(BOOST) = 2 •50mV •VIN(MIN) 2 •IOUT(MAX) •VOUT + ΔIL(BOOST) •VIN(MIN) The maximum current sense RSENSE in buck region is RSENSE(BUCK) = 2 •50mV 2 •IOUT(MAX) + ΔIL(BUCK) The final RSENSE value should be lower than the calculated RSENSE in both buck and boost regions. A 20% to 30% margin is usually recommended. Always choose a low ESL current sense resistor . Power MOSFET Selection The LT8253/LT8253A require four external N-channel power MOSFETs, two for the top switches (switches A and D shown in Figure 1) and two for the bottom switches (switches B and C shown in Figure 1). Important param- eters for the power MOSFETs are the breakdown volt - age VBR(DSS), threshold voltage V GS(TH), on-resistance RDS(ON), reverse transfer capacitance CRSS and maximum current IDS(MAX). To achieve 2MHz operation, the power MOSFET selec - tion is critical. With typical 25ns shoot-through protection deadtime, high performance power MOSFETs with low Qg and low RDS(ON) must be used. Since the gate drive voltage is set by the 5V INTVCC supply, logic-level threshold MOSFETs must be used in LT8253/ LT8253A applications. Switching four MOSFETs at higher frequency like 2MHz, the substantial gate charge current from INTVCC can be estimated as: IINTVCC =f • QgA +QgB +QgC +QgD( ) where: f is the switching frequency Q gA, Q gB, Q gC, Q gD are the total gate charges of MOSFETs A, B, C, D Make sure the total required INTV CC current does not exceed the INTVCC current limit in the datasheet. Typically, MOSFETs with less than 10nC Qg are recommended.

included in the calculation above.

• ρT •RDS(ON) where ρT is a normalization factor (unity at 25°C) ac- counting for the significant variation in on-resistance with temperature, typically 0.4%/°C as shown in Figure 7. For a maximum junction temperature of 125°C, using a value of ρT = 1.5 is reasonable. Switch B operates in buck region as the synchronous rectifier . Its power dissipation at maximum output cur- rent is given by: PB(BUCK) = VIN −VOUT VIN
• IOUT(MAX) 2 •ρT •RDS(ON) Switch C operates in boost region as the control switch. Its power dissipation at maximum current is given by: PC(BOOST) = VOUT −VIN( ) •VOUT VIN 2 •IOUT(MAX) 2 •ρT
• RDS(ON) + k •VOUT 3 • IOUT(MAX) VIN
• CRSS •f JUNCTION TEMPERATURE (°C) –50 ρT NORMALIZED ON-RESISTANCE (/uni03A9) 1.0 1.5 150 8253A F07 0.5 0 50 100 2.0

Figure 7. Normalized RDS(ON) vs Temperature the gate drive current and has an empirical value of 1.7.

• IOUT(MAX) 2 •ρT •RDS(ON) For the same output voltage and current, switch A has the highest power dissipation and switch B has the lowest power dissipation unless a short occurs at the output. From a known power dissipated in the power MOSFET , its junction temperature can be obtained using the following formula: T J = TA + P • RTH(JA) The junction-to-ambient thermal resistance R TH(JA) includes the junction-to-case thermal resistance R TH(JC) and the case-to-ambient thermal resistance RTH(CA). This value of TJ can then be compared to the original, assumed value used in the iterative calculation process.

Rev. A For more information www.analog.com APPLICATIONS INFORMATION CIN and COUT Selection Input and output capacitance is necessary to suppress voltage ripple caused by discontinuous current moving in and out the regulator . A parallel combination of capaci- tors is typically used to achieve high capacitance and low equivalent series resistance (ESR). Dry tantalum, special polymer , aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Capacitors with low ESR and high ripple current ratings, such as OS-CON and POSCAP are also available. Ceramic capacitors should be placed near the regulator input and output to suppress high frequency switching spikes. Ceramic capacitors, of at least 1µF, should also be placed from V IN to GND and V OUT to GND as close to the LT8253/LT8253A pins as possible. Due to their excellent low ESR characteristics, ceramic capacitors can significantly reduce input ripple voltage and help reduce power loss in the higher ESR bulk capacitors. X5R or X7R dielectrics are preferred, as these materials retain their capacitance over wide voltage and temperature ranges. Many ceramic capacitors, particularly 0805 or 0603 case sizes, have greatly reduced capacitance at the desired operating voltage. Input Capacitance C IN: Discontinuous input current is highest in the buck region due to the switch A toggling on and off. Make sure that the CIN capacitor network has low enough ESR and is sized to handle the maximum RMS current. In buck region, the input RMS current is given by: IRMS ≈IOUT(MAX) •VOUT VIN

• VIN VOUT The formula has a maximum at VIN = 2VOUT, where IRMS = IOUT(MAX)/2. This simple worst-case condition is com- monly used for design because even significant deviations do not offer much relief. Output Capacitance C OUT: Discontinuous current shifts from the input to the output in the boost region. Make sure that the COUT capacitor network is capable of reducing the output voltage ripple. The effects of ESR and the bulk capacitance must be considered when choosing the right capacitor for a given output ripple voltage. The maximum steady state ripple due to charging and discharging the bulk capacitance is given by: ΔVCAP(BOOST) = IOUT(MAX) • VOUT −VIN(MIN)( ) COUT •VOUT •f ΔVCAP(BUCK) = VOUT • 1− VOUT VIN(MAX) 8 •L •f2 •COUT The maximum steady ripple due to the voltage drop across the ESR is given by: ΔVESR(BOOST) = VOUT •IOUT(MAX) VIN(MIN)
• ESR ΔVESR(BUCK) = VOUT • 1− VOUT VIN(MAX) L •f •ESR INTVCC Regulator An internal P-channel low dropout regulator produces 5V at the INTVCC pin from the VIN supply pin. The INTVCC powers internal circuitry and gate drivers in the LT8253/ LT8253A. The INTV CC regulator must be bypassed to ground with a minimum of 4.7µF ceramic capacitor . Good local bypass is necessary to supply the high transient current required by MOSFET gate drivers. Higher input voltage applications with large MOSFETs being driven at higher switching frequencies may cause the maximum junction temperature rating for the LT8253/ LT8253A to be exceeded. The system supply current is normally dominated by the gate charge current. Additional external loading of the INTVCC also needs to be taken into account for the power dissipation calculation. The total LT8253/LT8253A power dissipation in this case is V IN • IINTVCC, and overall efficiency is lowered. The junction temperature can be estimated by using the equation: T J = TA + PD • θJA where θJA (in °C/W) is the package thermal resistance.

Rev. A For more information www.analog.com APPLICATIONS INFORMATION Soft-Start and Short-Circuit Protection As shown in Figure 6 and explained in the Operation sec- tion, the SS pin can be used to program the output volt- age soft-start by connecting an external capacitor from the SS pin to ground. The internal 12.5µA pull-up current charges up the capacitor , creating a voltage ramp on the SS pin. As the SS pin voltage rises linearly from 0.25V to 1V (and beyond), the output voltage rises smoothly into its final voltage regulation. The soft-start time can be calculated as: tSS =1V • CSS 12.5µA Make sure the CSS is at least five to ten times larger than the compensation capacitor on the VC pin for a well-con- trolled output voltage soft-start. The SS pin is also used as a fault timer . Once an output short-circuit fault is detected, a 1.25µA pull-down current source is activated. Using a single resistor from the SS pin to the V REF pin, the LT8253/LT8253A can be set to three different fault protection modes : hiccup (no resis- tor), latch-off (499k), and keep-running (100k). With a 100k resistor in keep-running mode, the LT8253/ LT8253A continue switching normally and regulates the current into ground. With a 499k resistor in latch-off mode, the LT8253/LT8253A stop switching until the EN/ UVLO pin is pulled low and high to restart. With no resis- tor in hiccup mode, the LT8253/LT8253A enter low duty cycle auto-retry operation. The 1.25µA pull-down current discharges the SS pin to 0.2V and then 12.5µA pull-up current charges the SS pin up. If the output short-circuit condition has not been removed when the SS pin reaches 1.75V, the 1.25µA pull-down current turns on again, ini- tiating a new hiccup cycle. This will continue until the fault is removed. Once the output short-circuit condition is removed, the output will have a smooth short-circuit recovery due to soft-start. Loop Compensation The LT8253/LT8253A use an internal transconductance error amplifier , the output of which, VC, compensates the control loop. The external inductor , output capacitor , and the compensation resistor and capacitor determine the loop stability. The inductor and output capacitor are chosen based on performance, size and cost. The compensation resistor and capacitor on the V C pin are set to optimize control loop response and stability. Efficiency Considerations The power efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Although all dissipative elements in circuits produce losses, four main sources account for most of the losses in LT8253/ LT8253A circuits: 1. DC I2R losses. These arise from the resistances of the MOSFETs, sensing resistor , inductor and PC board traces and cause the efficiency to drop at high output currents. 2. T ransition loss. This loss arises from the brief amount of time switch A or switch C spends in the saturated region during switch node transitions. It depends upon the input voltage, load current, driver strength and MOSFET capacitance, among other factors. 3. INTV CC current. This is the sum of the MOSFET driver and control currents. 4. C IN and COUT loss. The input capacitor has the diffi - cult job of filtering the large RMS input current to the regulator in buck region. The output capacitor has the difficult job of filtering the large RMS output current in boost region. Both CIN and COUT are required to have low ESR to minimize the AC I 2R loss and sufficient capacitance to prevent the RMS current from causing additional upstream losses in fuses or batteries.

Rev. AFor more information www.analog.com APPLICATIONS INFORMATION 5. Other losses. Schottky diode DB and DD are respon- sible for conduction losses during dead time and light load conduction periods. Inductor core loss occurs predominately at light loads. Switch A causes reverse recovery current loss in buck region, and switch C causes reverse recovery current loss in boost region. When making adjustments to improve efficiency, the input current is the best indicator of changes in effi- ciency. If you make a change and the input current decreases, then the efficiency has increased. If there is no change in the input current, then there is no change in efficiency. PC Board Layout Checklist The basic PC board layout requires a dedicated ground plane layer . Also, for high current, a multilayer board pro- vides heat sinking for power components. n The ground plane layer should not have any traces and it should be as close as possible to the layer with power MOSFETs. n Place CIN, switch A, switch B and DB in one compact area. Place COUT, switch C, switch D and D D in one compact area. n Use immediate vias to connect the components to the ground plane. Use several large vias for each power component. n Use planes for VIN and VOUT to maintain good voltage filtering and to keep power losses low. n Flood all unused areas on all layers with copper . Flooding with copper will reduce the temperature rise of power components. Connect the copper areas to any DC net (VIN or GND). n Separate the signal and power grounds. All small- signal components should return to the exposed GND pad from the bottom, which is then tied to the power GND close to the sources of switch B and switch C. n Place switch A and switch C as close to the controller as possible, keeping the PGND, BG and SW traces short. n Keep the high dV/dT SW1, SW2, BST1, BST2, T G1 and T G2 nodes away from sensitive small-signal nodes. n The path formed by switch A, switch B, D B and the CIN capacitor should have short leads and PCB trace lengths. The path formed by switch C, switch D, D D and the COUT capacitor also should have short leads and PCB trace lengths. n The output capacitor ( –) terminals should be con - nected as close as possible to the (–) terminals of the input capacitor . n Connect the top driver bootstrap capacitor C BST1 closely to the BST1 and SW1 pins. Connect the top driver bootstrap capacitor CBST2 closely to the BST2 and SW2 pins. n Connect the input capacitors CIN and output capaci- tors C OUT closely to the power MOSFETs. These capacitors carry the MOSFET AC current. n Route LSP and LSN traces together with minimum PCB trace spacing. Avoid sense lines pass through noisy areas, such as switch nodes. The filter capacitor between LSP and LSN should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the R SENSE resistor . Low ESL sense resistor is recommended. n Connect the V C pin compensation network close to the IC, between VC and the signal ground. The capaci- tor helps to filter the effects of PCB noise and output voltage ripple voltage from the compensation loop. n Connect the INTVCC bypass capacitor , CINTVCC, close to the IC, between the INTVCC and the power ground. This capacitor carries the MOSFET drivers ’ current peaks.

Rev. A For more information www.analog.com PACKAGE DESCRIPTION 4.00 ±0.10 (2 SIDES)

2.50 REF

5.00 ±0.10 (2 SIDES) NOTE: 1. DRAWING NOT TO SCALE 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT , SHALL NOT EXCEED 0.15mm ON ANY SIDE 4. SHADED AREA IS ONL Y A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (NOTE 6) 0.40 ±0.10 27 28 BOTTOM VIEW—EXPOSED PAD

3.50 REF

0.75 ±0.05 R = 0.115 TYP R = 0.05 TYP PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER 0.25 ±0.05

0.50 BSC

0.200 REF

0.00 – 0.05 (UFDM28) QFN 1218 REV Ø RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPL Y SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 0.25 ±0.05 4.10 ±0.05 5.50 ±0.05 2.65 ±0.05 3.10 ±0.05 4.50 ±0.05 PACKAGE OUTLINE 2.65 ±0.10 3.65 ±0.10 3.65 ±0.05 28-Lead Plastic Side Wettable QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1682 Rev Ø)

0.203 REF

0.40 ± 0.10

0.05 REF

0.10 REF

Rev. AFor more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 11/22 Added AEC-Q100 Qualified. Added Revision History Page.

Rev. A For more information www.analog.com  ANALOG DEVICES, INC. 2020-2022 www.analog.com TYPICAL APPLICATION 1.5µH 0.1µF 0.1µF 200k 59.0k 22nF 5m/uni03A9 RS1 0.47µF 100k VIN VOUT EN/UVLO FB SSFM ON NO SSFM/SYNC SYNC D1-D2: NEXPERIA BAT46WJ D3: DIODES INC BZT52C12TQ-7-F D4-D5: NEXPERIA PMEG2010AEB FBIN: 2× MURATA BLM31KN471SZ1L FBOUT : 2× TDK MPZ2012S102ATD25 L1: COILCRAFT XEL5030-152ME M1-M4: INFINEON IPZ40N04S5L-7R4 M5: DIODES INC DMP3010LPSQ RS1: SUSUMU KRL3216D-M-R005 RS2: SUSUMU KRL2012 L T8253A SW2 SW1 INTVCC PGOOD SYNC/SPRD VC RT SS f = 2MHz LSP LSN BST1 BST INTVCC INTVCC BG1 TG1 BG2 TG2 1µF 50V 1µF 25V VREF VOUTEN TEST GND 10µF 50V 10µF 25V VIN 47µF 50V 4.7µF 36k 1nF 200k 50k 100µF 25V 4.7µF 25V VBUS CC1 CC2 GND D+2 D-1 D+1 D-2 USB TYPE-C P1.0 P0.0 P0.1 P2.1 P_CTRL C_CTRL DP1 DM1 C_MON CC1 CC2 DP0 DM0 GND VCCD VDDD COMP FB CSP VBUS_IN CYPD3196 VTARG GND NC SCLK SDAT 221k 10k PVIN 59k 0.1µF 470/uni03A9 10nF RS2 5m/uni03A9 6.04k DP0 390pF 390pF SHEILD 100k 2.2nF 2kV PVIN 1µF 0.1µF 1µF 0.1µF 1µF 0.1µF VOUTEN VOUTEN EXT SYNC 2/uni03A9 5.1/uni03A9 10µF 0.1µF FBIN 10µF 0.1µF FBOUT 2/uni03A9 5.1/uni03A9 100k 10nF 10k INTVCC NTC 100k 10nF 10k INTVCC NTC 50V 8253A TA02 Automotive 45W USB-C Power Delivery Charger (2MHz)