LT8210

LT8210-1 AD | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 59

Technical content

analog.com Rev. A 2 of 59

REVISION HISTORY

Revision Number Revision Date Nature of Change Page Number Rev 0 02/2024 Initial Release — Rev A 04/2024 Updated Figure 57 and Figure 79 33, 56

analog.com Rev. A 3 of 59 TABLE OF CONTENTS

analog.com Rev. A 4 of 59

Table 1. Electrical Characteristics

analog.com Rev. A 6 of 59 (Specifications are at TA = 25°C. VIN = 12V, VINP = 12V, VEN/UVLO = 3.3V, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS GATEVCC Load Regulation IGATEVCC = 0mA to 50mA GATEVCC Regulator Dropout Voltage VGATE_VCC_DO VINP – VGATEVCC: IGATEVCC = 50mA -40°C ≤ TJ ≤ 125°C 750 1600 mV VEXTVCC – VGATEVCC: IGATEVCC = 50mA -40°C ≤ TJ ≤ 125°C 600 1400 GATEVCC Undervoltage Lockout Threshold VUVLO_TH Falling -40°C ≤ TJ ≤ 125°C 3.61 3.75 3.85 V GATEVCC Undervoltage Lockout Hysteresis VUVLO_HYST 0.20 V GATEVCC Backdrive Current IBK_DRV To VINP Pin, VGATEVCC = 10V, VINP = 0V 40 µA To EXTVCC Pin, VGATEVCC = 10V, VEXTVCC = EXTVCC Switchover Voltage VSW_OV_EXTVCC Rising -40°C ≤ TJ ≤ 125°C 7.3 8 8.8 V EXTVCC Switchover Hysteresis 1.2 V VDD Voltage VDD 3.15 3.3 3.4 V VDD Current Limit IVDD_LIM VDD = 3V 9 mA VDD Undervoltage Lockout Threshold VUVLO_TH_VDD Falling 2.7 2.8 2.9 V VDD Undervoltage Lockout Hysteresis 140 mV Enable Comparator EN/UVLO Enable Threshold VEN_TH Rising -40°C ≤ TJ ≤ 125°C 1.27 1.45 1.61 V EN/UVLO Enable Hysteresis VEN_HYST 100 mV EN/UVLO Pin Bias Current IEN_BIAS VEN/UVLO = 100V -40°C ≤ TJ ≤ 125°C 0.1 1 µA Reverse Input Protection

analog.com Rev. A 7 of 59 (Specifications are at TA = 25°C. VIN = 12V, VINP = 12V, VEN/UVLO = 3.3V, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS DG Gate Drive Voltage (VDG – VIN) VDG_DRIVE Non-Switching -40°C ≤ TJ ≤ 125°C 7.0 8.5 V Reverse Input Disconnect Threshold (VIN) VREV_DIS_TH IDG = 100µA -40°C ≤ TJ ≤ 125°C –1.8 –1.2 –0.5 V DG Pin Pull-Down Current IDB_PULL_DN VIN = –4V, VDG – VIN = 5V -40°C ≤ TJ ≤ 125°C 50 80 130 mA DG Pin Pull-Up Current IDG_PULL_UP VDG – VIN = 1.5V -40°C ≤ TJ ≤ 125°C 100 180 µA VDG – VIN = 8.5V -40°C ≤ TJ ≤ 125°C 4 25 DG Undervoltage Threshold (VDG – VIN) VDG_UV_TH Rising -40°C ≤ TJ ≤ 125°C 2.3 2.8 3 V DG Undervoltage Hysteresis (VDG – VIN) VDG_UV_HYST 700 mV Voltage Regulation FB1 Regulation Voltage VFB1 Regulation Voltage for CCM, DCM Operation, Pass-Thru Mode Boost Loop -40°C ≤ TJ ≤ 125°C 0.982 1.00 1.016 V FB2 Regulation Voltage VFB2 Regulation Voltage Pass- Thru Mode Buck Loop -40°C ≤ TJ ≤ 125°C 0.98 1.00 1.02 V FB1, FB2 Input Bias Current IB_FB1 IB_FB2 -40°C ≤ TJ ≤ 125°C 0.001 0.04 µA FB1, FB2 Line Regulation VINP = 3V to 100V -40°C ≤ TJ ≤ 125°C 0.001 0.008 %/V FB1, FB2 Error Amplifier Transconductance 450 µA/V

analog.com Rev. A 8 of 59 (Specifications are at TA = 25°C. VIN = 12V, VINP = 12V, VEN/UVLO = 3.3V, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS VC1, VC2 Output Impedance 5 MΩ VC1, VC2 Maximum Sourcing Current IVC1_SOURCE IVC2_SOURCE VFB1 = VFB2 = 0V 35 µA VC1, VC2 Maximum Sinking Current IVC1_SINK IVC2_SINK VFB1 = VFB2 = 2V –35 µA Soft-Start Charging Current ISS VSS = 0.5V -40°C ≤ TJ ≤ 125°C 3.5 5 6 µA Soft-Start Pull-Down Resistance RSS_PD 140 250 Ω Average Current Monitoring / Sharing / Limiting SNSP2, SNSN2 Operating Voltage Range VSNSP2_OPR VSNSN2_OPR -40°C ≤ TJ ≤ 125°C 0 100 V SNSP2, SNSN2 Pin Bias Current IB_SNSP2 VSNSP2 = VSNSN2 = 100V 1 3 µA IB_SNSN2 VSNSP2 = VSNSN2 = 0V –3 0 IMON Output Current IMON VSNSP2 – VSNSN2 = 150mV -40°C ≤ TJ ≤ 125°C 84 90 95 µA VSNSP2 – VSNSN2 = 50mV -40°C ≤ TJ ≤ 125°C 27 30 33 VSNSP2 – VSNSN2 = 10mV -40°C ≤ TJ ≤ 125°C 4 6 8 Current Sharing Mismatch (VSNSP2 – VSNSN2) VSNSP2 – VSNSN2 = 50mV, RIMON = 11kΩ 5 mV IMON DC CMRR VSNSP2 – VSNSN2 = 150mV, VSNSP2 = 3V to 100V 110 dB IMON Step Response Time Step VSNSP2 – VSNSN2 from 0mV to 150mV 2 ms

analog.com Rev. A 9 of 59 (Specifications are at TA = 25°C. VIN = 12V, VINP = 12V, VEN/UVLO = 3.3V, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS Overcurrent Warning Threshold (VIMON) VIMON Rising -40°C ≤ TJ ≤ 125°C 1.15 1.2 1.24 V Overcurrent Warning Hysteresis VHYST_OC 45 mV IMON Disable Threshold (VIMON) VIMON_TH Rising -40°C ≤ TJ ≤ 125°C 2.3 2.5 2.8 V IMON Disable Hysteresis VHYST_IMON 400 mV Cycle-by-Cycle Inductor Current Limiting Maximum Current Sense Threshold (VSNSP1 – VSNSN1) VSNS_TH Buck Regulation (VINP = 24V, VOUT = 0V) -40°C ≤ TJ ≤ 125°C 45 53 61 mV Maximum Current Sense Threshold (VSNSP1 – VSNSN1) VSNS_TH Buck Regulation (VINP = 24V, VOUT = 12V) -40°C ≤ TJ ≤ 125°C 55 62 70 mV Boost Regulation (VINP = 6V, VOUT = 12V) -40°C ≤ TJ ≤ 125°C 45 51 58 Buck Regulation (VINP = 100V, VOUT = 48V) -40°C ≤ TJ ≤ 125°C 73 85 101 Boost Regulation (VINP = 24V, VOUT = 48V) -40°C ≤ TJ ≤ 125°C 36 45 54 Maximum Non- Switching Current Sense Threshold in Pass-Thru (VSNSP1 – VSNSN1) VSNS_TH_PT VOUT = VINP, FB1 = 1.2V, FB2 = 0.8V MODE1 = MODE2 = 3.3V -40°C ≤ TJ ≤ 125°C 57 63 70 mV Reverse Current Sense Threshold (VSNSP1 – VSNSN1) VSNS_REV_TH DCM/Pass-Thru Modes 3 mV Pass-Thru Buck-Boost Regions –6

analog.com Rev. A 10 of 59 (Specifications are at TA = 25°C. VIN = 12V, VINP = 12V, VEN/UVLO = 3.3V, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS Negative Current Sense Threshold (VSNSP1 – VSNSN1) VSNS_NEG CCM Operating Mode (MODE1 = MODE2 = 0V) –55 mV MOSFET Gate Drivers TG1, TG2 Gate Driver Pull-Up Resistance RTG_PU 3 Ω TG1, TG2 Gate Driver Pull-Down Resistance RTG_PD 1 Ω BG1, BG2 Gate Driver Pull-Up Resistance RBG_PU 2.6 Ω BG1, BG2 Gate Driver Pull-Down Resistance RBG_PD 1 Ω TG1, TG2 Rise Time TTG_RISE CLOAD = 3300pF (10% to 90%) 30 ns TG1, TG2 Fall Time TTG_FALL CLOAD = 3300pF (10% to 90%) 20 ns BG1, BG2 Rise Time TBG_RISE CLOAD = 3300pF (10% to 90%) 20 ns BG1, BG2 Fall Time TBG_FALL CLOAD = 3300pF (10% to 90%) 25 ns TG Off to BG On-Delay TTGBG_DEL CLOAD = 3300pF 60 ns BG Off to TG On-Delay TBGTG_DEL CLOAD = 3300pF 60 ns Minimum TG1 On- Time TTG1_ON CLOAD = 3300pF 200 ns Minimum BG2 On- Time TBG2_ON CLOAD = 3300pF 100 ns BST1, BST2 Bias Current IB_BST1 Top Gate High, VBST – VSW = 10V 6 µA IB_BST2 Top Gate High, VBST – VSW = 10V, PassThru Mode 0.6 BST1, BST2 Charging Current IQ_BST1 Non-Switching, VBST – VSW = 8.25V 50 µA IQ_BST2 Non-Switching, VBST – VSW = 3V 610 Oscillator

analog.com Rev. A 11 of 59 (Specifications are at TA = 25°C. VIN = 12V, VINP = 12V, VEN/UVLO = 3.3V, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS Switching Frequency Range FRNG RT Set/Synchronized -40°C ≤ TJ ≤ 125°C 80 400 kHz Switching Frequency FSW RT = 110k -40°C ≤ TJ ≤ 125°C 91 100 108 kHz RT = 39.2k -40°C ≤ TJ ≤ 125°C 190 200 210 RT = 16.9k -40°C ≤ TJ ≤ 125°C 380 400 420 SYNC/SPRD Input Low Level VSYNC_LL -40°C ≤ TJ ≤ 125°C 0.8 V SYNC/SPRD Input High Level VSYNC_HL -40°C ≤ TJ ≤ 125°C 1.17 V Spread-Spectrum Max Frequency (% of fSW) VSYNC/SPRD = 3.3V 112.5 % Spread-Spectrum Min Frequency (% of fSW) VSYNC/SPRD = 3.3V 100 % Logic Inputs/Outputs MODE1, 2 Input Low Level VLL_MODE1 VLL_MODE2 -40°C ≤ TJ ≤ 125°C 0.8 V MODE1, 2 Input High Level VHL_MODE1 VHL_MODE2 -40°C ≤ TJ ≤ 125°C 1.17 V MODE1, 2 Leakage Current IL_MODE1, 2 VMODE1,2 = 6 V 0.01 1 μA PWGD Output Low Voltage VPWGD_LV IPWGD = 1mA -40°C ≤ TJ ≤ 125°C 0.07 0.2 V PWGD Trip Level VFB1 Falling -40°C ≤ TJ ≤ 125°C –13 –10 –8 % VFB2 Rising -40°C ≤ TJ ≤ 125°C 7.5 10 12 % PWGD Anti-Glitch Delay VPWGD Rising or Falling -40°C ≤ TJ ≤ 125°C 2 10 20 µs PWGD Leakage Current ILEAK_PWGD VPWGD = 40V 0.01 1 μA

TA = 25°C (6), unless otherwise specified. Table 2. Absolute Maximum Ratings 1 The LT8210A-1 is guaranteed to meet performance specifications from -40°C to 125°C junction temperature. otherwise permanent damage may occur. temperature range may impair the device reliability. these negative voltages in excess of one diode drop below ground, guaranteed by design. 5 Do not force voltage on the VC1, VC2, or SS pin.

6 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. operating conditions for extended periods may affect product reliability. Figure 3. Pin Diagram

Table 3. Pin Descriptions otherwise, connect to ground. state when the part is disabled. 400kHz. See Table 2 in Applications Information section. MODE2, and SYNC/SPRD pins logic high. inductor current at start-up via internal clamping of the VC1 and VC2 voltages. while switching is disabled. to local ground voltage variation. increases with this control voltage. Error Amplifier Feedback Input for CCM and DCM Operation Modes. the feedback voltage from an external resistive divider across the output.

analog.com Rev. A 15 of 59 PIN NAME DESCRIPTION Pin 13 VOUT Output Voltage Sense. This pin must have a Kelvin connection to the drain of switch D. Use a small RC low-pass filter (e.g., 50Ω and 22nF) for improved jitter performance when VOUT ripple is large. Pins 15, 16 SNSN2, SNSP2 Positive (+) and Negative (–) Inputs for the Average Current Sense Monitor. SNSP2, SNSN2 should connect to the positive and negative terminals of a sense resistor placed in series with the input, output or load. A filter network with a time constant of roughly 1µs should be placed between the sense resistor and the part to filter switching noise. Pin 18 TG2 Top Gate Drive for Boost Regulator. Drives the top N-channel MOSFET with a voltage swing equal to GATEVCC superimposed onto the SW2 node voltage. When operating in the buck region or within the pass-thru window, TG2 is held roughly at VOUT + GATEVCC. Pin 19 SW2 Boost Regulator Switch Node. The (–) terminal of the bootstrap capacitor connects here. Pin 20 BST2 Boosted Floating Driver Supply for Boost Regulator. The (+) terminal of the bootstrap capacitor connects here. The BST2 pin swings from roughly GATEVCC to VOUT + GATEVCC when the boost regulation loop is switching. When operating in the buck region or within the pass-thru window, this pin is held roughly at VOUT + GATEVCC. Pin 21 BG2 Bottom Gate Drive for Boost Regulator. Drives bottom N-channel MOSFET with a voltage swing between GATEVCC and PGND. Pin 22 PGND Driver Power Ground. Connect to CIN, COUT, and sources of MOSFETs, MC, and MD. Pin 23 BG1 Bottom Gate Drive for Buck Regulator. Drives bottom N-channel MOSFET with a voltage swing between GATEVCC and PGND. Pin 24 GATEVCC Power Supply for Gate Drivers. Internally regulated to 10.6V. Bypass this pin to ground with a minimum 4.7µF ceramic capacitor. Pin 25 EXTVCC External Power Supply Input for the GATEVCC Regulator. GATEVCC will be linearly regulated from EXTVCC if its voltage is higher than 8V and is simultaneously lower than VINP. May be driven with voltages up to 40V. If this feature is not used, connect this pin to ground through a 100k resistor. Pin 27 BST1 Boosted Floating Driver Supply for Buck Regulator. The (+) terminal of the bootstrap capacitor connects here. The BST1 pin swings from roughly GATEVCC to VIN + GATEVCC when the buck regulation loop is switching. When operating in the boost region or within the pass-thru window, this pin is held roughly at VIN + GATEVCC. Pin 28 SW1 Buck Regulator Switch Node. The (–) terminal of the bootstrap capacitor connects here. Pin 29 TG1 Top Gate Drive for Buck Regulator. Drives the top N-channel MOSFET with a voltage swing equal to GATEVCC superimposed onto the SW1 node voltage.

analog.com Rev. A 16 of 59 PIN NAME DESCRIPTION When operating in the boost region or within the pass-thru window, TG1 pin is held roughly at VIN + GATEVCC continuously. Pin 30, 31 SNSN1, SNSP1 Positive (+) and Negative (–) Inputs for the Inductor Current Sense Amplifier. Place an appropriately valued shunt resistor in series with the inductor on the SW1 side and connect to SNSP1 and SNSN1. The SNSP1 – SNSN1 voltage is used for current mode control and reverse current detection. Pin 33 VINP Protected Main Input Supply. This pin must connect to the drain terminal of switch A. Use a small RC low-pass filter (e.g., 1Ω and 1µF) for improved jitter performance. When reverse input protection is implemented, connect this pin to the drain of the DG MOSFET; otherwise, connect to VIN. Pin 34 DG Reverse Input Protection Gate Drive Output. When VIN is pulled below –1.2V, this pin is clamped internally to VIN with a low resistance switch, forcing an external MOSFET between the VIN and VINP pins into cutoff. In normal operation, this pin is charged to roughly VIN + GATEVCC with an internal charge pump to fully enhance the external MOSFET. DG can tolerate negative voltages down to –40V. Pin 35 VIN Input Voltage Pin. This pin is used for powering the start-up circuitry and the internal charge pump. VIN can withstand negative voltages down to –40V without damaging the regulator or drawing large currents. Pin 37 EN/UVLO Precision Enable Input. The part is enabled when this pin is pulled above 1.45V. A voltage below 1.35V causes the LT8210-1 to reside in a low-power shutdown mode. Tie to VIN for always-on operation. Connect to a resistor divider between VIN and ground to set an undervoltage lockout threshold. EN/UVLO can tolerate negative voltages up to 40V. Pin 39 MODE2 Operating Mode Selection Input #2. Used in conjunction with the MODE1 pin to select between continuous conduction switching (CCM), discontinuous switching (DCM), and pass-thru operating modes. See Table 1 in the Operation section for mode pin settings. Pin 40 MODE1 Operating Mode Selection Input #1. Used in conjunction with MODE2 pin to select between continuous conduction switching (CCM), discontinuous switching (DCM), and pass-thru operating modes. See Table 1 in the Operation section for mode pin settings. Pin 41/Exposed Pad GND Signal Ground. All small-signal components and compensation components should connect to this ground, which in turn connects to the PCB ground at one location away from high currents and switching noise. The exposed pad must be soldered to the PCB and connected to the GND pin using top layer metal.

Figure 4. Block Diagram

See Figure 4 when reading the following sections about the operation of the LT8210-1. high or to ground to set low. value programmed using the FB1 and FB2 resistor dividers, respectively. Table 4. LT8210-1 Operating Modes or reverse. The maximum recommended switching frequency for CCM operation is 350kHz. operation improves light load efficiency and also blocks significant current draw from the output back into the input. operated in CCM for full switching frequency operation.

greater than or equal to VOUT(BUCK), the buck loop will control the inductor current and regulate the output to VOUT(BUCK). Near the boundaries of the pass-thru window, interleaved buck-boost switching is used to avoid pulse-skipping. an extremely low quiescent current, it is possible to achieve efficiencies greater than 99.9% in the pass-thru region. added to prevent chattering between modes. Figure 47. Simplified Diagram of the Power Switches

Figure 48. Switching Region vs. VINP/VOUT Ratio current from falling any further. See Figure 49. or the negative current sense threshold in CCM. See Figure 50. below the reverse current sense threshold in DCM or the negative current sense threshold in CCM. See Figure 51.

Figure 51. Buck-Boost Region Switching Waveforms switches A and D will turn on continuously again after VOUT settles close to VINP.

operation or to a resistive divider between VIN and ground to program an undervoltage lockout (UVLO) threshold. Figure 54. Start-Up Sequence at 3W (typical). Figure 55 shows the typical GATEVCC current limit as a function of voltage on the VINP and EXTVCC pins.

• SWITCHER OFF
• GATEVCC, VDD LDOs OFF
• VIN, VINP, IQ < 1µA VEN/UVLO > 1.45V AND TJUNCTION < THERMAL LIMIT CHIP ON/SWITCHER OFF
• SWITCHER DISABLED
• GATEVCC AND VDD OUTPUTS ENABLED
• SS HELD LOW SWITCHER ENABLED VGATEVCC > 3.9V AND VDD > 2.9V VIN > –1.2V DG CHARGING
• CHARGE PUMP ENABLED
• DG PIN CHARGING
• SS HELD LOW
• SS PIN CHARGES
• SWITCHING BEGINS
• FORCED DISCONTINOUS MODE UNTIL SS > 2.5V VDG – VINP > 2.8V AND VINP > 2.8V 054

analog.com Rev. A 34 of 59 Multiple LT8210 -1 can share common resistor dividers for the FB1 and FB2 inputs, although routing these noise sensitive signals between phases can affect stability. Alternatively, each phase can use its own FB1 and FB2 dividers at the expense of less accurate current sharing. This can be mitigated by using 0.1% tolerance resistors for the feedback dividers. Buck Foldback The LT8210-1 actively prevents inductor current runaway while the buck loop is switching. The inductor current can run away when its rising slope exceeds the falling slope to such a degree that the current continues to increase each period even while switching at the minimum SW1 duty cycle. A buck regulator is most suscepti ble to runaway when the output voltage is near ground, causing the inductor current falling slope to be flat. This situation is exacerbated by a high input voltage and a high switching frequency. To prevent runaway, the LT8210 -1 may skip switch A pulses while VOUT is less than 10% of V INP and the FB1 voltage is lower than 900mV. At the start of the switch A on -time, the sensed inductor current must be below an internally set pulse -skipping threshold; otherwise, the next pulse on switch A will be skipped. If the inductor current exceeds the pulse -skipping threshold on the next switch A turn -on, the following three pulses will be skipped, and so on. The foldback circuit increases the number of skipped pulses with each successive switch A pulse where this thres hold is exceeded; otherwise, the skip count is reset. In addition to preventing inductor runaway, the LT8210-1 foldback scheme significantly reduces switch A power dissipation in a short circuit condition. When the output is shorted to ground, the power di ssipation in switch A is dominated by transitional losses as it turns on and off. Reducing the number of switch A pulses over a given period reduces the dissipated power proportionally. The boost loop is naturally protected from inductor current runaway in the LT8210- 1 as it can only occur when V INP ~ VOUT, which is within the buck -boost region. While the buck loop is simultaneously controlling the inductor current each cycle, it is not possible for the boost channel to run away. PWGD Pin The PWGD pin is an open drain logic output that goes high when the output voltage and IMON pin voltage are within preset limits after switching is enabled. The internal PWGD pull -down is released when V OUT is within ±10% of its programmed value. In CCM and DCM oper ations, this occurs when the FB1 voltage is within ±10% of the 1.00V reference. In pass-thru mode, PWGD will go high when VFB1 > 0.90V and VFB2 < 1.10V, indicating that the output voltage is within ±10% of the programmed output pass-thru window. PWGD will be pulled low if the voltage on the IMON pin exceeds 1.20V, indicating that the average current exceeds its programmed limit by 20% or more. The LT8210 -1 includes a built-in self-test to confirm the system reference circuitry is functioning properly. This reference voltage is used for voltage regulation, current regulation, clock generation, and fault detection. If the system reference is outside of preset tolerances, switching is disabled, and the PWGD pin is pulled low. Switching will also be disabled, and the PWGD pin will be pulled low if the V INP, GATEV CC, V DD, or DG pin voltages fall below their respective undervoltage lockout thresholds. The PWGD pin pull -up resistor can be connected to any external rail up to 40V. Using either V DD or GATEVCC as the p ull-up supply has the added advantage that PWGD will be in the correct state when the LT8210-1 is disabled. Figure 59 shows the conditions that determine the state of the PWGD pin.

Figure 59. PWGD Logic  RSENSE is selected based on the required output current and the input voltage range .  CBST1, CBST2, and CGATEVCC capacitors are selected to store adequate charge to power the gate drivers.  Type II compensation network is designed for VC1 (and VC2 if pass-thru mode is used).  CSS selected to set soft-start behavior. minimize conduction loss during regulation.  (Optional) – Current regulation and/or monitoring implemented with RSENSE2, RIMON, and CIMON.

Figure 60. Basic LT8210-1 Applications Circuit characteristics referred to in this section represent typical values unless otherwise specified. given maximum output current, IOUT(MAX) , can be calculated using Equation 1. D’BST ≅ (1-DBST) = VINP/ VOUT. Using VINP(MIN) the RSENSE for a desired IOUT(MAX) can be calculated using Equation 2.

analog.com Rev. A 38 of 59 compensation scheme is designed to provide optimal damping of the current sense loop for any input voltage when the inductor value is set to the value given by Equation 4. 𝐿𝑂𝑃𝑇𝐼𝑀𝐴𝐿 = (260 + (5.5 ∙ 𝑉𝑂𝑈𝑇)) ∙ 𝑅𝑆𝐸𝑁𝑆𝐸 ∙ 𝑓𝑆𝑊 (4) For example: 𝐿𝑂𝑃𝑇𝐼𝑀𝐴𝐿(𝑉𝑂𝑈𝑇=12𝑉) = 325 ∙ 𝑅𝑆𝐸𝑁𝑆𝐸 ∙ 𝑓𝑆𝑊 𝐿𝑂𝑃𝑇𝐼𝑀𝐴𝐿(𝑉𝑂𝑈𝑇=48) = 525 ∙ 𝑅𝑆𝐸𝑁𝑆𝐸 ∙ 𝑓𝑆𝑊 This simplifies loop compensation as the current sense loop damping becomes independent of the duty cycle and switching region. Selecting L OPTIMAL also optimizes line regulation and line step response. A lower inductance value will increase Q CS, and a sufficiently undersized inductor can result in subharmonic oscillation for buck duty cycles above 50% and boost duty cycles below 50%. Choose an inductor at le ast 70% of the calculated optimal value to avoid subharmonic instability. Inductor parasitics can significantly impact converter efficiency. For high efficiency, choose an inductor with low core loss, such as ferrite. The inductor should also have low DC r esistance (DCR) to reduce the I 2R losses. Selecting an inductor with a DCR comparable to the R DS(ON) of the power MOSFETs is a reasonable starting point. If radiated noise is a concern, a shielded inductor should be used. Ferrite cores saturate abruptly, leading to a significant increase in ripple when the saturation current rating, ISAT, is exceeded. ISAT should be greater than the worst-case peak inductor current with an added margin. The maximum peak inductor current can be approximated by Equation 5. 𝐼𝐿(𝑀𝐴𝑋) ≈ 60𝑚𝑉 𝑅𝑆𝐸𝑁𝑆𝐸 + ∆𝐼𝐿(𝑀𝐴𝑋)𝐴 (5) Assuming an inductor ripple current, ∆L L(MAX), of 40%, the peak inductor current could be 145% of the maximum output current. Adding an additional margin of 25% beyond the worst-case yields a conservative minimum inductor ISAT rating of 90mV/RSENSE, for example. Switching Frequency Selection The RT frequency adjust pin allows the user to program the switching frequency from 80kHz to 400kHz. The selection of the switching frequency is a trade-off between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses, but requires larger inductor and capacitor values. For high power applications, consider operating at lower frequencies to minimize MOSFET heating from switching losses. For low power applications, consider operating at hig her switching frequencies to minimize the total solution size. The selection of RSENSE, the inductor value, and the switching frequency are interrelated. To maintain the ripple current amplitude and subharmonic stability, the inductor value will track the product of RSENSE and the switching period, T. The RSENSE value is set by load requirements. The inductor value is determined by ripple current and subharmonic stability criteria. A practical approach is to adjust the switching frequency to optimize system performance once the RSENSE and L values have already been chosen. The component selection flow would be as follows: 1. Select RSENSE based on the required output current. 2. Select inductor value based on the desired ripple for a range of fSW (e.g., 80kHz to 120kHz). 3. Adjust the switching frequency to satisfy Equation 6.

rejection, and a flat average maximum inductor current across the duty cycle and switching region. synchronization signal is lost, the LT8210-1 will revert to the RT set value within approximately 20μs. Table 5. Switching Frequency vs. RT Value (1% Resistor) spectrum modulation; otherwise, connect to GND.

explicitly stated in the MOSFET data sheet. Figure 67. Normalized RDS(ON) vs. Temperature at either VIN(MIN) in the boost region or VIN(MAX) in the buck region. Table 6. Switch A Power Dissipation Switch B power dissipation is due mainly to conduction losses and reaches a maximum in the buck region at VIN(MAX). Table 7. Switch B Power Dissipation

Switch C power dissipation is due to both conduction and switching losses and reaches a maximum at VIN(MIN). Table 8. Switch C Power Dissipation

• f SW • QSW/VIN Boost IOUT2 • VOUT • (VOUT - VIN) • ρτ • RDS(ON)/Vin2 + k • IOUT • VOUT2
• f SW • QSW/VIN Pass-Thru (Non-Switching) 0 Switch D: Switch D power dissipation is due mainly to conduction losses and reaches a maximum in the boost region at VIN(MIN).

Table 9. Switch D Power Dissipation Figure 68. Other power loss sources include the gate drive current (f SW • ∑ switching MOSFET Q G) multiplied by the

Figure 68. Example of Switch Power Dissipation vs. VINP current is discontinuous. Selecting the proper input and output capacitors boils down to three considerations.

1. Voltage ripple is inversely proportional to capacitance.
2. ESR must be low to minimize its contribution to voltage ripple.
3. RMS current rating of the capacitor(s) should exceed the worst-case application conditions with a margin.

• ( 𝑉𝑂𝑈𝑇 𝑉𝐼𝑁 ) • (1 − 𝑉𝑂𝑈𝑇 𝑉𝐼𝑁 ) (7) ∆VIN is typically chosen at a level acceptable to the user. 100mV to 200mV is a good starting point. The ESR of the input capacitance should be less than Equation 8. 𝐸𝑆𝑅(𝐼𝑁,𝑀𝐴𝑋) < ∆𝑉𝐼𝑁 𝐼𝑂𝑈𝑇(𝑀𝐴𝑋) (8) The input RMS current can be approximated by Equation 9. 𝐼𝐼𝑁(𝑅𝑀𝑆) ≅ 𝐼𝑂𝑈𝑇(𝑀𝐴𝑋) • 𝑉𝑂𝑈𝑇 𝑉𝐼𝑁
• √ 𝑉𝐼𝑁 𝑉𝑂𝑈𝑇 − 1 (9) E9 has a maximum at VIN = 2VOUT, where IRMS = IOUT(MAX)/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. The capacitance necessary to achieve a desired output ripple, ∆VOUT, can be calculated with Equation 10 for the buck and boost switching regions. 𝐶𝑂𝑈𝑇(𝐵𝑂𝑂𝑆𝑇) = 𝐼𝑂𝑈𝑇(𝑀𝐴𝑋) • (𝑉𝑂𝑈𝑇−𝑉𝐼𝑁(𝑀𝐼𝑁)) ∆𝑉𝑂𝑈𝑇 • 𝑓𝑆𝑊 • 𝑉𝑂𝑈𝑇 (10) 𝐶𝑂𝑈𝑇(𝐵𝑈𝐶𝐾) = 𝑉𝑂𝑈𝑇 • (𝑉𝐼𝑁(𝑀𝐴𝑋) − 𝑉𝑂𝑈𝑇) ∆𝑉𝑂𝑈𝑇 • 𝑓𝑆𝑊 2 • 𝑉𝐼𝑁(𝑀𝐴𝑋) • 8 • 𝐿 MA MB MC MD TOTAL POWER LOSS INPUT VOLTAGE (V) 0 12 24 36 48 60 POWER LOSS (W) VOUT = 24V 068

analog.com Rev. A 45 of 59 The ESR of the output capacitor should be low enough to not significantly increase the ripple voltage (Equation 11). 𝐸𝑆𝑅(𝐵𝑂𝑂𝑆𝑇) < ∆𝑉𝑂𝑈𝑇 • 𝑉𝐼𝑁(𝑀𝐼𝑁) 𝐼𝑂𝑈𝑇(𝑀𝐴𝑋) • 𝑉𝑂𝑈𝑇 (11) 𝐸𝑆𝑅(𝐵𝑈𝐶𝐾) < ∆𝑉𝑂𝑈𝑇 • 𝐿 • 𝑓𝑆𝑊 𝑉𝑂𝑈𝑇 • (1 − 𝑉𝑂𝑈𝑇 𝑉𝐼𝑁(𝑀𝐴𝑋) COUT should also tolerate the maximum RMS output current when operating in the boost region (Equation 12). 𝐼𝑂𝑈𝑇(𝑅𝑀𝑆) ≅ 𝐼𝑂𝑈𝑇(𝑀𝐴𝑋) • √ 𝑉𝑂𝑈𝑇 𝑉𝐼𝑁(𝑀𝐼𝑁) − 1 (12) For both the CIN and COUT capacitors, a good approach for larger values is to use a parallel combination of aluminum electrolytics for bulk capacitance and ceramics for low ESR and to handle the RMS currents. When used together, the percentage of RMS current that will flow through the aluminum electrolytic capacitor can be approximated by Equation 13. %𝐼𝑅𝑀𝑆,𝐴𝐿𝑈𝑀 ≈ 100% √1+(2𝜋 • 𝑓𝑆𝑊 • 𝐶(𝐶𝐸𝑅) • 𝑅𝐸𝑆𝑅(𝐴𝐿𝑈𝑀))2 (13) Where RESR(ALUM) is the ESR of the aluminum capacitor and C(CER) is the total value of the ceramic capacitor(s). Ceramic capacitors should be placed nea r the regulator input and output to suppress high frequency switching spikes. Specifically, the ceramic capacitors on the input should be placed in close proximity to switches A and B, and the output ceramics should be placed close to switches C and D. Due to their excellent low ESR characteristics, ceramic capacitors can significantly reduce ripple voltage and help reduce power loss in higher ESR bulk capacitors. X5R and X7R are preferred, as these materials retain their capacitance over wide voltage and t emperature ranges. At higher input and output voltages, multiple ceramic capacitors in parallel may be needed due to the limited availability of high voltage, large value ceramic capacitors in standard footprints. In situations with high input and/or outpu t voltage ripple, an RC low-pass filter with a time constant of 1μs or greater is recommended for VINP and VOUT inputs to maintain low jitter on switching edges. Bootstrap Capacitors (CBST1 and CBST2) The top MOSFET gate drive signals, TG1 and TG2, are driven between their respective BST and SW pin voltages. The BST1 and BST2 voltages are biased from floating bootstrap capacitors CBST1 and CBST2, which are normally recharged from GATEVCC through diodes D BST1 and DBST2 when their respective top MOSFETs a re off. The bootstrap capacitors CBST1 and C BST2 need to store roughly 100 times the gate charge (Q G) required by top switches A and D. In most situations, a 0.1μF to 0.47μF, X5R or X7R, 25V capacitor is adequate. The bypass capacitance from GATEVCC to ground should be at least ten times the value of the CBST1 and CBST2 capacitors. The rise times of the SW1 and SW2 pins can be slowed down through the addition of series resistors between the respective bootstrap capacitors and the BST1 or BST2 pins. T he slowing down of the switch edges can improve overshoot but may also degrade efficiency due to increased transitional losses.

analog.com Rev. A 46 of 59 Bootstrap Diodes (DBST1 and DBST2) Silicon diodes rated for 1A with a very fast reverse recovery time (< 50ns) are recommended for the bootstrap diodes, DBST1 and DBST2. Although schottky diodes have the benefit of low forward drops, they can exhibit high reverse current leakage and have the potential for thermal runaway under high voltage and temperature conditions. Make sure that DBST1 and DBST2 have reverse breakdown voltage ratings higher than V INP(MAX) and VOUT(MAX), respectively, and have less than 50μA of reverse leakage at the maximum operating temperature. In pass -thru mode, low reverse leakage is critical. The bootstrap diode leakage current will have a disproportionate effect on the quiescent current due to the limited efficiency of the internal charge pump. For pass -thru, use diodes with reverse leakage currents 10μA or less at the maximum operating temperatu re. In some cases, it can be beneficial to add a small resistor (< 5Ω) in series with DBST1 and DBST2. The resistors reduce surge currents in the diodes and can reduce ringing at the SW and BST pins of the IC. Since SW pin ringing is highly dependent on PC B layout, SW pin edge rates, and the types of diodes used, careful measurements directly at the SW pins of the IC are recommended. If required, a single resistor can be placed between GATEVCC and the anodes of both D BST1 and DBST2, or by placing separate r esistors between the cathodes of each diode and the respective BST pins. Excessive resistance in series with D BST1 and DBST2 can reduce the bootstrap capacitor voltage when the switch B and C on-times are very short and should be avoided. EXTVCC, GATEVCC, and VDD GATEVCC is the power supply for the gate drivers and should be bypassed with a minimum 4.7μF, 25V, ceramic capacitor to the ground placed close to the pin. A good local bypass is necessary to supply the high transient current required by the MOSFET gate drivers. The GATEVCC voltage is regulated to 10.6V from PMOS low -dropout regulators powered from the VINP or EXTVCC pins. VINP is the default power supply, but if the voltage on EXTVCC exceeds 8V (typical) and is simultaneously lower than the V INP voltage, GATEVCC will be regulated from EXTV CC. The LT8210-1 selects the lower of the two supplies to minimize power dissipation. EXTVCC can be connected to VOUT or any supply up to 40V for improved system efficiency. If not used, EXTV CC should be tied to ground through a 100k resistor. The maximum current the GATEV CC regulator can supply is typically 110mA at V IN = 12V and drops linearly at higher voltages. This limits the power dissipation of the LT8210 -1 to roughly 3W. The current limit should be considered when selecting power MOSFETs and setting the switching frequency. I GATEVCC is dominated by gate charge current, which reaches a maximum in the buck-boost region when all four power MOSFETs are switching. The peak gate drive current is equal to the product of fSW and the sum of the MOSFET gate charges (Q G(TOT) = QG(A) + QG(B) + QG(C) + QG(D)). The GATEVCC pin is backdrive-protected should the voltage on either the VINP or EXTV CC drop below GATEV CC. This is a useful feature, allowing the LT8210-1 to operate during input brownout conditions even when EXTVCC is not used. The length of time GATEVCC is able to ride through an input transient will depend on I GATEVCC and the size of its bypass capacitor. The GATEVCC regulator is stable with capacitors up to 220μF for flexibility in designing for many millisecond ride-through conditions. The V DD pin is regulated to 3.3V from GATEV CC with a low -dropout PMOS regulator. The VDD pin powers internal low voltage circuitry within the LT8210-1 and can source a maximum of 10mA. It must have a minimum 2.2μF X5R/ X7R capacitor to ground placed close to the pin. The V DD supply is a convenient pull -up rail for the MODE1, MODE2, SYNC, and PWGD pins when tying those input logic high. For powering loads other than those specified, contact the factory for support.

analog.com Rev. A 48 of 59 If pass-thru mode is exited during operation, the FB1 and FB2 pins will be shorted with an internal switch, creating a composite value for V OUT between V OUT(BOOST) and V OUT(BUCK). The relative magnitude of the FB1 and FB2 resistive dividers can be used to place VOUT at a desired value between VOUT(BOOST) and VOUT(BUCK) (Equation 17). 𝑉𝑜𝑢𝑡 = 1.00𝑉 • 𝑅1𝐴||𝑅2𝐴+𝑅1𝐵||𝑅2𝐵 𝑅1𝐵||𝑅2𝐵 (17) If the resistor configuration shown in Figure 70 is used for defining the pass-thru window top and bottom, VOUT will equal VOUT(BUCK) when exiting the pass-thru. Programming Current Limit In boost and buck-boost operating modes, when VOUT > VINP, the current limit set by RSENSE will vary with the duty ratio (Equation 2). If less variation is desired at the expense of higher power loss, RSENSE2 can be used to program an average current limit. The recommended choice is to set RSENSE2  1.5* RSENSE. This value optimizes the tradeoff between power loss and current limit variation, i.e., minimizes power loss while still reducing somewhat the variation of the current limit when input voltage drops below output voltage. To program current limit variation that is independent of VINP (but with higher power loss), an alternate choice for RSENSE2 is: 𝑅𝑆𝐸𝑁𝑆𝐸2 = 0.15 𝐼𝑂𝑈𝑇(𝑀𝐴𝑋) 𝑉𝑂𝑈𝑇 𝑉𝐼𝑁𝑃(𝑀𝐼𝑁) ∙ 𝑅𝑆𝐸𝑁𝑆𝐸 ∙ (1 + ∆𝐼𝐿% 2 ) (18) A margin of 20% to 30% below the calculated value is recommended. Where: IOUT(MAX) is the maximum average current out. VINP(MIN) is the minimum input at the VINP pin. ∆IL % is the inductor ripple current divided by the output current. 30% to 40% is typically optimal. Multiphase Current Component Selection An RC network from the R SENSE2 terminals to SNSP2 and SNSN2 inputs is required to average out ripple current that may degrade current matching between phases at light loads. The time constant of this low -pass filter should be greater than 5µs (e.g., 49.9Ω and 100nF), but it can be increased for better current matching. Each LT8210 -1 phase should have its own 11k resist or from its IMON pin to that IC’s signal ground. The IMON pins of all phases should connect to a common node through resistors of several hundred Ohms or greater. Each IMON pin should have a local bypass capacitor (for example, 10nF) to prevent noise due to local ground voltage variation. The VC1 (and VC2 if pass- thru mode is used) pins for each phase must have their own Type II compensation networks and these pins should be connected to a common node through a resistor between 1k and 10k. The coupling of t he VC1 (and VC2 in pass- thru) pins dramatically reduces current matching error from reference voltage variation and feedback resistor divider mismatch. The resistors connecting the VC1 pins isolate the compensation networks from switching noise picked up in the PCB traces connecting them. It is recommended to use separate FB1 (and FB2 in pass -thru) resistor dividers for each phase. While this increases the current matching error, it can be greatly reduced by using 0.1% tolerance resistors. The risks of routing high-impedance feedback signals long distances between phases are not worth a slight increase in current mismatch.

cases, it is beneficial to choose a lower RDS(ON) MOSFET at the expense of a higher QG to minimize power dissipation. be connected and a 1nF, 25V capacitor placed between VIN and DG. conduction losses in the total series resistance between input and output (Equation 22). Figure 78. Non-Switching Pass-Thru Equivalent Circuit

analog.com Rev. A 53 of 59 While beneficial for efficiency, low series resistance leads to high Q and an underdamped transient response. Without increasing RSERIES, the quality factor can be reduced either by decreasing the inductor value or increasing the output capacitance. A lower inductor valu e requires operating at a higher switching frequency to maintain ripple performance and sub-harmonic stability while switching. Depending on the details of the application, this can be a good approach if the input voltage is expected to be within the pass-thru window the majority of the time, and lower efficiency due to increased switching losses is not a major concern. Otherwise, increasing the output capacitance is a more or less benign approach for lowering Q other than possibly requiring adjustment to t he loop compensation. The resonant frequency of the RLC network can be calculated using Equation 24. 𝑓0 = 2𝜋 ⋅ √ 𝐿⋅𝐶𝑂𝑈𝑇 (24) Generally speaking, the output closely tracks the input f or frequencies below resonance. Above the resonant frequency, the majority of the AC voltage from the input shows up as voltage across the inductor. The LT8210 -1 monitors the inductor’s voltage and current in the non -switching state, and switching will res ume if the inductor current exceeds the pass-thru DC current limit (typically, VSNSP1 – VSNSN1 > 63mV) or if the difference in voltage between VINP and VOUT exceeds 4% of the input voltage. This means that the total series resistance between VINP and VOUT should be sized less than Equation 25. 𝑅𝐷𝑆𝑂𝑁(𝐴) + 𝑅𝑆𝐸𝑁𝑆𝐸 + 𝑅𝐷𝐶𝑅 + 𝑅𝐷𝑆𝑂𝑁(𝐷) ≪ 0.04⋅𝑉𝑂𝑈𝑇(𝐵𝑂𝑂𝑆𝑇) 𝐼𝑂𝑈𝑇(𝑀𝐴𝑋) (25) If the input supply noise has an amplitude greater than 4% of the nominal value at frequencies above resonance, consider adding an input filter to reduce high frequency content and minimize/prevent switching in the pass -thru region. The load transient respons e in the pass -thru region is determined primarily by the ESR of the output capacitor, which should be kept low through the use of parallel ceramic capacitors. The ESR of the bulk output capacitor should also be kept relatively low, as this determines the output impedance near resonance. The soft-start capacitor, CSS, controls the ramping of the inductor current whenever the LT8210-1 exits the non-switching pass-thru state due to a line or load transient or mode change. A CSS value greater than 10nF may slow the output response at this non-switching to switching transition and should be verified in the application under the worst -case transient conditions. Efficiency at light loads (I OUT < 10mA) and system quiescent current draw are optimized through the use of large value resistors for the FB1, FB2, and EN/UVLO (if an input UVLO is implemented) dividers. If possible, use a single 3-resistor divider between the output and ground to program VOUT(BOOST) and VOUT(BUCK). Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting efficiency and which change would produce the most improvement. Although all dissipative elements in the circuit produce losses, these are the main sources of losses in LT8210-1 circuits: 1. Switching Losses. These losses arise from the brief amount of time switch A or switch C spends in the saturated region during SW1 and SW2 node transitions, respectively. Power loss depends on the input voltage, output voltage, load current, driver strength, and MOSFET capacitance, among other factors. See the Power MOSFET Selection section for more details. 2. DC I2R Losses. These arise from the resistances of the MOSFETs, sensing resistors, inductors, and PC board traces and cause the efficiency to drop at high output currents.

analog.com Rev. A 54 of 59 3. GATEV CC Current. The sum of the MOSFET driver current, V DD pin current, and control currents. The GATEV CC regulator’s power supply voltage times the current represents lost power. This loss can be reduced by supplying GATEVCC current through the EXTV CC pin from a high e fficiency source, such as the output or an alternate supply if available. Lower Q G MOSFETs can reduce GATEV CC current and power loss, as well as lowering the switching frequency. 4. CIN and COUT Loss. The input capacitor has the difficult job of filtering the large RMS input current to the regulator in buck mode. The output capacitor has the difficult job of filtering the large RMS output current in boost mode. Both CIN and COUT are required to have low ESR to minimize the AC I 2R loss and sufficient capacitance to prevent the RMS current from causing additional upstream losses in fuses or batteries. 5. Other Losses. Inductor core loss occurs predominately at light loads. When mak ing adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. If one makes a change and the input current decreases, then the efficiency has increased. If there is no change in input current, then there is no chan ge in efficiency. PC Board Layout Checklist The basic circuit board layout requires a dedicated ground plane layer. Also, for high current, a multilayer board provides heat sinking for power components.

• The ground plane layer should not have any trac es and should be as close as possible to the layer with the power MOSFETs.
• Separate the power ground from the signal ground. The power ground should connect to the ( –) terminals of C IN, COUT, C GATEVCC, and the sources of switches B and C. All small -signal components and compensation components should connect to a separate signal ground, which in turn connects to the PCB ground at one location away from high currents and switching noise. The GND pin and back tab must connect to this signal ground.
• Place switch A, switch B, and the input capacitor(s) in one compact area with short PC trace lengths.
• Place switch C, switch D, and the output capacitor(s) in one compact area with short PC trace lengths.
• Minimize the routing resistance from the TG1 and BG2 pins to power switches A and C, respectively.
• Use planes for VIN, VINP, and VOUT to maintain good voltage filtering and to keep power losses low.
• The SW1 and SW2 planes should be wide enough to provide low resistance connections between the power switches, inductor, and sense resistor, but otherwise as compact as possible to minimize parasitic capacitance.
• Route the inductor current sense traces (SNSP1/N1) together with minimum PC trace spacing. The optional filter network capacitor between po sitive and negative sense traces should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the RSENSE resistor.
• Route the average current sense traces (SNSP2/N2) together with the minimum PC trace spacing. Avoid crossing or running parallel to high dV/dT signals. The optional filter network capacitor between positive and negative sense traces should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the RSENSE2 resistor.
• Keep the high dV/dT nodes SW1, SW2, BST1, BST2, TG1, TG2, SNSP1, and SNSN1 away from sensitive small -signal nodes.
• Avoid running signal traces parallel to the traces that carry high di/dt current because they can receive inductively coupled voltage noise. This includes the SW1, SW2, TG1, TG2, BG1, and BG2 traces to the controller.

analog.com Rev. A 55 of 59

• Connect the top driver bootstrap capacitor, C BST1, closely to the BST1 and SW1 pins. Connect the top driver bootstrap capacitor, CBST2, closely to the BST2 and SW2 pins.
• Connect the FB1 and FB2 pin resistor dividers between the (+) terminal of COUT and signal ground. The resistor connections should not be along high current or noise paths.
• If EXTVCC is connected to VOUT, it should have a Kelvin connection to the (+) t erminal of COUT, and a ceramic bypass capacitor should be placed close to the EXTVCC pin.
• Connect the V C1/VC2 pin compensation networks closely to the IC, between V C1/VC2 and the signal ground pins. The capacitor helps to filter the effects of PCB noise and output ripple voltage from the compensation loop.
• Connect the GATEV CC and VDD bypass capacitors close to the IC. The capacitors carry the MOSFET drivers’ current peaks. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. Connect the copper areas to a DC net (e.g., quiet GND).

Figure 79. Typical Application, 4-Phase Schematic

Figure 80. Package Drawing

1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

4.50 REF

0.50 BSC

0.200 REF

analog.com Rev. A 58 of 59 ORDERING GUIDE Table 10.Ordering Guide LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE

DESCRIPTION

LT8210AUJ-1#PBF LT8210AUJ- 1#TRPBF LT8210UJ-1 40-Lead (6mm x 6mm) Plastic QFN –40°C to 125°C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3779 150V VIN and VOUT Synchronous 4-Switch Buck-Boost Controller 4.5V ≤ VIN ≤ 150V, 1.2V ≤ VOUT ≤ 150V, Up to 99% Efficiency Drives Logic Level or STD Threshold MOSFETs, TSSOP-38 LTC3777 150V VIN and VOUT Synchronous 4-Switch Buck-Boost Controller + Switching Bias Supply 4.5V ≤ VIN ≤ 150V, 1.2V ≤ VOUT ≤ 150V, Up to 99% Efficiency Drives Logic Level or STD Threshold MOSFETs, TSSOP-38 LT8705A 80V VIN and VOUT Synchronous 4-Switch Buck-Boost DC/DC Controller 2.8V ≤ VIN ≤ 80V, Input and Output Current Monitor, 5mm × 7mm QFN-28/TSSOP-38 LTC7813 60V Low IQ Synchronous Boost + Buck Controller Low EMI and Low Input/Output Ripple 4.5V (Down to 2.2V after Start-Up) ≤ VIN ≤ 60V, Boost VOUT Up to 60V, 0.8V < Buck VOUT < 60V, IQ = 29μA, 5mm × 5mm QFN-32 LT8390A High Efficiency Synchronous 4-Switch Buck-Boost Controller 4V ≤ VIN ≤ 60V, VOUT Range: 1V to 60V, ±1.5% Output Voltage Accuracy 4mm × 5mm QFN-2/TSSOP-28 Packages LTM8056 58V Buck-Boost DC/DC μModule® Regulator, Adjustable Input and Output Current Limiting 5V ≤ VIN ≤ 58V, 1.2V ≤ VOUT ≤ 48V 15mm × 15mm × 4.92mm BGA Package LTC3895/LTC7801 150V Low IQ, Synchronous Step-Down DC/DC Controller with 100% Duty Cycle 4V ≤ VIN ≤ 140V, 150V Abs Max, PLL Fixed Frequency 50kHz to 900kHz, 0.8V ≤ VOUT ≤ 60V, Adjustable 5V to 10V Gate Drive, IQ = 40μA 4mm × 5mm QFN-24/TSSOP-24/TSSOP-38(31) LTC7103 105V, 2.3A Low EMI Synchronous Step- Down Regulator 4.4V ≤ VIN ≤ 105V, 1V ≤ VOUT ≤ VIN, IQ = 2μA Fixed Frequency 200kHz to 2MHz, 5mm × 6mm QFN LT8210 100V VIN and VOUT Synchronus 4-Switch Buck-Boost DC/DC Controller with Pass-Thru 2.8V ≤ VIN ≤ 100V, 1V ≤ VOUT ≤ 100V, Pass-Thru Mode, 6mm × 6mm QFN LTC7878 70V Parallelable 4-Switch Buck-Boost Controller with Inductor DCR Current Sensing 5V to 70V input and output range, seamless low- noise transitions between operating regions, 5mm × 5mm QFN

ALL INFORMATION CONTAINED HEREIN IS PROVIDED “AS IS” WITHOUT REPRESENTATION OR WARRANTY. NO RESPONSIBILITY IS ASSUMED BY ANALOG DEVICES FOR ITS USE, NOR FOR ANY INFRINGEMENTS OF PATENTS OR OTHER RIGHTS OF THIRD PARTIES THAT MAY RESULT FROM ITS USE. SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. NO LICENCE, EITHER EXPRESSED OR IMPLIED, IS GRANTED UNDER ANY ADI PATENT RIGHT, COPYRIGHT, MASK WORK RIGHT, OR ANY OTHER ADI INTELLECTUAL PROPERTY RIGHT RELATING TO ANY COMBINATION, MACHINE, OR PROCESS WHICH ADI PRODUCTS OR SERVICES ARE USED. TRADEMARKS AND REGISTERED TRADEMARKS ARE THE PROPERTY OF THEIR RESPECTIVE OWNERS. analog.com Rev. A 59 of 59