LT8210 (Rev. B)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 46
Technical content
Rev. BFor more information www.analog.comDocument Feedback TYPICAL APPLICATION FEATURES DESCRIPTION 100V VIN and VOUT Synchronous 4-Switch Buck-Boost DC/DC Controller with Pass-Thru The LT®8210 is a 4-switch synchronous buck-boost DC/DC controller that can operate in pass-thru, forced continuous, pulse-skipping and Burst Mode ® operation. Pass-Thru is a feature that passes the input directly to the output when the input is within a user programmable window. Pass-Thru mode eliminates switching losses and EMI along with maximizing efficiency. For input voltages above or below the pass-thru window, the buck or boost regulation loops maintain the output at the set maximum or minimum values, respectively. The GATEVCC driver supply is regulated to 10.6V allow - ing the use of standard-level MOSFETs and can be pow- ered through the EXTVCC pin for improved efficiency. The GATEVCC regulator is back-drive-protected to ride through input brownouts while maintaining regulation. Optional reverse input protection down to –40V can be imple - mented with the addition of a single N-channel MOSFET . The LT8210 includes a precision current sense ampli - fier that can accurately monitor and limit output or input average current. Pass-Thru T ransfer Characteristic (VOUT(BOOST) = 8V, VOUT(BUCK) = 16V)
APPLICATIONS
n Pin-Selectable Pass-Thru or Fixed Output CCM, DCM, Burst Mode® Operation n Programmable Non-Switching Pass-Thru Window n 18μA Pass-Thru Mode IQ with 99.9% Efficiency n VIN Range: 2.8V to 100V (4.5V for Start-Up) n VOUT Range: 1V to 100V n Reverse Input Protection to –40V n ±1.25% Output Voltage Accuracy (–40°C to 125°C) n ±3% Accurate Current Monitoring n ±5% Accurate Current Regulation n 10V Quad N-Channel MOSFET Gate Drivers n EXTVCC LDO Powers Drivers from VOUT/External Rail n ±20% Cycle-by-Cycle Inductor Current Limit n No Top MOSFET Refresh Noise in Buck or Boost n Fixed/Phase-Lockable Frequency: 80kHz to 400kHz n Spread Spectrum Frequency Modulation for Low EMI n Power Good Output Voltage/Overcurrent Monitor n Available in a 38-Lead TSSOP and 40-Lead (6mm x 6mm) QFN Packages n Automotive, Industrial, Telecom, Avionics Systems n Automotive Start-Stop, Emergency Call Applications n ISO 7637, ISO 16750, MIL-1275, DO-160 Applications B 4.7µH VOUT 8V TO 16V VIN REGULATES: 4V TO 100V SURVIVES: –40V TO 100V 0.1µF 100k 7.15k 22µF D 4m 7.15k 2.2µF BST1 BST2 15nF71.5k 2.2nF VDD 4.7µF A C FB1 TG1 BST1 SW1 BG1 SNSP1 SNSN1 PGND BG2 SW2 BST2 TG2 LT8210 SYNC/ SPRD DG VOUTEN/UVLO GATEVCC VDD VC2 FB2 IMON PWGD MODE1 EXTVCC VINP MODE2 SNSP2 SNSN2 0.1µF 220µF 10µF 220µF VIN 100k 100pF46.4k VC1GNDSSRT 59k 4.7nF330pF 38.3k 1nF
8210 TA01a
All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. patents, including 10135340. PASS– THRU REGION V IN V OUT EFFICIENCY INPUT VOL TAGE (V) 100 VOL TAGE (V) EFFICIENCY (%) T ransfer Characteristic
8210 TA01b
Rev. B For more information www.analog.com TABLE OF CONTENTS Power Switch Control (CCM, DCM, Burst Power Switch Control: Buck Region Power Switch Control: Boost Region Power Switch Control: Buck-Boost Region Maximum Output Current and RSENSE Selection ....23 Component Optimization for Pass-Thru Operation .34
Rev. BFor more information www.analog.com PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS (Note 1) TOP VIEW FE PACKAGE 38-LEAD PLASTIC TSSOP TJMAX = 125°C, θJA = 25°C/W EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB EN/UVLO MODE2 MODE1 SYNC/SPRD PWGD RT GND VDD SS IMON VC1 VC2 FB2 FB1 NC VOUT NC SNSN2 SNSP2 VIN DG VINP NC SNSP1 SNSN1 TG1 SW1 BST1 NC EXTVCC GATEVCC BG1 PGND BG2 NC BST2 SW2 TG2 GND 3940 38 37 36 35 34 33 32 31 11 2012 13 14 15 TOP VIEW GND UJ PACKAGE 40-LEAD (6mm × 6mm) PLASTIC QFN 16 17 18 19 SYNC/SPRD PWGD RT GND VDD SS IMON VC1 VC2 FB2 SNSN1 TG1 SW1 BST1 NC EXTVCC GATEVCC BG1 PGND BG2 MODE1 MODE2 NC EN/UVLO NC VIN DG VINP NC SNSP1 FB1 NC VOUT NC SNSN2 SNSP2 NC TG2 SW2 BST2 Operating Junction Temperature ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LT8210EFE#PBF LT8210EFE#TRPBF LT8210FE 38-Lead Plastic TSSOP –40°C to 125°C LT8210IFE#PBF LT8210IFE#TRPBF LT8210FE 38-Lead Plastic TSSOP –40°C to 125°C LT8210EUJ#PBF LT8210EUJ#TRPBF 8210UJ 40-Lead (6mm x 6mm) Plastic QFN –40°C to 125°C LT8210IUJ#PBF LT8210IUJ#TRPBF 8210UJ 40-Lead (6mm x 6mm) Plastic QFN –40°C to 125°C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Rev. B For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VINP = 12V, VEN/UVLO = 3.3V PARAMETER CONDITIONS MIN TYP MAX UNITS Voltage Supplies and Regulators VIN, VINP Input Operating Voltage Range Minimum Voltage for Start-Up (VEXTVCC = 0V) l 4.5 100 V After Start-Up, VEXTVCC = 12V l 2.8 100 V VIN Quiescent Current Shutdown (VEN/UVLO = 0V) Not Switching Internal Charge Pump Enabled (VDG – VIN = 3.5V) l l l 1400 1800 µA µA µA VINP Quiescent Current Shutdown (VEN/UVLO = 0V) Not Switching Internal Charge Pump Enabled (VDG – VIN = 3.5V) Burst Mode Operation (Sleep) Pass-Thru (Non-Switching, VINP = 48V) l l l l l 0.1 650 1900 1.0 1300 2700 µA µA µA µA µA VOUT Quiescent Current VOUT = 12V l 1.5 3 µA GATEVCC Voltage IGATEVCC = 25mA l 10 10.6 11.2 V GATEVCC Current Limit Regulated from VINP, VINP =12V, VGATEVCC = 9V Regulated from VINP, VINP = 100V, VGATEVCC = 9V Regulated from EXTVCC, VEXTVCC = 12V, VGATEVCC = 9V Regulated from EXTVCC, VEXTVCC = 40V, VGATEVCC = 9V l l l l 110 115 mA mA mA mA GATEVCC Load Regulation IGATEVCC = 0mA to 50mA l 1.8 5 % GATEVCC Regulator Dropout Voltage VINP – VGATEVCC: IGATEVCC = 50mA VEXTVCC – VGATEVCC: IGATEVCC = 50mA l l 750 600 1600 1400 mV mV GATEVCC Undervoltage Lockout Threshold Falling l 3.65 3.75 3.85 V GATEVCC Undervoltage Lockout Hysteresis 0.20 V GATEVCC Backdrive Current To VINP Pin, VGATEVCC = 10V, VINP = 0V To EXTVCC Pin, VGATEVCC = 10V, VEXTVCC = 0V µA µA EXTVCC Switchover Voltage Rising l 7.3 8 8.8 V EXTVCC Switchover Hysteresis 1.2 V VDD Voltage l 3.2 3.3 3.4 V VDD Current Limit VDD = 3V 10 mA VDD Undervoltage Lockout Threshold Falling l 2.7 2.8 2.9 V VDD Undervoltage Lockout Hysteresis 140 mV Enable Comparator EN/UVLO Enable Threshold Rising l 1.28 1.45 1.61 V EN/UVLO Enable Hysteresis 100 mV EN/UVLO Pin Bias Current VEN/UVLO = 100V l 0.08 0.3 µA Reverse Input Protection DG Gate Drive Voltage (VDG – VIN) Non-Switching l 7.0 8.5 V Reverse Input Disconnect Threshold (VIN) IDG = 100 µA l –1.8 –1.2 –0.5 V DG Pin Pull-Down Current VIN = –4V, VDG – VIN = 5V l 50 80 130 mA DG Pin Pull-Up Current VDG – VIN = 1.5V VDG – VIN = 8.5V l l 100 180 µA µA DG Undervoltage Threshold (VDG – VIN) Rising l 2.3 2.8 3 V DG Undervoltage Hysteresis (VDG – VIN) 700 mV Voltage Regulation FB1 Regulation Voltage Regulation Voltage for CCM, DCM, Burst Mode Operation, Pass-Thru Mode Boost Loop l 0.9875 1.00 1.0125 V
Rev. BFor more information www.analog.com PARAMETER CONDITIONS MIN TYP MAX UNITS FB2 Regulation Voltage Regulation Voltage Pass-Thru Mode Buck Loop l 0.985 1.00 1.015 V FB1, FB2 Input Bias Current l 0.001 0.04 µA FB1, FB2 Line Regulation VINP = 3V to 100V l 0.001 0.007 %/V FB1, FB2 Error Amplifier T ransconductance 450 µA/V VC1, VC2 Output Impedance 5 MΩ VC1, VC2 Maximum Sourcing Current VFB1 = VFB2 = 0V 35 µA VC1, VC2 Maximum Sinking Current VFB1 = VFB2 = 2V –35 µA Soft-Start Charging Current VSS = 0.5V l 4 5 6 µA Soft-Start Pull-Down Resistance l 140 250 Ω Average Current Monitoring and Regulation SNSP2, SNSN2 Operating Voltage Range l 0 100 V SNSP2, SNSN2 Pin Bias Current VSNSP2 = VSNSN2 = 100V VSNSP2 = VSNSN2 = 0V l l 3 µA µA IMON Output Current Common Mode Voltage = 12V VSNSP2 – VSNSN2 = 150mV VSNSP2 – VSNSN2 = 50mV VSNSP2 – VSNSN2 = 10mV l l l 87.3 28.6 5.1 92.7 31.4 6.6 µA µA µA IMON Output Current Common Mode Voltage = 0V VSNSP2 – VSNSN2 = 150mV VSNSP2 – VSNSN2 = 50mV VSNSP2 – VSNSN2 = 10mV l l l 90.5 8.5 µA µA µA Common Mode Switchover Voltage VSNSP2 = VSNSN2 1.8 V IMON DC CMRR VSNSP2 – VSNSN2 = 150mV, VSNSP2 = 3V to 100V 120 dB IMON Error Amplifier T ransconductance 200 µA/V IMON Regulation Voltage (VIMON) l 0.98 1.01 1.03 V Sense Regulation Voltage (VSNSP2 – VSNSN2) RIMON = 33.2k l 48 50.5 53 mV Over-Current Warning Threshold (VIMON) Rising l 1.15 1.2 1.24 V Over-Current Warning Hysteresis 45 mV IMON Disable Threshold (VIMON) Rising l 2.3 2.5 2.8 V IMON Disable Hysteresis 400 mV Cycle-by-Cycle Inductor Current Limiting Maximum Current Sense Threshold (VSNSP1 – VSNSN1) Buck Regulation (VINP = 24V, VOUT = 0V) Buck Regulation (VINP = 24V, VOUT = 12V) Boost Regulation (VINP = 6V, VOUT = 12V) Buck Regulation (VINP = 100V, VOUT = 48V) Boost Regulation (VINP = 24V, VOUT = 48V) l l l l l mV mV mV mV mV Maximum Non-Switching Current Sense Threshold in Pass-Thru (VSNSP1 – VSNSN1) VOUT = VINP , FB1 = 1.2V, FB2 = 0.8V MODE1 = MODE2 = 3.3V l 57 63 70 mV Reverse Current Sense Threshold (VSNSP1 – VSNSN1) DCM/Pass-Thru/Burst Mode Operation Pass-Thru Buck-Boost Regions mV mV Negative Current Sense Threshold (VSNSP1 – VSNSN1) CCM Operating Mode (MODE1 = MODE2 = 0V) –55 mV MOSFET Gate Drivers TG1, TG2 Gate Driver Pull-Up Resistance 3 Ω TG1, TG2 Gate Driver Pull-Down Resistance 1 Ω BG1, BG2 Gate Driver Pull-Up Resistance 2.6 Ω ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VINP = 12V, VEN/UVLO = 3.3V
Rev. B For more information www.analog.com PARAMETER CONDITIONS MIN TYP MAX UNITS BG1, BG2 Gate Driver Pull-Down Resistance 1 Ω TG1, TG2 Rise Time CLOAD = 3300pF (10% to 90%) 25 ns TG1, TG2 Fall Time CLOAD = 3300pF (10% to 90%) 15 ns BG1, BG2 Rise Time CLOAD = 3300pF (10% to 90%) 20 ns BG1, BG2 Fall Time CLOAD = 3300pF (10% to 90%) 15 ns TG Off to BG On-Delay CLOAD = 3300pF 60 ns BG Off to TG On-Delay CLOAD = 3300pF 60 ns Minimum TG1 On-Time CLOAD = 3300pF 200 ns Minimum BG2 On-Time CLOAD = 3300pF 220 ns BST1, BST2 Bias Current Top Gate High, VBST – VSW = 10V Top Gate High, VBST – VSW = 10V, Pass-Thru Mode 0.6 µA µA BST1, BST2 Charging Current Non-Switching, VBST – VSW = 8.25V Non-Switching, VBST – VSW = 3V 610 µA µA Oscillator Switching Frequency Range RT Set/Synchronized l 80 400 kHz Switching Frequency RT = 110k RT = 39.2k RT = 16.9k l l l 190 380 100 200 400 108 210 420 kHz kHz kHz SYNC/SPRD Input Low Level l 0.8 V SYNC/SPRD Input High Level l 1.17 V Spread-Spectrum Max. Frequency (% of fSW) VSYNC/SPRD = 3.3V 112.5 % Spread-Spectrum Min. Frequency (% of fSW) VSYNC/SPRD = 3.3V 100 % Logic Inputs/Outputs MODE1,2 Input Low Level l 0.8 V MODE1,2 Input High Level l 1.17 V MODE1,2 Leakage Current VMODE1,2 = 6 V 0.01 1 μA PWGD Output Low Voltage IPWGD = 1mA l 0.07 0.2 V PWGD T rip Level VFB1 Falling VFB2 Rising l l –13 –10 PWGD Anti-Glitch Delay VPWGD Rising or Falling l 2 10 20 µs PWGD Leakage Current VPWGD = 40V 0.01 1 μA ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VINP = 12V, VEN/UVLO = 3.3V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT8210E is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT8210I is guaranteed over the full –40°C to 125°C junction temperature range. Note 3: Do not apply a voltage or current source to these pins. They must be connected to capacitive loads only, otherwise permanent damage may occur . Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature range may impair the device reliability. Note 5: Negative voltages on the SW1, SW2, SNSP1 and SNSN1 pins are limited, in an application, by the body diodes of the external NMOS devices, MB and MC, or parallel Schottky diodes when present. These pins are tolerant of these negative voltages in excess of one diode drop below ground, guaranteed by design. Note 6: Do not force voltage on the VC1, VC2, or SS pin.
Rev. BFor more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs Load Current (VIN = 20V – Figure 37) Efficiency vs Load Current (VIN = 48V – Figure 37) Efficiency vs Load Current (VIN = 70V – Figure 37) Efficiency and Power Loss vs Input Voltage (Figure 37) Shutdown Currents vs Voltage Pass-Thru Non-Switching Currents vs Input Voltage IMON Current Limit vs Input Voltage (Figure 37) IMON Measurement Accuracy (Figure 37) IMON CMRR vs Frequency V OUT = 48V V OUT(PASS–THRU) = 36V CCM DCM Burst Mode OPER. PASS–THRU LOAD CURRENT (A) 0.001 0.01 0.1 2.5 100 EFFICIENCY (%) IN
8210 G01
V OUT = 48V CCM DCM Burst Mode OPER. PASS–THRU LOAD CURRENT (A) 0.001 0.01 0.1 2.5 100 EFFICIENCY (%) IN
8210 G02
V OUT = 48V V OUT(PASS–THRU) = 52V CCM DCM Burst Mode OPER. PASS–THRU LOAD CURRENT (A) 0.001 0.01 0.1 2.5 100 EFFICIENCY (%) IN
8210 G03
I OUT = 2A CCM PASS–THRU INPUT VOL TAGE (V) 100 EFFICIENCY (%) POWER LOSS (W)
8210 G04
V OUT = 95% × V OUT(NOM) V OUT = 90% × V OUT(NOM) V OUT = 50% × V OUT(NOM) V OUT = 10% × V OUT(NOM) INPUT VOL TAGE (V) 3.30 3.32 3.34 3.36 3.38 3.40 99.1 99.7 100.3 100.9 101.2 101.8 I OUT (A) NORMALIZED CURRENT LIMIT (%)
8210 G07
V OUT = 48V V IN = 20V V IN = 48V V IN = 60V V IN = 80V OUTPUT CURRENT (A) 0.5 1.5 2.5 ERROR (%)
8210 G08
I VIN I VINP I SNSP2 I SNSN2 I VOUT VOL TAGE (V) 100 0.0001 0.001 0.01 0.1 CURRENT (µA) Shutdown Currents
8210 G05
I VINP I VIN I VOUT INPUT VOL TAGE (V) 100 CURRENT (µA) Currents vs Input Voltage
8210 G06
R IMON = 150kΩ C IMON = 3.3nF NO C IMON FREQUENCY (Hz) 100 10k 100k 400k 70.0 80.0 90.0 100.0 110.0 120.0 130.0 CMRR (dB)
8210 G09
Rev. B For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Maximum Inductor Current: fSW = fSW(Optimal) (Figure 39) Maximum Inductor Current: fSW = 0.7 × fSW(Optimal) (Figure 39) Maximum Inductor Current: fSW = 1.3 × fSW(Optimal) (Figure 39) Start-Up (CCM Mode – Figure 36) Pre-Biased Output Start-Up (CCM Mode – Figure 36) Static Reverse Input Protection (Figure 36) Dynamic Reverse Input Protection (Figure 36) T ransition to Current Regulation (Figure 36) Inductor Current at Light Load (Figure 37) V OUT = 24V BOOST REGION BUCK REGION BB REGION I L PEAK I L AVERAGE I L VALLEY MAXIMUM I OUT INPUT VOL TAGE (V) 108 126 144 CURRENT (A) NORMALIZED CURRENT (%) SW SW(OPTIMAL)
8210 G10
V OUT = 24V BOOST REGION BUCK REGION BB REGION I L PEAK I L AVERAGE I L VALLEY MAXIMUM I OUT INPUT VOL TAGE (V) 108 126 144 CURRENT (A) NORMALIZED CURRENT (%)
8210 G11
V OUT = 24V BOOST REGION BUCK REGION BB REGION I L PEAK I L AVERAGE I L VALLEY MAXIMUM I OUT INPUT VOL TAGE (V) 108 126 144 CURRENT (A) NORMALIZED CURRENT (%) Figure 39
8210 G12
V OUT = 12V I OUT = 3A V IN = 12V 400µs/DIV DG 10V/DIV PWGD 3V/DIV V OUT 5V/DIV I L 5A/DIV
8210 G13
V IN FROM 0V TO –14V 2ms/DIV V IN 10V/DIV V INP 1V/DIV DG 10V/DIV I IN 1A/DIV
8210 G15
V OUT = 6V V OUT = 12V 400µs/DIV
8210 G14
V OUT 5V/DIV I L 5A/DIV V IN = 12V V IN FROM 10V TO –6V V OUT = 12V I OUT = 1A 4ms/DIV V IN 10V/DIV DG 10V/DIV V OUT 10V/DIV V INP 10V/DIV
8210 G16
V OUT 5V/DIV I OUT 10A/DIV I L 10A/DIV
8210 G17
V IN = 48V; I OUT = 250mA 20µs/DIV I L (Burst) 2A/DIV I L (DCM) 1A/DIV I L (CCM) 1A/DIV IL (PASS– THRU) 1A/DIV
8210 G18
Rev. BFor more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Load Step (Boost Region – Figure 37) Load Step (Buck-Boost Region – Figure 37) Load Step (Buck Region – Figure 37) Line Step (Boost Region – Figure 37) Line Step (Buck-Boost Region – Figure 37) Line Step (Buck Region – Figure 37) Input Voltage Sweep (CCM Mode – Figure 37) Input Voltage Sweep (Pass-Thru – Figure 37) High Frequency Switching Region T ransitions (CCM Mode – Figure 37) LOAD STEP FROM 500mA TO 2A V IN = 20V , V OUT = 48V , CCM MODE 400µs/DIV I OUT 1A/DIV I L 5A/DIV V OUT (AC) 500mV/DIV IMON 500mV/DIV
8210 G19
LOAD STEP FROM 500mA TO 2A V IN = 48V , V OUT = 48V , CCM MODE 400µs/DIV I OUT 1A/DIV I L 2A/DIV V OUT (AC) 500mV/DIV IMON 500mV/DIV
8210 G20
LOAD STEP FROM 500mA TO 2A V IN = 70V , V OUT = 48V , CCM MODE 400µs/DIV I OUT 1A/DIV I L 5A/DIV V OUT (AC) 500mV/DIV IMON 500mV/DIV
8210 G21
V IN FROM 20V TO 30V 40µs/DIV V IN 20V/DIV SW2 50V/DIV V OUT (AC) 500mV/DIV I L 5A/DIV
8210 G22
IOUT = 2A CCM MODE V IN FROM 48V TO 58V 20µs/DIV
8210 G23
V IN 20V/DIV SW2 50V/DIV V OUT (AC) 500mV/DIV I L 5A/DIV IOUT = 2A CCM MODE V IN FROM 60V TO 70V I OUT = 2A CCM MODE 20µs/DIV
8210 G24
V IN 10V/DIV SW1 50V/DIV V OUT (AC) 500mV/DIV I L 5A/DIV V OUT = 48V 400µs/DIV V IN 15V/DIV SW1 50V/DIV V OUT 15V/DIV SW2 50V/DIV
8210 G25
V OUT = 36V V OUT = 52V 400µs/DIV V IN 15V/DIV SW1 50V/DIV V OUT 15V/DIV SW2 50V/DIV
8210 G26
T ransitions (CCM Mode – Figure 38) 20µs/DIV V IN 25V/DIV SW2 50V/DIV SW1 50V/DIV I L 10A/DIV
8210 G27
Rev. B For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Pass-Thru Start-Up: VIN Below Pass-Thru Window (Figure 38) Pass-Thru Start-Up: VIN in Pass-Thru Window (Figure 38) Pass-Thru Start-Up: VIN Above Pass-Thru Window (Figure 38) Pass-Thru Regulation with Noisy Input Supply (Figure 38) Pass-Thru Line Step (Figure 38) Pass-Thru Load Step (Figure 38) Pass-Thru Positive Surge (Figure 38) Pass-Thru Negative Surge (Figure 38) Pass-Thru Current Limit (Figure 38) V OUT = V OUT(BOOST) = 22V V IN = 9V 1ms/DIV DG 10V/DIV PWGD 3V/DIV 10V/DIV
8210 G28
V OUT I L 5A/DIV Figure 38 V OUT = V IN = 28V 1ms/DIV
8210 G29
V OUT I L 3A/DIV V OUT = V OUT(BUCK) = 32V V IN = 50V 1ms/DIV
8210 G30
V OUT I L 5A/DIV V OUT = V IN = 28V 2ms/DIV
8210 G31
V IN (AC) 2V/DIV V OUT (AC) 2V/DIV SW1 20V/DIV SW2 20V/DIV V OUT = V IN = 23V V OUT = V IN = 29V 100µs/DIV V IN 5V/DIV SW1 20V/DIV V OUT 5A/DIV I L 2A/DIV
8210 G32
V IN = 28V 1ms/DIV V OUT (AC) 500mV/DIV IMON 500mV/DIV I OUT 2A/DIV I L 2A/DIV
8210 G33
V IN = V OUT = 28V V IN = 70V V OUT = 32V 50µs/DIV
8210 G34
V IN 10V/DIV 10V/DIV V OUT I L 10A/DIV V OUT = V IN = 28V V OUT = 22V V IN = 12V 400µs/DIV V IN 5V/DIV V OUT 5V/DIV I L 2A/DIV
8210 G35
V IN = 28V 40µs/DIV
8210 G36
I OUT 10A/DIV V OUT 20V/DIV I L 10A/DIV
Rev. BFor more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Pass-Thru IMON Limit (Figure 38) GATEVCC Max Current vs Voltage GATEVCC Backdrive Current EXTVCC, VINP, Switchover Thresholds for GATEVCC Regulation GATEVCC Response to Input Brownout (EXTVCC = 12V) GATEVCC Response to Input Brownout (EXTVCC = 0V) DG Pin Charging Current vs Voltage BST1, BST2 Average Charging Current for Non-Switching Channel DG, BST1, BST2 Charging in Pass-Thru (Figure 36) V IN = 28V 1ms/DIV V OUT 20V/DIV IMON 500mV/DIV I OUT 5A/DIV I L 5A/DIV
8210 G37
V GATEV CC = 9V FROM V INP FROM EXTV CC VOL TAGE (V) 100 105 120 135 I GATEV CC (mA) DISSIPATED POWER (W) GATEV CC Max Current vs Voltage
8210 G38
V GATEV CC = 10V V INP = V EXTV CC = 0V TO EXTV CC PIN TO V INP PIN TEMPERATURE (°C) –40 120 I GATEV CC (µA) GATEV CC Backdrive Current
8210 G39
V IN FROM 12V TO 4V V OUT = 12V V GATEVCC = 10.6V V DD = 3.3V 200µs/DIV V DD
8210 G41
V IN 5V/DIV 5V/DIV GATEV CC 2V/DIV V OUT 10V/DIV GATEVCC UVLO C GATEV CC = 68µF V IN FROM 12V TO 4V V GATEVCC < 3.7V V GATEVCC = 10.6V 4ms/DIV
8210 G42
V IN 5V/DIV SS 5V/DIV GATEV CC 5V/DIV V OUT 10V/DIV V IN = 4.5V V IN = 8V V IN = 12V V IN = 48V V DG – V IN (V) 100 125 150 175 200 225 250 I DG (µA) DG Pin Charging Current vs Voltage
8210 G43
I BST2 I BST1 V OUT = 12V DCM (I OUT = 0.02A, f SW = 80kHz) DCM (I OUT = 0.02A, f SW = 400kHz) CCM INPUT VOL TAGE (V) 100 10k CURRENT (µA) Non-Switching Channel
8210 G44
DG (AC) 2V/DIV BST2 (AC) 2V/DIV BST1 (AC) 2V/DIV
8210 G45
V INP RISING V INP FALLING TEMPERATURE (°C) –60 –30 120 150 VOL TAGE (V) CC
8210 G40
Rev. B For more information www.analog.com EN/UVLO (Pin 1/Pin 37): Precision Enable Input. The LT8210 is enabled when this pin is pulled above 1.45V. A voltage below 1.35V on this pin will cause the LT8210 to reside in a low-power shutdown mode. Tie to V IN for always-on operation. Connect to a resistor divider between VIN and ground to set an undervoltage lockout threshold. EN/UVLO can tolerate negative voltages to –40V. MODE2 (Pin 2/Pin 39): Operating Mode Selection Input #2. Used in conjunction with MODE1 pin to select between continuous conduction switching (CCM), dis - continuous switching (DCM), Burst Mode operation, and pass-thru operating modes. Refer to Table 1 in the Operation section for operating mode pin settings. MODE1 (Pin 3/Pin 40): Operating Mode Selection Input #1. Used in conjunction with MODE2 pin to select between continuous conduction switching (CCM), dis - continuous switching (DCM), Burst Mode operation, and pass-thru operating modes. Refer to Table 1 in the Operation section for operating mode pin settings. SYNC/SPRD (Pin 4/Pin 1): External Clock Synchronization Input. For external sync apply a clock signal between 80kHz and 400kHz to this pin. An internal PLL will synchronize the oscillator to the external clock signal. Connect this pin to the VDD pin to enable spread spectrum operation on the RT set switching frequency, otherwise connect to ground. PWGD (Pin 5/Pin 2): Power Good Indicator . Open-drain logic output which is pulled to ground when the output voltage is outside ±10% of its programmed value or the IMON pin voltage is greater than 1.20V. This pin can be connected to any voltage rail up to 40V through a pull- up resistor . Using either VDD or GATEVCC for the pull-up supply has the advantage that PWGD will be in the correct state when the part is disabled. RT (Pin 6/Pin 3): Frequency Set Pin. Place a resistor from this pin to GND to set the switching frequency. The range of frequency adjustment is between 80kHz and 400kHz. Refer to Table 2 in Applications Information. GND (Exposed Pad Pin 7/Pin 4): Signal Ground. All small-signal components and compensation components should connect to this ground, which in turn connects to the PCB ground at one location away from high currents and switching noise. The exposed pad must be soldered PIN FUNCTIONS to the PCB and connect to the GND pin using top layer metal. VDD (Pin 8/Pin 5) : Internally Regulated 3.3V Supply Rail. Bypass this pin to ground with a minimum of 2.2µF ceramic capacitor . VDD can be used for tying MODE1 , MODE2, and SYNC/SPRD pins logic high. SS (Pin 9/Pin 6): Soft-Start Input. A capacitor to ground at this pin sets the ramp rate of the inductor current at start-up via internal clamping of the VC1 and VC2 voltages. The SS pin sources 5µA once switching is enabled and is held at ground while switching is disabled. IMON (Pin 10/Pin 7): Current Monitor Output. The cur - rent sourced from this pin is proportional to the voltage difference between the SNSP2 and SNSN2 inputs. Place a resistor from the IMON pin to ground to set the average current limit. The loop will transition from voltage to cur- rent regulation when the voltage on IMON exceeds 1.01V. VC1 (Pin 11/Pin 8): Error Amplifier Output and Switching Regulator Compensation Point for CCM, DCM and Burst Mode Operation. In pass-thru mode, this pin is the com- pensation point for the boost regulator loop. The cur - rent mode comparator trip point increases with this control voltage. VC2 (Pin 12/Pin 9): Error Amplifier Output and Switching Regulator Compensation Point for Buck Loop When in Pass-Thru Mode. The current mode comparator trip point increases with this control voltage. If pass-thru mode is not used leave VC2 floating. FB2 (Pin 13/Pin 10): Error Amplifier Feedback Input for Buck Regulation Loop When in Pass-Thru Mode. Receives the feedback voltage for the buck controller from an exter- nal resistive divider across the output. If pass-thru mode is not used leave this pin floating. FB1 (Pin 14/Pin 11): Error Amplifier Feedback Input for CCM, DCM, Burst Operation Modes. Feedback input for boost regulation loop in pass-thru mode. Receives the feedback voltage from an external resistive divider across the output. VOUT (Pin 16/Pin 13) : Output Voltage Sense. This pin must have a Kelvin connection to the drain of switch D. (TSSOP/QFN)
Rev. BFor more information www.analog.com PIN FUNCTIONS Use a small RC low-pass filter (e.g., 50Ω and 22nF) for improved jitter performance when VOUT ripple is large. SNSP2, SNSN2 (Pins 19,18/Pins 16,15): Positive (+) and Negative (– ) Inputs for the Average Current Sense Monitor . SNSP2, SNSN2 should connect to the positive and negative terminals of a sense resistor placed in series with the input, output or load. A current linearly propor - tional to difference in voltage between the SNSP2 and SNSN2 pins is sourced from the IMON pin and can be used for current monitoring and limiting with the selection of the RIMON resistor . TG2 (Pin 20/Pin 18): Top Gate Drive for Boost Regulator . Drives top N-channel MOSFET with a voltage swing equal to GATEVCC superimposed onto the SW2 node voltage. When operating in the buck region or within the pass-thru window TG2 is held roughly at VOUT + GATEVCC. SW2 (Pin 21/Pin 19): Boost Regulator Switch Node. The (–) terminal of the bootstrap capacitor connects here. BST2 (Pin 22/Pin 20): Boosted Floating Driver Supply for Boost Regulator . The (+) terminal of the bootstrap capaci- tor connects here. The BST2 pin swings from roughly GATEVCC to VOUT + GATEVCC when the boost regulation loop is switching. When operating in the buck region or the within pass-thru window this pin is held roughly at VOUT + GATEVCC. BG2 (Pin 24/Pin 21): Bottom Gate Drive for Boost Regulator . Drives bottom N-channel MOSFET with a volt- age swing between GATEVCC and PGND. PGND (Pin 25/Pin 22): Driver Power Ground. Connect to CIN, COUT and sources of MOSFETs, MC and MD. BG1 (Pin 26/Pin 23): Bottom Gate Drive for Buck Regulator . Drives bottom N-channel MOSFET with a volt- age swing between GATEVCC and PGND. GATEVCC (Pin 27/Pin 24): Power Supply for Gate Drivers. Internally regulated to 10.6V. Bypass this pin to ground with a minimum 4.7µF ceramic capacitor . EXTVCC (Pin 28/Pin 25): External Power Supply Input for the GATEVCC Regulator . GATEVCC will be linearly regulated from EXTVCC if its voltage is higher than 8V and is simul- taneously lower than V INP. May be driven with voltages up to 40V. If this feature is not used, connect this pin to ground through a 100k resistor . BST1 (Pin 30/Pin 27): Boosted Floating Driver Supply for Buck Regulator . The (+) terminal of the bootstrap capaci- tor connects here. The BST1 pin swings from roughly GATEVCC to V IN + GATEV CC when the buck regulation loop is switching. When operating in the boost region or within the pass-thru window this pin is held roughly at VIN + GATEVCC. SW1 (Pin 31/Pin 28): Buck Regulator Switch Node. The (–) terminal of the bootstrap capacitor connects here. TG1 (Pin 32/Pin 29): Top Gate Drive for Buck Regulator . Drives top N-channel MOSFET with a voltage swing equal to GATEV CC superimposed onto the SW1 node voltage. When operating in the boost region or within the pass-thru window TG1 pin is held roughly at VIN + GATEV CC continuously. SNSP1, SNS N1 (Pins 34, 33/Pin 31,30): Positive (+) and Negative (–) Inputs for the Inductor Current Sense Amplifier . Place an appropriately valued shunt resistor in series with the inductor on the SW1 side and connect to SNSP1 and SNSN1. The SNSP1 – SNSN1 voltage is used for current mode control and reverse current detection. VINP (Pin 36/Pin 33): Protected Main Input Supply. This pin must connect to the drain terminal of switch A. Use a small RC low-pass filter (e.g., 1Ω and 1µF) for improved jitter performance. When reverse input protec- tion is implemented connect this pin to the drain of the DG MOSFET , otherwise connect to VIN. DG (Pin 37/Pin 34): Reverse Input Protection Gate Drive Output. When V IN is pulled below –1.2V, this pin is clamped internally to VIN with a low resistance switch forcing an external MOSFET between the V IN and V INP pins into cutoff. In normal operation, this pin is charged to roughly VIN + GATEVCC with an internal charge pump to fully enhance the external MOSFET . DG can tolerate negative voltages down to –40V. VIN (Pin 38/Pin 35): Input Voltage Pin. This pin is used for powering start-up circuitry and the internal charge pump. VIN can withstand negative voltages down to –40V without damaging the regulator or drawing large currents. (TSSOP/QFN)
Figure 1. Block Diagram
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following sections about the operation of the LT8210. to VDD to set high or to ground to set low. Table 1. LT8210 Operating Modes ing frequency for CCM operation is 350kHz. nificant current draw from the output back into the input. in CCM for full switching frequency operation. inhibited and above which switching activity is re-enabled. current in the same manner as DCM mode.
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Figure 2. Simplified Diagram of the Power Switches Figure 3. Switching Region vs VINP/VOUT Ratio
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region, switch D is always on while switch C is always off. preventing the inductor current from falling any further . the negative current sense threshold in CCM. in DCM or the negative current sense threshold in CCM. Figure 4. Buck Region Switching Waveforms
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Figure 5. Boost Region Switching Waveforms
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Figure 6. Buck-Boost Region Switching Waveforms
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prevent large amplitude ringing in the inductor current. continuously again after VOUT settles close to VINP. switching regions in pass-thru mode versus input voltage. Figure 7. Pass-Thru Regions vs VINP
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Figure 8. Output Voltage when Exiting Pass-Thru Mode
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Figure 9. Start-Up Sequence to program an undervoltage lockout (UVLO) threshold. discharging the bypass capacitor and resetting the part.
- SWITCHER OFF
- GATEVCC, VDD LDOs OFF
- VIN, VINP, IQ < 1µA
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- SWITCHER DISABLED
- GATEVCC AND VDD OUTPUTS ENABLED
- SS HELD LOW SWITCHER ENABLED
- SS PIN CHARGES
- SWITCHING BEGINS
- FORCED DISCONTINOUS MODE UNTIL SS > 2.5V VGATEVCC > 3.9V AND VDD > 2.9V VIN > –1.2V DG CHARGING
- CHARGE PUMP ENABLED
- DG PIN CHARGING
- SS HELD LOW VDG–VINP > 2.8V AND VINP > 2.8V
Figure 10. GATEVCC Current Limit vs VINP , EXTVCC The LT8210 start-up sequence is shown in Figure 9.
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and powers the low voltage circuitry within the LT8210. SYNC/SPRD) and as the pull-up supply for the PWGD pin. rail please contact the factory for support. transitions from voltage regulation to current regulation. and reduce quiescent current. Figure 11. Implementing Reverse Input Protection
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sourced from the BST pin of the non-switching channel. Figure 12. Output Current Sense Figure 13. Input Current Sense Figure 14. Ground Current Sense
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Figure 15. PWGD Logic
the basic LT8210 application circuit shown in Figure 16.
- R SENSE is selected based on the required output cur-
- Inductor value (L) and switching frequency (f SW)
- Power MOSFETs (A, B, C, D) are selected to maximize
- C IN and C OUT capacitors selected to filter input
- C BST1, CBST2, and C GATEVCC capacitors are selected
to store adequate charge to power the gate drivers.
- Type II compensation network designed for VC1 (and
also VC2 if pass-thru mode is used).
- C SS selected to set soft-start behavior .
- (Optional) – Reverse input protection (DG) MOSFET
and minimize conduction loss during regulation.
- (Optional) – Current regulation and/or monitoring
implemented with RSENSE2, RIMON, CIMON. values unless otherwise specified. RSENSE is chosen based on the required output current. inductor current ripple, duty cycle, and switching region. Figure 16. Basic LT8210 Applications Circuit
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Figure 17. Example of Maximum Average Inductor equal to the inductor current multiplied by D’BST ≅ VINP/VOUT.
- VINP(MIN) VOUT Inductor Selection The operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. The inductor value is inversely related to the ripple current. Typically, the inductor ripple current, ∆IL, is set to 20%to 40% of the maximum inductor current. The minimum inductor value necessary to maintain a desired ripple can be calculated for both buck and boost regions as: L( BUCK) > VOUT • VIN(MAX) − VOUT( ) fSW • IOUT(MAX) • ΔIL % • VIN(MAX) L( BOOST) > VIN(MIN)2 • VOUT − VIN(MIN)( ) fSW • IOUT(MAX) • ΔIL % • VOUT 2 In addition to ripple considerations, the inductance should be large enough to prevent subharmonic oscillations. In a current mode controlled regulator , the current sense loop creates a double pole at half the switching frequency which can degrade system stability when its quality factor (QCS) is much greater than 1.0. The current sense loop damping is a function of the inductor current slope and the internal slope compensating ramp. The LT8210 slope compensation scheme is designed to provide optimal damping of the current sense loop for any input voltage when the inductor value is set to the following value. LOPTIMAL = (260 + (5.5 • VOUT ))•RSENSE • 1 fSW for example : LOPTIMAL(VOUT =12V) = 325 •RSENSE • 1 fSW LOPTIMAL(VOUT =48V) = 525 •RSENSE • 1 fSW This simplifies loop compensation as the current sense loop damping becomes independent of duty cycle and switching region. Selecting LOPTIMAL also optimizes line regulation and line step response. A lower inductance value will increase QCS, and a sufficiently undersized inductor can result in sub- harmonic oscillation for buck duty cycles above 50% and boost duty cycles below 50%. Choose an inductor at least 70% of the calculated optimal value to avoid subharmonic A margin of 20% to 30% on the lower of the two cal- culated R SENSE values is usually recommended. The RSENSE resistor should be a low inductance type so as not to degrade stability. A small low pass filter between RSENSE and the SNSP1 and SNSN1 pins like that shown in Figure 18 is not required but may improve switching edge jitter in some applications. These filter components should be placed near the pins.
Figure 18. Optional SNSP1, SNSN1 Filter for Improved Jitter
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have low DC resistance (DCR) to reduce the I 2R losses. tor ISAT rating of 90mV/RSENSE, for example. cies to minimize MOSFET heating from switching losses. switching frequencies to minimize total solution size. period, T . The RSENSE value is set by load requirements.
- Select RSENSE based on required output current.
- Select inductor value based on desired ripple for a
range of fSW (e.g., 80kHz to 120kHz).
- Adjust switching frequency to satisfy:
across duty cycle and switching region. revert to the RT set value within approximately 20μs. Table 2. Switching Frequency vs RT Value (1% Resistor)
while in Burst Mode operation. waveforms with the spread spectrum feature enabled. Figure 19. T ransition from RT Set Frequency to Synchronization Figure 20. T ransition from Synchronization to RT Set Frequency Figure 21. Conducted Average EMI Comparison (AM Band) Example Figure 22. Switching Waveforms with Spread-Spectrum Enabled
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on the other hand, scale with frequency and voltage. VIN(MAX) in the buck region. Table 3. Switch A Power Dissipation Table 4. Switch B Power Dissipation Figure 23. Normalized RDS(ON) vs Temperature
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Table 5. Switch C Power Dissipation Table 6. Switch D Power Dissipation Figure 24. Example of Switch Power Dissipation vs VINP
- Voltage ripple is inversely proportional to capacitance.
- ESR must be low to minimize its contribution to volt-
- RMS current rating of the capacitor(s) should exceed
worst-case application conditions with margin.
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Rev. BFor more information www.analog.com For buck operation, the value of CIN to achieve a desired input ripple voltage (∆VIN) can be calculated as: CIN ≅ IOUT(MAX) ∆VIN • fsw
- VOUT VIN ⎟• 1− VOUT VIN ∆VIN is typically chosen at a level acceptable to the user . 100mV to 200mV is a good starting point. The ESR of the input capacitance should be less than: ESR(IN,MAX) < ∆VIN IOUT(MAX) The input RMS current can be approximated by: IIN(RMS) ≈ IOUT(MAX) • VOUT VIN
- VIN VOUT − 1 This formula has a maximum at V IN = 2VOUT, where IRMS = I OUT(MAX)/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. The capacitance nec- essary to achieve a desired output ripple, ∆VOUT, can be calculated for the buck and boost switching regions: COUT(BOOST) = IOUT(MAX) • VOUT − VIN(MIN)( ) ∆VOUT • fsw • VOUT COUT(BUCK) = VOUT • VIN(MAX) − VOUT( ) ∆VOUT • fsw 2 • VIN(MAX) • 8 •L The ESR of the output capacitor should be low enough to not significantly increase the ripple voltage: ESR(BOOST) < ∆VOUT • VIN(MIN) IOUT(MAX) • VOUT ESR(BUCK) < ∆VOUT •L • fSW VOUT • 1– VOUT VIN(MAX) COUT should also tolerate the maximum RMS output cur- rent of when operating in the boost region: IOUT(RMS) ≈ IOUT(MAX) • VOUT VIN(MIN) − 1 For both the CIN and COUT capacitors, a good approach for larger values is to use a parallel combination of aluminum electrolytics for bulk capacitance and ceramics for low ESR and to handle the RMS currents. When used together , the percentage of RMS current that will flow through the aluminum electrolytic capacitor can be approximated by the following equation: %IRMS,ALUM ≈ 100% 1+ 2π • fSW •C(CER) •RESR(ALUM)( ) Where RESR(ALUM) is the ESR of the aluminum capacitor and C(CER) is the total value of the ceramic capacitor(s). Ceramic capacitors should be placed near the regulator input and output to suppress high frequency switching spikes. Specifically, the ceramic capacitors on the input should be placed in close proximity to switches A and B, and output ceramics should be placed close to switches C and D. Due to their excellent low ESR characteristics, ceramic capacitors can significantly reduce ripple voltage and help reduce power loss in higher ESR bulk capacitors. X5R and X7R are preferred, as these materials retain their capacitance over wide voltage and temperature ranges. At higher input and output voltages multiple ceramic capaci- tors in parallel may be needed due to limited availability of high voltage, large value ceramic capacitors in standard footprints. In situations with high input and/or output volt- age ripple a RC low-pass filter with time constant of 1μs or greater is recommended for V INP and VOUT inputs to maintain low jitter on switching edges. Bootstrap Capacitors (CBST1, CBST2) The top MOSFET gate drive signals, T G1 and T G2, are driven between their respective BST and SW pin voltages. The BST1 and BST2 voltages are biased from floating bootstrap capacitors CBST1 and CBST2, which are normally recharged from GATEVCC through diodes DBST1 and DBST2 when their respective top MOSFET is off. The bootstrap capacitors CBST1 and C BST2 need to store roughly 100 times the gate charge (Q G) required by top switches A and D. In most situations, a 0.1μF to 0.47μF, X5R or X7R, 25V capacitor is adequate. The bypass capacitance from GATEVCC to ground should be at least ten times the value APPLICATIONS INFORMATION
Rev. B For more information www.analog.com of the CBST1, CBST2 capacitors. The rise times of the SW1 and SW2 pins can be slowed down through the addi - tion of series resistors between the respective bootstrap capacitors and the BST1 or BST2 pins. The slowing down of the switch edges can improve overshoot but may also degrade efficiency due to increased transitional losses. Bootstrap Diodes (DBST1, DBST2) Silicon diodes rated for 1A with very fast reverse recov - ery time ( <50ns) are recommended for the bootstrap diodes, DBST1 and DBST2. Although Schottky diodes have the benefit of low forward drops, they can exhibit high reverse current leakage and have the potential for thermal runaway under high voltage and temperature conditions. Make sure that DBST1 and DBST2 have reverse breakdown voltage ratings higher than V INP(MAX) and V OUT(MAX), respectively, and have less than 50μ A of reverse leak - age at the maximum operating temperature. In pass- thru mode low reverse leakage is critical. The bootstrap diode leakage current will have a disproportionate effect on quiescent current due to the limited efficiency of the internal charge pump. For pass-thru use diodes with reverse leakage currents 10μA or less at the maximum operating temperature. In some cases, it can be benefi - cial to add a small resistor (< 5Ω) in series with D BST1 and DBST2. The resistors reduce surge currents in the diodes and can reduce ringing at the SW and BST pins of the IC. Since SW pin ringing is highly dependent on PCB layout, SW pin edge rates and the types of diodes used, careful measurements directly at the SW pins of the IC are recommended. If required, a single resistor can be placed between GATEVCC and the anodes of both DBST1 and DBST2 or by placing separate resistors between the cathodes of each diode and the respective BST pins. Excessive resistance in series with DBST1 and DBST2 can reduce the bootstrap capacitor voltage when the switch B and C on-times are very short and should be avoided. EXTVCC, GATEVCC and VDD GATEVCC is the power supply for the gate drivers and should be bypassed with a minimum 4.7μF, 25V, ceramic capacitor to ground placed close to the pin. Good local APPLICATIONS INFORMATION bypass is necessary to supply the high transient current required by the MOSFET gate drivers. The GATEVCC volt- age is regulated to 10.6V from PMOS low-dropout regula- tors powered from the V INP or EXTVCC pins. VINP is the default power supply but if the voltage on EXTVCC exceeds 8V (typical) and is simultaneously lower than the VINP volt- age, GATEVCC will be regulated from EXTVCC. The LT8210 automatically selects the lower of these two supplies to minimize power dissipation. The comparison criteria is invalid when VINP drops below 8.5V to allow EXTV CC to hold up GATEVCC during input brownouts. EXTVCC can be connected to VOUT or any supply up to 40V for improved system efficiency. If not used, EXTVCC should be tied to ground through a 100k resistor . The maximum current the GATEVCC regulator can supply is typically 110mA at V IN = 12V and drops linearly at higher voltages. This limits the internal power dissipation of the LT8210 to roughly 3W. The GATEV CC current limit foldback helps prevent triggering a thermal shutdown (typically 175 °C) due to excessive internal power dissipation. The current limit should be considered when selecting power MOSFETs and setting the switching frequency. I GATEVCC is domi - nated by gate charge current which reaches a maximum in the buck-boost region when all four power MOSFETs are switching. The peak gate drive current is equal to the product of fSW and the sum of the MOSFET gate charges (QG(TOT) = QG(A) + QG(B) + QG(C) + QG(D)). The GATEVCC pin is backdrive-protected should the voltage on either the VINP or EXTVCC drop below GATEVCC. This can be a useful feature, allowing the LT8210 to maintain operation dur - ing input brownout conditions even when EXTVCC is not used. The length of time GATEVCC is able to ride-through an input transient will depend on I GATEVCC and the size of its bypass capacitor . The GATEVCC regulator is stable with capacitors up to 220μF for flexibility in designing for many millisecond ride-through conditions. The V DD pin is regulated to 3.3V from GATEV CC with a low-dropout PMOS regulator . The VDD pin powers internal low-voltage circuitry within the LT8210 and can source a maximum of 10mA. It should be bypassed with a minimum 2.2μF X5R/X7R capacitor to ground placed close to the pin. The VDD supply is a convenient pull-up rail for the MODE1, MODE2, SYNC, and PWGD pins when tying those inputs
please contact the factory for support. between VOUT(BOOST) and VOUT(BUCK). will equal VOUT(BUCK) when exiting pass-thru. Figure 25. Setting the Output Voltage for CCM, DCM,
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Figure 26. Setting the Output Voltage Window for
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Figure 27. Power Saving Feedback Resistor
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switching noise and stabilize the current regulation loop. A typical range for the RF resistor would be 10Ω to 100Ω. transfer function approximates that of the voltage loop. sense amplifier and minimize quiescent current. Figure 28. Input Current Monitor and Limit Using Input Filter Figure 29. Output Current Monitor and Limit Using CIMON Filter
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falling threshold is set at 1.35V with 100mV of hysteresis. connect to the VIN pin for ‘always on’ operation. approach. In pass-thru mode use CSS ≤10nF. Figure 31. Typical Start-Up with No CSS Figure 30. VIN UVLO Implementation Using the EN/UVLO Pin
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Figure 34. For most applications, a CC1 of 2.2nF is a good
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Figure 32. Typical Start-Up with CSS = 10nF
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Figure 33. Loop Compensation on VC1 Figure 34. Loop Compensation on VC2
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mode control please refer to Application Note 149. 25V capacitor placed between VIN and DG.
between VINP and VOUT exceeds 4% of the input voltage. to program VOUT(BOOST) and VOUT(BUCK). Figure 35. Non-Switching Pass-Thru Equivalent Circuit
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- 1 RSERIES While beneficial for efficiency, low series resistance leads to high Q and underdamped transient response. Without increasing RSERIES the quality factor can be reduced either by decreasing the inductor value or increasing the output capacitance. A lower inductor value requires operating at a higher switching frequency to maintain ripple per - formance and sub-harmonic stability while switching. Depending on the details of the application this can be a good approach if the input voltage is expected to be within the pass-thru window the majority of the time and lower efficiency due to increased switching losses is not a major concern. Otherwise, increasing the output capacitance is a more or less benign approach for lowering Q other than possibly requiring adjustment to the loop compensa- tion. The resonant frequency of the RLC network can be calculated as: fO = 1
- 1 L • COUT APPLICATIONS INFORMATION
Rev. B For more information www.analog.com is limiting the efficiency and which change would produce the most improvement. Although all dissipative elements in the circuit produce losses, these are the main sources of losses in LT8210 circuits: 1. Switching Losses. These losses arises from the brief amount of time switch A or switch C spends in the saturated region during SW1, SW2 node transitions, respectively. Power loss depends upon the input volt- age, output voltage, load current, driver strength and MOSFET capacitance, among other factors. See the Power MOSFET Selection section for more details. 2. DC I2R Losses. These arise from the resistances of the MOSFETs, sensing resistors, inductor and PC board traces and cause the efficiency to drop at high output currents. 3. GATEV CC Current. The sum of the MOSFET driver current, VDD pin current and control currents. The GATEVCC regulator’ s power supply voltage times the current represents lost power . This loss can be reduced by supplying GATEV CC current through the EXTVCC pin from a high efficiency source, such as the output or alternate supply if available. Lower Q G MOSFETs can reduce GATEV CC current and power loss as can lowering the switching frequency. 4. C IN and COUT Loss. The input capacitor has the dif - ficult job of filtering the large RMS input current to the regulator in buck mode. The output capacitor has the difficult job of filtering the large RMS output current in boost mode. Both CIN and COUT are required to have low ESR to minimize the AC I 2R loss and sufficient capacitance to prevent the RMS current from causing additional upstream losses in fuses or batteries. 5. Other Losses. Inductor core loss occurs predomi - nately at light loads. 6. When making adjustments to improve efficiency, the input current is the best indicator of changes in effi- ciency. If one makes a change and the input current decreases, then the efficiency has increased. If there is no change in input current, then there is no change in efficiency. PC Board Layout Checklist The basic circuit board layout requires a dedicated ground plane layer . Also, for high current, a multilayer board pro- vides heat sinking for power components.
- The ground plane layer should not have any traces and should be as close as possible to the layer with the power MOSFETs.
- Separate the power ground from the signal ground. The power ground should connect to the (–) terminals of CIN, COUT, CGATEVCC, and the sources of switches B and C. All small-signal components and compensa - tion components should connect to a separate signal ground which in turn connects to the PCB ground at one location away from high currents and switching noise. The GND pin and back tab must connect to this signal ground.
- Place switch A, switch B and the input capacitor(s) in one compact area with short PC trace lengths.
- Place switch C, switch D and the output capacitor(s) in one compact area with short PC trace lengths.
- Minimize the routing resistance from the TG1 and BG2 pins to power switches A and C, respectively.
- Use planes for VIN, VINP, and VOUT to maintain good voltage filtering and to keep power losses low.
- The SW1 and SW2 planes should be wide enough to provide low resistance connections between the power switches, inductor and sense resistor , but otherwise as compact as possible to minimize parasitic capacitance.
- Route the inductor current sense traces (SNSP1 / N1) together with minimum PC trace spacing. The optional filter network capacitor between positive and negative sense traces should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the RSENSE resistor . APPLICATIONS INFORMATION
Rev. BFor more information www.analog.com
- Route the average current sense traces (SNSP2/ N2) together with minimum PC trace spacing. Avoid crossing or running parallel to high dV/dT signals. The optional filter network capacitor between posi - tive and negative sense traces should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the RSENSE2 resistor .
- Keep the high dv/dt nodes SW1, SW2, BST1, BST2, TG1, TG2, SNSP1 and SNSN1 away from sensitive small-signal nodes.
- Avoid running signal traces parallel to the traces that carry high di/dt current because they can receive inductively coupled voltage noise. This includes the SW1, SW2, TG1, TG2, BG1 and BG2 traces to the controller .
- Connect the top driver bootstrap capacitor , C BST1, closely to the BST1 and SW1 pins. Connect the top driver bootstrap capacitor , CBST2, closely to the BST2 and SW2 pins.
- Connect the FB1 and FB2 pin resistor dividers between the (+) terminal of COUT and signal ground. The resis- tor connections should not be along the high current or noise paths.
- If EXTV CC is connected to V OUT it should have a Kelvin connection to the (+) terminal of C OUT and a ceramic bypass capacitor should be placed close to the EXTVCC pin.
- Connect the V C1/VC2 pin compensation networks closely to the IC, between V C1/VC2 and the signal ground pins. The capacitor helps to filter the effects of PCB noise and output voltage ripple voltage from the compensation loop.
- Connect the GATEV CC and V DD bypass capacitors close to the IC. The capacitors carry the MOSFET drivers’ current peaks.
- Flood all unused areas on all layers with copper . Flooding with copper will reduce the temperature rise of power components. Connect the copper areas to a DC net (e.g., quiet GND). APPLICATIONS INFORMATION
Figure 36. 10A, 12V Buck-Boost (CCM)/8V to 16V Pass-Thru Regulator
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8210 F36f
8210 F36g
Figure 37. 2.5A, 48V Buck-Boost Regulator/36V to 52V Pass-Thru Regulator
8210 F37a
8210 F37b
8210 F37c
8210 F37d
8210 F37e
8210 F37f
8210 F37g
Figure 38. 2A, 22V to 32V Pass-Thru Regulator for Noise Sensitive Applications
8210 F38a
8210 F38b
8210 F38d
8210 F38e
8210 F38f
8210 F38g
8210 F38c
Figure 39. 24V Buck-Boost Regulator in Burst Mode Operation
8210 F39a
8210 F39b
8210 F39c
8210 F39d
8210 F39e
8210 F39f
8210 F39g
Figure 40. 24A/16A, 8V to 16V Pass-Thru Regulator
8210 F40a
18A to 25A output current limit by roughly 20ms when the L T8210 transitions from the nonswitching to switching.
8210 F40b
8210 F40c
8210 F40d
8210 F40e
8210 F40f
8210 F40g
Rev. BFor more information www.analog.com PACKAGE DESCRIPTION 4.75 (.187) REF FE38 (AA) TSSOP REV C 0910 0.09 – 0.20 (.0035 – .0079) 0° – 8° 0.25 REF 0.50 – 0.75 (.020 – .030) 4.30 – 4.50* (.169 – .177) 1 19 REF 9.60 – 9.80* (.378 – .386) 1.20 (.047) MAX 0.05 – 0.15 (.002 – .006) 0.50 (.0196) BSC 0.17 – 0.27 (.0067 – .0106) TYP RECOMMENDED SOLDER PAD LAYOUT 0.315 ±0.05
0.50 BSC
4.50 REF
6.60 ±0.10 1.05 ±0.10
4.75 REF
2.74 REF
2.74 (.108) MILLIMETERS (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE SEE NOTE 4 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT 6.40 (.252) BSC 38-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1772 Rev C) Exposed Pad Variation AA
Rev. B For more information www.analog.com PACKAGE DESCRIPTION 6.00 ±0.10 (4 SIDES) NOTE: 1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (SEE NOTE 6) PIN 1 NOTCH R = 0.45 OR 0.35 × 45° CHAMFER 0.40 ±0.10 4039 BOTTOM VIEW—EXPOSED PAD (4-SIDES) 4.42 ±0.10 4.42 ±0.10 4.42 ±0.05 4.42 ±0.05 0.75 ±0.05 R = 0.115 TYP 0.25 ±0.05
0.200 REF
0.00 – 0.05 (UJ40) QFN REV Ø 0406 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 4.50 ±0.05 (4 SIDES) 5.10 ±0.05 6.50 ±0.05 0.25 ±0.05 R = 0.10 TYP 40-Lead Plastic QFN (6mm × 6mm) (Reference LTC DWG # 05-08-1728 Rev Ø)
Rev. BFor more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER A 09/19 Added QFN Package and changed Pass-Through to Pass-Thru 1, 3, 12, 13, 44 B 02/20 Corrected QFN Pin 30 Name/Minor Typo’s 2, 3, 4, 5, 6, 19, 27, 32, 34
Rev. B For more information www.analog.com ANALOG DEVICES, INC. 2019-2020 www.analog.com RELATED PARTS TYPICAL APPLICATION B 4.2/uni03BCH VOUT 8V TO 16V (INPUT APPLIED) VIN 0.1/uni03BCF 402k 402k 4.7/uni03BCF D BST1 BST2 2.2nF 100k 4.7/uni03BCF A C FB1 TG1 BST1 SW1 BG1 SNSP1 SNSN1 PGND BG2 SW2 BST2 TG2 LT8210 SYNC/ SPRD DG SNSN2 EN/UVLO GATEVCC VDD VC2 FB2 IMON PWGD MODE1 VINP MODE2 EXTVCC VOUT SNSP2 0.1/uni03BCF 5V BATTERY 100/uni03BCF +4.7/uni03BCF 100/uni03BCF VIN 5.62MEG 220pF 16.9k VC1GNDSSRT 60.4k 2.2nF220pF 38.3k 0.1/uni03BCF
8210 TA02
(400kHz) VDD 4.7/uni03BCF DBST1 DBST2 604k 604k MOSFETS A, B, DG: INFINEON BSZ150N10LS3 MOSFETS C, D: INFINEON BSZ036NE2LS DBST1, DBST2: DIODES INC. US1GWF L1: 4.2/uni03BCH WURTH ELECTRONICS 744325420 REGULATES: 3.5V TO 100V SURVIVES: –40V TO 100V IIN(NO LOAD) = 55/uni03BCA WHEN VIN = 12V IOUT = 1.9/uni03BCA WHEN INPUT DISCONNECTED/DISABLED DG RUN/STOP CONTROL Low Quiescent Current Battery Backup Power Supply Utilizing Pass-Thru Mode PART NUMBER DESCRIPTION COMMENTS LTC3779 150V VIN and VOUT Synchronous 4-Switch Buck-Boost Controller 4.5V ≤ VIN ≤ 150V, 1.2V ≤ VOUT ≤ 150V, Up to 99% Efficiency Drives Logic Level or STD Threshold MOSFETs, TSSOP-38 LTC 3777 150V VIN and VOUT Synchronous 4-Switch Buck-Boost Controller + Switching Bias Supply 4.5V ≤ VIN ≤ 150V, 1.2V ≤ VOUT ≤ 150V, Up to 99% Efficiency Drives Logic Level or STD Threshold MOSFETs, TSSOP-38 LT8705A 80V VIN and VOUT Synchronous 4-Switch Buck-Boost DC/DC Controller 2.8V ≤ VIN ≤ 80V, Input and Output Current Monitor , 5mm × 7mm QFN-28/TSSOP-38 LTC7813 60V Low IQ Synchronous Boost + Buck Controller Low EMI and Low Input/Output Ripple 4.5V (Down to 2.2V After Start-Up) ≤ VIN ≤ 60V, Boost VOUT Up to 60V, 0.8V < Buck VOUT < 60V, IQ = 29μA, 5mm × 5mm QFN-32 LT8390A High Efficiency Synchronous 4-Switch Buck-Boost Controller 4V ≤ VIN ≤ 60V, VOUT Range: 1V to 60V, ±1.5% Output Voltage Accuracy 4mm × 5mm QFN-2/TSSOP-28 Packages LTM 8056 58V Buck-Boost DC/DC μModule Regulator , Adjustable Input and Output Current Limiting 5V ≤ VIN ≤ 58V, 1.2V ≤ VOUT ≤ 48V 15mm × 15mm × 4.92mm LTC3895/LTC7801 150V Low IQ, Synchronous Step-Down DC/DC Controller with 100% Duty Cycle 4V ≤ VIN ≤ 140V, 150V Abs Max, PLL Fixed Frequency 50kHz to 900kHz, 0.8V ≤ VOUT ≤ 60V, Adjustable 5V to 10V Gate Drive, IQ = 40μA 4mm × 5mm QFN-24/TSSOP-24/TSSOP-38(31) LTC7103 105V, 2.3A Low EMI Synchronous Step-Down Regulator 4.4V ≤ VIN ≤ 105V, 1V ≤ VOUT ≤ VIN, IQ = 2μA Fixed Frequency 200kHz to 2MHz, 5mm × 6mm QFN