LT80602 AD | Alldatasheet
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LT80602, LT80603 3V to 65V, 2.5A/3.5A/4.5A Synchronous Step-Down Silent Switcher with 8μA Quiescent Current Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT
FEATURES
Silent Switcher® Architecture Ultralow EMI Emissions Spread Spectrum Frequency Modulation High Efficiency at High Frequency Up to 94.3% at 400kHz, 90% at 2.1MHz, 24VIN to 5VOUT Up to 95.6% at 400kHz, 91.1% at 2.1MHz, 48VIN to 12VOUT Pin Selectable Fixed 3.3V, Fixed 5V, or Adjustable Output from 0.8V to 99% of VIN Low Quiescent Current Burst Mode Operation 8μA IQ Regulating 24VIN to 5VOUT On-the-Fly Mode Change Among Burst Mode, Pulse-Skipping Mode, and FCM Built-in Output-Voltage Monitoring and Die Temperature Monitoring with PG/TJ 200kHz to 3MHz Adjustable Switching Frequency with External Clock Synchronization 80V Transient-Input Tolerant (LT8060xHV) Programmable Soft-Start and Tracking Small 17-Lead 3mm × 3mm Quad Flat No-lead (QFN)
APPLICATIONS
General Purpose Step-Down Automotive and Industrial Supplies GENERAL DESCRIPTION The LT8060x and LT8060xHV step -down regulators family feature the Silent Switcher® architecture to minimize electromagnetic interference (EMI) emissions while delivering high efficiency at frequencies up to 3MHz. The LT80602 and LT80602HV deliver up to 2.5A continuous current, the LT80603 and LT80603HV support up to 3.5A, and the LT80603A and LT80603AHV provide up to 4.5A continuous current. An ultralow 8µA quiescent current, with the output in full regulation, enables applications requiring the highest efficiency at light loads. An accurate enable threshold can be set using the EN/UV pin and a resistor at the RT pin to program the switch frequency. The LT8060x and LT8060xHV enable high-VIN to low-VOUT conversion at high frequency, featuring a production - tested fast minimum top-switch on-time of 25ns (typ). In addition, the device features a PG/T J pin that can be used to monitor the status of the output voltage or the die temperature. The die temperature monitor allows for direct measurement of the silicon die temperature, enabling a robust and reliable power supply design. GENERIC PART NUMBER AbsMax VIN LT8060x 70V LT8060xHV 80V SIMPLIFIED APPLICATION DIAGRAM Figure 1. Typical Application Circuit Figure 2. Efficiency vs. Load Current
Data Sheet LT80602, LT80603 analog.com Rev. 0 2 of 52 TABLE OF CONTENTS
Data Sheet LT80602, LT80603 analog.com Rev. 0 3 of 52
Data Sheet LT80602, LT80603 analog.com Rev. 0 4 of 52
REVISION HISTORY
0 1/26 Initial release —
Table 1. Electrical Characteristics
Data Sheet LT80602, LT80603 analog.com Rev. 0 6 of 52 (VIN1 = VIN2 = VIN = VEN/UV = 24V, RT = unconnected (fSW = 400kHz), CINTVCC = 2.2µF, VGND = VGND1 = VGND2 = VBIAS/VOUT = 0V, VSYNC/MODE = 0V , VFB/Vos = 0.84V, SW = TR/SS = PG/TJ = unconnected, VBST to VSW = 1.8V, TJ = −40°C to +150°C, unless otherwise noted. Typical values are at TA = +25°C. All voltages are referenced to GND, unless otherwise noted. 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS BIAS/VOUT BIAS/VOUT Operating Voltage Range 2.35 25.00 V BIAS/VOUT Switchover Threshold VBIAS/VOUT Rising 2.24 2.30 2.35 V VBIAS/VOUT Falling 2.135 2.200 2.250 V BIAS/VOUT Shutdown Current VEN/UV = 0V, VBIAS/VOUT = 12V 0 μA BIAS/VOUT Current Consumption VBIAS/VOUT = 3.3V, fSW = 2MHz 13 mA POWER MOSFETS High-Side NMOS On-Resistance RDS-ONH ISW = 1A, Sourcing 105 200 mΩ Low-Side NMOS On-Resistance RDS-ONL ISW = 1A, Sinking 50 105 mΩ SW Leakage Current ISW_LKG VIN = 65V, VSW = 0V, 65V, TA = TJ = +25°C -5.5 +5.5 μA VIN = 65V, VSW = 0V, 65V, LT8060xAFOA/VY+ and LT8060xAFOAH/VY+ Only -20 110 μA TRACKING and SOFT-START (TR/SS) Charging Current ISS VTR/SS = 0.3V 4.675 5.000 5.300 μA TR/SS Pull-Down Resistance Fault Condition, TR/SS = 0.1V 4 Ω FEEDBACK (FB) FB Regulation Voltage VFB-REG 0.792 0.800 0.808 V BIAS/VOUT Regulation Voltage VFB/Vos = INTVCC 4.95 5.00 5.05 V VFB/Vos = Float 3.26 3.30 3.33 V FB/VOS Input Bias Current IFB VFB/Vos = 1V (TA = TJ = +25°C) −50 +50 nA VFB/Vos = 1V, LT8060xAFOA/VY+ and LT8060xAFOAH/VY+ Only -100 +100 nA SYNC/MODE MODE Threshold VSYNC/MODE-Float SYNC/MODE = Float 0.835 0.935 V VSYNC/MODE-High SYNC/MODE = INTVCC 1.3 V VSYNC/MODE -Low SYNC/MODE = GND 0.5 V
Data Sheet LT80602, LT80603 analog.com Rev. 0 7 of 52 (VIN1 = VIN2 = VIN = VEN/UV = 24V, RT = unconnected (fSW = 400kHz), CINTVCC = 2.2µF, VGND = VGND1 = VGND2 = VBIAS/VOUT = 0V, VSYNC/MODE = 0V , VFB/Vos = 0.84V, SW = TR/SS = PG/TJ = unconnected, VBST to VSW = 1.8V, TJ = −40°C to +150°C, unless otherwise noted. Typical values are at TA = +25°C. All voltages are referenced to GND, unless otherwise noted. 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SYNC Frequency Capture Range fSYNC fSW set by RT 1.0 x fSW 1.4 x fSW kHz Minimum SYNC High Pulse Width 66 ns Minimum SYNC Low Pulse Width 66 ns CURRENT LIMIT Peak Current-Limit Threshold IPEAK-LIMIT LT80602 and LT80602HV 4.09 4.81 5.53 A LT80603 and LT80603HV 4.75 5.50 6.75 A LT80603A and LT80603AHV 5.40 6.30 7.20 A Bottom Power N- channel Metal-Oxide- Semiconductor (NMOS) Current Limit 3.9 A Valley Current-Limit Threshold IVALLEY-LIMIT Pulse-Skipping Mode, Burst Mode +70 mA FCM −2.5 A ILIM Blanking Before Device Enters HICCUP TILIMBLANK 2 20 ms HICCUP Timeout 2 130 ms RT Switching Frequency fSW RT = 78.7kΩ 175 205 237 kHz RT = Open 370 400 435 kHz RT = 24.9kΩ 760 800 864 kHz RT = INTVCC 1910 2100 2250 kHz RT = 5.23kΩ 2780 3050 3325 kHz Minimum On-Time tON-MIN All Modes, IOUT = 1A 25 40 ns Minimum Off-Time tOFF-MIN All Modes, VIN ≥ VIN(MIN) 160 190 ns Maximum High-Side Switch On-Time All Modes 15 μs Spread Spectrum Modulation Frequency Range LT8060xAFOA/VY+ and LT8060xAFOAH/VY+ Only 20 % Spread Spectrum Modulation Frequency LT8060xAFOA/VY+ and LT8060xAFOAH/VY+ Only 12 kHz
Data Sheet LT80602, LT80603 analog.com Rev. 0 8 of 52 (VIN1 = VIN2 = VIN = VEN/UV = 24V, RT = unconnected (fSW = 400kHz), CINTVCC = 2.2µF, VGND = VGND1 = VGND2 = VBIAS/VOUT = 0V, VSYNC/MODE = 0V , VFB/Vos = 0.84V, SW = TR/SS = PG/TJ = unconnected, VBST to VSW = 1.8V, TJ = −40°C to +150°C, unless otherwise noted. Typical values are at TA = +25°C. All voltages are referenced to GND, unless otherwise noted. 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PG/TJ (OUTPUT VOLTAGE MONITOR OPERATION) PG/TJ Output Leakage Current IPGLKG TA = TJ = +25°C, VPG/TJ = 5.5V −50 +50 nA VPG/TJ = 5.5V, LT8060xAFOA/VY+ and LT8060xAFOAH/VY+ Only -100 +1900 nA PG/TJ Upper Threshold Offset from VFB/VOS VFB-OV VFB Rising 8 10 12 % PG/TJ Lower Threshold Offset from VFB/VOS VFB-UV VFB Falling −11.0 −8.5 −6.5 % PG/TJ Delay after FB/Vos Reaches 93% Regulation 200 μs PG/TJ Pull-Down Resistance 60 Ω PG/TJ (DIE TEMPERATURE MONITOR OPERATION) PG/TJ Pin Voltage VT25 TA = +25°C; PG/TJ = 20kΩ, Connected to GND 580 595 610 mV PG/TJ Pin Voltage Variation with Respect to Die Temperature dVTJ/dT 2 mV/°C THERMAL SHUTDOWN (TEMP) Thermal Shutdown Threshold Temperature Rising 175 °C Thermal Shutdown Hysteresis 10 °C Electrical specifications are production tested at T A = +25 °C. Specifications over the entire operating temperature range are guaranteed by design and characterization. The device is designed for continuous operation up to T J = 125°C for 95,000 hours and T J = 150°C for 5,000 hours. 2 See the Overcurrent Protection (OCP)/Hiccup Mode section for more details.
Table 2. Absolute Maximum Ratings 1 Junction temperature greater than +125°C degrades operating lifetimes. extended periods may affect product reliability.
Figure 3. LT8060x and LT8060xHV Pin Configuration Table 3. Pin Descriptions
2 BST
the IC. See the BST Capacitor Selection section for more details.
3 VIN1
Application Information section for the sample layout. Application Information section for the sample layout.
Data Sheet LT80602, LT80603 analog.com Rev. 0 11 of 52 PIN NAME DESCRIPTION 7, 8 GND2 Power Switch Ground. This pin is the return path of the internal bottom-side power switch. Also, be sure to tie GND2 to the ground plane. See the Application Information section for a sample layout.
9 VIN2
Power Supply Input Pin. The LT8060x and LT8060xHV require two 0.1µF small-input bypass capacitors. One 0.1µF capacitor should be placed between VIN1 (pin 3) and GND1 (pin 4). A second 0.1µF capacitor should be placed between VIN2 (pin 9) and GND2 (pin 8). These capacitors must be placed as close as possible to the LT8060x and LT8060xHV. A third larger capacitor of 4.7µF or more should be placed close to the LT8060x, and LT8060xHV, with the positive terminal connected to VIN1 and VIN2, and the negative terminal connected to ground. See the Application Information section for the sample layout.
10 EN/UV
Enable/Undervoltage Lockout Pin. The LT8060x and LT8060xHV are shut down when this pin is low and active when it is high. The enable threshold voltage is 1V rising and 0.9V falling. Tie this pin to VIN if the shutdown feature is not required. To program a VIN threshold below which the LT8060x and LT8060xHV shut down, use an external resistor divider from VIN.
11 BIAS/VOUT
External Bias input for LDO. Connect the BIAS/VOUT pin to the converter output- voltage node for output voltages ranging from 2.35V to 25V for improved efficiency. If this pin is tied to a supply other than VOUT, use a 1µF local bypass capacitor on this pin. Connect the BIAS/VOUT pin to GND when this feature is not in use. The BIAS/VOUT pin should be tied to VOUT for programming internal 5V or 3.3V output. See the INTVcc Regulator section for more details.
12 FB/Vos
Output Feedback/Fixed Output Voltage Selection Pin. Output is sensed and regulated through this pin, when a resistor divider is connected to this pin from VOUT to GND. This pin can also be used to select the internal VOUT options by either connecting to INTVCC or leaving it floating. Choose maximum RFB-TOP or RFB-BOTTOM such that the maximum effective impedance at FB/VOS is less than 170kΩ. 13 RT Switching Frequency Programming Input Pin. A resistor is tied between RT and ground to set the switching frequency between 200kHz and 3MHz. Leave the RT pin floating to program the device to 400kHz. Connect the RT pin to INTVCC for programming the device to 2100kHz.
14 TR/SS
Output Tracking and Soft-Start Pin. This pin allows control of the output voltage ramp rate during start-up. A TR/SS voltage below the internal reference voltage of 0.8V forces the LT8060x and LT8060xHV to regulate the feedback node equal to the TR/SS pin voltage. When the TR/SS voltage is above the internal reference voltage of 0.8V, the tracking function is disabled, and the internal reference resumes control of the error amplifier. An internal 5μA pull-up current from INTVcc on this pin allows a capacitor to program the output-voltage slew rate. This pin is pulled to ground with an internal 4Ω MOSFET during shutdown and fault conditions; use a series resistor if driving from a low-impedance output. 15 SYNC/MODE Mode Selection Input/ External Clock Synchronization Input Pin. This pin programs four different operating modes:
Data Sheet LT80602, LT80603 analog.com Rev. 0 12 of 52 PIN NAME DESCRIPTION Burst Mode. Tie this pin to GND for Burst Mode operation at light loads. This results in ultralow quiescent current. Pulse-skipping mode. Leave this pin unconnected for pulse-skipping mode. This mode offers full-frequency operation down to low output loads before pulse skipping occurs. Forced continuous mode (FCM). This mode offers fast transient response and full-frequency operation over a wide load range. Tie this pin to INTVCC or a voltage more than 1.3V for FCM. Synchronization mode. Drive this pin with a clock source to synchronize to an external frequency. During synchronization, the part operates in forced- continuous mode. See the Mode Selection and External Clock Synchronization (SYNC/MODE) section for more details.
16 PG/TJ
Open-Drain Status Output/ Die Temperature Monitor Output Pin. The output voltage status can be monitored by connecting the PG/TJ pin to a power supply through a pull-up resistor. The PG/TJ output is driven low if the feedback node voltage falls below 91.5% of the internal reference voltage (0.8V) or increases above 110% of the internal reference voltage (0.8V). PG/TJ goes high after a delay of 200µs whenever the feedback node voltage reaches within +10%/−8.5% of the internal reference voltage (0.8V). The PG/TJ pin can also be used to monitor the die temperature of the device by connecting a 20kΩ resistor from the PG/TJ pin to GND. See the Output Power Good and Die Temperature Monitor section for more details. During fault conditions like thermal shutdown, VIN UVLO, and VCC UVLO, this pin is pulled low, and die temperature monitoring is not supported. The die temperature monitoring is also not supported during low IQ Burst Mode.
17 INTVCC
1.8V Linear Regulator Output Pin. The internal power drivers and control circuits are powered from this voltage. Decouple this pin to GND with at least a 2.2µF low ESR ceramic capacitor placed close to the IC. Do not load the INTVCC pin with external circuitry. See the INTVcc Regulator section for more details. ─ EP Exposed Pad. Internally connected to VIN1 and VIN2 pins. Always connect EP to the VIN1 and VIN2 pins on the PCB using a plane. Refer to the LT80603 evaluation board user guide for a layout example.
Figure 4. LT8060x and LT8060xHV Functional Diagram
Data Sheet LT80602, LT80603 analog.com Rev. 0 26 of 52 OPERATION The LT8060x and LT8060xHV are monolithic, constant -frequency, current-mode, step-down DC/DC converters. The LT80602 and LT80602HV support up to 2.5A continuous current, the LT80603 and LT80603HV support up to 3.5A, and the LT80603A and LT80603AHV support u p to 4.5A continuous current. An oscillator, whose frequency is set by a resistor on the RT pin, turns on the internal top power switch at the beginning of each clock cycle. The current in the inductor then increases until the top switch current comparator trips and turns off the top power switch. The peak inductor current at which the top switch turns off is controlled by the voltage on the internal V C node. The error amplifier servos the VC node by comparing the feedback node voltage with an internal 0.8V reference. When the load current increases, it causes a reduction in the feedback node voltage relative to the reference, leading the error amplifier to raise the VC voltage until the average inductor current matches the new load current. When the top power switch turns off, the synchronous power switch turns on until the next clock cycle begins, or in Burst Mode and pulse- skipping mode, the inductor current falls to zero. If overload conditions result in the top switch turning OFF by a peak current limit event, 4.81A (typ) for LT80602 and LT80602HV, 5.5A (typ) for LT80603 and LT80603HV and 6.3A for LT80603A and LT80603AHV, the synchronous low -side power switch turns ON and remains ON, till the current through the synchronous low-side switch current returns to a safe level (3.9A). If the current returns to a safe level (3.9A) within the same clock cycle, then the low-side switch remains ON for the remainder of the clock cycle. If the EN/UV pin is below the true shutdown voltage (0.45V), the LT8060x and LT8060xHV are shut down and draw 0.75μA from the input. When the EN/UV pin is above 1V, the switching regulator becomes active. To optimize efficiency at light loads, the LT8060x and LT8060xHV operate in Burst Mode operation in light load situations. Between bursts, all circuitry associated with controlling the output switch is shut down, reducing the input supply current consumed by the device. In a typical application, 8μA is consumed from the input supply when regulating with no load. The SYNC/MODE pin is connected to GND to program Burst Mode operation and should be left unconnected to program pulse-skipping mode. For forced continuous mode (FCM), the SYNC/MODE pin should be tied to INTVCC or a voltage greater than 1.3V. If a clock is applied to the SYNC/MODE pin, the device synchronizes to an external clock frequency and operates in forced continuous mode. While in pulse -skipping mode, the oscillator operates continuously, and positive SW transitions are aligned to the clock. During light loads, switch pulses are skipped to regulate the output, and the quiescent current is several hundred μA. The LT8060x and LT8060xHV can operate in forced continuous mode (FCM) for fast transient response and full frequency operation over a wide load range. In FCM, the oscillator operates continuously, and positive SW transitions are aligned to the clock. N egative inductor current is allowed. The LT8060x/LT8060xHV can sink current from the output and return this charge to the input in this mode, thereby improving load-step transient response. To improve EMI performance, LT8060x and LT8060xHV offer spread spectrum mode. This feature varies the clock with a triangular frequency modulation depth of +20%. For example, if the LT8060x and LT8060xHV’s frequencies are programmed to switch at 2MHz, spread spectrum mode modulates the oscillator between 2MHz and 2.4MHz. Spread spectrum modulation is available when the device is configured in Pulse -Skipping Mode, FCM, or Burst Mode. To improve efficiency across all loads, supply current to internal circuitr y can be sourced from the BIAS/V OUT pin when biased at 2.35V or above. Otherwise, the internal circuitry draws current from V IN. The BIAS/V OUT pin should be connected to VOUT if the LT8060x and LT8060xHV’s outputs are programmed at 2.35V to 25V. Comparators monitoring the FB node voltage pull the PG/TJ pin low if the output voltage varies more than +10% or −8% (typical) from the set point, or if a fault condition is present. In addition, the device features a die temperature monitor to directly measure the silicon die temperature, instead of relying on theoretical estimation, thus enabling robust, reliable power supply design.
Data Sheet LT80602, LT80603 analog.com Rev. 0 27 of 52
APPLICATION INFORMATION
The LT8060x and LT8060xHV are specifically designed to minimize EMI emissions and maximize efficiency when switching at high frequencies. For optimal performance, the LT8060x and LT8060xHV require the use of multiple VIN bypass capacitors. Two small 0.1 μF capacitors should be placed as close as possible to the LT8060x and LT8060xHV. One capacitor should be tied to V IN1 (pin 3) and GND1 (pin 4). A second capacitor should be tied to V IN2 (pin 9) and GND2 (pin 8). A third capacitor with a larger value, 4.7μF or higher, should be placed near VIN1 or VIN2. See Figure 73 for a recommended PCB layout. For more details and PCB design files, refer to the LT80603 evaluation board user guide. Note that large, switched currents flow in the LT80603 V IN1, VIN2, GND1, and GND2 pins, and the input capacitors (CIN1, CIN2). The loops formed by the input capacitors should be as small as possible by placing the capacitors adjacent to the V IN1, V IN2, and GND1 or GND2 pins. Capacitors with a small case size, such as 0603, are optimal due to the lowest parasitic inductance. The input capacitors, along with the inductor and output capacitors, should be placed on the same side of the circuit board, and their connections should be made on that layer. Place a local, unbroken ground plane under the application circuit on the layer closest to the surface layer. The SW and BST nodes should be as small as possible. Finally, keep the FB/V os and RT nodes small so that the ground traces shield them from the SW and BST nodes. A bypass capacitor for the INTVCC pin should also be placed close to the pin to reduce the effects of trace impedance. To keep thermal resistance low, extend the ground plane from GND1 and GND2 as much as possible, and add thermal vias to additional ground planes within the circuit board and on the bottom side. Mode Selection and External Clock Synchronization (SYNC/MODE) The LT8060x and LT8060xHV support forced continuous mode (FCM), Burst (ultralow quiescent current) Mode, and pulse skipping modes of operation. The device enters the programmed mode of operation based on the setting of the MODE/SYNC pin. If the MODE/SYNC pin is high (> VSYNC/MODE-High), the device operates in a constant-frequency FCM mode at all loads. If the MODE/SYNC pin is low (< VSYNC/MODE-Low), the device operates in Burst Mode at light loads. If the MODE/SYNC pin is left open, the device operates in p ulse skip mode at light loads. The device supports on -the-fly mode change. When there is a state transition on the MODE/SYNC pin, the device waits for 60µs and transitions into the mode based on the MODE/SYNC pin voltage at the end of the 60µs period. During sleep mode, transition can be detected only at the next IPK-BURST pulse. The MODE/SYNC pin can also be used to synchronize the internal oscillator of the device to an external clock in all three modes of operation. To synchronize the LT8060x and LT8060xHV oscillator to an external frequency, connect a square wave to the SYNC/MO DE pin. The square wave amplitude should have valleys below 0.5V and peaks above 1.3V (up to 5V). The external clock frequency must be between 1.0 × f SW and 1.4 × f SW, where fSW is the programmed switching frequency. When an external clock is applied to the MODE/SYNC pin, if eight or more external clock rising edges are detected in 60µs, the device operates in FCM mode and the internal oscillator frequency changes to the external clock frequency at the end of the 60µs period. When the external clock is removed, the device continues to operate in FCM mode for 60µs and enters a mode based on the SYNC/MODE pin status. The external clock logic high and low pulse widths should be more than 66ns.
the output capacitor, followed by sleep periods in which the output power is supplied by the output capacitor. Figure 73. Recommended PCB Layout for the LT80603 In a typical application circuit, the quiescent current can be reduced by connecting the V OUT to the BIAS/V OUT pin.
resistor divider must be minimized to improve the quiescent current performance. is desired, a higher inductor value should be chosen. See the curve in Typical Performance Characteristics. but only up to the switching frequency programmed by the resistor at the RT pin, as shown in Figure 74. Figure 74. Output Current vs. Switching Frequency and comparable with FCM mode. To program pulse-skipping mode, leave the SYNC/MODE pin unconnected. converter starts monotonically.
Figure 75. Load-Step Transient Performance with Burst and FCM Modes spectrum operation is unavailable when the device is synchronized to an external clock. necessary RT values for desired switching frequencies. resistor values for a few common switching frequencies. Table 4. Switching Frequency vs. RT Resistor
Data Sheet LT80602, LT80603 analog.com Rev. 0 31 of 52 Operating Frequency Selection and Trade-Offs Selection of the operating frequency is a trade-off between efficiency, component size, and input voltage range. The advantage of high frequency operation is that smaller inductor and capacitor values can be used. The disadvantages are lower efficiency and a smaller input voltage range. The highest switching frequency (fSW(MAX)) for a given application can be calculated by Equation 3. fSW(MAX) = VOUT + VSW(BOT) tON(MIN) × (VIN - VSW(TOP) + VSW(BOT)) (3) where, VIN is the typical input voltage, V OUT is the output voltage, V SW(TOP) and VSW(BOT) are the internal switch drops (~0.3V, ~0.15V, respectively, at maximum load), and tON(MIN) is the minimum top switch on-time (see the Specifications section). Equation 3 shows that a slower switching frequency is necessary to accommodate a high VIN/VOUT ratio. For transient operations, VIN may reach 65V regardless of the RT value. However, the LT8060x and LT8060xHV reduce switching frequency as necessary to maintain control of the inductor current, ensuring safe operation. The LT8060x and LT8060xHV are capable of a maximum duty cycle of approximately 99%, and the VIN-to-VOUT dropout is limited by the RDS(ON) of the top switch. In this mode, the LT8060x and LT8060xHV skip switch cycles, resulting in a lower switching frequency than programmed by the RT resistor. For applications that cannot allow deviation from the programmed switching frequency at low V IN/VOUT ratios, use Equation 4 to set the switching frequency. VIN(MIN)= VOUT + VSW(BOT) 1 - (fSW × tOFF-MIN) - VSW(BOT)+ VSW(TOP) ( 4) where, VIN(MIN) is the minimum input voltage without skipped cycles, VOUT is the output voltage, VSW(TOP) and VSW(BOT) are the internal switch drops (~0.3V, ~0.15V, respectively, at maximum load), f SW is the switching frequency (set by R T), and t OFF(MIN) is the minimum switch off -time. Note that higher switching frequency increases the minimum input voltage, below which cycles are dropped to achieve a higher duty cycle. High Duty Operation The LT8060x and LT8060xHV feature high -duty operation, which enhances the output -to-input voltage ratio. To regulate the output voltage with an input voltage close to the output voltage, the operating switching frequency is reduced by skipping off -time pul ses. The high -duty operation extends the high -side switch on time beyond the programmed switching cycle, until the inductor peak current reaches the reference set by the controller or Burst Mode peak current limit (IPEAK-BURST). After the high-side switch is turned off, the low-side switch is turned on, and the next switching cycle starts with the rising edge of the clock signal. In scenarios where the maximum on -time (15μs + up to one programmed t SW) is reached, the high -side switch is turned off for a minimum off-time (tOFF-MIN), and the low-side switch is turned on. After the tOFF-MIN, the new switching cycle starts. When the device is synchronized to an external clock with f SYNC frequency, the operating switching frequency is reduced in discrete fractions of the external clock frequency (f SYNC/2, f SYNC/3, and so on). SW rising edges are synchronized to the external clock.
Data Sheet LT80602, LT80603 analog.com Rev. 0 32 of 52 Inductor Selection and Maximum Output Current The LT8060x and LT8060xHV are designed to minimize solution size by allowing the inductor to be selected based on the output load requirements of the application. During overload or short -circuit conditions, the LT8060x and LT8060xHV safely tolerate operation with a saturated inductor with a high-speed peak-current mode architecture. For LT8060x and LT8060xHV, a good first choice for the inductor value is calculated by Equation 5. L = (VOUT fSW ) × K1 ( 5 ) where, fSW is the switching frequency in MHz, V OUT is the output voltage, and L is the inductor value in μH. K1 = 0.75 for LT80602 and LT80602HV, K1 = 0.65 for LT80603 and LT80603HV, K1 = 0.55 for LT80603A and LT80603AHV. To avoid overheating and poor efficiency, an inductor must be chosen with an RMS current rating greater than the maximum expected output load of the application. In addition, the saturation current (typically labeled I SAT) rating of the inductor must be higher than the load current plus 1/2 of the inductor ripple current. IL(PEAK) = ILOAD(MAX) + 1 2 ΔIL ( 6 ) where, ∆IL is the inductor ripple current, as calculated in Equation 6, and I LOAD(MAX) is the maximum output load for a given application. As a quick example, an application requiring 3.5A output should use an inductor with an RMS rating of greater than 3.5A and an I SAT of greater than 5.5A. During long -duration overload or short -circuit conditions, the inductor’s root mean square (RMS) rating requirement is greater to avoid overheating of the inductor. To maintain high efficiency, the series resistance (DCR) should be less than 15mΩ, and the core material should be intended for high -frequency applications. The LT8060x and LT8060xHV limit the peak switch current to protect the switches and the system from overload faults. The typical top switch current limit (I LIM) is 5.5A for the LT80603 and LT80603HV, 4.81A for the LT80602 and LT80602HV, 6.3A for the LT80603A and LT80603AHV. The inductor value must then be sufficient to supply the desired maximum output current (I OUT(MAX)), which is a function of the switch current limit (I LIM) and the ripple current (Equation 7). IOUT(MAX) = ILIM - 1 2 ΔIL ( 7) The peak-to-peak ripple current in the inductor can be calculated using Equation 8. ΔIL= VOUT L × fSW × (1 - VOUT VIN(MAX) ) (8) where, fSW is the switching frequency of the LT8060x and LT8060xHV, and L is the value of the inductor. Therefore, the maximum output current delivered by the LT8060x and LT8060xHV depends on the switch current limit, inductor value, and input and output voltages. The inductor value may need to be increased if the inductor ripple current does not allow sufficient maximum output current (I OUT(MAX)) given the switching frequency, and maximum input voltage used in the desired application. The optimum inductor for a given application may differ from the one indicated by this design guide. A larger-value inductor provides a higher maximum load current and reduces the output voltage ripple. For applications requiring smaller load currents, the value of the inductor may be lower, and the LT8060x and LT8060xHV may operate with higher ripple current. This allows the use of a physically smaller inductor, or one with a lower direct current resistance (DCR), resulting in higher efficiency. Be aware that low inductance may reduce the maximum load current.
Data Sheet LT80602, LT80603 analog.com Rev. 0 33 of 52 For duty cycles greater than 50% (VOUT/VIN > 0.5), a minimum inductance is required to avoid subharmonic oscillation (see Equation 9). Refer to the Analog Devices Application Note 19 for more details. LMIN = VIN K2 × fSW × (2 × DC - 1) (9) where, DC is the duty cycle, and fSW is the switching frequency. K2 = 1 for LT80602 and LT80602HV, K2 = 1.2 for LT80603 and LT80603HV, K2 = 1.4 for LT80603A and LT80603AHV. Input Capacitors The V IN of the LT8060x and LT8060xHV should be bypassed with at least three ceramic capacitors for best performance. Two small ceramic capacitors, 0.1µF, each, should be placed close to the device: one at the VIN1/GND1 pins and a second at the VIN2/GND2 pins. These capacitors should be 0402 or 0603 in size. For automotive applications requiring two series input capacitors, two small capacitors (0402 or 0603) may be placed at each side of the LT8060x and LT8060xHV near the VIN1/GND1 and VIN2/GND2 pins. A third, larger ceramic capacitor of 4.7µF or greater should be placed close to VIN1 or VIN2. See the Low EMI PCB Layout section for more details. X7R or X5R capacitors are recommended for best performance across temperature and input voltage variations. Note that a larger input capacitance is required when a lower switching frequency is used. If the input power source has high impedance, or there is significant inductance due to long wires or cables, additional bulk capacitance may be necessary. This can be provided with a low-performance electrolytic capacitor. A ceramic input capacitor combined with trace or cable inductance forms a high-quality (underdamped) tank circuit. If the LT8060x and LT8060xHV circuits are plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the LT8060x and LT8060xHV’s voltage rating. Refer to the Analog Devices Application Note 88 for more details. In applications where the source is located far from the device input, an appropriate electrolytic capacitor should be added in parallel with the ceramic capacitor to provide the necessary damping to prevent potential oscillations caused by the inductance of the longer input power path and the input ceramic capacitor. Output Capacitor and Output Ripple The output capacitor has two essential functions. Along with the inductor, it filters the square wave generated by the LT8060x and LT8060xHV to produce the DC output. The second function is to store energy to satisfy transient loads and stabilize the LT8060x and LT8060xHV’s control loop. For good starting values, see Typical application circuits for LT80603 and LT80603HV, Table 5 for LT80602 and LT80602HV, Table 6 for LT80603A and LT80603AHV. X5R/X7R/X8M ceramic output capacitors have very low equivalent series resistance (ESR) and are preferred for their temperature stability in industrial applications. This choice provides low output ripple and good transient response. Transient performance c an be improved with a higher value output capacitor and an appropriate feedforward capacitor placed between V OUT and FB/V OS. Increasing the output capacitance also decreases the output voltage ripple. A lower value for the output capacitor can save space a nd cost, but transient performance suffers and may cause loop instability. The choice of output capacitance is influenced by the closed -loop bandwidth. When the RT pin is left floating or connected with a resistor to GND, the maximum recommended bandwidth is approximately f SW/10 or 80kHz. The LT8060x and LT8060xHV offer a unique feature when the RT pin is connected to INTV CC. The internal compensation parameters are selected to facilitate a high bandwidth exceeding 150kHz. This enhanced bandwidth improves the
Actual derating of ceramic capacitors under DC bias voltage must be considered when selecting the output capacitor. Derating curves are available from all major ceramic capacitor manufacturers. resistor values according to Equation 10. RFB-BOT to 205kΩ such that the maximum effective impedance at FB/VOS is less than 170kΩ. device, which is approximately given by Equation 11. current from the 24V supply. Note that Equation 11 implies that the no-load current is a function of VIN. shifts to lower frequencies. Figure 76. Setting the Output Voltage voltages. The internal feedback divider is connected to the BIAS/VOUT pin.
Table 5. Typical Component Values for LT80602 Table 6. Typical Component Values for LT80603A
3.3 External FB Divider 2100 1 1 x 47µF, 10V, 1210 + 1 x
ceramic capacitors are also available. situation can be easily avoided. Refer to Analog Devices Application Note 88 for more details. capacitor must be selected appropriately to hold sufficient charge and supply the BST from the SW rail in sleep mode. programmed to operate in pulse-skipping or FCM mode, it is recommended to use a 0.1µF BST to SW capacitor. Table 7. Switching Frequency vs. BST Capacitance
Data Sheet LT80602, LT80603 analog.com Rev. 0 37 of 52 Enable Pin The LT8060x and LT8060xHV are in shutdown when the EN pin is low and active when the pin is high. The rising threshold of the EN comparator is 1V, with a 100mV hysteresis. The EN pin can be tied to VIN if the shutdown feature is not used, or tied to a logic level if shutdown control is required. Adding a resistor divider from VIN to EN/UV programs the LT8060x and LT8060xHV to regulate the output only when VIN exceeds a desired voltage (see the Functional Diagram). Typically, this threshold, V IN(EN), is used when the input supply is current-limited or has a relatively high source resistance. A switching regulator draws constant power from the source. So, the source current increases as the source voltage drops. This is a negative -resistance load to t he source and can cause the source to current -limit or latch low under low -source-voltage conditions. The V IN(EN) threshold ensures the regulator does not operate at source voltages that could cause issues. This threshold can be adjusted by setting REN-TOP and REN-BOTTOM values to satisfy Equation 12. REN-BOTTOM = REN-TOP × 1 (VIN(EN) - 1) (12) where, the LT8060x and LT8060xHV remain off until VIN is above VIN(EN). Due to the comparator’s hysteresis, switching does not stop until the input falls slightly below VIN(EN). When operating in Burst Mode operation for light load currents, the current through the V IN(EN) resistor network can easily be greater than the supply current consumed by the LT8060x and LT8060xHV. Therefore, the V IN(EN) resistors should be large to minimize their effect on efficiency at low loads. INTVcc Regulator An internal low-dropout (LDO) regulator provides the 1.8V supply that powers the drivers and internal bias circuitry. Bypass INTVCC to GND with a minimum of 2.2µF low-ESR ceramic capacitor. The internal low-dropout linear regulator is powered either from VIN or BIAS/VOUT. During soft-start, INTVCC is powered from VIN. At the end of the programmed soft-start time, if the BIAS/VOUT pin voltage is greater than 2.35V, INTVCC switches to BIAS/VOUT. Powering INTVCC from BIAS/VOUT reduces on-chip dissipation and increases efficiency at higher input voltages. Connect the BIAS/VOUT pin to the converter output-voltage node to achieve output voltages ranging from 2.35V to 25V, improving efficiency. If the BIAS/VOUT pin is tied to a supply other than VOUT, use a 1µF local bypass capacitor on this pin. The LT8060x and LT8060xHV start switching only when the voltage at INTV CC is greater than 1.64V. The device employs an undervoltage lockout circuit that forces the converter off when the INTVCC voltage falls below 1.58V. The 65mV hysteresis prevents chattering during power-up/power-down. Connect the BIAS/VOUT pin to GND when not in use. Do not connect an external load to the INTVCC pin. Always connect BIAS/VOUT to the converter’s output of the when programmed to internal 5V or 3.3V, and the internal feedback is connected to BIAS/VOUT.
Data Sheet LT80602, LT80603 analog.com Rev. 0 38 of 52 Output Voltage Tracking and Soft-Start The LT8060x and LT8060xHV allow programming of the output-voltage ramp rate via the TR/SS pin. An internal 5μA pulls up the TR/SS pin to INTV CC. Adding an external capacitor on TR/SS enables soft -starting of the output, preventing a current surge on the input supply. During the soft-start ramp, the output voltage proportionally tracks the TR/SS pin voltage. For output -tracking applications, TR/SS can be externally driven by another voltage source. From 0V to 0.8V, the TR/SS voltage overrides the internal 0.8V reference input to the error amplifier, therby regulating the feedback node voltage to that of the TR/SS pin. When TR/SS is above 0.8V, tracking is disabled, and the feedback node voltage regulates to the internal reference voltage. If the TR/SS voltage is held below 0.78V, regardless of the programmed mode, the device operates in pulse skip mode. During the soft-start operation, if VTR/SS increases above 0.78V, the device transits from pulse skipping mode to programmed mode. Once soft-start is complete, irrespective of the VTR/SS voltage, the device operates in the programmed mode. The selected output capacitance (COUT_SEL) and the output voltage (VOUT) determine the minimum required soft-start capacitor as follows: CSS ≥ 25 × 10-6 × COUT_SEL× VOUT (13) The soft-start time (tSS) is related to the capacitor connected at TR/SS (CSS) by the following equation: tSS = CSS 6.25 × 10-6 (14) An internal 4Ω MOSFET to GND is connected on the TR/SS pin, which discharges the external soft -start capacitor in the case of fault conditions and restarts the ramp when the faults are cleared. Fault conditions that clear the soft - start capacitor are the EN/UV pin transitioning low, VIN voltage falling too low, or thermal shutdown. Output Power Good and Die Temperature Monitor The LT8060x and LT8060xHV offer the PG/TJ pin to monitor either the output voltage status or the die temperature. When the LT8060x and LT8060xHV are used for power good functionality, and the output voltage is within the window of the regulation point specified in the Table 1 (Electrical Characteristics table). The output voltage is considered good, and the open -drain PG/T J pin is in high -impedance mode and is typically pulled high with an external resistor. Otherwise, the internal pull -down device pulls the PG/T J pin low. To prevent glitching both the upper and lower thresholds, include 1% of hysteresis. The PG/TJ pin is also actively pulled low during several fault conditions: EN/UV pin is below 1V, INTVCC has fallen too low, VIN is too low, or thermal shutdown. To monitor the die temperature, connect a 20kΩ resistor from PG/TJ to GND. The die temperature monitor feature is functional only when the output voltage is good, and the internal open -drain power good MOSFET is in high - impedance mode. The die temperature (TJ) in °C is calculated as follows: TJ = (VTJ - 0.595) where, VTJ is the PG/TJ pin voltage in V when the device is loaded. Note: A minimum of 1V pull-up is needed on PG/TJ for the PGOOD functionality to not interact with the TJ loop at HOT and consume quiescent current.
of operation ensures low power dissipation under output short-circuit conditions. The device provides a valley current protection scheme that protects itself in FCM mode from large negative currents. if the output voltage is taken above regulation voltage. a shorted or reversed input. Figure 78. Reverse VIN Protection
Figure 87. 1.8V/3.5A Output with 400kHz Switching Frequency
Figure 88. 24V/3.5A Output with 400kHz Switching Frequency
Figure 91. 12V/3.5A Output with 400kHz Switching Frequency for Ultralow EMI
Table 9. Thermal Resistance of 17L FC2QFN Note 1: Package thermal resistances are obtained using the LT80603 evaluation kit with no airflow. the drawing pertains to the package regardless of RoHS status. Figure 92. Package Outline for Non-Side Wettable Version
Figure 93. Package Outline for Side Wettable Version
Figure 94. Package Land Pattern for Side Wettable/Non-Side Wettable Version
Table 10. Ordering Guide + Denotes a lead (Pb)-free/RoHS-compliant package. ** Potential future product. Contact the factory for other sequence options.
Data Sheet LT80602, LT80603 ALL INFORMATION CONTAINED HEREIN IS PROVIDED “AS IS” WITHOUT REPRESENTATION OR WARRANTY. NO RESPONSIBILITY IS ASSUMED BY ANALOG DEVICES FOR ITS USE, NOR FOR ANY INFRINGEMENTS OF PATENTS OR OTHER RIGHTS OF THIRD PARTIES THAT MAY RESULT FROM ITS USE. SPECIFI CATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. NO LICENCE, EITHER EXPRESSED OR IMPLIED, IS GRANTED UNDER ANY ADI PATENT RIGHT, COPYRIGHT, MASK WORK RIGHT, OR ANY OTHER ADI INTELLECTUAL PROPERTY RIGHT RELATING TO ANY COMBINATION, MACHINE, OR PROCESS, IN WHICH ADI PRODUCTS OR SERVICES ARE USED. TRADEMARKS AND REGISTERED TRADEMARKS ARE THE PROPERTY OF THEIR RESPECTIVE OWNERS. ALL ANALOG DEVICES PRODUCTS CONTAINED HEREIN ARE SUBJECT TO RELEASE AND AVAILABILITY. analog.com Rev. 0 52 of 52