LT7200S Rev. 2
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 38
Technical content
analog.com Rev. 2 2 of 38 TABLE OF CONTENTS
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REVISION HISTORY
0 10/2022 – ─ 1 10/2023 Updated Electrical Characteristics Updated Table 3 5, 6 2 11/2024 Updated Features: Added AEC-Q100 Automotive Qualification Updated Ordering Guide: Added #W option
Table 1. Electrical Characteristics
analog.com Rev. 2 6 of 38 (Specifications are at TA = 25°C. VIN = 12V, unless otherwise noted) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS INTVCC Undervoltage Lockout Threshold VUVLO INTVCC Falling 2.2 2.4 2.6 V INTVCC Hysteresis (Rising) 0.21 RUN Threshold VRUN RUN Rising 1.16 1.2 1.24 V RUN Hysteresis (Falling) 100 mV PGOOD Pull-Down Resistance RPGOOD 1mA Load 5 10 Ω Output Overvoltage PGOOD Upper Threshold OV VFB Rising 4.5 6.5 8.5 % VFB Hysteresis 2 Output Undervoltage PGOOD Lower Threshold UV VFB Falling -9 -7 -5 % VFB Hysteresis 2 PGOOD Leakage IPGOOD VFB = 0.5V 2 µA TRACK Pull-Up Current ITRACK VTRACK = 0V 5 10 µA Internal Soft-Start Time tss 0% to 90% Output Rise Time 115 µs Oscillator Frequency fosc RRT = 100kΩ -40°C ≤ TJ ≤ 125°C 0.9 1 1.1 MHz Oscillator Frequency Range fosc_range RRT = 249kΩ to 33.2kΩ 0.4 3 MHz SYNC Capture Range fSYNC % of Programmed Frequency ±30 % MODE/SYNC Threshold VIH(MODE/SYNC) MODE/SYNC HIGH 1 V VIL(MODE/SYNC) MODE/SYNC LOW 0.3 MODE/SYNC Current IMODESYNC MODE/SYNC = 0V 5 10 µA PHMODE Threshold VPHASEMODE 90° (4 Phase) 0.3 V 120° (3 Phase) 1 1 The LT7200S is tested under pulsed load conditions such that TJ ≈ TA. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization, and correlation with statistical process controls. The LT7200S is guaranteed over the full –40°C to 125°C operating junction temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance, and other environmental factors. The junction temperature (TJ, in °C) is calculated from the ambient temperature (TA, in °C) and power dissipation (PD, in watts) according to the formula: TJ = TA + (PD • θJA), where θJA (in °C/W) is the package thermal impedance. 2 The quiescent current in Discontinuous Mode does not include switching loss of the power FETs. 3 VFB is measured in a feedback loop that servos VITH to a specified voltage. 4 There is additional switch current due to internal resistor to ground.
Table 2. Absolute Maximum Ratings extended periods may affect product reliability.
Figure 3. Pin Configurations Table 3. Pin Descriptions 1 PHMODE Control Input to Phase Selector. Determines the phase relationship of the 4 channels. Tie it to GND for 4-phase operation, tie it to INTVCC for 3-phase operation. GND Ground for Power and Signal Ground. 11 PVIN1 Channel 1 Power VIN . Input voltage to the on-chip Power MOSFETs. 4, 5 PVIN2 Channel 2 Power VIN . Input voltage to the on-chip Power MOSFETs. 34, 35 PVIN3 Channel 3 Power VIN . Input voltage to the on-chip Power MOSFETs. 28, 29 PVIN4 Channel 4 Power VIN . Input voltage to the on-chip Power MOSFETs. a diode voltage drop below ground to a diode voltage above PVIN1.
analog.com Rev. 2 9 of 38 6, 7 SW2 Channel 2 Switch Node Connection of External Inductor. Voltage swing of SW2 is from a diode voltage drop below ground to a diode voltage above PVIN2. 32, 33 SW3 Channel 3 Switch Node Connection of External Inductor. Voltage swing of SW3 is from a diode voltage drop below ground to a diode voltage above PVIN3. 30, 31 SW4 Channel 4 Switch Node Connection of External Inductor. Voltage swing of SW4 is from a diode voltage drop below ground to a diode voltage above PVIN4. 10 SVIN Signal VIN. Filtered input voltage to the on-chip 5V regulator. Bypass signal into the SVIN pin with a 1µF ceramic capacitor.
14 MODE/SYNC
Mode Selection and Oscillator Synchronization Pin. Tie MODE/SYNC to GND for Discontinuous Mode (DCM). Floating MODE/SYNC or tying it to a voltage above 1V selects Forced Continuous Mode (FCM). Furthermore, connecting MODE/SYNC to an external clock synchronizes the system clock to the external clock and puts the part in Forced Continuous Mode (FCM). The synchronization is +/- 30% of the frequency set by the external resistor RRT connected at RT pin. 15 PGOOD1 Channel 1 Output Power Good with Open-Drain Logic. PGOOD1 is pulled to ground when the voltage of the FB1 pin is not within +/- 7.5% of the internal 0.5V reference. 48 PGOOD2 Channel 2 Output Power Good with Open-Drain Logic. PGOOD2 is pulled to ground when the voltage of the FB2 pin is not within +/- 7.5% of the internal 0.5V reference. 39 PGOOD3 Channel 3 Output Power Good with Open-Drain Logic. PGOOD3 is pulled to ground when the voltage of the FB3 pin is not within +/- 7.5% of the internal 0.5V reference. 24 PGOOD4 Channel 4 Output Power Good with Open-Drain Logic. PGOOD4 is pulled to ground when the voltage of the FB4 pin is not within +/- 7.5% of the internal 0.5V reference.
16 TRACK1
Channel 1 Output Tracking and Soft-Start Pin. Allows to control the rise time of the output voltage. Connecting a voltage between 0V to 0.5V on this pin relative to GND bypasses error amplifier’s internal reference input. Instead, it servos the FB pin to that voltage. There’s an internal 5µA pullup current from INTVCC to this pin; putting a capacitor from this pin to GND provides soft-start function.
47 TRACK2
Channel 2 Output Tracking and Soft-Start Pin. Allows to control the rise time of the output voltage. Connecting a voltage between 0V to 0.5V on this pin relative to GND bypasses error amplifier’s internal reference input. Instead, it servos the FB pin to that voltage. There’s an internal 5µA pullup current from INTVCC to this pin; putting a capacitor from this pin to GND provides soft-start function.
40 TRACK3
Channel 3 Output Tracking and Soft-Start Pin. Allows to control the rise time of the output voltage. Connecting a voltage between 0V to 0.5V on this pin relative to GND bypasses error amplifier’s internal reference input. Instead, it servos the FB pin to that voltage. There’s an internal 5µA pullup current from INTVCC to this pin; putting a capacitor from this pin to GND provides soft-start function.
23 TRACK4
Channel 4 Output Tracking and Soft-Start Pin. Allows to control the rise time of the output voltage. Connecting a voltage between 0V to 0.5V on this pin relative to GND bypasses error amplifier’s internal reference input. Instead, it servos the FB pin to that voltage. There’s an internal 5µA pullup current from INTVCC to this pin; putting a capacitor from this pin to GND provides soft-start function.
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17 FB1
Channel 1 Feedback Input to the Error Amplifier of the Step-Down Regulator. LT7200S regulates this pin to a 0.5V accurate internal reference voltage. Connect resistor divider tap to this pin. The output voltage, VOUT, can be adjusted from 0.5V to 0.9 x VIN by: VOUT = 0.5V x [1+(R2/R1)].
46 FB2
Channel 2 Feedback Input to the Error Amplifier of the Step-Down Regulator. LT7200S regulates this pin to a 0.5V accurate internal reference voltage. Connect resistor divider tap to this pin. The output voltage, VOUT, can be adjusted from 0.5V to 0.9 x VIN by: VOUT = 0.5V x [1+(R2/R1)].
41 FB3
Channel 3 Feedback Input to the Error Amplifier of the Step-Down Regulator. LT7200S regulates this pin to a 0.5V accurate internal reference voltage. Connect resistor divider tap to this pin. The output voltage, VOUT, can be adjusted from 0.5V to 0.9 x VIN by: VOUT = 0.5V x [1+(R2/R1)].
22 FB4
Channel 4 Feedback Input to the Error Amplifier of the Step-Down Regulator. LT7200S regulates this pin to a 0.5V accurate internal reference voltage. Connect resistor divider tap to this pin. The output voltage, VOUT, can be adjusted from 0.5V to 0.9 x VIN by: VOUT = 0.5V x [1+(R2/R1)].
18 ITH1
Channel 1 Error Amplifier Output and Switching Regulator Compensation Point. The current comparator’s trip threshold is linearly proportional to this voltage. Normal range is from 0.3V to 1.6V.
45 ITH2
Channel 2 Error Amplifier Output and Switching Regulator Compensation Point. The current comparator’s trip threshold is linearly proportional to this voltage. Normal range is from 0.3V to 1.6V.
42 ITH3
Channel 3 Error Amplifier Output and Switching Regulator Compensation Point. The current comparator’s trip threshold is linearly proportional to this voltage. Normal range is from 0.3V to 1.6V.
21 ITH4
Channel 4 Error Amplifier Output and Switching Regulator Compensation Point. The current comparator’s trip threshold is linearly proportional to this voltage. Normal range is from 0.3V to 1.6V. 19 RUN1 Channel 1 Logic Controlled RUN Input. Do not leave this pin floating. Logic High activates the step-down regulator. 44 RUN2 Channel 2 Logic Controlled RUN Input. Do not leave this pin floating. Logic High activates the step-down regulator. 43 RUN3 Channel 3 Logic Controlled RUN Input. Do not leave this pin floating. Logic High activates the step-down regulator. 20 RUN4 Channel 4 Logic Controlled RUN Input. Do not leave this pin floating. Logic High activates the step-down regulator.
25 INTVCC
Internal 5V Regulator Output. The internal power drivers and control circuits are powered from this voltage. Decouple this pin to power ground with a minimum of 4.7µF low ESR ceramic capacitor. 38 RT Switching Frequency Program Pin. Connect an external resistor RRT (between 249kΩ to 33.2kΩ) from this pin to GND to program the frequency from 400kHz to 3MHz.
Figure 32. Block Diagram
analog.com Rev. 2 17 of 38 THEORY OF OPERATION Main Control Loop The LT7200S is a quad -channel, current-mode monolithic step -down regulator capable of providing ±5A of output current from each channel. In normal operation, the internal top power MOSFET is turned on for a fixed interval determined by a one-shot timer (“ON” signal in Block Diagram). When the top power MOSFET turns off, the bottom power MOSFET turns on until the current comparator, ICMP, trips, restarting the one-shot timer and initiating the next cycle. Inductor current is determined by sensing the voltage drop across SW and GND nodes of the bottom power MOSFET when it is on. The voltage on the ITH pin sets the comparator threshold corresponding to the inductor valley current. The error amplifier, EA, adjusts this ITH voltage by comparing the feedback signal, VFB, with an internal 0.5V reference. If the load current increases, it causes a drop in the feedback voltage relative to the internal reference, the ITH voltage then rises until the average inductor current matches that of the load current. At light load currents, the inductor current can drop to zero and become negative. In Discontinuous Mode (DCM) operation, this is detected by the current reversal comparator, IREV, which then shuts off the bottom power MOSFET. Both power MOSFETs remain off with the output capacitor supplying the load current until the ITH voltage rises above zero current level to initiate the next cycle. If continuous mode of operation is desired, simply float the MODE/SYNC pin or tie it to INTVCC. The operating frequency is determined by the value of the R RT resistor, which programs the current for the internal oscillator. An internal phase-lock loop servos the switching regulator on-time to track the internal oscillator and force a constant switching frequency. A clock signal can be applied to the MODE/SYNC pin to synchronize the switching frequency to an external clock. The regulator defaults to force continuous operation once the clock signal is present. The “S” in LTC7200S refers to the second generation Silent Switcher technology. The IC has integrated ceramic capacitors for VIN, INTVCC, and BOOST to keep all the fast AC current loops small, thus improving the EMI performance. Furthermore, it allows for faster switching edges, which greatly improves efficiency at high switching frequencies. “Power Good” Status Output PGOOD open-drain output is pulled low if the regulator output feedback voltage, V FB, exits a ±7.5% window around the regulation point while the overvoltage (OV) or undervoltage (UV) comparator is tripped. This condition is released once regulation within a ±5.5% window is achieved. Continuous operation is forced during OV and UV conditions, except during start-up when the TRACK pin is ramping up to 0.5V. VIN Overvoltage Protection To protect the internal power MOSFET devices against transient voltage spikes, the LT7200S constantly monitors the PVIN pin for an overvoltage condition. When the PV IN rises above 20V, the regulator suspends operation by shutting off both power MOSFETs. Once PVIN drops below 18V, the regulator immediately resumes normal operation. During an overvoltage event, the internal soft-start voltage is clamped to a voltage slightly higher than the feedback voltage. Thus, the soft-start feature is present upon exiting an overvoltage condition. Overcurrent and Short-Circuit Protection The LT7200S protects itself against output overcurrent and short -circuits by sensing the inductor valley current. When the current limit is reached, the output begins to fall, decreasing on-time of the top power MOSFET. If the short is prolonged enough for the on-time to reach its minimum, the off-time lengthens, lowering the switching frequency
executes its soft-start function to prevent the output voltage from overshooting. The MODE/SYNC pin is a multipurpose pin allowing both mode selection and operating frequency synchronization. together to run out of phase to provide more output current. Tying the PHMODE pin to GND forces 4-phase operation. Tie it to INTVCC for 3-phase operation. Table 4. PHMODE Configuration Table
analog.com Rev. 2 19 of 38 APPLICATIONS INFORMATION The first page of the data sheet shows a general LT7200S application circuit. External component selection is largely driven by the target current ripple, load requirement, and switching frequency. Component selection typically begins with the selection of the inductor L and resistor RRT. Once the inductor is chosen, select the input capacitor, CIN, and the output capacitor, C OUT. Next, select the feedback resistors to set the desired output voltage. Finally, select the remaining optional external components for functions such as external loop compensation, tracking/soft-start, input UVLO, and PGOOD. Programming Switching Frequency Selection of the switching frequency is a trade-off between efficiency and component size. High frequency operation allows the use of smaller inductor and capacitor values. Operation at lower frequencies improves efficiency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. Connecting a resistor, R RT, from the RT pin to SGND pro grams the switching frequency, f, from 400kHz to 3MHz according to the following formula: f(Hz) = 1e11 RRT(Ω) The internal PLL has a synchronization range of ±30% around its programmed frequency. Therefore, during external clock synchronization be sure that the external clock frequency is within this ±30% range of the R RT programmed frequency. Inductor Selection For a given input voltage, V IN, output voltage, V OUT, the inductor value, L, and operating frequency, f, determine the ripple current: ∆IL = VOUT f x L x (1 − VOUT VIN The inductor current ripple decreases with higher inductor value and higher operating frequency. Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors, and output voltage ripple. Highest efficiency operation is obtained at low frequency with small ripple current. However, achieving this requires a large inductor. There is a trade-off between component size, efficiency, and operating frequency. A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX), which is around 5A per channel. Exceeding 60% of I OUT(MAX) is not recom mended. Note that the largest ripple current occurs at the highest V IN. To guarantee that ripple current does not exceed a specified maximum, the inductance should be chosen according to: L = VOUT f x ∆IL(MAX) (1 − VOUT VIN(MAX) Once the value for L is known, select the type of inductor. Actual core loss is independent of core size for a fixed inductor value, but is very dependent on the induc tance selected. As the inductance or frequency increases, core losses decrease. Unfortunately, increased inductance requires more turns of wire leading to increased DCR and copper losses.
inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate. Table 5. Inductor Selection Table prevent large voltage transients from occurring, use a low ESR input capacitor sized for the maximum RMS current. makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. applications, sufficient bulk input capacitance is needed to minimize transient effects during output load changes.
analog.com Rev. 2 21 of 38 Selecting the Output Capacitor (COUT) The selection of C OUT is determined by the effective series resistance (ESR) required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance necessary to ensure the control loop is stable. Loop stability can be checked by viewing the load transient response. The output ripple, ΔVOUT, is determined by: ∆VOUT < ∆IL( 1 8 x f x COUT + ESR) The output ripple is highest at maximum input voltage since ΔI L increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic, and ceramic capacitors are all available in surface mount packages. Special polymer capacitors are very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density, but it is important to only use types that are surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR, but can be used in cost -sensitive app lications provided consideration is given to ripple current ratings and long -term reliability. Ceramic capacitors have excellent low ESR characteristics and small footprints. Since the ESR of a ceramic capacitor is so low, it is more useful to choose the output capacitor value to fulfill a charge storage requirement. During a load step, the output capacitor must instantaneously supply the current to support the load until the f eedback loop raises the switch current enough to support the load. The time required for the feedback loop to respond is dependent on the compensation and the output capacitor size. Typically, five cycles are required to respond to a load step, but only in the first cycle does the output voltage drop linearly. The output droop, VDROOP, is usually about three times the linear drop of the first cycle. Thus, a good place to start with the output capacitor value is approximately COUT = 3 ∆IOUT f0 x VDROOP Using Ceramic Input and Output Capacitors Higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating, and low ESR make them ideal for switching regulator applications. However, due to the self-resonant and high Q cha racteristics of some types of ceramic capacitors, take care when these capacitors are used at the input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the V IN input. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. For a more detailed discussion, refer to Application Note 88. When choosing the input and output ceramic capacitors, choose the X5R and X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. Choose X8R for 150°C applications. More capacitance may be required depending on the duty cycle and load step requirements. In most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. A 47μF ceramic capacito r is usually enough for these conditions. Place this input capacitor as close to the PV IN and GND pins as possible.
An internal low dropout (LDO) regulator produces the 5V supply that powers the drivers and internal bias circuitry. available, consider using that to drive the SVIN pin to lower the power dissipation across the internal LDO. feedforward compensation capacitor, CFF, can also be placed between VOUT and FB to improve transient performance. Figure 33. Setting the Output Voltage switching frequency may deviate from the programmed frequency.
channels 2, 3, and 4 respectively. In practice, use either channel as the master. Figure 34. Output Tracking Applications the slave channels shown in Figure 35(b).
Figure 35. Output Tracking Configuration MOSFET, tripping the current comparator and turning the power MOSFET back off. This time is generally about 40ns. frequencies allow the use of smaller board components, thus reducing the size of the application circuit. for applications with fSW > 1MHz. corresponding ITH pins together to accurately share the output current.
Figure 36. External Compensation Network Select the proper ITH components for OPTI -LOOP® optimization. The compensation network is shown in Figure 36. values may be required depending on the application's required output capacitance. Table 6. Compensation Values damping factor can be estimated using the percentage of overshoot seen at this pin. The ITH external component shown in the Table 6 circuit provides an adequate starting point for most applications.
analog.com Rev. 2 26 of 38 charge or discharge C OUT, generating a feedback error signal used by the regulator to return V OUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that indicates a stability problem. The initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/DC ratio cannot be used to determine phase margin. The output voltage settling behavior is related to the stability of the closed -loop system and demonstrates the actual overall supply performance. For detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to Analog Devices Application Note 76. In some applications, a more severe transient can be caused by switching in loads with large (> 47μF) input capacitors. The discharge input capacitors are effectively put in parallel with C OUT, causing a rapid drop in V OUT. No regulator can deliver enough current to prevent this problem if the switch connecting the load has low resistance and is driven quickly. The solution is to limit the turn -on speed of the load switch driver. A hot swap controller is designed specifically for this purpose and usually in corporates current limiting, short -circuit protection, and soft - starting. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change produces the most improvement. Percent efficiency can be expressed as: % Efficiency = 100% – (L1 + L2 + L3 + …) where L1, L2, etc., are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, three main sources usually account for most of the losses in LT7200S circuits: 1) I2R losses, 2) switching and biasing losses, 3)other losses. I2R losses are calculated from the DC resistances of the internal switches, R SW, and external inductor, R L. In continuous mode, the average output current flows through inductor L but is “chopped” between the internal top and bottom power MOSFETs. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP) (DC) + (RDS(ON)BOT) (1 – DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus to obtain I2R losses: I2R losses = IOUT2 (RSW + RL) The switching current is the sum of the MOSFET driver and control currents. The power MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a power MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from PVIN to ground. The resulting dQ/dt is a current out of IN typically much larger than the DC control bias current. In continuous mode, IGATECHG = f(QT + QB), where QT and QB are the gate charges of the internal top and bottom power MOSFETs, and f is the switching frequency. The power loss is thus: Switching Loss = IGATECHG x PVIN The gate charge loss shows up as current through the INTVCC pin as well as frequency. Thus, their effects are more pronounced in applications with higher input voltage and higher frequency.
- Are COUT and L closely connected? The (–) plate of COUT returns current to GND and the (–) plate of CIN.
- Place the FB dividers close to the part with kelvin connections to VOUT and GND at the point of load.
- Keep sensitive components away from the SW pin. Route the FB resistors, RT resistor, compensation component,
and INTVCC bypass caps away from the SW trace and inductor.
- A ground plane is preferred.
- Flood all unused areas on all layers with copper, which reduces the temperature rise of power components.
Connect these copper areas to GND. Figure 38. Example of Top Layer PCB Design both resistors is 10kΩ. For best accuracy, use a 0.1% resistor.
analog.com Rev. 2 29 of 38 CSS = 20nF Use a typical 22nF capacitor for CSS. Because efficiency is important at both high and low load current, discontinuous mode operation is utilized. Select from the characteristic curves the correct RT resistor for the 1MHz switching frequency. Based on that, RRT should be 100kΩ. Then calculate the inductor value to achieve a current ripple that is about 40% of the maximum peak current limit (5A) at maximum VIN: L = VOUT f x ∆IL x (1 − VOUT VIN L = 1.2V 1MHz x 2A x (1 − 1.2V 15V) = 0.55μH The closest standard value inductor higher is 0.6μH. Select COUT based on the ESR required to satisfy the output ripple requirement and the bulk capacitance needed for loop stability. For this design, use two 47μF ceramic capacitors. Size CIN for a maximum current rating of: IRMS_Channel = 5A x (1.2V 15V)√(15V 1.2V − 1) = 1.36A IRMS_Total = 36A x 4 = 5.4A, if connect outputs of four channels together. Decoupling VIN with two 22μF ceramic capacitor, as shown in Figure 38, is adequate for most applications.
Figure 39. Quad 1.2V/5A, 1.8V/5A, 3.3V/5A, 5V/5A, 2MHz, Buck Regulator
Figure 44. Quad 1.2V/5A, 1.8V/5A, 3.3V/5A, 5V/5A Buck Regulator with Coincident Tracking
Figure 45. Quad 1.2V/5A, 1.8V/5A, 3.3V/5A, 5V/5A Sequenced Buck Regulator with 8V Input UVLO
analog.com Rev. 2 35 of 38 OUTLINE DIMENSIONS
analog.com Rev. 2 36 of 38 ORDERING GUIDE PART NUMBER PART MARKING FINISH CODE PAD FINISH PACKAGE TYPE MSL RATING TEMPERATURE RANGE LT7200SAV#PBF 7200S e4 * Au(RoHS) LQFN 3 -40°C to 125°C LT7200SAV#TRPBF Automotive Products LT7200SAV#WPBF 7200S e4 * Au(RoHS) LQFN ** 3 -40°C to 125°C LT7200SAV#WTRPBF 7200S e4 * Au(RoHS) LQFN ** 3 -40°C to 125°C Contact the factory for parts specified with wider operating temperature ranges. Recommended LGA and BGA PCB Assembly and Manufacturing Procedures. LGA and BGA Package and Tray Drawings. * Pad or ball finish code is per IPC/JEDEC J-STD-609. Laminate Package with QFN Footprint. * Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3605/ LTC3605A 20V, 5A Synchronous Step-Down Regulator 4V < VIN < 20V, 0.6V < VOUT < 20V, 96% Maximum Efficiency, 4mm × 4mm QFN-24 Package LTC3613 24V, 15A Monolithic Step-Down Regulator with Differential Output Sensing 4.5V < VIN < 24V, 0.6V < VOUT < 5.5V, 0.67% Output Voltage Accuracy, Valley Current Mode, Programmable from 200kHz to 1MHz, Current Sensing, 7mm × 9mm QFN-56 Package LTC3622 17V, Dual 1A Synchronous Step- Down Regulator with Ultralow Quiescent Current 2.7V < VIN < 17V, 0.6V < VOUT < VIN, 95% Maximum Efficiency, 3mm × 4mm DFN-14 and MSOP-16 Package LTC3623 15V, ±5A Rail-to-Rail Synchronous Buck Regulator 4V ≤ VIN ≤ 15V, 0V < VOUT < VIN – 0.5V, Programmable Wire Drop Compensation, Current Sensing, 96% Maximum Efficiency, 3mm × 5mm QFN-24 Package LTC3624 17V, 2A Synchronous Step-Down Regulator with 3.5µA Quiescent Current 2.7V < VIN < 17V, 0.6V < VOUT < VIN, 95% Maximum Efficiency, 3.5µA IQ, Zero-Current Shutdown, 3mm × 3mm DFN-8 Package LTC3633A/ LTC3633A-1 Dual Channel 3A, 20V Monolithic Synchronous Step-Down Regulator 3.6V < VIN < 20V, 0.6V < VOUT < VIN, 95% Maximum Efficiency, 4mm × 5mm QFN-28 and TSSOP-28 Package LTM4639 Low VIN 20A DC/DC µModule® Step- Down Regulator Complete 20A Switch Mode Power Supply, 2.375V < VIN < 7V, 0.6V < VOUT < 5.5V, 1.5% Maximum Total DC Output Voltage Error, Differential Remote Sense Amp, 15mm × 15mm BGA Package
analog.com Rev. 2 37 of 38 LTM4637 20A DC/DC µModule Step-Down Regulator Complete 20A Switch Mode Power Supply, 4.5V < VIN < 20V, 0.6V < VOUT < 5.5V, 1.5% Maximum Total DC Output Voltage Error, Differential Remote Sense Amp, 15mm × 15mm BGA or LGA Package LTC7130 20V, 20A Monolithic Buck Converter with Ultralow DCR Sensing 4.5V < VIN < 20V, 95% Maximum Efficiency, Optimized for Low Duty Cycle Applications, 6.25mm × 7.5mm BGA Package
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