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Rev. 0For more information www.analog.com Document Feedback TYPICAL APPLICATION FEATURES DESCRIPTION Dual Channel 6A, 20V PolyPhase Step-Down Silent Switcher 2 with Digital Power System Management The LT®7182S is a dual-output monolithic PolyPhase DC/DC synchronous step-down regulator that deliv - ers up to 6A of continuous current from both channels simultaneously and supports loads up to 8A from either channel. The LT7182S features the second generation Silent Switcher® architecture with integrated VIN bypass capacitors for fast, clean, low-overshoot switching edges delivering high efficiency at high switching frequencies while minimizing EMI emissions. The I 2C-based PMBus 1.3 compliant serial interface enables control of device functions and provides telemetry information for system monitoring. The LT7182S is sup- ported by the L TpowerPlay® graphical user interface tool. Output voltage, frequency, phase, and device address can be configured using resistors for operation without programming. Settings may also be written via the serial interface and/or stored in EEPROM. The controlled on-time valley current mode control archi- tecture with 20ns (typical) minimum on-time enables high switching frequency at low output voltage with excellent transient response in a small overall solution size. 12VIN to 1.2VOUT Efficiency

APPLICATIONS

n Silent Switcher®2 Architecture: Enables Compact, Efficient, low EMI Solution n PMBus/I2C Serial Interface n Telemetry Read Back Includes VOUT, IOUT, VIN, Die Temperature, Faults n Programmable Voltage, Current Limit, Digital Soft- Start/Stop, Sequencing, UV/OV , Phase, Frequency (Up to 4MHz), Loop Compensation n Integrated EEPROM with Fault Event Log n Key Parameters May Be Set by Configuration Resistors for Operation without Programming n ±0.25% Output Voltage Accuracy Over Temperature for 0.6V to 1.375V n PolyPhase Load Sharing for Up to Eight Phases n Wide VIN Range: Down to 2.9V, or 1.5V with EXTVCC n Up to 95% Efficiency at 1MHz, 12VIN to 3.3VOUT n VOUT Range 0.4V to 5.5V (Up to 0.85 • VIN) n Differential Remote VOUT Sense n External Frequency Synchronization n 40-lead (5mm × 7mm) LQFN Package n Communications, Storage, and Industrial Systems n Data Center and Solid State Drive Power Supplies All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. patents, including 8823345. SDA SCL SW0 VSENSE0P LT7182S 7182s TA01 FAULT0 PVIN0 PVIN1 ALERT VSENSE0N BOOST0 PGOOD0 SHARE_CLK PGOOD1 EXTVCC FAULT1 WP VOUT0 RUN1 RUN0 VIN 20V ITH0 INTVCC ITH1 SYNC/PWM_CFG ASEL VOUT1_CFG/ POLYPHASE_CFG VOUT0_CFG DRVCC SW1 VSENSE1P VSENSE1N BOOST1 VOUT1 1.2V VDD18 EFFICIENCY POWER LOSS 0.4MHz, 1µH 1MHz, 0.47µH 2MHz, 0.22µH LOAD CURRENT (A) 100 EFFICIENCY (%) POWER LOSS (W) 7182s TA0b

Rev. 0 For more information www.analog.com TYPICAL APPLICATIONS T

Description

T Operation Programmable P L T T See also, the companion document LT7182S PMBus/I2C Reference Manual. It provides a detailed description of digital functionality including PMBus commands, serial device address selection, and physical interface details.

Rev. 0For more information www.analog.com PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS SYNC/PWM_CFG, WP , SHARE_CLK, ALERT, SDA, SCL, FAULT0, FAULT1, RUN0, V to 6V Operating Junction Temperature (Note 2) C to 150°C Maximum Peak Reflow (Package Body) 0°C (Note 1) 39 34 SW0 SW1 PGND PGND 38 37 36 35 PGND BOOST0 PVIN0 SW0 SW0 PV IN0 PGND PGOOD0 PGND BOOST1 PV IN1 SW1 SW1 PV IN1 PGND DRVCC PGOOD1 FAUL T1 WP RUN0 RUN1 EXTVCC FAUL T0 ALERT SCL SDA V SENSE0N INTVCC ITH1 ITH0 SGND VOUT0_CFG VDD18 ASEL VOUT1_CFG/ POLYPHASE_CFG VSENSE1N VSENSE1P VSENSE0P TOP VIEW LQFN PACKAGE 40-LEAD (5mm × 7mm × 0.9mm) θJA = 27°C/W, ΨJT = 0.28°C/W, EXPOSED PAD (PINS 41 - 44) MUST BE SOLDERED TO APPROPRIATE PCB NETS 40 33 13 14 15 16 17 18 19 20 SHARE_CLK SYNC/ PWM_CFG ORDER INFORMATION PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE TYPE** MSL RATING TEMPERATURE RANGE (SEE NOTE 2)DEVICE FINISH CODE LT7182SRV#PBF Au (RoHS) 7182S e4 LQFN 3 –40°C to 150°C

  • *Pad or ball finish code is per IPC/JEDEC J-STD-609. The temperature grade is identified by a label on the shipping container **LQFN is Laminate Package with QFN Footprint. The LT7182S package has the same X, Y dimensions as a standard 5mm × 7mm QFN package.
  • Recommended LGA and BGA PCB Assembly and Manufacturing Procedures LGA and BGA Package and Tray Drawings

Rev. 0 For more information www.analog.com

ELECTRICAL CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITS Input Supply Channel 0 Input Supply Range EXTVCC = 0V l 2.9 20 V Channel 0 Input Supply Range with EXTVCC 3V ≤ EXTVCC ≤ 5.5V l 1.5 20 V Channel 1 Input Supply Range PVIN0 ≥ 2.9V or EXTVCC ≥ 3V l 1.5 20 V Optional EXTVCC Input Supply Range l 3 5.5 V EXTVCC + PVIN0 + PVIN1 Quiescent Current Both channels switching Sleep (Pulse Skip Mode) or Shutdown fSW = 1MHz, Forced Continuous Mode, VIN = 12V, No Load mA mA Initialization Time (Delay from RESTORE_USER_ALL, MFR_RESET, or Application of P VIN0 or EXTVCC, Until TON_DELAY Timer Can Begin) With CFG Pins Enabled (Default) CFG Pins Ignored ms ms Switching Regulator V OUT Range PVIN > 6.1V PVIN ≤ 6.1V l l 0.4 0.4 5.5 0.85 • VIN V V V OUT Set Point Accuracy High-Performance Low-VOUT Mode, 0.6V ≤ VOUT ≤ 1.375V 0.4V ≤ V OUT ≤ 5.5V l l –0.25 –0.5 0.25 0.5 VOUT Set-Point Resolution 1 mV VSENSE0P, VSENSE1P Input Resistance VSENSE0N = VSENSE1N = 0V 30 kΩ Error Amplifier T ransconductance Programming Resolution 3 bits Error Amplifier T ransconductance g m(MAX) Full VOUT Range Mode, 0.4V ≤ VOUT ≤ 5.5V. Includes Internal VOUT Feedback Divider 300 µS Error Amplifier T ransconductance gm(MIN) Full VOUT Range Mode, 0.4V ≤ VOUT ≤ 5.5V. Includes Internal VOUT Feedback Divider 37.5 µS Error Amplifier T ransconductance gm Step Size Full VOUT Range Mode, 0.4V ≤ VOUT ≤ 5.5V. Includes Internal VOUT Feedback Divider 37.5 µS Error Amplifier T ransconductance gm(MAX) High-Performance Low-VOUT Mode, 0.4V ≤ VOUT ≤ 1.375V, Includes Internal VOUT Feedback Divider 1.2 mS Error Amplifier T ransconductance gm(MIN) High-Performance Low-VOUT Mode, 0.4V ≤ VOUT ≤ 1.375V, Includes Internal VOUT Feedback Divider 150 µS Error Amplifier T ransconductance gm Step Size High-Performance Low-VOUT Mode, 0.4V ≤ VOUT ≤ 1.375V, Includes Internal VOUT Feedback Divider 150 µS Max Programmable Internal Compensation Resistor R ITH(MAX) Internal Compensation (ITH Tied to INTVCC) (Note 5) 120 kΩ Min Programmable Internal Compensation Resistor R ITH(MIN) Internal Compensation (ITH Tied to INTVCC) (Note 5) 5 kΩ Internal Compensation Capacitor Programming Resolution Internal Compensation (ITH Tied to INTVCC) 3 bits Internal Compensation Capacitor CITH(MAX) Internal Compensation (ITH Tied to INTVCC) 80 pF Internal Compensation Capacitor CITH(MIN) Internal Compensation (ITH Tied to INTVCC) 10 pF Internal Compensation Capacitor CITH Step Size Internal Compensation (ITH Tied to INTVCC) 10 pF The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.

Rev. 0For more information www.analog.com PARAMETER CONDITIONS MIN TYP MAX UNITS Positive Inductor Valley Current Limit ILIM-POS (Note 6) (Sourcing Output Current) ILIM Range 0 ILIM Range 1 ILIM Range 2 ILIM Range 3 l l l l 2.3 3.5 6.5 4.5 6.5 8.5 3.7 5.5 10.5 A A A A Negative Inductor Valley Current Limit ILIM-NEG (Note 6) (Sinking Output Current) ILIM Range 0 ILIM Range 1 ILIM Range 2 ILIM Range 3 l l l l –4.4 –5.5 –2.3 –3.4 –4.25 –1.6 –2.4 A A A A Power FET On-Resistance Main Switch (Top) Synchronous Switch (Bottom) mΩ mΩ SW Leakage V IN = 20V, VSW = 0V,20V –120 120 µA Minimum On-Time ILOAD = 1A l 20 40 ns Minimum Off-Time l 60 100 ns Output Voltage Supervisors VOUT Undervoltage (UV) Fault/Warning Programming Range 0.36 5.5 V VOUT Overvoltage (OV) Fault/Warning Programming Range 0.4 6 V VOUT UV/OV Fault/Warning Threshold Accuracy VOUT UV/OV Threshold < 0.6V VOUT UV/OV Threshold ≥ 0.6V l l –12 mV VOUT UV/OV Fault/Warning Programming Step Size 4 mV VOUT UV/OV Fault/Warning Time VOUT = 10mV Beyond Threshold l 25 µs Input Voltage Supervisors ON Threshold Programming Range 1.4 20 V OFF Threshold Programming Range 1.35 20 V ON/OFF Threshold Programming Step Size 25 mV ON/OFF Threshold Set Point Accuracy VIN_ON/OFF ≤ 5V l –100 100 mV ON/OFF Threshold Set Point Accuracy 5V ≤ VIN_ON/OFF ≤ 20V l –2 2 % VIN Overvoltage Lockout Threshold VIN Rising VIN Falling l 22 23.3 22.3 V V Oscillator and Phase Locked Loop SYNC/PWM_CFG Pin Input Frequency Range l 0.4 4 MHz Switching Frequency Programming Range 0.4 4 MHz Switching Frequency Set Point Accuracy l –7.5 7.5 % Switching Phase Programming Range 0 345 degrees Switching Phase Programming Resolution 15 degrees Telemetry Readback Telemetry Measurement Period, All Except Die Temperature 6.5 ms Telemetry Measurement Period, Die Temperature 26 ms Output Voltage Readback READ_VOUT Accuracy High-Performance Low-V OUT Mode, 0.6V ≤ VOUT ≤ 1.375V l –0.15 0.15 % READ_VOUT Accuracy 0.4V < VOUT < 5.5V l –0.35 0.35 % The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.

Rev. 0 For more information www.analog.com PARAMETER CONDITIONS MIN TYP MAX UNITS PVIN0, PVIN1 Input Voltage Readback READ_VIN Accuracy VIN = 1.5V to 2.5V VIN = 2.5V to 20V l l –25 mV Output Current Readback READ_IOUT Accuracy IOUT = 0A to 4A, (VOUT/VIN) ≤ 0.5 IOUT = 4A to 8A, (VOUT/VIN) ≤ 0.5 IOUT = 0A to 4A, (VOUT/VIN) > 0.5 IOUT = 4A to 8A, (VOUT/VIN) > 0.5 l l l l –200 –600 –15 200 600 mA mA Input Current Readback READ_IIN Accuracy IIIN = 0A to 1A, IIIN = 1A to 5A l l –250 –25 250 mA Frequency Readback READ_FREQUENCY Accuracy f SW ≤ 400kHz fSW ≥ 400kHz –20 kHz EEPROM Characteristics Retention (Note 4) l 10 years Endurance (Note 4) l 10,000 writes Mass Write Time (STORE_USER_ALL) l 250 500 ms Digital Inputs RUN0, RUN1, FAUL T0, FAUL T1, PGOOD0, PGOOD1, SHARE_CLK, SCL, SDA, ALERT, WP Input High Threshold (V IH) l 1.1 1.35 V Input Low Threshold (VIL) l 0.8 0.9 V Hysteresis (VHYS) 50 200 400 mV Leakage Current Applied Voltage = 0V, 5.5V ±10 µA Input Capacitance 10 pF Digital Clock Input SYNC/PWM_CFG Peak-to-Peak Input Voltage Swing SYNC Input Mode l 1.6 5.5 V Rise Time SYNC Input Mode 25 ns Duty Cycle SYNC Input Mode 30 70 % Digital Clock Output SYNC/PWM_CFG Output High Voltage SYNC Output Mode l 1.6 1.88 1.98 V Output Low Voltage SYNC Output Mode l 0 0.1 V Current-Limited Open-Drain Output RUN0, RUN1, FAUL T0, FAUL T1 Pulldown Current Applied Voltage = 0.4V to 5.5V l 1 1.5 2 mA Open-Drain Outputs PGOOD0, PGOOD1, SHARE_CLK Output Low Voltage I = 6mA l 0.4 V Digital I/O SCL, SDA, ALERT Output Low Voltage I = 20mA l 0.4 V The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.

Rev. 0For more information www.analog.com Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT7182SR is specified over the –40°C to 150°C operating junction temperature range. High Junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125°C. Note the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Note 3: The LT7182S includes overtemperature protection that is intended to protect the device during momentary overload conditions. The maximum rated junction temperature will be exceeded when this protection is active. Continuous operation above the specified maximum operating junction temperature will reduce lifetime. Note 4: EEPROM endurance is guaranteed by design, characterization and correlation with statistical process controls. Data retention is production tested via a high temperature bake at wafer level. The minimum retention specification applies for devices whose EEPROM has been cycled less than the minimum endurance specification. Note 5: When internal compensation is selected (by connecting I TH to INTVCC), eight internal resistor values are available in non-linear increments. See the MFR_PWM_MODE_LT7182S command in the LT7182S PMBus/I2C Reference Manual. Note 6: The LT7182S switching regulators use valley current mode control so the current limits specified correspond to the valley of the inductor current waveform. Maximum load current is higher and equals the valley current limit plus one half of the inductor ripple current. See Applications Information for more details. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I2C/PMBus Timing fSCL Serial Bus Operating Frequency l 10 1000 kHz tBUF Bus Free Time Between Stop and Start l 500 ns tHD:STA Hold Time After repeated Start Condition l 260 ns tSU:STA Repeated Start Condition Setup Time l 260 ns tSU:STO Stop Condition Setup Time l 260 ns tSU:DAT Data Input Setup Time l 50 ns tHD:DAT Data Input Hold Time l 0 ns Data Output Hold Time l 0 450 ns tTIMEOUT Bus Timeout l 25 35 ms tLOW Serial Clock Low Period l 0.5 10000 µs µs tHIGH Serial Clock High Period l 260 ns The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.

Rev. 0 For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS 12VIN Efficiency at fSW = 1MHz, Different VOUT 12VIN to Various VOUT Low Load Efficiency 5VIN to 0.8VOUT Efficiency at Different fSW 0.8VOUT Efficiency at fSW = 1MHz, Various VIN VOUT vs Temperature fSW vs Temperature EFFICIENCY POWER LOSS EXTV CC = 4V 1MHz, L = XGL4040-301 2MHz, L = XGL4040-150 4MHz, L = XGL3530-101 LOAD CURRENT (A) 100 EFFICIENCY (%) POWER LOSS (W) 7182s G04 EFFICIENCY POWER LOSS L = XGL4040 EXTV CC = 4V 0.4V OUT , 0.15µH 0.7V OUT , 0.30µH OUT , 0.47µH LOAD CURRENT (A) 100 EFFICIENCY (%) POWER LOSS (W) 7182s G02 EFFICIENCY POWER LOSS L = XGL5030-351 EXTV CC = 4V V IN = 5V V IN = 12V V IN = 20V LOAD CURRENT (A) 100 EFFICIENCY (%) POWER LOSS (W) 7182s G05 EXTV CC = 4V f SW = 1MHz PULSE-SKIP FCM 3.3V OUT , L = 1µH 2.5V OUT , L = 0.82µH 1.8V OUT , L = 0.65µH LOAD CURRENT (A) 0.001 0.01 0.1 100 EFFICIENCY (%) 7182s G03 VOUT_COMMAND = 0.4V TEMPERATURE (°C) –60 –40 –20 100 120 140 160 399.000 399.125 399.250 399.375 399.500 399.625 399.750 399.875 400.000 400.125 400.250 400.375 400.500 400.625 400.750 400.875 401.000 V OUT (mV) 7182s G06 FREQUENCY_SWITCH = 4000 FREQUENCY_SWITCH = 3000 FREQUENCY_SWITCH = 2000 FREQUENCY_SWITCH = 1000 FREQUENCY_SWITCH = 400 TEMPERATURE (°C) –60 –40 –20 100 120 140 160 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400 3600 3800 4000 4200 f SW (kHz) 7182s G07

Rev. 0For more information www.analog.com Switch RDSON vs Temperature Minimum On-Time TYPICAL PERFORMANCE CHARACTERISTICS Minimum Off-Time READ_TEMPERATURE Error vs Temperature EXTVCC Idle Current vs Temperature TJ Rise vs Load Case Temperature Rise READ_IOUT Error vs IOUT TOP SWITCH BOTTOM SWITCH TEMPERATURE (°C) –60 –40 –20 100 120 140 160 RDSON (m/uni03A9) 7182s G08 I LOAD = 0A I LOAD = 1A I LOAD = 2A I LOAD = 3A TEMPERATURE (°C) –60 –40 –20 100 120 140 160 T ON,MIN (ns) 7182s G09 I LOAD = 1A I LOAD = 2A I LOAD = 3A TEMPERATURE (°C) –60 –40 –20 100 120 140 160 t OFF ,MIN (ns) 7182s G10 ACTUAL TEMPERATURE (°C) –60 –40 –20 100 120 140 160 READ_TEMPERATURE ERROR (°C) 7182s G11 CH[0] AND CH[1] DISABLED TEMPERATURE (°C) –60 –40 –20 100 120 140 160 6.00 6.25 6.50 6.75 7.00 7.25 7.50 7.75 8.00 8.25 8.50 8.75 9.00 I EXTVCC (mA) 7182s G12 EXTVCC = 4V DEMO BOARD IN STILL AIR PV IN = 12V V OUT = 0.8V EXTV CC = 4V 1MHz 2MHz LOAD CURRENT (SINGLE CHANNEL) (A) T J RISE (°C) 7182s G13 DEMO BOARD IN STILL AIR PV IN = 12V V OUT = 0.8V EXTV CC = 4V 1MHz 2MHz LOAD CURRENT (SINGLE CHANNEL) (A) CASE TEMPERATURE RISE (°C) 7182s G14 12V IN , 0.8VOUT, 1MHz 12V IN , 1.8VOUT, 2MHz IN , 2.5VOUT, 3MHz LOAD CURRENT (A) –200 –160 –120 –80 –40 120 160 200 READ_IOUT ERROR (mA) 7182s G15

Rev. 0 For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Soft-Start Ramp Startup into a Prebiased Load Soft-Off Ramp SW Node and SYNC Output Switching Waveforms in Continuous Conduction Switching Waveforms in Pulse-Skip Mode T ransient Response: Load Current Stepped 3A to 6A, Internal Compensation T ransient Response: Dual Phase Stepped 0A to 6A, External Compensation TON_RISE = 1ms TON_DELAY = 0ms VOUT_COMMAND = 0.8V 500µs/DIV V OUT 0.5V/DIV RUN 1V/DIV 7182s G16 TON_RISE = 1ms TON_DELAY = 0ms VOUT_COMMAND = 2V PREBIASED AT 1V 500µs/DIV V OUT 0.5V/DIV RUN 1V/DIV 7182s G17 TOFF_FALL = 2ms TOFF_DELAY = 0ms VOUT_COMMAND = 1.5V 500µs/DIV V OUT 1V/DIV RUN 1V/DIV 7182s G18 f SW = 2MHz CH1 MFR_PWM_PHASE = 180 250ns/DIV SW CH0 10V/DIV SYNC 1V/DIV SW CH1 10V/DIV 7182s G19 I LOAD = 2A PV IN = 12V V OUT = 1.5V 500ns/DIV V SW 5V/DIV I L 2A/DIV 7182s G20 V IN = 12V V OUT = 1.5V I LOAD = 100mA 2µs/DIV SW 5V/DIV I L 1A/DIV 7182s G21 V IN = 12V , V OUT = 0.8V , C OUT = 47µF ×2 FCM, f SW = 2MHz R COMP = 10k, C COMP = 80pF , g MEA = 750µS 10µs/DIV V OUT 20mV/DIV I LOAD 2A/DIV 7182s G22 V IN = 12V , V OUT = 1.2V , C OUT = 100µF ×4 FCM, f SW = 1MHz R COMP = 7k, C COMP = 470pF , g MEA = 1.2mS 20µs/DIV I LOAD 3A/DIV V OUT 20mV/DIV 7182s G23

Rev. 0For more information www.analog.com PIN FUNCTIONS VSENSE0N, V SENSE1N (Pin 1, Pin 12): Output Voltage Negative Sense Inputs. Connect these pins to the output voltage ground sense points. VSENSE0P, V SENSE1P (Pin 2, Pin 11): Output Voltage Positive Sense Inputs. Connect these pins to the output voltage sense points. SGND (Pin 3): Signal Ground. This pin should be con- nected to board ground in exactly one place, directly beneath the LT7182S. ITH0, I TH1 (Pin 4, Pin 5): Error Amplifier Output and Switching Regulator Compensation Points. Connect the appropriate external components between these pins and SGND to compensate the regulator loop frequency response, or connect the ITH pin to INTVCC to select inter- nal compensation for the channel. INTVCC (Pin 6): Internal 3V LDO Regulator Bypass. This regulator provides the supply current for internal circuitry. This pin must be bypassed to SGND with a 10µF or greater , low ESR ceramic capacitor , as close as possible to the IC. Do not load the INTVCC pin with external circuitry. VDD18 (Pin 7): Internal 1.8V Regulator Bypass. This pin must be bypassed to ground (SGND or PGND) with a 4.7µF or greater , low ESR ceramic capacitor . Do not load the V DD18 pin with external circuitry. VOUT0_CFG (Pin 8): Output Voltage Configuration for Channel 0. Connect a 1% resistor from V OUT0_CFG to ground (SGND or PGND) according to Table 2 in the Applications Information section to select one of six - teen output voltage set points. If left floating or tied to VDD18, the LT7182S will use the value of VOUT_COMMAND programmed in EEPROM. The V OUT0_CFG pin is read at LT7182S startup and reset. VOUT1_CFG /POLYPHASE_CFG (Pin 9) : Output Voltage Configuration for Channel 1 or Polyphase Configuration. If the SYNC/PWM_CFG pin is NOT configured for Polyphase, then a 1% resistor from V OUT1_CFG / POLYPHASE_CFG to ground (SGND or PGND) selects the voltage set point according to Table 2 in the Applications Information Section. If the SYNC/PWM_CFG pin is con- figured for Polyphase, then the channel 1 output is set to the same value as channel 0 based on V OUT0_CFG and a 1% resistor from V OUT1_CFG /POLYPHASE_CFG to SGND selects a Polyphase configuration according to Table 4 in the Applications Information section. The VOUT1_CFG /POLYPHASE_CFG pin is read at LT7182S startup and reset. ASEL (Pin 10): Serial Bus Address Configuration. Connect a 1% resistor from ASEL to ground (SGND or PGND) to select one of sixteen serial bus interface addresses. See the description of MFR_ADDRESS in the LT7182S PMBus/I2C Reference Manual. The ASEL pin is read at LT7182S startup and reset. If the ASEL pin is left float- ing, the factory default 7-bit device address is 0x4F . If the ASEL pin is grounded, the factory default device address is 0x40. BOOST1 (Pin 13): Boosted Floating Driver Supply. Connect a 0.1µF boost capacitor from BOOST1 to SW1 as close as possible to the IC, using the top PCB layer . The normal operation voltage swing of this pin is from DRVCC to PVIN1+DRVCC PGND (Pins 14, 19, 34, 39, Exposed Pad Pins 42-43): Power Ground. The (–) terminal of the PV IN0, PVIN1 input bypass capacitors, and the ( –) terminal of the output capacitors, C OUT0 and C OUT1, should be tied to these pins with low impedance connections. The PCB must be designed to provide low impedance electrical and thermal contact to power ground.

Rev. 0 For more information www.analog.com PIN FUNCTIONS PVIN1 (Pins 15, 18): Power Supply Input for Channel 1. These pins must be tied together and bypassed as close as possible to the LT7182S, with a low ESR capacitor of value 4.7µF or more. SW1 (Pins 16, 17, Exposed Pad Pin 44): Output of the Channel1 Internal Power Switches. Tie these pins together and connect them to the channel1 inductor and BOOST1 capacitor . This node should be kept small on the PCB for good performance. DRVCC (Pin 20): Internal 3.5V LDO Regulator Bypass. This regulator provides the supply current for the power FET drivers. This pin must be bypassed to PGND with a 10µF or greater , low ESR ceramic capacitor , as close as possible to the IC, using the top PCB layer . Do not load the DRVCC pin with external circuitry, with the optional exceptions of the pull-up resistor for the SHARE_CLK pin and/or the RUN0, RUN1, FAUL T0, or FAUL T1 pins. EXTVCC (Pin 21): Optional Power Supply Input. If con - nected to 3V to 5.5V, this pin will be used to derive the DRVCC, INTVCC, and VDD18 supplies. If one of the regulator outputs is set to VOUT of 3V or greater , that VOUT may be connected to EXTVCC to reduce power loss. If this pin is not tied to a regulator output, use a 0.1μF or greater local bypass ceramic capacitor on this pin, as close as possible to the LT7182S. SYNC/PWM_CFG (Pin 22): External Clock Synchronization Input/Output and/or PWM Configuration. When driven with an external clock, an internal phase-locked loop syn- chronizes the switching regulator output with the rising edge of the external clock. If this pin is to be used as a clock input, then a 1.5nF AC-coupling capacitor must be inserted in series with the clock source, unless the EEPROM is programmed to ignore the configuration resistors (MFR_CONFIG_ALL_LT7182S bit 6 set) in which case the clock source can be connected directly. If config- ured as an output (MFR_SYNC_CONFIG_LT7182S bit 0 set), the LT7182S will drive the SYNC/PWM_CFG pin out- put at the switching clock frequency set by FREQUENCY_ SWITCH, with a voltage swing of 0V to 1.88V (typical). Connect a 1% resistor from SYNC/PWM_CFG to ground (PGND or SGND) according to Table 3 in Applications Information to select frequency, phase, and mode con- figurations. The SYNC/PWM_CFG pin is read at LT7182S startup and reset. See Applications Information for more details. RUN0, RUN1 (Pin 24, Pin 23): Regulator Enable Inputs. Logic high enables the regulators. The RUN0 and RUN1 pins are pulled down with 1.5mA (typical) during POR and reset to facilitate sequencing with other regulators, but may be over-driven high by a digital output of another device. The pins may be tied directly to DRVCC to enable the regulators when input power is present. SHARE_CLK (Pin 25): Bidirectional Open-Drain Sequence Time Base Share Clock. Nominally 100kHz. Used to align startup and shutdown of regulator outputs among multiple ADI products when PolyPhase or time-based sequencing is employed. A pull-up resistor to 1.6V to 5.5V is required if the SHARE_CLK function is used. If neither PolyPhase nor time-based sequencing are required, SHARE_CLK may be tied to ground if bit 2 of MFR_CHAN_CONFIG_ LT7182S is programmed to zero for both channels (to ignore SHARE_CLK). WP (Pin 26): Write Protect Input. When this pin is high, only the PAGE, OPERATION, MFR_EE_UNLOCK , and CLEAR_FAULTS commands are writable. Clear individ- ual fault bits by writing a 1 to the respective bits in the STATUS commands.

Rev. 0For more information www.analog.com PIN FUNCTIONS FAUL T0, FAUL T1 (Pin 28, Pin 27): Fault Input/Open-Drain Outputs. The LT7182S pulls the pin down with 1.5mA (typical) when an unmasked fault occurs on the regula - tor . If another device pulls down on the FAUL T pin, the LT7182S regulator will turn off immediately. If PolyPhase configuration is used, tie together the FAUL T pins of all PolyPhase channels. If PolyPhase configuration is used, or if FAUL T pin reporting or sharing is required, a pull-up resistor of 6.8k or greater to 1.6V to 5.5V is required. FAUL T pins may be tied directly to DRVCC if the FAUL T pin function is not required. ALERT (Pin 29): Open Drain Alert Output. If the ALERT pin function is used, a pull-up resistor to 1.6V to 5.5V is required. If the ALERT pin function is not used, the pin may be tied to ground. SCL (Pin 30): Serial Bus Clock Input and Output. The LT7182S may hold SCL low if clock stretching is enabled (PMBus speeds 400kHz-1MHz only). A pull-up resistor to 1.6V to 5.5V is required for PMBus/I2C operation. If serial bus operation is not required, SCL may be tied to ground. SDA (Pin 31): Serial Bus Data Input and Output. A pull-up resistor to 1.6V to 5.5V is required for PMBus/I 2C oper- ation. If serial bus operation is not required, SDA may be tied to ground. PGOOD0, PGOOD1 (Pin 33, Pin 32): Power Good Indicator Open-Drain Outputs. PGOOD is pulled low when the regulator output is outside of the OV/UV fault thresh- olds, when the channel is disabled, and during on/off sequencing. The PGOOD output is deglitched by internal configurable timers. If the PGOOD pin function is used, a pull-up resistor to 1.6V to 5.5V is required. If the PGOOD pin function is not used, these pins may tied to PGND. PV IN0 (Pins 35, 38): Power Supply Input for Channel 0 and Internal LDO Regulators. These pins must be tied together and bypassed to PGND as close as possible to the LT7182S, with a low ESR capacitor of value 4.7µF or more. If EXTV CC < 3V, then the internal LDO regulators (for DRVCC, INTVCC, and VDD18) pull power from PVIN0. SW0 (Pins 36, 37, Exposed Pad Pin 41): Output of the Channel0 Internal Power Switches. Tie these pins together and connect them to the channel0 inductor and BOOST0 capacitor . This node should be kept small on the PCB for good performance. BOOST0 (Pin 40): Boosted Floating Driver Supply. Connect a 0.1µF boost capacitor from BOOST0 to SW0 as close as possible to the IC, using the top PCB layer . The normal operation voltage swing of this pin is from DRVCC to PVIN0+DRVCC.

Rev. 0 For more information www.analog.com BLOCK DIAGRAM 7182s BD SYNC/ PWM_CFG ASEL SWRCLK1 VOUT1_CFG/ POLYPHASE_CFG VOUT0_CFG DRVCC VDD18 INTVCC PHASE SELECT SWRCLK0 PLL/ OSCILLATOR CONFIGURATION RESISTOR READER LDO PGOOD1 SHARE_CLK PGOOD0 RUN1 RUN0 FAULT1 FAULT0 SEQUENCE CONTROL WP ALERT SCL SDA I2C/PMBUS INTERFACE FAULT CONTROL MAIN CONTROL LOGIC ON-TIME CONTROL VOUT DIVIDER COMP SELECT PWM LOGIC ADC CURRENT SENSE CHANNEL1 (SAME AS CHANNEL0) CHANNEL0 LDO A/D D/A VOUT CONTROL EN 2.925V ADC CONTROL EXTVCC LDO PVIN0 EN LDO EN LDO PVIN0 EN IOUT0 VOUT0 VOUT1 IOUT1 PVIN1 PVIN0 EEPROM PGND ITH1 VSENSE1N VSENSE1P SW1 PVIN1 PGND PVIN BOOST0 BOOST0 VSENSE0N VSENSE0P SW0 SWRCLK0 SW0 gMEA CONTROL PVIN0 ITH0 DRVCC MPBST MNTOP DRVCC MNBOT CURRENT COMPARATOR REVERSE CURRENT COMPARATOR BG FB TG VOUT_OV + EA D/A VOUT_OV CONTROL VOUT_UV + D/A VOUT_UV CONTROL VIN_ON + D/A VIN_ON CONTROL RITH SELECT CITH SELECT

Rev. 0For more information www.analog.com OPERATION OVERVIEW The LT7182S is a dual-output monolithic PolyPhase DC/ DC synchronous step-down regulator . The S in LT7182S refers to the second generation Silent Switcher tech - nology, which provides fast and clean switching edges, reduces overall solution size, improves efficiency, and minimizes EMI emissions. The I2C-based serial interface is compatible with PMBus 1.3 which supports bus speeds of up to 1MHz. Major features include: Programmable Output Voltage

  • Programmable Current Limit
  • Programmable Switching Frequency
  • Programmable Output Overvoltage and Undervoltage Fault and Warning Thresholds
  • Programmable On and Off Delay Times
  • Programmable Output Rise/Fall Times
  • Programmable Control Loop Compensation
  • Programmable Input Undervoltage Threshold
  • Dedicated Power Good Pin for Each Channel
  • Phase-Locked Loop for Synchronous, PolyPhase Operation (2, 3, 4, 6 or 8 Phases)
  • Input and Output Voltage/Current, and Die T emperature Telemetry
  • Fully Differential Remote VOUT Sense
  • Nonvolatile Configuration Memory with ECC
  • Nonvolatile Event-Based Fault Log
  • Optional External Configuration Resistors for Key Operating Parameters
  • Optional Time-Base Inter connect for Synchronization Between Multiple Devices
  • WP Pin to Write-Protect Internal Configuration
  • Standalone Operation using Configuration Resistors or Nonvolatile Configuration Memory A variety of mechanisms for fault and warning handling are available. Fault and warning detection capabilities include: Output Undervoltage/Over voltage Fault and Warning
  • Internal Overtemperature Fault and Warning
  • Communication, Memory or Logic (CML) Fault
  • Input Overvoltage Fault and Under voltage Warning
  • Output Overcurrent Fault and W arning
  • Average Input Overcurrent W arning
  • Internal Reference Fault
  • External Fault Detection via the Bidirectional F AUL T Pins. A dedicated ALERT pin is provided to indicate that faults or warnings have occurred. Individual status commands enable fault and warning reporting to identify the specific event. The FAUL T pins of the LT7182S enable fault sharing between channels and with other ADI power system management products including the LTC3880, LTC2974, LTC2978, LTC4676 µModule®, etc. Fault reporting and shutdown behavior are fully con - figurable using the FAUL T pins and the MFR_FAULT_ PROPAGATE_LT7182S command. Faults can be individ- ually masked and the fault responses can be programmed to retry (unlatched) or latch-off the regulator output. SWITCHING REGULATOR CONTROL LOOP The LT7182S employs a controlled on-time, valley current mode architecture. In normal operation, the internal top power MOSFET is turned on for an interval determined by an on-time control circuit. When the top power MOSFET turns off, the bottom power MOSFET turns on until the valley current comparator trips, restarting the on-time control circuit and initiating the next cycle. Inductor cur- rent is determined by sensing the voltage drop across the bottom power MOSFET when it is on. The voltage on the ITH pin sets the comparator threshold correspond - ing to the inductor valley current. The error amplifier , EA, adjusts the I TH voltage by comparing the output voltage

average inductor current matches that of the load current. resistors (see Applications Information for more details). Table 4. Pulse-skip mode is always used during soft-start. switching frequency, and faster transient response. atile user configuration settings and fault log information. until the issue is resolved. gramming, including bulk EEPROM programming. is 2.9V to 20V. The PVIN1 operating range is 1.5V to 20V. supply sequencing of the LT7182S. determined by EEPROM or factory defaults.

Rev. 0For more information www.analog.com OPERATION LT7182S initialization typically requires 13ms. If CFG pins are disabled (MFR_CONFIG_ALL_LT7182S bit 6 set to 1 in EEPROM), the initialization time is reduced to 10ms (typical). After initialization is complete, comparators monitor PVIN0 and PVIN1. The PVIN voltage must exceed the channel’s programmable VIN_ON threshold for the channel to oper- ate. By default, SHARE_CLK will be held low until PV IN0 exceeds VIN_ON for PAGE 0, or if PVIN0 falls below VIN_OFF. By default, PVIN1 does not affect SHARE_CLK. The default behavior for both channels is to turn off and remain off if SHARE_CLK is low. See the MFR_CHAN_CONFIG_ LT7182S command in the LT7182S PMBus/I2C Reference Manual for information on how to configure this behavior . The RUN pin pull-down current (1.5mA typical) is released by the LT7182S after the device completes POR initializa- tion and the first time the channel’s PVIN potential exceeds the VIN_ON threshold. SOFT-START When all conditions required for startup have been met, and a channel is enabled, the LT7182S waits for the com- manded turn-on delay and ramps the target output voltage up to the commanded voltage set-point. The soft-start rise time is set by the TON_RISE command, default 1ms. The turn-on delay is set by TON_DELAY, which is 0ms by fac- tory default. The LT7182S PWM always uses pulse-skip mode during soft-start, which allows the regulator to start up into a pre-biased load. If forced continuous conduc - tion mode is selected (MFR_PWM_MODE_LT7182S bit 0 cleared to 0), the channel will transition to continuous conduction mode after the commanded voltage set-point is reached. SHUTDOWN The LT7182S can be programmed to turn off immediately or to sequence off. When sequencing off, the LT7182S waits for the turn-off delay then performs a soft-stop ramp in which the regu- lation target voltage is ramped down to zero. The turn-off delay is set by the TOFF_DELAY command, default zero. The target voltage ramp-down time is set by TOFF_FALL, default 2ms. By default, the channel will ramp down in forced continuous conduction mode. The ramp-off behav- ior can be configured using MFR_PWM_MODE_LT7182S. Sequencing off occurs if OPERATION is set to 0x40, or if the RUN pin is de-asserted and ON_OFF_CONFIG bit 0 is set to 0 and bit 2 is set to 1. When immediate turn-off occurs, the regulator ramps the inductor current to zero as quickly as possible and then stops switching. In this case, the output voltage will decay based only on the load current and the optional internal 250Ω pull-down. The internal 250Ω pull-down can be disabled by clearing bit 6 of MFR_CHAN_CONFIG_ LT7182S. Immediate shutdown occurs in any the follow- ing situations:

  • PVIN falls below the VIN_OFF threshold
  • If the OPERATION command is cleared to 0x00, if ON_OFF_CONFIG bit 3 is set to 1
  • A fault condition occurs which causes the output to turn off
  • The RUN pin is de-asserted and ON_OFF_CONFIG has been configured such that RUN pin de-assertion causes immediate shutdown (ON_OFF_CONFIG bits 0 and 2 both set to 1) The F AUL T pin for the channel is pulled low externally, unless MFR_FAULT_RESPONSE has been cleared to 0x00.
  • Loss of SHARE_CLK , unless bit 2 of MFR_CHAN_ CONFIG_LT7182S has been cleared WARNING AND FAUL T HANDLING The LT7182S continuously monitors the system for fault and warning conditions. Fault responses are configurable using the correspond - ing FAULT_RESPONSE commands, such as VOUT_UV_ FAULT_RESPONSE, VOUT_OV_FAULT_RESPONSE, etc. Possible fault responses are as follows:
  • Continue Operation (Ignore)
  • Shut down immediately and retry if fault condition is no longer present

Rev. 0 For more information www.analog.com OPERATION

  • Shut down immediately and latch off The remainder of this section describes the factory default warning and fault behavior . See Table 1. See the LT7182S PMBus/I2C Reference Manual for details on configuring fault and warning behavior . All faults and warnings are indicated in PMBus STATUS commands. When a warning occurs related to output voltage, output current, or temperature, the LT7182S pulls the ALERT pin low, the corresponding bit is set in the appropriate STATUS command(s), and the channel continues to operate. If the output voltage falls below VOUT_UV_FAULT_LIMIT, the LT7182S responds as follows: The channel’s PGOOD pin is pulled low
  • The ALER T pin is pulled low
  • The VOUT_UV fault bit is set in the STATUS_VOUT, STATUS_BYTE, and STATUS_WORD commands.
  • The channel continues to operate while limiting the maximum valley current If a fault occurs due to output overvoltage, or input over- voltage, the LT7182S responds as follows: The faulted channel(s) are shut down immediately.
  • The channel’s FAUL T pin and PGOOD pin are pulled low
  • The ALERT pin is pulled low
  • The corresponding indicator bit(s) are set in the appro- priate STATUS command(s)
  • After 10ms (time defined by MFR_RETRY_DELAY), the channel attempts to restart when the fault condition is no longer present If a fault occurs due to overtemperature, the LT7182S responds as follows:
  • Both channels are shut down immediately.
  • Both channels’ FAUL T pins and PGOOD pins are pulled low
  • The ALER T pin is pulled low
  • The overtemperature (OT) bit is set in the appropriate STA TUS command(s)
  • When the ADC measures that the temperature is below the overtemperature threshold, the channel attempts to restart The LT7182S periodically compares the primary internal voltage reference against a secondary internal voltage ref- erence using the ADC. If a failure is detected, the LT7182S responds as follows:
  • Both channels are shut down immediately.
  • The F AUL T pins, PGOOD pins, and ALERT pins are pulled low
  • The internal reference fault bit is set in the STATUS commands
  • Both channels remain off unless the reference recovers (for example due to temperature drift), a RESTORE_ USER_ALL or MFR_RESET command is received, or input power is removed from both PV IN0 and EXTVCC FAUL T Pins A fault will cause the FAUL T pin to pull low if the corre- sponding FAULT_RESPONSE command is programmed to shut down the regulator output and the MFR_FAULT_ PROPAGATE_LT7182S command is configured to prop- agate the fault to the open-drain FAUL T pins. Once the LT7182S pulls down a FAUL T pin, the device will continue to hold the pin low until one of the following occurs:
  • The channel retries, for faults that are configured to retry
  • The faulted channel is disabled then re-enabled
  • A RESTORE_USER_ALL or MFR_RESET command is received
  • Input power is removed from both PVIN0 and EXTVCC The FAUL T pin can also be used as an input to provide a method for the LT7182S to respond to external faults. The channel turns off immediately if the channel’s FAUL T pin is pulled low externally. This enables coordination of faults among multiple power system management products.

down the open-drain ALERT pin.

  • A CLEAR_FAULTS, RESTORE_USER_ALL or MFR_ RESET command is received
  • All unmasked status bits are cleared by writing a 1 to each bit
  • The LT7182 S successfully transmits its address during a PMBus ARA
  • Input power is removed from both PVIN0 and EXTVCC Fault Event Logging If a fault condition occurs that is configured to turn off the regulator output, an event is written in the fault log in EEPROM. Any preceeding warning or fault that is not configured to turn off the output is written as a sub - event when an event is written. A timestamp is written with each event and subevent. The fault log stores up to three fault-off events. The fault log may be read by the MFR_FAULT_LOG command. The fault log is cleared from EEPROM by writing the MFR_FAULT_LOG_CLEAR command. The fault log function is enabled by default and may be disabled by clearing bit 7 of MFR_CONFIG_ALL. See the MFR_FAULT_LOG command in the LT7182S PMBus/I2C Reference Manual for more details.

Table 1. Factory-Default Warning and Fault Behavior (Note 1) Note 1. See the LT7182S PMBus/I2C Reference Manual for detailed information including configuring thresholds and responses. Note 2. The IOUT_OC_FAULT valley current threshold is controlled by MFR_PWM_MODE_LT7182S bits [10:9].

configuration pin is described in the sections below. configuration resistor selection. output voltage when the channel is enabled. Table 2. VOUTn_CFG Pin Configuration Resistor Selection (Note 1) Regulator disabled and RUN pin ignored. VOUT1_CFG/POLYPHASE_CFG configuration resistor controls PWM settings including frequency and phase per Table 4. Note 2. Output voltage set point is controlled by VOUT_COMMAND. Note 3. VOUT Range Mode selection is controlled by MFR_PWM_MODE_LT7182S bit 1. A value of 1 selects High-Performance Low-VOUT mode. Note 4. The PMBus ON_OFF_CONFIG command selects whether the RUN pin and/or PMBus OPERATION command enable the regulator .

Table 3. SYNC/PWM_CFG Pin Configuration Resistor Selection configuration, VOUT for both channels is initialized to the value specified by the VOUT0_CFG resistor . Note 1. PWM Switching frequency set point is controlled by FREQUENCY_SWITCH, if no SYNC/PWM_CFG input clock is present. switching frequency to a similar value to the input clock. Note 3. Steady-State PWM Switching Phase is controlled by MFR_PWM_PHASE_LT7182S. Note 4. PWM Mode is controlled by MFR_PWM_MODE_LT7182S bit 0. A value of 1 enables pulse-skip mode. Note 5. Poly-phase follower/leader mode is controlled by MFR_CHAN_CONFIG_LT7182S bit 8. A value of 1 selects follower mode. mode and gmEA = 150µS for Standard mode, regardless of internal or external compensation. Note 8. The SYNC/PWM_CFG pin is a clock output when MFR_SYNC_CONFIG_LT7182S bit 0 is set to 1.

  • 625kHz to 1.25MHz: RITH = 40kΩ, CITH = 80pF
  • 1.25MHz to 2.5MHz: RITH = 40kΩ, CITH = 80pF
  • 2.5MHz to 4MHz: RITH = 40kΩ, CITH = 60pF

resistor must be added in series with the clock source. See Table 2 for PWM_CFG resistor selections. figuration resistor that selects a PWM frequency of 1MHz. uration resistor that selects a PWM frequency of 4MHz. figuration resistor or AC-coupling capacitor is required. regarding pin configuration faults. Figure 2. PWM Resistor Configuration and an External be configured as followers (value set to 1). CONFIG_ALL_LT7182S bit 6 is not set to ignore CFG pins. the appropriate phase (MFR_PWM_PHASE_LT7182S).

primary disadvantage is lower efficiency. VIN and minimum VOUT for the application. Figure 3. Example Four-Phase PolyPhase 1.2V, 1Mhz, 24A Regulator Using Resistor Configuration Pins with No External Clock

Table 4. PolyPhase Operation VOUT1_CFG/POLYPHASE_CFG Pin Configuration Resistor Selection (Note 1) voltage for channel 1 according to Table 2. Note 2. PWM Switching frequency is controlled by FREQUENCY_SWITCH, if no SYNC/PWM_CFG input clock is present. Note 3. Steady-State PWM Switching Phase is controlled by MFR_PWM_PHASE_LT7182S. Note 4. PWM Mode is controlled by MFR_PWM_MODE_LT7182S bit 0. A value of 1 enables pulse-skip mode. Note 5. PolyPhase follower mode is controlled by MFR_CHAN_CONFIG_LT7182S bit 8. A value of 1 selects follower mode. sponds to the maximum tOFF(MIN) for the LT7182S. waveform, as shown in Figure 4 and Figure 5.

Table 7. Programmable Internal Compensation Lead Resistor RITH Table 8. Programmable Internal Compensation Capacitor CITH soft-start ramp begins at the correct point in the sequence. using the TOFF_DELAY command. the value set in VOUT_UV_FAULT_LIMT. Figure 8. Event-Based Sequencing system management products including the LT7182S.

Figure 9. L TpowerPlay GUI Screen Shot ing the supported PMBus commands.

Rev. 0 For more information www.analog.com PMBUS COMMAND SUMMARY COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE PAGE_PLUS_READ 0x06 Read a command directly from a specified page. Block R/W N ZONE_CONFIG 0x07 Assigns current page to specified zone number for ZONE_WRITE operations. W Word Y Reg Y 0xFEFE ZONE_ACTIVE 0x08 Selects active zone for ZONE_WRITE operations. W Word Reg 0xFEFE WRITE_PROTECT 0x10 Level of protection provided by the device against accidental changes. R/W Byte N Reg Y 0x00 STORE_USER_ALL 0x15 Store user operating memory to EEPROM. Send Byte N RESTORE_USER_ALL 0x16 Restore user operating memory from EEPROM. Send Byte N CAPABILITY 0x19 Summary of PMBus optional communication protocols supported by this device. R Byte N Reg 0xD8 QUERY 0x1A Asks if a given command is supported, and what data formats are supported. Block R/W N Reg SMBALERT_MASK 0x1B Masks ALERT activity. Block R/W Y Reg Y VOUT_MODE 0x20 Output voltage format and exponent. R Byte N Reg 0x60 VOUT_COMMAND 0x21 Nominal output voltage set point. R/W Word Y IEEE/ UL16 V Y 0.5 0x3800 VOUT_MAX 0x24 Upper limit on the commanded output voltage. R/W Word Y IEEE/ UL16 V Y 0.537 0x384C VOUT_MARGIN_HIGH 0x25 Margin high output voltage set point. R/W Word Y IEEE/ UL16 V Y 0.525 0x3833 VOUT_MARGIN_LOW 0x26 Margin low output voltage set point. R/W Word Y IEEE/ UL16 V Y 0.475 0x379A VOUT_TRANSITION_RATE 0x27 Rate the output changes when VOUT commanded to a new value. R/W Word Y IEEE/ L11 V/ms Y 0.25 0x3400 FREQUENCY_SWITCH 0x 33 Switching frequency of the regulator . R/W Word N IEEE/ L11 kHz Y 1000.0 0x63D0 VIN_ON 0x35 Input voltage at which the unit should start power conversion. R/W Word Y IEEE/ L11 V Y Ch. 0: 1.5 0x3E00 Ch. 1: 1.4 0x3D9A VIN_OFF 0x36 Input voltage at which the unit should stop power conversion. R/W Word Y IEEE/ L11 V Y Ch. 0: 1.45 0x3DCD Ch. 1: 1.35 0x3D66 VOUT_OV_FAULT_LIMIT 0x 40 Output overvoltage fault limit. R/W Word Y IEEE/ L11 V Y 0.55 0x3866 VOUT_OV_FAULT_ RESPONSE 0x41 Action to be taken by the device when an output overvoltage fault is detected. R/W Byte Y Reg Y 0xB8 VOUT_OV_WARN_LIMIT 0x42 Output overvoltage warning limit. R/W Word Y IEEE/ L11 V Y 0.537 0x384C VOUT_UV_WARN_LIMIT 0x43 Output undervoltage warning limit. R/W Word Y IEEE/ L11 V Y 0.467 0x3779 VOUT_UV_FAULT_LIMIT 0x44 Output undervoltage fault limit. R/W Word Y IEEE/ L11 V Y 0.465 0x3771 VOUT_UV_FAULT_ RESPONSE 0x45 Action to be taken by the device when an output undervoltage fault is detected. R/W Byte Y Reg Y 0x00 IOUT_OC_FAULT_ RESPONSE 0x47 Action to be taken by the device when an output overcurrent fault is detected. R/W Byte Y Reg Y 0x00

Rev. 0For more information www.analog.com PMBUS COMMAND SUMMARY COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE IOUT_OC_WARN_LIMIT 0x4A Output overcurrent warning limit. R/W Word Y IEEE/ L11 A Y 8.0 0x4800 OT_FAULT_LIMIT 0x4F Internal overtemperature fault limit. R/W Word N IEEE/ L11 C Y 160.0 0x5900 OT_FAULT_RESPONSE 0x50 Action to be taken by the device when an internal overtemperature fault is detected. R/W Byte N Reg Y 0xC0 OT_WARN_LIMIT 0x51 Internal overtemperature warning limit. R/W Word N IEEE/ L11 C Y 140.0 0x5860 VIN_OV_FAULT_RESPONSE 0x56 Action to be taken by the device when an input overvoltage fault is detected. R/W Byte Y Reg Y 0xB8 VIN_UV_WARN_LIMIT 0x58 Input supply undervoltage warning limit. R/W Word Y IEEE/ L11 V Y -1.0 0xBC00 IIN_OC_WARN_LIMIT 0x5D Input supply overcurrent warning limit. R/W Word Y IEEE/ L11 A Y 8.0 0x4800 TON_DELAY 0x60 Time from RUN and/or Operation on to output rail turn-on. R/W Word Y IEEE/ L11 ms Y 0.0 0x0000 TON_RISE 0x61 Time from when the output starts to rise until the output voltage reaches the V OUT commanded value. R/W Word Y IEEE/ L11 ms Y 1.0 0x3C00 TON_MAX_FAULT_LIMIT 0x62 Maximum time from the start of TON_RISE for V OUT to cross the VOUT_UV_FAULT_LIMIT. R/W Word Y IEEE/ L11 ms Y 5.0 0x4500 TON_MAX_FAULT_ RESPONSE 0x63 Action to be taken by the device when a TON_ MAX_FAULT event is detected. R/W Byte Y Reg Y 0x00 TOFF_DELAY 0x64 Time from RUN and/or Operation off to the start of TOFF_FALL ramp. R/W Word Y IEEE/ L11 ms Y 0.0 0x0000 TOFF_FALL 0x65 Time from when the output starts to fall until the output reaches zero volts. R/W Word Y IEEE/ ms Y 2.0 0x4000 TOFF_MAX_WARN_LIMIT 0x66 Maximum allowed time, after TOFF_FALL completed, for the unit to decay below MFR_DISCHARGE_THRESHOLD. R/W Word Y IEEE/ L11 ms Y 0.0 0x0000 STATUS_BYTE 0x78 One byte summary of the unit’s fault condition. R/W Byte Y Reg STATUS_WORD 0x79 T wo byte summary of the unit’s fault condition. R/W Word Y Reg STATUS_VOUT 0x7A Output voltage fault and warning status. R/W Byte Y Reg STATUS_IOUT 0x7B Output current fault and warning status. R/W Byte Y Reg STATUS_INPUT 0x7C Input supply fault and warning status. R/W Byte Y Reg STATUS_TEMPERATURE 0x7D Internal temperature fault and warning status for READ_TEMERATURE_1. R/W Byte N Reg STATUS_CML 0x7E Communication and memory fault and warning status. R/W Byte N Reg STATUS_MFR_SPECIFIC 0x80 Manufacturer specific fault and state information. R/W Byte Y Reg READ_VIN 0x88 Measured input supply voltage. R Word Y IEEE/ L11 V READ_IIN 0x89 Measured input supply current. R Word Y IEEE/ L11 A READ_VOUT 0x8B Measured output voltage. R Word Y IEEE/ UL16 V

Rev. 0 For more information www.analog.com PMBUS COMMAND SUMMARY COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE READ_IOUT 0x8C Measured output current. R Word Y IEEE/ L11 A READ_TEMPERATURE_1 0x8D Measured internal temperature. R Word N IEEE/ L11 C READ_FREQUENCY 0x95 Measured PWM switching frequency. R Word Y IEEE/ L11 READ_POUT 0x96 Calculated output power . R Word Y IEEE/ L11 PMBUS_REVISION 0x98 PMBus revision supported by this device. Current revision is 1.3. R Byte N Reg 0x33 MFR_ID 0x99 The manufacturer ID in ASCII. R Block N “ADI” MFR_MODEL 0x9A The part number in ASCII. R Block N “LT7182S” MFR_REVISION 0x9B Part revision number . R Block N MFR_SERIAL 0x9E Unique part serial number . R Block N IC_DEVICE_ID 0xAD Identification of the IC in ASCII. R Block N “LT7182S” IC_DEVICE_REV 0xAE Revision of the IC. R Block N MFR_EE_UNLOCK 0xBD Contact factory. MFR_EE_ERASE 0xBE Contact factory. MFR_EE_DATA 0xBF Contact factory. MFR_USER_DATA_00 0xC9 EEPROM word available for user . R/W Word N Reg Y 0x0000 MFR_USER_DATA_01 0xCA EEPROM word available for user . R/W Word N Reg Y 0x0000 MFR_USER_DATA_02 0xCB EEPROM word available for user . R/W Word N Reg Y 0x0000 MFR_USER_DATA_03 0xCC EEPROM word available for user . R/W Word N Reg Y 0x0000 MFR_READ_EXTVCC 0xCD Measured EXTV CC voltage, when enabled. R Word N IEEE/ L11 V MFR_READ_ITH 0xCE Measured I TH voltage, when enabled. R Word Y IEEE/ L11 V MFR_CHAN_CONFIG_ LT7182S OxD0 Configuration bits that are channel specific. R/W Word Y Reg Y Ch. 0: 0x00D7 Ch. 1: 0x0057 MFR_CONFIG_ALL_ LT7182S 0xD1 General configuration bits. R/W Word N Reg Y 0x0100 MFR_FAULT_PROPAGATE_ LT7182S 0xD2 Configuration that determines which faults are propagated to the FAUL T pin. R/W Word Y Reg Y 0xE0D7 MFR_PWM_MODE_ LT7182S 0xD4 Configuration for the PWM engine. R/W Word Y Reg Y 0x1DD4 MFR_FAULT_RESPONSE 0xD5 Action to be taken by the device when the FAUL T pin is externally asserted low. R/W Byte Y Reg Y 0xC0 MFR_IOUT_PEAK 0xD7 Report the maximum measured value of READ_ IOUT since last MFR_CLEAR_PEAKS. R Word Y IEEE/ L11 A MFR_ADC_CONTROL_ LT7182S 0xD8 Configures the update rate of the measurements taken by the ADC. R/W Byte N Reg Y 0x00 MFR_RETRY_DELAY 0xDB Retry interval during fault retry mode. R/W Word Y IEEE/ L11 ms Y 10.0 0x4900

Rev. 0For more information www.analog.com PMBUS COMMAND SUMMARY COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE MFR_RESTART_DELAY 0xDC Minimum time the RUN pin is held low by the LT7182S. R/W Word Y IEEE/ L11 ms Y 10.0 0x4900 MFR_VOUT_PEAK 0x DD Maximum measured value of READ_VOUT since last MFR_CLEAR_PEAKS. R/W Word Y IEEE/ UL16 V MFR_VIN_PEAK 0xDE Maximum measured value of READ_VIN since last MFR_CLEAR_PEAKS. R/W Word Y IEEE/ L11 V MFR_TEMPERATURE_1_ PEAK 0xDF Maximum measured value of internal temperature (READ_TEMPERATURE_1) since last MFR_CLEAR_PEAKS. R/W Word N IEEE/ L11 C MFR_CLEAR_PEAKS 0xE3 Clears all peak values. Send Byte N MFR_DISCHARGE_ THRESHOLD 0xE4 Output voltage used to determine output has decayed sufficiently to re-enable the channel. R/W Word Y IEEE/ L11 Y 0.2 0x3266 MFR_PADS_LT7182S 0xE5 Digital status of the I/O pads. R Word N Reg MFR_ADDRESS 0xE6 Sets the 7-bit I 2C address byte. R/W Word N Reg Y 0x4F MFR_SPECIAL_ID 0xE7 ID code used by manufacturer . R Word N Reg 0x1C1D MFR_FAULT_LOG_ TIMESTAMP_MSBS 0xE8 Sets the fault log timestamp upper 13 bits, clears lower 32 (read and write first) R/W 32 N MFR_FAULT_LOG_ TIMESTAMP_LSBS 0xE9 Sets the fault log timestamp lower 32 bits. R/W 32 N MFR_FAULT_LOG_STORE 0xEA Force a fault log entry to be written. Send Byte N MFR_FAULT_LOG_CLEAR 0xEC Erases all fault log entries, if any. Send Byte N MFR_FAULT_LOG 0xEE Read contents of fault log, if any. R Block N Reg MFR_COMMON 0xEF Manufacturer status bits that are common across multiple ADI chips. R Byte N Reg MFR_COMPARE_USER_ALL 0xF0 Compares current command contents with EEPROM. Send Byte N MFR_CHANNEL_STATE 0xF1 Returns the state of the channel. R Byte Y Reg MFR_PGOOD_DELAY 0xF2 Time output voltage must be between UV and OV before PGOOD transitions high. R/W Word Y IEEE/ L11 ms Y 1.0 0x3C00 MFR_NOT_PGOOD_DELAY 0xF3 Time output voltage must be below UV or above OV before PGOOD transitions low. R/W Word Y IEEE/ L11 ms Y 0.1 0x2E66 MFR_PWM_PHASE_ LT7182S 0xF5 Set PWM phase. R/W Word Y IEEE/ L11 Degrees Y Ch. 0: 0.0 0x0000 Ch. 1: 180.0 0x59A0 MFR_SYNC_CONFIG_ LT7182S 0xF6 SYNC pin input/output configuration. R/W Byte N Reg Y 0x00 MFR_PIN_CONFIG_STATUS 0xF7 Pin configuration fault status. R Byte N Reg MFR_RAIL_ADDRESS 0xFA Common address for PolyPhase outputs to adjust common parameters. R/W Byte Y Reg Y 0x80 MFR_DISABLE_OUTPUT 0xFB Disables regulator outputs until reset. R/W Byte N Reg 0x00 MFR_EE_USER_WP 0xFC Disables commands that write user NVM. R/W Byte N Reg Y 0x00 MFR_RESET 0xFD Commanded reset without requiring a power down. Send Byte N

Rev. 0 For more information www.analog.com PMBUS COMMAND SUMMARY Abbreviations of Supported Data Formats PMBus DEFINITION EXAMPLETERMINOLOGY SPECIFICATION REFERENCE L11 Linear11 Rev 1.3.1 Part II 7.3 Floating point 16-bit data: value = Y • 2 N, where N = b[15:11] and Y = b[10:0], both two’s compliment binary integers. b[15:0] = 0x9807 = 7 • 2 –13 = 8.54 • 10–4 where Y = b[15:0], an unsigned integer . b[15:0] = 0x4C00 = 19456 • 2–12 = 4.75 Reg Per-bit meaning defined in command description in the LT7182S PMBus/I Reference Manual PMBus STATUS_BYTE command. IEEE IEEE-754 Half Precision Floating Point Rev 1.3.1 Part II 8.4.4 Floating point 16-bit data: for normal values, value = (−1 )S • 2N−15 • 1+ M 1024 ⎝⎜ ⎞ ⎠⎟ , where 1024 ⎝⎜ ⎞ ⎠⎟ = 5.5 BOARD LAYOUT CONSIDERATIONS LAYOUT CONSIDERATIONS Note that large, switched currents flow in the LT7182S PVIN and PGND pins and the input capacitors. The loops formed by the input capacitors should be as small as possible by placing the capacitors adjacent to the PV IN and PGND pins. The input capacitors, along with the inductor and output capacitors, should be placed on the same side of the circuit board, and their connections should be made on that layer . Place a local, unbroken ground plane under the applica - tion circuit on the layer closest to the surface layer . SGND should be connected to PCB ground at exactly one point, directly under the LT7182S adjacent to the SGND pin. The SW and BOOST nodes should be as small as possible. For more detail and PCB design files refer to the Demo Board guide for the LT7182S. THERMAL CONSIDERATIONS Care should be taken in the layout of the PCB to ensure good heat dissipation from the LT7182S. The ground pins on the bottom of the package should be soldered to a ground plane. This ground should be tied to large copper layers below with thermal vias; these layers will spread heat dissipated by the LT7182S. Placing additional vias can reduce thermal resistance further . The maximum load current must be derated as the ambient temperature approaches the maximum junction rating. Temperature rise of the LT7182S is worst when operat - ing at high load, high VIN, and high switching frequency. If the case temperature is too high for a given applica - tion, then either V IN, switching frequency, or load cur - rent can be decreased to reduce the temperature to an acceptable level. The internal junction temperature of the LT7182S is reported via the READ_TEMPERATURE_1 command.

Figure 10. Recommended PCB Layout

Rev. 0 For more information www.analog.com TYPICAL APPLICATIONS Three-Phase 0.8V, 18A, 1MHz Regulator and Single-Phase 3.3V, 6A, 1MHz Regulator PMBUS/ I2C BUS L T7182S SYNC/PWM_CFG VOUT1_CFG/ POL YPHASE_CFG PVIN0 PVIN1 SHARE_CLK FAUL T0 FAUL T1 VSENSE0P VSENSE0N VOUT0_CFG SW0 21k 10µF VOUT1 3.3V VOUT0 0.8V 18A INTVCC ITH0 ITH1 RUN0 RUN1 200µF WP PGOOD0 PGOOD1 VDD18 SDA SCL ALERT 1.5µH BOOST0 SGND PGND 4.7µF 0.1µF BOOST1 EXTVCC SW1 VSENSE1P VSENSE1N 7182S TA02 0.1µF 400µF DRVCC ASEL 107k 10µF 0.47µH 80.6k L T7182S SYNC/PWM_CFG VOUT1_CFG/ POL YPHASE_CFG PVIN0 VIN 2.9V TO 20V PVIN1 SHARE_CLK FAUL T0 FAUL T1 VSENSE0P VSENSE0N VOUT0_CFG SW0 21k 10µF DRVCC ITH0 RUN0 RUN1 WP PGOOD0 PGOOD1 EXTVCC VOUT1 SDA SCL ALERT 0.47µH BOOST0 PGND ITH1 10µF INTVCC VDD18 SGND 4.7µF 1.5nF 1.5nF 0.1µF BOOST1 SW1 VSENSE1P VSENSE1N 0.1µF ASEL 51.1k 0.47µH 5.6k 10k 10k 10k 10k

Rev. 0For more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. PACKAGE DESCRIPTION 40-Lead (7mm × 5mm × 0.9mm) (Reference L TC DWG # 05-08-1607 Rev Ø) DETAIL B A PACKAGE TOP VIEW PAD “A1” CORNER Y X aaa Z2× PACKAGE BOTTOM VIEW SEE NOTES E D b 0.375 e e b 0.25 0.25 0.40 0.40 0.25 0.25 0.25 1.275 1.275 2.65 1.575 1.60 1.60 LQFN 40 0118 REV ØPACKAGE IN TRAY LOADING ORIENTATION DETAIL B SUBSTRATE MOLD CAP // bbb Z Z DETAIL A DETAIL C SUGGESTED PCB LAYOUT TOP VIEW 0.000 0.000 0.250 0.250 0.750 0.750 1.250 1.250 1.750 1.750 2.750 2.250 2.750 2.250 0.750 0.250 0.250 0.750 1.750 1.250 1.250 1.750 PIN 1 NOTCH 0.25 × 45° 33 40 20 13 aaa Z 2× M X Y Z ccc MXY Z ccc 0.25 0.25 0.25 1.275 1.275 2.65 1.5751.575 0.25 ±0.05 0.70 ±0.05 7.50 ±0.05 5.50 ±0.05 TRAY PIN 1 BEVEL COMPONENT PIN “A1” L TXXXXXX ddd Z 40 × 40b e SYMBOL A L b D E e aaa bbb ccc ddd eee fff MIN 0.80 0.02 0.30 0.22 NOM 0.90 0.03 0.40 0.25 5.00 7.00 0.50 0.20 0.70 MAX 1.00 0.04 0.50 0.28 0.10 0.10 0.10 0.10 0.15 0.08 NOTES DIMENSIONS Z DETAIL C DETAIL A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. PRIMARY DATUM -Z- IS SEATING PLANE METAL FEATURES UNDER THE SOLDER MASK OPENING NOT SHOWN SO AS NOT TO OBSCURE THESE TERMINALS AND HEAT FEATURES DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE

6 THE EXPOSED HEAT FEATURE IS SEGMENTED AND ARRANGED

IN A MATRIX FORMAT . IT MAY HAVE OPTIONAL CORNER RADII ON EACH SEGMENT

7 CORNER SUPPORT PAD CHAMFER IS OPTIONAL

0.375 0.375 1.60

Rev. 0 For more information www.analog.com  ANALOG DEVICES, INC. 2021 www.analog.com RELATED PARTS TYPICAL APPLICATION Dual-Phase 0.9V 2MHz 12A Regulator PART NUMBER DESCRIPTION COMMENTS LT8652S Dual Channel 8.5A, 18V, Synchronous Step-Down Silent Switcher 2 with 16μA Quiescent Current VIN: 3V to 18V, VOUT(MIN) = 0.6V, 4mm × 6mm LQFN-32 package LT8642S 18V, 10A Synchronous Step-Down Silent Switcher 2 V IN: 3V to 18V, VOUT(MIN) = 0.6V, 4mm × 4mm LQFN-24 package LTC7150S 20V, 20A Synchronous Step-Down Silent Switcher 2 V IN: 3.1V to 20V, VOUT(MIN) = 0.6V, 5mm × 6mm BGA-42 package LTC7151S 20V, 15A Synchronous Step-Down Silent Switcher 2 V IN: 3.1V to 20V, VOUT(MIN) = 0.6V, 4mm × 5mm LQFN-28 package LTC3636 Dual Channel 6A, 20V Monolithic Synchronous Step-Down Regulator V IN: 3.1V to 20V, VOUT(MIN) = 0.6V, 4mm × 5mm QFN-28 package LT8650S Dual Channel 4A, 42V, Synchronous Step-Down Silent Switcher 2 with 6.2µA Quiescent Current V IN: 3V to 42V, VOUT(MIN) = 0.8V, 4mm × 6mm LQFN-32 package LT8640S 42V, 6A Synchronous Step-Down Silent Switcher 2 with 2.5μA Quiescent Current V IN: 3.4V to 42V, VOUT(MIN) = 0.97V, 4mm × 4mm LQFN-24 package LTC3887 Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management 4.5V ≤ V IN ≤ 24V, 0.5V ≤ VOUT ≤ 5.5V, ±0.5% VOUT Accuracy, I2C/PMBus Interface with EEPROM and 16-Bit ADC. LTM4700 Dual 50A or Single 100A Step-Down DC/DC μModule Regulator with Digital Power System Management 4.5V ≤ V IN ≤16V; 0.5V ≤ VOUT ≤ 1.8V, ±0.5% VOUT Accuracy I2C/PMBus Interface, 15mm × 22mm × 7.87mm BGA Package PMBus Interface, 16mm × 16mm × 5.01mm, BGA Package PMBUS/ I2C BUS L T7182S SYNC/PWM_CFG VOUT1_CFG/ POL YPHASE_CFG PVIN0 PVIN1 FAUL T0 FAUL T1 VOUT0_CFG 30.9k 10µF INTVCC ITH0 ITH1 RUN0 SHARE_CLK VDD18 EXTVCC SDA SCL ALERT SGND PGND RUN1 4.7µF 7182S TA04 1.5nF 400µF DRVCC ASEL 30.9k 10k 10µF 5.6k VIN 2.9V TO 20V 10k WP PGOOD0 PGOOD1 VSENSE0P VSENSE0N SW0 0.2µH BOOST0 0.1µF BOOST1 SW1 VSENSE1P VSENSE1N 0.1µF 0.2µH VOUT 0.9V 12A