LT7171 AD | Alldatasheet
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Data Sheet LT7171/LT7171-1 analog.com Rev. A 2 of 54 TABLE OF CONTENTS
Data Sheet LT7171/LT7171-1 analog.com Rev. A 3 of 54
Figure 3. LT7171 Functional Block Diagram
Figure 4. LT7171-1 Functional Block Diagram
Data Sheet LT7171/LT7171-1 analog.com Rev. A 6 of 54
ELECTRICAL CHARACTERISTICS
Table 1. Electrical Characteristics
5 Bits
Data Sheet LT7171/LT7171-1 analog.com Rev. A 7 of 54 (TA = 25°C for typical values. For minimum and maximum values, specifications apply over the full operating temperature range, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS gMEA Step Size VOUT Range 0 150 μS VOUT Range 1 75 μS VOUT Range 2 37.5 μS Positive Inductor Valley Current Limit, ILIM_POS (Sourcing Output Current) 1 LT7171 Current-Limit Selection 0 7.2 9.0 10.8 A Current-Limit Selection 1 11 13 15 A Current-Limit Selection 2 13.4 15.6 17.8 A Current-Limit Selection 3 18.0 21.4 25.0 A Positive Inductor Valley Current Limit, ILIM_POS (Sourcing Output Current) 1 LT7171-1 Limit per Phase Current-Limit Selection 0 3.6 4.5 5.4 A Current-Limit Selection 1 5.5 6.5 7.5 A Current-Limit Selection 2 6.7 7.8 8.9 A Current-Limit Selection 3 9.0 10.7 12.5 A Negative Inductor Valley Current Limit, ILIM_NEG (Sinking Output Current)
1 LT7171
Current-Limit Selection 0 −7.8 −6.0 −4.2 A Current-Limit Selection 1 −9.4 −7.6 −5.8 A Current-Limit Selection 2 −11.4 −9.4 −7.4 A Current-Limit Selection 3 −14.6 −12.0 −9.4 A Negative Inductor Valley Current Limit, ILIM_NEG (Sinking Output Current)
1 LT7171-1 Limit per Phase
Current-Limit Selection 0 −3.9 −3.0 −2.1 A Current-Limit Selection 1 −4.7 −3.8 −2.9 A Current-Limit Selection 2 −5.7 −4.7 −3.7 A Current-Limit Selection 3 −7.3 −6.0 −4.7 A LT7171 Switch On Resistance Top 9 mΩ Bottom 3.2 mΩ LT7171-1 Switch On Resistance, Each Phase Top 18 mΩ Bottom 6.4 mΩ SWx Leakage VIN = 16V, SWx voltage = 0V and 16V, TA = 25°C −20 +20 μA Minimum OnTime (tON) Load current (ILOAD) = 2A 25 40 ns Minimum Off Time (tOFF) 110 150 ns OUTPUT VOLTAGE FAULT AND WARNING SUPERVISORS VOUT Undervoltage (UV) Threshold Programming Range (VOUT_UV_FAULT_LIMIT and VOUT_UV_WARN_LIMIT) TA = 25°C 0.360 5.5 V
Data Sheet LT7171/LT7171-1 analog.com Rev. A 8 of 54 (TA = 25°C for typical values. For minimum and maximum values, specifications apply over the full operating temperature range, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS VOUT Overvoltage (OV) Threshold Programming Range (VOUT_OV_FAULT_LIMIT and VOUT_OV_WARN_LIMIT) TA = 25°C 0.4 6.0 V VOUT UV and OV Fault and Warning Threshold Accuracy <0.6V −12 +12 mV ≥0.6V −2 +2 % VOUT UV and OV Threshold Programming Step Size 4 mV VOUT UV and OV Response Time VOUT = 10mV beyond threshold 25 μs INPUT VOLTAGE FAULT AND WARNING SUPERVISORS VIN_ON Programming Range TA = 25°C 1.4 16 V VIN_OFF Programming Range TA = 25°C 1.35 16 V VIN_ON, VIN_OFF Programming Step Size 25 mV VIN_ON, VIN_OFF Set-Point Accuracy VIN_ON/VIN_OFF ≤ 5V −100 +100 mV 5V ≤ VIN_ON/VIN_OFF ≤ 16V −2 2 % VIN Overvoltage Lockout Threshold VIN rising 16.8 17.6 V VIN falling 16.5 17.25 V OSCILLATOR AND PHASE-LOCKED LOOP (PLL) SYNC Pin Input Frequency Range 0.4 4 MHz fSW Programming Range TA = 25°C 0.4 4 MHz fSW Set-Point Accuracy −7.5 +7.5 % Switching Phase Programming Range TA = 25°C 0 345 Degrees Switching Phase Programming Resolution
15 Degrees
Telemetry Measurement Period All Measurements Standard telemetry mode 5.5 ms Telemetry Measurement Period All Measurements Low frequency telemetry 110 ms Telemetry Measurement Period All Except Output Current IOUT scope telemetry mode 9 ms Telemetry Measurement Period Output Current Only IOUT scope telemetry mode 2.5 ms
Data Sheet LT7171/LT7171-1 analog.com Rev. A 9 of 54 (TA = 25°C for typical values. For minimum and maximum values, specifications apply over the full operating temperature range, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS OUTPUT VOLTAGE READBACK READ_VOUT Accuracy 0.6V ≤ VOUT ≤ 1.375V, VOUT Range 0 −0.20 +0.20 % VIN INPUT VOLTAGE READBACK READ_VIN Accuracy 1.5V < VIN < 2.5V −25 +25 mV 2.5V < VIN < 16V −1 +1 % OUTPUT CURRENT READBACK DC ACCURACY READ_IOUT DC Accuracy VOUT/VIN ≤ 0.25, fSW ≤ 2MHz, 0A ≤ IOUT ≤ 10A −300 +300 mA VOUT/VIN ≤ 0.25, fSW ≤ 2MHz, IOUT > 10A −3 +3 % All other conditions, 0A ≤ IOUT ≤ 10A −1 +1 A All other conditions, IOUT > 10A −10 +10 % FREQUENCY READBACK READ_FREQUENCY Accuracy fSW ≤ 400kHz, TA = 25°C −20 +20 kHz READ_FREQUENCY Accuracy fSW ≥ 400kHz, TA = 25°C −5 +5 % NVM CHARACTERISTICS Retention2, 3 10 Years Endurance2 3 Writes STORE_USER_ALL Mass Write Time 0.25 2 Sec SYNC PIN Peak-to-Peak Input Voltage Swing SYNC input mode 1.4 5.5 V Rise Time SYNC input mode 25 ns Duty Cycle SYNC input mode 30 70 % Output High Voltage, VOH SYNC output mode, current = 1mA 1.6 V Output Low Voltage, VOL SYNC output mode, current = 1mA 0.2 V RUN, FAULT, PGOOD, SCL, SDA, SHARE_CLK, WP, and ALERT INPUTS Input High Threshold 1.1 1.35 V Input Low Threshold 0.8 0.9 V Hysteresis 50 200 400 mV Leakage Current Applied voltage = 0V and 5.5V, TA = 25°C ±10 μA Input Capacitance, CIN
2 TA = 25°C 10 pF
the valley current limit plus one half of the inductor ripple current. 2 Guaranteed by design, characterization, and correlation with statistical process controls. the devices was between −40°C and +125°C and while VIN was biased at 9.6V to 16V. Table 2. I2C/PMBus Timing
TA = 25°C unless otherwise specified. Table 3. Absolute Maximum Ratings LT7171/LT7171-1 may affect device reliability and lifetime. for extended periods may affect product reliability.
attention to PCB thermal design is required. Using enhanced heat removal (PCB, heat sink, and airflow) techniques improve thermal resistance values. Table 4. Thermal Resistance for Demonstration Board in Still Air
Figure 5. Pin Configuration Table 5. Pin Descriptions or Pin 24, and its negative terminal connected to ground. electrical and thermal contact to power ground.
17 FAULT
18 SYNC
19 SHARE_CLK
20 EXTVCC
21 VSENSEP
22 VSENSEN
23 PGND
24 VIN
26 SW1
27 SW1
28 SW0
29 SW0
30 BOOST0
Data Sheet LT7171/LT7171-1 analog.com Rev. A 14 of 54 PIN NAME DESCRIPTION
3 DRVCC
Internal Low Dropout (LDO) Regulator Bypass Pin. This regulator provides the supply current for the power field effect transistor (FET) drivers. Decouple the DRVCC pin to PGND with an 0201 0.1µF low ESR ceramic capacitor rated for at least 6V as close to the device pins as possible and a second capacitor with 10µF or greater close to LT7171/LT7171-1, using the top printed circuit board (PCB) layer. Do not load the DRVCC pin with external circuitry.
4 PWM_CFG
Pulse-Width Modulation (PWM) Configuration Resistor Pin (PWM_CFG). Connect a 1% resistor from PWM_CFG to either PGND or SGND according to Table 9 and Table 10 to select the frequency, phase configurations. The configuration resistor is read at LT7171/LT7171-1 startup and reset. PWM_CFG may be floated, but do not ground it. See the Applications Information for more details.
5 VOUT_CFG
Output Voltage Configuration Input Pin. Connect a 1% resistor from VOUT_CFG to either SGND or PGND according to Table 8 to select the output voltage set point. If left floating or tied to VDD18, the LT7171/LT7171-1 use the value for the VOUT_COMMAND command programmed in the NVM. The VOUT_CFG pin is read at LT7171/LT7171- 1 startup and reset.
6 ASEL
Serial Bus Address Configuration. Connect a 1% resistor from ASEL to ground (SGND or PGND) to select one of sixteen serial bus interface addresses according to Table 7. Refer to the description of MFR_ADDRESS in the LT7171/LT7171-1 PMBus/I2C Reference Manual. The ASEL pin is read at LT7171/LT7171-1 startup and reset. If the ASEL pin is left floating, the factory default 7-bit device address is 0x4F. If the ASEL pin is grounded, the factory default device address is 0x40.
7 ITH
Error Amplifier Output and Switching Regulator Compensation Point. Connect the appropriate external components between this pin and SGND to compensate the regulator loop frequency response, or connect the ITH pin to INTVCC to select internal compensation.
8 INTVCC
Internal 3V LDO Regulator Bypass Pin. This regulator provides the supply current for internal circuitry. Decouple the INTVCC pin to SGND with a 10μF or greater, low ESR ceramic capacitor, as close as possible to the LT7171/LT7171-1. Do not load the INTVCC pin with external circuitry.
9 SGND
Signal Ground Pin. The bypass capacitors for INTVCC and VDD18 must be connected to SGND. The SGND pin is connected to PGND inside the LT7171/LT7171-1. Do not connect SGND to PGND on the PCB.
10 VDD18
Internal 1.8V Regulator Bypass Pin. Decouple the VDD18 pin to SGND with a 1μF or greater, low ESR ceramic capacitor. Do not load the VDD18 pin with external circuitry.
Data Sheet LT7171/LT7171-1 analog.com Rev. A 15 of 54 PIN NAME DESCRIPTION 11 WP Write Protect Input. When this pin is high, only the PAGE, OPERATION, MFR_EE_UNLOCK, and CLEAR_FAULTS commands are writable. Clear individual fault bits by writing a 1 to the respective bits in the STATUS commands.
12 ALERT
Open-Drain Output Pin. If the ALERT pin function is used, a pull-up resistor from a 1.6V to 5.5V supply is required. If the ALERT pin function is not used, the ALERT pin can be tied to ground.
13 RUN
Regulator Enable Input Pin. Logic high enables the regulators. The RUN pin can be tied directly to DRVCC to enable the regulator when input power is present.
14 PGOOD
Power-Good Indicator Open-Drain Output. PGOOD is pulled low when the output is outside of the overvoltage and undervoltage fault thresholds, when the regulator is disabled, or during on and/or off sequencing. The PGOOD output is deglitched by internal configurable timers. If the PGOOD pin function is used, a pull-up resistor from a 1.6V to 5.5V supply is required. If the PGOOD pin function is not required, PGOOD can be tied to ground.
15 SDA
Serial Bus Data Input and Output Pin. A pull-up resistor from a 1.6V to 5.5V supply is required for I2C/PMBus operation. If serial bus operation is not required, SDA can be tied to ground.
16 SCL
Serial Bus Clock Input Pin. The LT7171/LT7171-1 can hold SCL low if clock stretching is enabled (PMBus speeds, 400kHz to 1MHz only). A pull-up resistor from a 1.6V to 5.5V supply is required for I2C/PMBus operation. If serial bus operation is not required, SCL can be tied to ground. Fault Input/Open-Drain Output. The LT7171/LT7171-1 pull the pin down with 1.5mA (typical) when an unmasked fault occurs on the regulator. If another device pulls down on the FAULT pin, the LT7171/LT7171-1 regulator will turn off immediately. If PolyPhase configuration is used, tie together the FAULT pins of all PolyPhase devices. If PolyPhase configuration is used, or if FAULT pin reporting or sharing is required, a pull-up resistor of 6.8k or greater to 1.6V to 5.5V is required. If the FAULT pin function is not required, the FAULT pin may be left floating. External Clock Synchronization Input (SYNC)/Output Pin. When driven with an external clock, an internal PLL synchronizes the switching regulator output with the rising edge of the external clock. If configured as an output by setting MFR_SYNC_CONFIG_LT7171, Bit 0, the LT7171/LT7171-1 drive the SYNC pin output at the switching clock frequency set by the FREQUENCY_SWITCH command. SYNC may be floated, but do not ground it. See the Applications Information for more details.
Data Sheet LT7171/LT7171-1 analog.com Rev. A 16 of 54 PIN NAME DESCRIPTION Bidirectional Open-Drain Sequence Time Base Share Clock Pin. Nominally 100kHz. Used to align the startup and shutdown of regulator outputs among multiple ADI products when PolyPhase or time-based sequencing is employed. A pull-up resistor from 1.6V to 5.5V is required if the SHARE_CLK function is used. If SHARE_CLK is not connected to other devices, SHARE_CLK may be left floating. Optional Power Supply Input. If connected from 3V to 5.5V, the EXTVCC pin is used to derive the INTVCC and DRVCC supplies. If the LT7171/LT7171-1 output is 3V or greater, the output can be connected to EXTVCC to reduce power loss. If the EXTVCC pin is tied to a supply other than VOUT, connect a 0.1μF or greater local bypass ceramic capacitor from this pin to PGND. 21 VSENSEP Output Voltage Positive Sense Input. Kelvin connect the VSENSEP pin to the output voltage sense point. 22 VSENSEN Output Voltage Negative Sense Input. Kelvin connect the VSENSEN pin to the output voltage ground sense point.
25 BOOST1
Boosted Floating Driver Supply Pin. Connect a 0.1μF boost capacitor from BOOST1 to SW1 as close as possible to the LT7171/ LT7171-1, using the top PCB layer. The normal operating voltage swing of the BOOST1 pin is from DRVCC to VIN + DRVCC. 26, 27, 32 SW1 Output of the Phase 1 Internal Power Switches. For the LT7171-1, tie the SW1 pins together and connect these pins to the Phase 1 inductor and BOOST1 capacitor. For the LT7171, tie the SW0 and SW1 pins together and connect these pins to the Phase 0 inductor and BOOST0 capacitor. For optimal performance, keep the SW1 node small on the PCB. 28, 29, 31 SW0 Output of the Phase 0 Internal Power Switches. Tie the SW0 pins together and connect these pins to the Phase 0 inductor and BOOST0 capacitor. For optimal performance, keep the SW0 node small on the PCB. Boosted Floating Driver Supply Pin. Connect a 0.1μF boost capacitor from BOOST0 to SW0 as close as possible to the LT7171/LT7171-1, using the top PCB layer. The normal operating voltage swing of the BOOST0 pin is from DRVCC to VIN + DRVCC.
Data Sheet LT7171/LT7171-1 analog.com Rev. A 22 of 54 THEORY OF OPERATION Overview The LT7171/LT7171-1 are monolithic, PolyPhase, DC/DC synchronous step-down regulators capable of providing up to 20A of continuous output current with input supply voltages up to 16V. For the LT7171, connect SW0 and SW1 together to a single inductor to drive a single-regulated output supply. For the LT7171-1 dual-phase option, connect an inductor to each of the switch pins, SW0 and SW1, to drive a single-regulated output supply. The switching phases are set to 180° out of phase. The phase selected by configuration resistors or by the MFR_PWM_PHASE_LT7171 command sets the phase difference between the SYNC input and the SW0 ou tput. The I 2C-based serial peripheral interface (SPI) is compatible with PMBus 1.3, which supports bus speeds up to 1MHz. Major features include the following: Programmable Output Voltage Programmable Current Limit Programmable Switching Frequency Programmable Overvoltage and Undervoltage Comparators Programmable On and Off Delay Times Programmable Output Rise and/or Fall Times Programmable Control Loop Compensation Programmable Input Undervoltage Threshold Selectable Switch Slew Rate for EMI and Efficiency Optimization Dedicated Power-Good Pin Phase-Locked Loop (PLL) for Synchronous Operation with an External Clock, PolyPhase Operation (up to 4 devices) Input and Output Voltage, Output Current, and Die Temperature Telemetry Programmable Output Current Readback Sampling Window Reduced Power Telemetry Mode that Slows Analog-to-Digital Converter (ADC) Sampling Frequency to Reduce Input Quiescent Current Fully Differential Remote VOUT Sense 3x Programmable Nonvolatile Configuration Memory with Error Correcting Code (ECC) Optional External Configuration Resistors to Set Key Operating Parameters Standalone Operation using either Configuration Resistors or Nonvolatile Configuration Memory A Variety of Fault and Warning Handling and Reporting Mechanisms Optional Time-Base Interconnect for Synchronization Between Multiple Devices WP Pin to Write-Protect Internal Configuration A dedicated ALERT pin is provided to indicate that faults or warnings have occurred. Individual status commands enable fault and warning reporting to identify the specific event. The FAULT pins of the LT7171/LT7171 -1 enable fault sharing between channels and with other ADI power system management products, including the LTC3880, LTC2974, LTC2978, LTC4676 μModule ®, etc. Fault reporting and shutdown behavior are fully configurable using the FAULT pins and the MFR_FAULT_PROPAGATE_LT7171 command. Faults can be individually masked, and the fault responses can be programmed to retry (unlatched) or remain shut down (latch-off) the regulator output. Fault and warning detection capabilities include the following:
Data Sheet LT7171/LT7171-1 analog.com Rev. A 23 of 54 Output Undervoltage and Overvoltage Faults and Warnings Internal Overtemperature Fault and Warning Communication, Memory, or Logic (CML) Faults Input Overvoltage Fault and Undervoltage Warning Output Overcurrent Fault and Warning External Fault Detection via the Bidirectional FAULT Pins Switching Regulator Control Loop The LT7171/LT7171-1 employ a controlled on-time, valley current mode architecture. In normal operation, the internal top power, metal-oxide semiconductor FET (MOSFET) is turned on for an interval determined by an on- time control circuit. When the top power MOSFET turns off, the bottom power MOSFET turns on until the valley current comparator trips, restarting the on-time control circuit and initiating the next cycle. Inductor current is determined by sensing the voltage drop across the bottom power MOSFET when it is on. The error amplifier adjusts the average inductor current (ITH) pin voltage by comparing the regulator output voltage with an internal reference digital-to-analog converter (DAC) output. The voltage on the ITH pin sets the comparator threshold, which is compared with the sensed-inductor valley current. An increase in load current causes a drop in the output voltage relative to the internal reference. The error amplifier responds by forcing the ITH voltage higher until the average inductor current matches that of the load current. An internal PLL synchronizes the oscillator frequency to an external clock signal if one is present on the SYNC pin. If no external clock is applied, the fSW is set by the FREQUENCY_SWITCH command, which can be initialized by using configuration resistors (see the Setting Switching Frequency, Compensation Components, PWM for more details). NVM The LT7171/LT7171-1 contain internal programmable NVM with ECC to store user configuration settings. The NVM can be programmed up to three times. During NVM write operations, T J must be between −40°C and +125°C, and VIN must be biased between 9.6V to 16V. In addition to ECC, the integrity of the on -board NVM is checked with a cyclic redundancy check (CRC) calculation after a power -on reset or execution of a RESTORE_USER_ALL command. If an invalid CRC is detected, the ALERT, SHARE_CLK, PGOOD and RUN pins are pulled low, and the regulator output remains disabled until the issue is resolved. Refer to the LT7171/LT7171-1 PMBus/I2C Reference Manual for more information about NVM programming. Power-Up and Initialization The LT7171/LT7171-1 are capable of standalone supply sequencing and controlled turn-on and turn-off operation. To reduce LT7171/ LT7171-1 power dissipation, EXTVCC can be driven with an external 3.0V to 5.5V supply. If EXTVCC is driven by a 3.0V to 5.5V supply, the supported VIN input operating range is from 1.5V to 16V. Note that without EXTVCC, the VIN operating range is from 2.9V to 16V. The LT7171/LT7171-1 initialize upon application of power to VIN or EXTVCC, or when an MFR_RESET or RESTORE_USER_ALL command is sent. In the initialization step, the LT7171/LT7171-1 read the NVM configuration and/or resistor configuration pins to set the initial state of the PMBus commands. The PGOOD pin is held low during initialization and released after the output voltage reaches the target value. During initialization SHARE_CLK is held low, and the FAULT pin is in high impedance state.
Data Sheet LT7171/LT7171-1 analog.com Rev. A 24 of 54 If the resistor configuration pins are enabled, the LT7171/LT7171-1 initialize certain commands based on the configuration resistor values, which supersede the NVM settings. Resistor configuration pins are enabled by factory default. Set Bit 6 of the MFR_CONFIG_ALL_LT7171 command in the NVM to disable the configuration pins. See the Using Resistor Configuration Pins section for additional information. For commands that are not initialized based on the configuration resistors, initial values are determined by the NVM or factory defaults. LT7171/LT7171-1 initialization typically requires 5ms. If the resistor configuration pins are disabled, the initialization time is reduced to 3ms (typical). After initialization is complete, comparators monitor VIN. For the devices to operate, VIN must exceed the programmable threshold set by the VIN_ON command. By default, SHARE_CLK will be held low until VIN exceeds VIN_ON, or if VIN falls below VIN_OFF. The default behavior is to turn off and remain off if SHARE_CLK is low. Refer to the MFR_CHAN_CONFIG_ LT7171 command in the LT7171/LT7171-1 PMBus/I2C Reference Manual for information on how to configure this behavior. Soft start When all conditions required for startup are met and the output of the LT7171 or LT7171-1 is enabled, the device waits for the commanded turn-on delay and ramps the target output voltage up to the commanded voltage set point. The turn-on delay is set by the TON_DELAY command, which is 0ms by default. The soft-start ramp time is set by the TON_RISE command, which is 1ms by default. During soft-start, the LT7171/LT7171-1 devices use a discontinuous mode in which the inductor current is not allowed to reverse. The reverse-current comparator, IREV, turns off the bottom switch just before the inductor current reaches zero, preventing the inductor current from reversing and going negative. Both power MOSFETs remain off while the output capacitor supplies the load current until the ITH pin voltage rises to more than the zero current threshold to initiate the next cycle. After the commanded voltage set point is reached, the channel transitions to forced continuous conduction mode. To guarantee clean start-up of the powered devices, the LT7171/ LT7171-1 actively pull down the output using VSENSEP when the output is disabled. The LT7171/LT7171-1 wait until the VOUT is less than 0.2V before enabling the output and beginning a soft start. This VOUT discharge threshold is programmable from 0.2V to 2.2V. Shutdown The LT7171/LT7171-1 can be programmed to turn off immediately or to sequence off. When sequencing off, the LT7171/LT7171-1 wait for the turn-off delay and then perform a soft stop ramp by which the regulation target voltage is ramped down to zero. The turn-off delay is set by the TOFF_DELAY command, which defaults to zero. The target voltage ramp-down time is set by the TOFF_FALL command, which defaults to 2ms. Sequencing off occurs if OPERATION is set to 0x40, or if the RUN pin is deasserted, and Bit 0 of the ON_OFF_CONFIG command is set to 0 and Bit 2 of the ON_OFF_CONFIG command is set to 1. When immediate shutdown occurs, the regulators ramp the inductor current to zero as quickly as possible and then stop switching. In this case, the output voltage decays based only on the load current and the internal 250Ω pull-down on the VSENSEP pin. Immediate shutdown occurs in any of the following situations: VIN falls to less than the VIN_OFF threshold. If the OPERATION command is cleared to 0x00, or if Bit 3 of the ON_OFF_CONFIG command is set to 1. A fault condition occurs that causes the output to turn off. The RUN pin is deasserted and the ON_OFF_CONFIG command is configured such that the RUN pin deassertion causes immediate shut down as determined by Bit 0 and Bit 1 of the ON_OFF_CONFIG command.
Data Sheet LT7171/LT7171-1 analog.com Rev. A 25 of 54 The FAULT pin for the channel is pulled low externally, unless MFR_FAULT_RESPONSE has been cleared to 0x00. Loss of SHARE_CLK, unless bit 2 of MFR_CHAN_CONFIG_LT7171 has been cleared. Warning and Fault Handling The LT7171/LT7171-1 continuously monitor the system for fault and warning conditions. Fault responses are configurable using the corresponding FAULT_RESPONSE commands, such as VOUT_UV_ FAULT_RESPONSE and VOUT_OV_FAULT_RESPONSE, etc. Possible fault responses are as follows: ► Ignores fault or warning condition and continues operation. ► Shuts down immediately and retries if the fault condition is no longer present. ► Shuts down immediately and latches off. The remainder of this section describes the factory default warning and fault behavior. Refer to the supported PMBus and MFR commands table in the LT7171/LT7171-1 PMBus/I2C Reference Manual for details on configuring fault and warning behavior. All faults and warnings are indicated in the PMBus status commands. The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits in all status commands simultaneously. This command also deasserts the ALERT pin. If the fault is still present when the bit is cleared, the fault bit remains set, and the host is notified by asserting the ALERT pin low. The CLEAR_FAULTS command does not cause a unit that has latched off for a fault condition to restart. Units that have shut down for a fault condition are restarted only when the fault condition is no longer present, and the following occurs: The output is commanded to turn off and then to turn back on via the RUN pin and/or OPERATION command. A MFR_RESET command is issued. VIN and EXTVCC bias power are removed and reapplied to the LT7171/LT7171-1. An LT7171/LT7171 -1 retry following a fault does not clear the status command bits. Therefore, when the output powers on after a fault, the status bits can be read to determine the cause of the fault. When a warning occurs related to the output voltage, output current, or temperature, the LT7171/LT7171 -1 pull the ALERT pin low, the corresponding bit is set in the appropriate status commands, and the regulators continue to operate. If the output voltage falls to less than VOUT_UV_FAULT_LIMIT, the LT7171/LT7171-1 respond as follows: The PGOOD pin pulls low. The ALERT pin pulls low. The VOUT_UV fault bit is set in the STATUS_VOUT, STATUS_BYTE, and STATUS_WORD commands. The devices continue to operate while limiting the maximum valley current. If a fault occurs due to output overvoltage or input overvoltage, the LT7171/LT7171-1 respond as follows: The faulted device(s) are shut down immediately. The FAULT pin and PGOOD pin are pulled low. The ALERT pin pulls low. The corresponding indicator bits are set in the appropriate status commands.
The faulted device(s) are shut down immediately. The FAULT pin and PGOOD pin are pulled low. The overtemperature (OT) bit is set in the appropriate status commands. Table 6. Factory Default Warnings and Faults Behavior
Data Sheet LT7171/LT7171-1 analog.com Rev. A 27 of 54 NVM Error CRC, ECC Not applicable Locks off until next reset Pull low High-Z Pull low PMBus/I2C Communication Error (CML) Logic Not applicable Not applicable High-Z High-Z Pull low 1 The IOUT_OC_FAULT valley current threshold is controlled by MFR_PWM_MODE_LT7171, Bits[10:9]. 2 When a SYNC input clock error is detected during initialization, the output of the devices is disabled. 3 When a pin configuration error is detected during initialization, the device pulls low the following pins: FAULT, SHARE_CLK, PGOOD and ALERT. FAULT Pin A fault will cause the FAULT pin to pull low if the corresponding FAULT_RESPONSE command is programmed to shut down the regulator output and the MFR_FAULT_PROPAGATE_LT7171 command is configured to propagate the fault to the open-drain FAULT pin. Once the LT7171/7171_1 pulls down a FAULT pin, the device will continue to hold the pin low until one of the following occurs: The device retries for faults that are configured to retry. The faulted device is disabled and then re-enabled. A RESTORE_USER_ALL or MFR_RESET command is received. Input power is removed from both VIN and EXTVCC. The FAULTpin can also be used as an input to provide a method for the L T7171/L T7171-1 to respond to external faults. The L T7171/L T7171-1 turn off immediately if the FAULTpin is pulled low externally. This enables coordination of faults among multiple power system management products. The default pin response of FAULT is defined in Table 6. PGOOD Pin The open-drain PGOOD pin is pulled low when the output is off for any reason, during soft start and soft stop, or if the output voltage is less than the VOUT_UV_FAULT_LIMIT. ALERT Pin The SMBALERT_MASK command configures which warning and fault indicators cause the LT7171/LT7171 -1 to pull down the open-drain ALERT pin. Once the LT7171 or LT7171-1 pulls down the ALERT pin, the device continues to hold the ALERT pin low until one of the following occurs: The output is shut off and turned on. A CLEAR_FAULTS, RESTORE_USER_ALL, or MFR_RESET command is received. All unmasked status bits are cleared by writing a 1 to each bit. The device successfully transmits its address in response to the PMBus alert response address. Input power is removed from VIN and EXTVCC.
configuration pin is described in the sections below. VOUT_CFG and PWM_CFG pins while the ASEL resistor is always respected. the ASEL pin is grounded, the factory default device address is 0x40. Table 7. LT7171/LT7171-1 Address Configuration Using ASEL Resistor
The VOUT_COMMAND command specifies the output voltage when the regulator is enabled. loaded from the NVM to set the output voltage. Table 8. VOUT_CFG Pin Configuration Resistor Selection
1 Output voltage set point is controlled by VOUT_COMMAND.
2 The PMBus ON_OFF_CONFIG command selects whether the RUN pin and/or the PMBus OPERATION command
used to initialize the PWM configuration including frequency, phase, loop compensation, and PolyPhase operation. If PWM_CFG is open or tied to VDD18, the VOUT_COMMAND command is loaded from the NVM to set the output voltage. Table 9. PWM_CFG Pin Configuration Resistor Selection for LT7171
Table 10. PWM_CFG Pin Configuration Resistor Selection for LT7171-1
Data Sheet LT7171/LT7171-1 analog.com Rev. A 32 of 54 1 If an external synchronization clock is applied, the configuration resistor value should be chosen to set the internal PWM switching frequency to a similar value to the input clock. 2 For internal compensation, C ITH is controlled by MFR_PWM_MODE_LT7171, Bits [8:6], and R ITH is controlled by MFR_PWM_MODE_LT7171, Bits [5:3]. 3 When an external clock is detected during power -on reset and/or reset of the LT7171/LT7171 -1, the external clock frequency is measured and internal compensation parameters, CITH and RITH, are chosen automatically as follows: For 400kHz to 625kHz, RITH = 14kΩ and CITH = 320pF. For 625kHz to 1.25MHz, RITH = 14kΩ and CITH = 320pF. For 1.25MHz to 2.5MHz, RITH = 20kΩ and CITH = 320pF. For 2.5MHz to 4MHz, RITH = 60kΩ and CITH = 80pF. Synchronization The LT7171/LT7171-1 automatically synchronize PWM switching to an external clock input on the SYNC pin unless the LT7171/LT7171-1 are configured as an output driver or are programmed to ignore the input clock. The LT7171/ LT7171-1 continue PWM operation using their own internal oscillator if the external clock signal is lost. If an external synchronization clock is used, it is recommended to program the FREQUENCY_SWITCH command or to use R PWM_CFG to set the internal oscillator frequency to a value close to the external clock frequency to ensure that the PWM frequency remains consistent if the external clock is lost. The LT7171/LT7171 -1 can be programmed to ignore an external clock by writing a 1 to MFR_SYNC_CONFIG_ LT7171, Bit 1. For an input clock frequency of 400kHz to 625kHz, it is recommended to use a RPWM_CFG that selects a PWM frequency of 500kHz. For an input clock frequency from 625kHz to 1.25MHz, it is recommended to use a R PWM_CFG that selects a PWM frequency of 1MHz. For an input clock frequency from 1.25MHz to 4MHz, it is recommended to use a R PWM_CFG that selects a PWM frequency of 2MHz. The LT7171/LT7171-1 can be configured to provide a synchronizing clock output on the SYNC pin to other devices by setting Bit 0 of MFR_SYNC_CONFIG_LT7171 to 1. If the SYNC output clock is enabled, the LT7171/ LT7171 -1 drive the SYNC pin as a square wave from 0V to 1.88V (typical) at the frequency programmed in the FREQUENCY_SWITCH command. The phase of SYNC leads the phase of the SW0 PWM output by the value set i n the MFR_PWM_PHASE_ LT7171 command. When using multiple devices connected with a common SYNC pin, only one device can be configured as an output. When a clock is active on the SYNC pin, the MFR_PWM_PHASE_LT7171 command specifies the phase relationship between the rising edge of the SYNC pin and the rising edge of the LT7171/LT7171-1 SW0 pin. If an external clock is applied to the SYNC pin throughout initialization, and the function of the resistor configuration pins is not disabled, the LT7171/LT7171 -1 measure the clock frequency and initialize the FREQUENCY_SWITCH command to the measured freq uency rounded to the nearest 100kHz. In this case, MFR_PWM_PHASE is set to 0°. Note that, unless the functionality of the resistor configuration pins is disabled, an external clock applied to the SYNC pin must be either active or inactive throughout the entire LT7171/LT7171-1 initialization process. If the clock activity changes during initialization, for example, if the clock starts after initialization begins but before it completes, the frequency measurement may be inaccurate, which can lead to the LT717 1/LT7171-1 incorrectly initializing the FREQUENCY_SWITCH command or declaring a pin configuration fault. Refer to the MFR_PIN_CONFIG_STATUS command in the LT7171/LT7171-1 PMBus/I2C Reference Manual for more information regarding pin configuration faults.
Data Sheet LT7171/LT7171-1 analog.com Rev. A 33 of 54 Single Phase for the LT7171 The LT7171 is a single -phase, monolithic, DC/DC synchronous, step -down regulator that delivers up to 20A of continuous output current. A single phase drives the SW0 and SW1 pins tied to one inductor to drive a single - regulated output supply. For single-phase operation, connect the LT7171 SW0 and SW1 pins together and to a single inductor. The phase selected by the configuration resistors or by MFR_PWM_PHASE_LT7171 sets the phase difference between SW0 and SYNC. Dual Phase for the LT7171-1 The LT7171-1 is a dual-phase, monolithic, DC/DC synchronous, step-down regulator that delivers up to 20A of continuous output current. The switching phases are set to 180° out of phase. Connect an inductor to each of the switch pins, SW0 and SW1, to drive a single-regulated output supply. The phase selected by the configuration resistors or by MFR_PWM_PHASE_LT7171 sets the phase difference between SW0 and SYNC. PolyPhase Load Sharing Multiple LT7171/LT7171-1 parts can be connected in parallel to provide a balanced PolyPhase load -share solution. The analog current mode control architecture of the LT7171/LT7171 -1 ensure that load -sharing remains balanced among the phases. The corresponding I TH, FAULT, V IN, V SENSEP, VSENSEN, SYNC, SHARE_CLK, and RUN pins must be connected among all PolyPhase devices. The phases should be separated by 360/n degrees, where n is the number of phases in the PolyPhase array. In PolyPhase, exactly one device, either an LT7171/LT7171 -1 or an external clock source, must be configured to drive a clock on SYNC. In a PolyPhase array, exactly one LT7171-1 device must be configured as a leader (MFR_CHAN_CONFIG_LT7171 bit 8 value of 0), and all other PolyPhase devices must be configured as followers (value set to 1). PolyPhase mode can also be selected by connecting an appropriate resistor to set one device as a leader and other devices as followers from PWM_CFG to ground if MFR_CONFIG_ALL_LT7171 bit 6 is not set to ignore the PWM_CFG pin, as shown in Table 9 and Table 10. Operating Frequency Trade-Offs The selection of the operating frequency is a trade-off between efficiency, component size, and input voltage range. The advantage of high frequency operation is that smaller inductor and capacitor values may be used, while the primary disadvantage is lower efficiency. Minimum On-Time and Minimum Off-Time Considerations The minimum on-time, tON (MIN), is the smallest time duration in which the top power MOSFET can be in its on state. This time is a function of the output load and is typically 25ns at a 2A load. In continuous conduction, the worst-case minimum on-time limit imposes a maximum switching frequency as following: fSW (MAX) = VOUT/(VIN × 40ns) where 40ns is the worst-case upper limit of tON (MIN) for a 2A load.
when the frequency is set higher than tON (MIN) allows. voltage drops out of regulation. where 150ns is the maximum tOFF (MIN) for the LT7171/LT7171-1. ripple waveform, as shown in Figure 34 and Figure 35. MAX)) is I LIM_POS + ΔIL, where ΔI L is the inductor ripple current. If I LIM_POS is reached, the IOUT_OC fault status bit is set. Refer to the status commands in the LT7171/LT7171-1 PMBus/I2C Reference Manual. Figure 34. Positive Valley Current Limit Figure 35. Negative Valley Current Limit
Table 11. LT7171 Valley Current-Limit Selection Table 12. LT7171-1 Valley Current-Limit Selection per Phase
Table 14. PROGRAMMABLE COMPENSATION RESISTANCE (RITH) Table 15. PROGRAMMABLE COMPENSATION CAPACITANCE (CITH) coordinated using the TOFF_DELAY command. the devices be connected to a pull-up resistor from a 1.6V to 5.5V. the value set in the VOUT_UV_FAULT_LIMIT command.
of the available digital functionality. Table 16 lists the supported commands. Some of the unpublished commands are read only and generate a current-mode logic (CML), Bit 6, fault if written to. Do not write to commands not published in Table 16. Floating-point values listed in the default value column are half-precision IEEE floating-point numbers. the data sheet of the manufacturer for each device for a complete definition of the function of the command. Table 16. Supported Commands (Cells Left Intentionally Blank)
Data Sheet LT7171/LT7171-1 analog.com Rev. A 40 of 54 WRITE_PROTECT 0x10 Level of protection provided by the device against accidental changes. R/W Byte Register Y 0x00 STORE_USER_ALL 0x15 Stores user operating memory to the NVM and can be written to three times. Send byte RESTORE_USER_ALL 0x16 Restores user operating memory from the NVM. Send byte CAPABILITY 0x19 Summary of PMBus optional communication protocols supported by this device. R byte Register 0xD8 QUERY 0x1A Asks if a given command is supported, and what data formats are supported. Block R/W Register SMBALERT_MASK 0x1B Masks ALERT activity. Block R/W Register Y VOUT_MODE 0x20 Output voltage format and exponent. R byte Register 0x60 VOUT_COMMAND 0x21 Nominal output voltage set point. R/W word IEEE V Y 0.5, 0x3800 VOUT_MAX 0x24 Upper limit on the commanded output voltage. R/W word IEEE V Y 0.537, 0x384C VOUT_MARGIN_HIGH 0x25 Margin high output voltage set point. R/W word IEEE V Y 0.525, 0x3833 VOUT_MARGIN_LOW 0x26 Margin low output voltage set point. R/W word IEEE V Y 0.475, 0x3799 VOUT_TRANSITION_RATE 0x27 Rates the output changes when VOUT commanded to a new value. R/W word IEEE V/ms Y 0.25, 0x3400 FREQUENCY_SWITCH 0x33 fSW of the regulator. R/W word IEEE kHz Y 1000.0, 0x63D0 VIN_ON 0x35 Input voltage at which the unit must start power conversion. R/W word IEEE V Y 1.4, 0x3D9A VIN_OFF 0x36 Input voltage at which the unit must stop power conversion. R/W word IEEE V Y 1.35, 0x3D66
Data Sheet LT7171/LT7171-1 analog.com Rev. A 41 of 54 IOUT_CAL_OFFSET 0x39 Offset for READ_IOUT. R/W word IEEE A Y 0.1, 0x2E66 VOUT_OV_FAULT_LIMIT 0x40 Output overvoltage fault limit. R/W word IEEE V Y 0.55, 0x3866 VOUT_OV_FAULT_RESPONSE 0x41 Action taken by the device when an output overvoltage fault is detected. R/W byte Register Y 0xB8 VOUT_OV_WARN_LIMIT 0x42 Output overvoltage warning limit. R/W word IEEE V Y 0.537, 0x384C VOUT_UV_WARN_LIMIT 0x43 Output undervoltage warning limit. R/W word IEEE V Y 0.467, 0x3779 VOUT_UV_FAULT_LIMIT 0x44 Output undervoltage fault limit. R/W word IEEE V Y 0.465, 0x3770 VOUT_UV_FAULT_RESPONSE 0x45 Action taken by the device when an output undervoltage fault is detected. R/W byte Register Y 0x00 IOUT_OC_FAULT_RESPONSE 0x47 Action taken by the device when an output overcurrent fault is detected. R/W byte Register Y 0x00 IOUT_OC_WARN_LIMIT 0x4A Output overcurrent warning limit. R/W word IEEE A Y 20.0, 0x4D00 OT_FAULT_LIMIT 0x4F Internal overtemperature fault limit. R/W word IEEE C Y 160.0, 0x5900 OT_FAULT_RESPONSE 0x50 Action taken by the device when an internal overtemperature fault is detected. R/W byte Register Y 0xC0 OT_WARN_LIMIT 0x51 Internal overtemperature warning limit. R/W word IEEE C Y 140.0, 0x5860 VIN_OV_FAULT_RESPONSE 0x56 Action taken by the device when an input overvoltage fault is detected. R/W byte Register Y 0xB8 VIN_UV_WARN_LIMIT 0x58 Input supply undervoltage warning limit. R/W word IEEE V Y -1.0, 0xBC00
Data Sheet LT7171/LT7171-1 analog.com Rev. A 42 of 54 TON_DELAY 0x60 Time from RUN and/or OPERATION on to output rail turn-on. R/W word IEEE ms Y 0.0, 0x0000 TON_RISE 0x61 Time from when the output starts to rise until the output voltage reaches the VOUT commanded value R/W word IEEE ms Y 1.0, 0x3C00 TON_MAX_FAULT_LIMIT 0x62 Maximum time from the start of TON_RISE for VOUT to cross the VOUT_UV_FAULT_LIMIT. R/W word IEEE ms Y 5.0, 0x4500 TON_MAX_FAULT_RESPONSE 0x63 Action taken by the device when a TON_MAX_FAULT event is detected. R/W byte Register Y 0x00 TOFF_DELAY 0x64 Time from RUN and/or OPERATION off to the start of TOFF_FALL ramp. R/W word IEEE ms Y 0.0, 0x0000 TOFF_FALL 0x65 Time from when the output starts to fall until the output reaches 0V. R/W word IEEE ms Y 2.0, 0x4000 TOFF_MAX_WARN_LIMIT 0x66 Maximum allowed time, after TOFF_FALL completed, for the unit to decay to less than MFR_DISCHARGE_THRESHOLD. R/W word IEEE ms Y 0.0, 0x0000 STATUS_BYTE 0x78 One byte summary of the fault condition of the unit. R/W byte Register STATUS_WORD 0x79 Two byte summary of the fault condition of the unit. R/W Register STATUS_VOUT 0x7A Output voltage fault and warning status. byte Register STATUS_IOUT 0x7B Output current fault and warning status. R/W Register STATUS_INPUT 0x7C Input supply fault and warning status. byte Register
Data Sheet LT7171/LT7171-1 analog.com Rev. A 43 of 54 STATUS_TEMPERATURE 0x7D Internal temperature fault and warning status for READ_TEMERATURE_1. R/W Register STATUS_CML 0x7E Communication and memory fault and warning status. byte Register STATUS_MFR_SPECIFIC 0x80 Manufacturer-specific fault and state information. R/W Register READ_VIN 0x88 Measured input supply voltage. R word IEEE V READ_VOUT 0x8B Measured output voltage. R word IEEE V READ_IOUT 0x8C Measured output current. R word IEEE A READ_TEMPERATURE_1 0x8D Measured internal temperature. R word IEEE C READ_FREQUENCY 0x95 Measured PWM fSW. R word IEEE PMBUS_REVISION 0x98 PMBus revision supported by this device. Current revision is 1.3. R Byte Register 0x33 MFR_ID 0x99 The manufacturer ID in ASCII. R block ADI MFR_SERIAL 0x9E Unique part serial number. R block IC_DEVICE_ID 0xAD Identification of the IC in ASCII. R block LT7171 or LT7171-1 IC_DEVICE_REV 0xAE Revision of the IC. R block MFR_NVM_UNLOCK 0xBD Contact Analog Devices, Sales. Only used for MFR_NVM_DATA bulk programming. MFR_NVM_USER_WRITES_REMAINING 0xBE Number of STORE_USER_ALL writes remaining R byte Register
Data Sheet LT7171/LT7171-1 analog.com Rev. A 44 of 54 MFR_NVM_DATA 0xBF Contact Analog Devices, Sales. Used for bulk programming. Not needed for STORE_USER_ALL. MFR_USER_DATA_00 0xC9 NVM word available for the user. R/W word Register Y 0x0000 MFR_USER_DATA_01 0xCA NVM word available for the user. R/W word Register Y 0x0000 MFR_READ_EXTVCC 0xCD Measured EXTVCC voltage, when enabled. R word IEEE V MFR_READ_ITH 0xCE Measured ITH voltage, when enabled. R word IEEE V MFR_CHAN_CONFIG_LT7171 0xD0 Configuration bits that are channel specific. R/W word Register Y 0x02C8 MFR_CONFIG_ALL_LT7171 0xD1 General configuration bits. R/W word Register Y 0x0000 MFR_FAULT_PROPAGATE_LT7171 0xD2 Configuration that determines which faults are propagated to the FAULT pin R/W word Register Y 0xA097 MFR_READ_ASEL 0xD3 Read ASEL pin resistor value R word IEEE kΩ MFR_PWM_MODE_LT7171 0xD4 Configuration for the PWM engine. R/W word Register Y 0x0FDC MFR_FAULT_RESPONSE 0xD5 Action to be taken by the device when the FAULT pin is externally asserted low. R/W byte Register Y 0xC0 MFR_IOUT_PEAK 0xD7 Reports the maximum measured value of READ_IOUT since the last MFR_CLEAR_PEAKS. R word IEEE A MFR_ADC_CONTROL_LT7171 0xD8 Configures the update rate of the measurements taken by the ADC. R/W byte Register Y 0x06 MFR_RETRY_DELAY 0xDB Retry interval during fault retry mode. R/W word IEEE ms Y 10.0, 0x4900
Data Sheet LT7171/LT7171-1 analog.com Rev. A 45 of 54 MFR_VOUT_PEAK 0xDD Maximum measured value of READ_VOUT since the last MFR_CLEAR_PEAKS. R/W word IEEE V MFR_VIN_PEAK 0xDE Maximum measured value of READ_VIN since the last MFR_CLEAR_PEAKS. R/W word IEEE V MFR_TEMPERATURE_1_PEAK 0xDF Maximum measured value of internal temperature (READ_TEMPERATURE_1) since the last MFR_CLEAR_PEAKS. R/W word IEEE C MFR_READ_PWM_CFG 0xE0 Measured PWM_CFG resistor value. R word IEEE kΩ MFR_READ_VOUT_CFG 0xE1 Measured VOUT_CFG resistor value. R word IEEE kΩ MFR_CLEAR_PEAKS 0xE3 Clears all peak values. Send byte MFR_DISCHARGE_THRESHOLD 0xE4 Output voltage used to determine that the output has decayed sufficiently to re- enable the channel. R/W word IEEE Y 0.2, 0x3266 MFR_PADS_LT7171 0xE5 Digital status of the input and/or output pads. R word Register MFR_I2C_ADDRESS 0xE6 Sets the 7-bit I2C address byte. R/W word Register Y 0x4F MFR_SPECIAL_ID 0xE7 ID code used by manufacturer. R word Register 0x1C1D MFR_COMMON 0xEF Manufacturer status bits that are common across multiple Analog Devices chips. R byte Register MFR_COMPARE_USER_ALL 0xF0 Compares current command contents with the NVM. Send byte MFR_CHANNEL_STATE 0xF1 Returns the state of the channel. R byte Register
Data Sheet LT7171/LT7171-1 analog.com Rev. A 46 of 54 MFR_PGOOD_DELAY 0xF2 Time output voltage must be between the undervoltage and overvoltage before PGOOD transitions high. R/W word IEEE Y 1.0, 0x3C00 MFR_NOT_PGOOD_DELAY 0xF3 Time output voltage must be less than the undervoltage or more than the overvoltage before PGOOD transitions low. R/W word IEEE Y 0.1, 0x2E66 MFR_PWM_PHASE_LT7171 0xF5 Sets the PWM phase. R/W byte Register Y 0x00 MFR_SYNC_CONFIG_LT7171 0xF6 SYNC pin input/output configuration. R/W byte Register Y 0x01 MFR_PIN_CONFIG_STATUS 0xF7 Pin configuration fault status. R byte Register MFR_RAIL_ADDRESS 0xFA Common address for PolyPhase outputs to adjust common parameters. R/W byte Register Y 0x80 MFR_DISABLE_OUTPUT 0xFB Disables regulator outputs until reset. R/W byte Register 0x00 MFR_NVM_USER_WP 0xFC Disables commands that write user NVM. R/W byte Register Y 0x00 MFR_RESET 0xFD Commanded reset without requiring a power down. Send byte 1 A Y in the NVM column indicates that these commands are stored and restored using the STORE_USER_ALL and RESTORE_USER_ALL commands, respectively.
layer closest to the surface layer. that the selection of the PCB copper thickness and width supports the maximum SW current. Figure 40. LT7171 Recommended PCB Layout
Figure 41. LT7171-1 Recommended PCB Layout temperature to an acceptable level.
Table 17. Related Parts
Figure 44. 30-lead (3.5mm × 4mm) LQFN Package (05-08-7066) Dimensions shown in millimeters
Table 18. Ordering Guide 1 The LT7171RV#TRPBF and LT7171RV-1#TRPBF are RoHS compliant parts. Table 19. Evaluation Boards
Data Sheet LT7171/LT7171-1 analog.com Rev. A 53 of 54
REVISION HISTORY
0 5/2024 Initial Release — A 9/2024 Updated Pin Descriptions Table Updated Table 9 Updated Table 10
Data Sheet LT7171/LT7171-1 ALL INFORMATION CONTAINED HEREIN IS PROVIDED “AS IS” WITHOUT REPRESENTATION OR WARRANTY. NO RESPONSIBILITY IS ASSUMED BY ANALOG DEVICES FOR ITS USE, NOR FOR ANY INFRINGEMENTS OF PATENTS OR OTHER RIGHTS OF THIRD PARTIES THAT MAY RESULT FROM ITS USE. SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOU T NOTICE. NO LICENCE, EITHER EXPRESSED OR IMPLIED, IS GRANTED UNDER ANY ADI PATENT RIGHT, COPYRIGHT, MASK WORK RIGHT, OR ANY OTHER ADI INTELLECTUAL PROPERTY RIGHT RELATING TO ANY COMBINATION, MACHINE, OR PROCESS WHICH ADI PRODUCTS OR SERVICES ARE USED. TRA DEMARKS AND REGISTERED TRADEMARKS ARE THE PROPERTY OF THEIR RESPECTIVE OWNERS. ALL ANALOG DEVICES PRODUCTS CONTAINED HEREIN ARE SUBJECT TO RELEASE AND AVAILABILITY. analog.com Rev. A 54 of 54