LT7170/LT7170-1 (Rev.A)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 36
Technical content
20 A, 16 V, Single- or Dual-Phase, Silent Switcher Step-Down Regulators with
Digital Power System Management Rev. A DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
FEATURES
►Silent Switcher architecture: enables a compact, efficient, low EMI solution ►PMBus/I2C serial interface ►Telemetry read back includes VOUT, IOUT, VIN, die tempera- ture, and faults ►Programmable voltage, current limit, sequencing, soft start and stop, undervoltage and overvoltage, phase, frequency (up to 4 MHz), and loop compensation ►Integrated three times programmable NVM ►Key parameters selectable by resistor ►VOUT set point range: 0.4 V to 5.5 V ►VOUT accuracy: ±0.25%, 0.6 V ≤ VOUT ≤ 1.375 V ►Differential remote VOUT sense ►Fast transient response ►Wide VIN supply range: down to 2.9 V or 1.5 V with EXTVCC ►Programmable and synchronizable: 400 kHz to 4 MHz ►24-lead (3.5 mm × 4 mm) LQFN package
APPLICATIONS
►Communications, storage, and industrial systems ►Data center and solid state drives TYPICAL APPLICATION Figure 1. Typical Application for the LT7170-1 graphical user interface (GUI) tool. small overall solution size. than 0.2 V before enabling the output and beginning a soft start. This VOUT discharge threshold is programmable from 0.2 V to 2.2 V. The LT7170/LT7170-1 use forced-continuous switching operation. Figure 2. LT7170-1 12 VIN to 1.0 VOUT Efficiency
Data Sheet LT7170/LT7170-1 TABLE OF CONTENTS analog.com Rev. A | 2 of 36 Minimum On-Time and Minimum Off-Time Programmable PWM Control Loop
REVISION HISTORY
9/2024—Rev. 0 to Rev. A Changed PGOOD and ALERT Open-Drain Outputs, Output High Voltage, VOL Parameter to PGOOD Changed Setting Switching Frequency and PWM Mode Section to Setting SYNC and PWM 1/2024—Revision 0: Initial Version
Figure 3. LT7170 Functional Block Diagram
Figure 4. LT7170-1 Functional Block Diagram
Data Sheet LT7170/LT7170-1
ELECTRICAL CHARACTERISTICS
analog.com Rev. A | 5 of 36 TA = 25°C for typical values. For minimum and maximum values, specifications apply over the full operating temperature range, unless otherwise noted. Table 1. Electrical Characteristics
Data Sheet LT7170/LT7170-1 analog.com Rev. A | 6 of 36 Table 1. Electrical Characteristics (Continued)
5 V ≤ VIN_ON/VIN_OFF ≤ 16 V −2 2 %
Data Sheet LT7170/LT7170-1 analog.com Rev. A | 7 of 36
2.5 V < VIN < 16 V −1 +1 %
1 The LT7170/LT7170-1 switching regulators use valley current mode control so that the current limits specified correspond to the valley of the inductor current waveform. The maximum load current is higher and equals the valley current limit plus one half of the inductor ripple current. 2 Guaranteed by design, characterization, and correlation with statistical process controls. was biased at 9.6 V to 16 V. Table 2. I2C/PMBus Timing
Data Sheet LT7170/LT7170-1 analog.com Rev. A | 8 of 36 Table 2. I2C/PMBus Timing (Continued)
Table 3. Absolute Maximum Ratings
1 The average VIN input current to the LT7170/LT7170-1 is a function of VIN, the
may affect device reliability and lifetime.
2 The LT7170/LT7170-1 are specified over the –40°C to 150°C operating TJ
other environmental factors. ing conditions for extended periods may affect product reliability. ques improve thermal resistance values. tion-to-case bottom thermal resistance. Table 4. Thermal Resistance for Demonstration Board in Still Air damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.
Figure 5. Pin Configuration Table 5. Pin Function Descriptions provide low impedance electrical and thermal contact to power ground.
4 SYNC/
External Clock Synchronization Input (SYNC)/Output Pin and Pulse-Width Modulation (PWM) Configuration Resistor Pin (PWM_CFG). Applications Information for more details. programmed in the NVM. The VOUT_CFG pin is read at LT7170/LT7170-1 startup and reset. supply other than VOUT, connect a 0.1 μF or greater local bypass ceramic capacitor from this pin to PGND. function is not used, the ALERT pin can be tied to ground.
Table 5. Pin Function Descriptions (Continued) required, PGOOD can be tied to ground. operation is not required, SDA can be tied to ground. the VDD18 pin with external circuitry. inside the LT7170/LT7170-1. Do not connect SGND to PGND on the PCB. 15 VSENSEP Output Voltage Positive Sense Input. Connect the VSENSEP pin to the output voltage sense point. 16 VSENSEN Output Voltage Negative Sense Input. Connect the VSENSEN pin to the output voltage ground sense point. LT7170-1, using the top PCB layer. The normal operating voltage swing of the BOOST1 pin is from DRVCC to VIN + DRVCC. and BOOST0 capacitor. For optimal performance, keep the SW1 node small on the PCB. BOOST0 capacitor. For optimal performance, keep the SW0 node small on the PCB. LT7170-1, using the top PCB layer. The normal operating voltage swing of the BOOST0 pin is from DRVCC to VIN + DRVCC.
Data Sheet LT7170/LT7170-1 THEORY OF OPERATION analog.com Rev. A | 17 of 36 OVERVIEW The LT7170/LT7170-1 are monolithic, dual-phase, DC/DC synchro- nous step-down regulators capable of providing up to 20 A of continuous output current with input supply voltages up to 16 V. For the LT7170, connect SW0 and SW1 together to a single inductor to drive a single-regulated output supply. For the LT7170-1 dual-phase option, connect an inductor to each of the switch pins, SW0 and SW1, to drive a single-regulated output supply. The switching phases are set to 180° out of phase. The phase selected by configuration resistors or by the MFR_PWM_PHASE_LT7170 command sets the phase difference between the SYNC/PWM_CFG input and the SW0 output. The I2C-based serial peripheral interface (SPI) is compatible with PMBus 1.3, which supports bus speeds up to 1 MHz. Major features include the following: ►Programmable VOUT ►Programmable current limit ►Programmable fSW ►Programmable overvoltage and undervoltage comparators ►Programmable on and off delay times ►Programmable output rise and/or fall times ►Programmable control loop compensation ►Programmable input undervoltage threshold ►Selectable switch slew rate for EMI and efficiency optimization ►Dedicated power-good pin ►PLL for synchronous operation with an external clock ►Input and output voltage, output current, and die temperature telemetry ►Programmable output current readback sampling window ►Reduced power telemetry mode that slows analog-to-digital converter (ADC) sampling frequency to reduce input quiescent current ►Fully differential remote VOUT sense ►3x programmable nonvolatile configuration memory with error correcting code (ECC) ►Optional external configuration resistors to set key operating parameters ►Standalone operation using either configuration resistors or non- volatile configuration memory ►A variety of fault and warning handling and reporting mecha- nisms A dedicated ALERT pin is provided to indicate that faults or warn- ings have occurred. Individual status commands enable fault and warning reporting to identify the specific event. Fault reporting and shutdown behavior are fully configurable. Faults can be individually masked, and the fault responses can be pro- grammed to retry or remain shutdown. Fault and warning detection capabilities include the following: ►Output undervoltage and overvoltage faults and warnings ►Internal overtemperature fault and warning ►Communication, memory, or logic (CML) faults ►Input overvoltage fault and undervoltage warning ►Output overcurrent fault and warning SWITCHING REGULATOR CONTROL LOOP The LT7170/LT7170-1 employ a controlled on-time, valley current- mode architecture. In normal operation, the internal top power, metal-oxide semiconductor FET (MOSFET) is turned on for an interval determined by an on-time control circuit. When the top power MOSFET turns off, the bottom power MOSFET turns on until the valley current comparator trips, restarting the on-time control circuit and initiating the next cycle. Inductor current is determined by sensing the voltage drop across the bottom power MOSFET when it is on. The error amplifier adjusts the average inductor cur- rent (ITH) node voltage by comparing the regulator output voltage with an internal reference digital-to-analog converter (DAC) output. The voltage on the ITH node sets the comparator threshold, which is compared with the sensed-inductor valley current. An increase in load current causes a drop in the output voltage relative to the internal reference. The error amplifier responds by forcing the ITH voltage higher until the average inductor current matches that of the load current. An internal PLL synchronizes the oscillator frequency to an external clock signal if one is present on the SYNC/PWM_CFG pin. If no ex- ternal clock is applied, the fSW is set by the FREQUENCY_SWITCH command, which can be initialized by using configuration resistors (see the Setting SYNC and PWM Configuration for more details). NVM The LT7170/LT7170-1 contain internal programmable NVM with ECC to store user configuration settings. The NVM can be pro- grammed up to three times. During NVM write operations, TJ must be between −40°C and +125°C, and VIN must be biased between 9.6 V to 16 V. In addition to ECC, the integrity of the on-board NVM is checked with a cyclic redundancy check (CRC) calculation after a power-on reset or execution of a RESTORE_USER_ALL command. If an invalid CRC is detected, the regulator output remains disabled until the issue is resolved. See the LT7170/LT7170-1 PMBus/I2C Reference Manual for more information about NVM programming.
Data Sheet LT7170/LT7170-1 THEORY OF OPERATION analog.com Rev. A | 18 of 36 POWER-UP AND INITIALIZATION The LT7170/LT7170-1 are capable of standalone supply sequenc- ing and controlled turn-on and turn-off operation. To reduce LT7170/ LT7170-1 power dissipation, EXTVCC can be driven with an external supply, the supported VIN input operating range is from 1.5 V to 16 V. Note that without EXTVCC, the VIN operating range is from 2.9 V to 16 V. The LT7170/LT7170-1 initialize upon application of power to VIN or EXTVCC, or when an MFR_RESET or RESTORE_USER_ALL command is sent. In the initialization step, the LT7170/LT7170-1 read the NVM configuration and/or resistor configuration pins to set the initial state of the PMBus commands. The PGOOD pin is held low during initialization and released after the output voltage reach- es the target value. If the resistor configuration pins are enabled, the LT7170/LT7170-1 initialize certain commands based on the configuration resistor values, which supersede the NVM settings. Resistor configuration pins are enabled by factory default. Set Bit 6 of the MFR_CONFIG_ALL_LT7170 command in the NVM to disable the configuration pins. See the Using Resistor Configuration Pins section for additional information. For commands that are not initialized based on the configuration resistors, initial values are determined by the NVM factory defaults. LT7170/LT7170-1 initialization typically requires 5 ms. If the resistor configuration pins are disabled, the initialization time is reduced to 3 ms (typical). After initialization is complete, VIN is checked. For the devices to operate, VIN must exceed the programmable threshold set by the VIN_ON command. SOFT START When all conditions required for startup are met and the output of the LT7170 or LT7170-1 is enabled, the device waits for the commanded turn-on delay and ramps the target output voltage up to the commanded voltage set point. The turn-on delay is set by the TON_DELAY command, which is 0 ms by default. The soft-start ramp time is set by the TON_RISE command, which is 1 ms by default. During soft-start, the LT7170/LT7170-1 devices use a discontinuous mode in which the inductor current is not allowed to reverse. The reverse-current comparator, IREV, turns off the bottom switch just before the inductor current reaches zero, preventing the inductor current from reversing and going negative. Both power MOSFETs remain off while the output capacitor supplies the load current until the ITH node voltage rises to more than the zero current threshold to initiate the next cycle. After the commanded voltage set point is reached, the channel transitions to forced continuous conduction mode. SHUTDOWN The LT7170/LT7170-1 can be programmed to turn off immediately or to sequence off. When sequencing off, the LT7170/LT7170-1 wait for the turn-off delay and then perform a soft stop ramp by which the regulation target voltage is ramped down to zero. The turn-off delay is set by the TOFF_DELAY command, which defaults to zero. The target voltage ramp-down time is set by the TOFF_FALL command, which defaults to 2 ms. By default, the channel ramps down in forced con- tinuous conduction mode. The ramp-off behavior can be configured using the MFR_PWM_MODE_ LT7170 command. Sequencing off occurs if OPERATION is set to 0x40, or if the RUN pin is deasserted, and Bit 0 of the ON_OFF_CONFIG command is set to 0 and Bit 2 of the ON_OFF_CONFIG command is set to 1. When immediate shutdown occurs, the regulators ramp the inductor current to zero as quickly as possible and then stop switching. In this case, the output voltage decays based only on the load current and the internal 250 Ω pull-down on the VSENSEP pin. Immediate shutdown occurs in any of the following situations: ►VIN falls to less than the VIN_OFF threshold. ►If the OPERATION command is cleared to 0x00, of if Bit 3 of the ON_OFF_CONFIG command is set to 1. ►A fault condition occurs that causes the output to turn off. ►The RUN pin is deasserted and the ON_OFF_CONFIG com- mand is configured such that the RUN pin deassertion causes immediate shut down as determined by Bit 0 and Bit 1 of the ON_OFF_CONFIG command. WARNING AND FAULT HANDLING The LT7170/LT7170-1 continuously monitor the system for fault and warning conditions. Fault responses are configurable using the corresponding FAULT_RESPONSE commands, such as VOUT_UV_ FAULT_RE- SPONSE and VOUT_OV_FAULT_RESPONSE. Possible fault re- sponses are as follows: ►Ignores fault or warning condition and continues operation. ►Shuts down immediately and retries if the fault condition is no longer present. ►Shuts down immediately and latches off. The remainder of this section describes the factory default warning and fault behavior. See the supported PMBus and MFR commands table in the LT7170/LT7170-1 PMBus/I2C Reference Manual for details on configuring fault and warning behavior. All faults and warnings are indicated in the PMBus status com- mands. The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits in all sta- tus commands simultaneously. This command also deasserts the ALERT pin. If the fault is still present when the bit is cleared, the fault bit remains set, and the host is notified by asserting the ALERT pin low. The CLEAR_FAULTS command does not cause a unit that has latched off for a fault condition to restart. Units that have shut down
the RUN pin and/or OPERATION command. ►A MFR_RESET command is issued. the status bits can be read to determine the cause of the fault. and the regulators continue to operate. TUS_BYTE, and STATUS_WORD commands. ►The output shuts down immediately. attempt to restart when the fault condition is no longer present. Table 6. Factory Default Warnings and Faults Behavior 1 The IOUT_OC_FAULT valley current threshold is controlled by MFR_PWM_MODE_LT7170, Bits[10:9]. 2 When a SYNC input clock error is detected during initialization, the output of the devices is disabled.
Data Sheet LT7170/LT7170-1 THEORY OF OPERATION analog.com Rev. A | 20 of 36 If a fault occurs due to overtemperature, the LT7170/LT7170-1 respond as follows: ►The output shuts down immediately. ►The PGOOD pin pulls low. ►The ALERT pin pulls low. ►The overtemperature (OT) bit is set in the appropriate status commands. ►When the ADC measures that the temperature is less than the overtemperature threshold, the LT7170/LT7170-1 attempt to restart. PGOOD PIN The open-drain PGOOD pin is pulled low when the output is off for any reason, during soft start and soft stop, or if the output voltage is less than the VOUT_UV_FAULT_LIMIT. Other pin conditions are defined in Table 6. ALERT PIN The SMBALERT_MASK command configures which warning and fault indicators cause the LT7170/LT7170-1 to pull down the open- drain ALERT pin. Once the LT7170 or LT7170-1 pulls down the ALERT pin, the de- vice continues to hold the ALERT pin low until one of the following occurs: ►The output is shut off and turned on. ►A CLEAR_FAULTS, RESTORE_USER_ALL, or MFR_RESET command is received. ►All unmasked status bits are cleared by writing a 1 to each bit. ►The device successfully transmits its address in response to the PMBus alert response address. ►Input power is removed from VIN and EXTVCC.
RESTORE_USER_ALL or MFR_RESET command. when the regulator is enabled. Table 7. VOUT_CFG Pin Configuration Resistor Selection 1 Output voltage set point is controlled by VOUT_COMMAND. 2 The PMBus ON_OFF_CONFIG command selects whether the RUN pin and/or the PMBus OPERATION command enables the regulator.
input as well as a clock input or output. Table 8. SYNC/PWM_CFG Pin Configuration Resistor Selection 2 For internal compensation, CITH is controlled by MFR_PWM_MODE_LT7170, Bits[8:6], and RITH is controlled by MFR_PWM_MODE_LT7170, Bits[5:3]. ► For 400 kHz to 625 kHz, RITH = 14 kΩ and CITH = 320 pF. ► For 2.5 MHz to 4 MHz, RITH = 60 kΩ and CITH = 80 pF.
Table 9. LT7170 Valley Current-Limit Selection Table 10. LT7170-1 Valley Current-Limit Selection per Phase losses in the output capacitors and reduces output voltage ripple. over temperature and applied voltage. to support the input ripple current. ed PWM control loop, as shown in Figure 38. Figure 38. Programmable Internal Compensation
- The internal compensation capacitor, CITH, can be adjusted
MFR_PWM_MODE_LT7170, Bits[8:6], as shown in Table 13. Table 11. Programmable Error Amplifier Transconductance Table 12. Programmable Compensation Resistance (RITH) Table 13. Programmable Compensation Capacitance (CITH)
ble via the LT7170/LT7170-1 SPI; however, it is not exhaustive. tionality. Table 14 lists the supported commands. meaning of these commands can change without notice. commands not published in Table 14. cision IEEE floating-point numbers. Table 14. Supported Commands (Cells Left Intentionally Blank) can be written to three times. protocols supported by this device.
Table 14. Supported Commands (Cells Left Intentionally Blank) (Continued) overvoltage fault is detected. undervoltage fault is detected. overcurrent fault is detected. overtemperature fault is detected. overvoltage fault is detected. VOUT to cross the VOUT_UV_FAULT_LIMIT. MAX_FAULT event is detected.
MFR_NVM_DATA bulk programming. READ_IOUT since the last MFR_CLEAR_PEAKS.
has decayed sufficiently to re-enable the channel. multiple Analog Devices chips. 1 A Y in the NVM column indicates that these commands are stored and restored using the STORE_USER_ALL and RESTORE_USER_ALL commands, respectively.
the input capacitors next to the VIN and PGND pins. copper thickness and width supports the maximum SW current. EVAL-LT7170-1 user guides for the LT7170/LT7170-1. Figure 41. LT7170 Recommended PCB Layout
Figure 42. LT7170-1 Recommended PCB Layout
Data Sheet LT7170/LT7170-1 THERMAL CONSIDERATIONS analog.com Rev. A | 34 of 36 Ensure that the layout of the PCB includes good heat dissipation from the LT7170/LT7170-1. Solder the ground pins on the bottom of the package to a ground plane. Tie this ground to the large copper layers underneath with thermal vias. These layers spread heat dissipated by the LT7170/LT7170-1. Placing additional vias can reduce thermal resistance further. The maximum load current must be derated as the ambient temperature approaches the maximum junction rating. The temperature rise of the LT7170/LT7170-1 is worst when oper- ating at a high load, a high VIN, and a high fSW. If the case temperature is too high for a given application, either the VIN, fSW, or ILOAD can be decreased to reduce the temperature to an acceptable level.
Data Sheet LT7170/LT7170-1 OUTLINE DIMENSIONS ©2024 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. A | 36 of 36 Package Drawing (Option) Package Type Package Description 05-08-7065 LQFN 24-Lead Package For the latest package outline information and land patterns (footprints), go to Package Index. ORDERING GUIDE Model1 Temperature Range Package Description Packing Quantity Package Option LT7170RV#TRMPBF −40°C to +150°C 24-Lead (3.5 mm × 4 mm) LQFNReel, 500 05-08-7065 LT7170RV#TRPBF −40°C to +150°C 24-Lead (3.5 mm × 4 mm) LQFNReel, 2500 05-08-7065 LT7170RV-1#TRMPBF −40°C to +150°C 24-Lead (3.5 mm × 4 mm) LQFNReel, 500 05-08-7065 LT7170RV-1#TRPBF −40°C to +150°C 24-Lead (3.5 mm × 4 mm) LQFNReel, 2500 05-08-7065 1 All models are RoHS compliant. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). EVALUATION BOARDS Model1 Description EVAL-LT7170-AZ LT7170 Evaluation Board EVAL-LT7170-1-AZ LT7170-1 Evaluation Board 1 Z = RoHS Compliant Part.