LT7153SPAV#TRPBF

LT7153SP AD | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 31

Technical content

analog.com Rev 0 2 of 31 TABLE OF CONTENTS

analog.com Rev 0 3 of 31

REVISION HISTORY

0 05/25 Initial release ─

Table 1. Electrical Characteristics

analog.com Rev 0 5 of 31 (Specifications are at TA = 25°C. VIN = 5V, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS Oscillator Oscillator Frequency fosc RRT = 232kΩ 0.4 MHz RRT = 100kΩ 0.85 1 1.15 RRT = 20kΩ 5 SYNC Input Range fSYNC % of programmed frequency ±30 % MODE, SYNC/SPREAD Threshold VIL(MODE) VIL(SYNC/SPREAD) MODE or SYNC/SPREAD LOW 0.3 V VIH(MODE) VIH(SYNC/SPREAD) MODE or SYNC/SPREAD HIGH 1.0 MODE, SYNC/SPREAD Currents IMODE ISYNC/SPREAD MODE = 0, SYNC = 0V 6 14 µA CLKOUT Threshold VIL(CLKOUT) CLKOUT High VINTVCC –

0.2 VINTVCC V

VIH(CLKOUT) CLKOUT Low 0 0.2 Phasing SYNC to Oscillator ɸ(SYNC to OSC) PHSMD1 = 0, PHSMD2 = 0 0 Degree PHSMD1 = INTVcc, PHSMD2 = 0 0 PHSMD1 = 0, PHSMD2 = INTVcc/2 -30 PHSMD1 = INTVcc, PHSMD2 = INTVcc/2 -45 PHSMD1 = 0, PHSMD2 = INTVcc -60 PHSMD1 = INTVcc, PHSMD2 = INTVcc -90 Oscillator to CLKOUT ɸ(OSC to CLKOUT) PHSMD1 = 0, PHSMD2 = 0 180 Degree PHSMD1 = INTVcc, PHSMD2 = 0 120 PHSMD1 = 0, PHSMD2 = INTVcc/2 180 PHSMD1 = INTVcc, PHSMD2 = INTVcc/2 180 PHSMD1 = 0, PHSMD2 = INTVcc 120 PHSMD1 = INTVcc, PHSMD2 = INTVcc 180 AVPSEL, PHSMD1, PHSMD2, Threshold VIH AVPSEL, PHSMD1, PHSMD2 High VINTVCC – 0.2 V AVPSEL, PHSMD1, PHSMD2 Threshold VIL AVPSEL, PHSMD1, PHSMD2 Low 0.2 V ILIM Reduced Max Current Limit ILIM55 PHSMD1 = INTVcc /2, PHSMD2 = 0 14 A ILIM70 PHSMD1 = INTVcc /2, PHSMD2 = INTVcc 18 Power Good PGOOD Over Voltage Threshold OV VFB Rising 4 6.5 9 % VFB Hysteresis (Falling) 1.5 PGOOD Under Voltage Threshold UV VFB Falling -9 -6.5 -4 % VFB Hysteresis (Rising) 1.5

analog.com Rev 0 6 of 31 (Specifications are at TA = 25°C. VIN = 5V, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS PGOOD Leakage Current IPGOOD 0.5 µA PGOOD Pull-Down Resistance RPGOOD VPG = 0.1V 5 Ω PGOOD Delay PG(Delay) PGOOD Low to High 6 Cycles PGOOD High to Low 25 Track/Soft-Start Source Current ITRACK/SS VTRACK/SS = 0V 10 15 µA Pull-Down Resistance RTRACK/SS VTRACK/SS = 0.1V 2500 Ω 1 The LT7153SP is tested under pulsed load conditions such that TJ ≈ TA. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization, and correlation with statistical process controls. The LT7153SP is guaranteed over the full –40°C to 125°C operating junction temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance, and other environmental factors. The junction temperature (TJ, in °C) is calculated from the ambient temperature (TA, in °C) and power dissipation (PD, in watts) according to the formula: TJ = TA + (PD • θJA), where θJA (in °C/W) is the package thermal impedance. 2 The quiescent current in Discontinuous Mode does not include switching loss of the power FETs. 3 VFB is measured in a feedback loop that servos VITH to a specified voltage. 4 Inductor should be selected such that peak inductor current does not exceed 39A in application.

Table 2. Absolute Maximum Ratings extended periods may affect product reliability.

Figure 3. Pin Configurations

Table 3. Pin Descriptions

1 INTVcc

4.7µF low ESR ceramic capacitor. voltage drop below ground to a diode voltage above PVIN.

15 PHSMD1/

used to select between three lower ILIM settings.

16 PHSMD2/

three different lower ILIM settings. MODE to a voltage above 1V selects forced continuous mode. voltage of the FB pin is not within ±6.5% of the internal 0.5V reference. 19-27 PVIN Power VIN. Input voltage to the on-chip power MOSFETs.

28 SYNC/

to disable spread spectrum operation; tie to INTVcc or float to start spread spectrum. put the part in forced continuous mode. the SVIN pin through a 2.2Ω resistor in series with 10µF ceramic capacitor.

30 CLKOUT

phase errors. When RUN is low, this pin defaults high. 31 SGND Ground for signal ground. GND to program the frequency from 400kHz to 5MHz.

analog.com Rev 0 10 of 31

33 ITH

Error amplifier output and switching regulator compensation point. The current comparator’s trip threshold is linearly proportional to this voltage, whose normal range is from 0.3V to 1.3V.

34 TRACK/SS

Output tracking and soft-start pin. Allows to control the rise time of the output voltage. Connecting a voltage between 0V and 0.5V on this pin relative to VOUT- bypasses the internal reference input to the error amplifier. Instead, it servos the FB pin relative to VOUT- to this voltage. There’s an internal 10µA pullup current from INTVcc to this pin; so putting a capacitor from this pin to VOUT- provides a soft-start function. 35 FB Feedback input to the error amplifier of the step-down regulator. Connect the feedback resistor divider center tap to this pin. The output can be adjusted from 0.5V to 4.5V.

36 VOUT-

Negative return of output rail. Connect this pin directly to the bottom terminal of the remote output capacitor near the load in order to minimize error incurred by voltage drops across the metal traces of the PCB. GND Exposed Pad. 38-41 Corner Ground Pins.

Figure 26. Block Diagram

analog.com Rev 0 16 of 31 THEORY OF OPERATION Main Control Loop The LT7153SP is a single channel, current-mode monolithic step-down regulator capable of providing ±25A of output current. In normal operation, the internal top power MOSFET is turned on for a fixed interval determined by a one - shot timer (ON signal in Block Diagram Figure 26). When the top power MOSFET turns off, the bottom power MOSFET turns on until the current comparator, ICMP, trips, restarting the one-shot timer and initiating the next cycle. Inductor current is determined by sensing the voltage drop across SW and GND nodes of the bottom power MOSFET when it is on. The voltage on the ITH pin sets the comparator threshold corr esponding to the inductor valley current. The error amplifier, EA, adjusts this ITH voltage by comparing the feedback signal, VFB, with an internal 0.5V reference. If the load current increases, it causes a drop in the feedback voltage relative to the internal reference, the ITH voltage then rises until the average inductor current matches that of the load current. At light load currents, the inductor current can drop to zero and become negative. In Burst Mode operation, this is detected by the current reversal comparator, IREV, which then shuts off the bottom power MOSFET. Both power MOSFETs remain off with the output capacitor supplying the load current until the ITH voltage rises above zero current level to initiate the next cycle. If continuous mode of operation is desired, simply float the MODE pin or tie it to INTVcc. The operating frequency is determined by the value of the R RT resistor, which programs the current for the internal oscillator. An internal phase-lock loop servos the switching regulator on-time to track the internal oscillator and force a constant switching frequency. A clock signal can be applied to the SYNC/SPREAD pin to synchronize the switching frequency to an external clock. The regulator defaults to force continuous operation once the clock signal is present. The S in LT7153SP refers to the second -generation Silent Switcher technology. The IC has integrated ceramic capacitors for VIN, INTVcc, and BOOST to keep all the fast AC current loops small, thus improving the EMI performance. Furthermore, it allows for faster switching edges, which greatly improves efficiency at high switching frequencies. Low IQ Shutdown (RUN) Pulling the RUN pin to ground forces the LT7153SP into its shutdown state, drawing very little current. Bringing RUN above 0.6V turns on the internal reference while keeping the MOSFETs off. Further increasing RUN above the RUN rising threshold of 1.2V nominal, the entire chip turns on. The accurate 1.2V RUN threshold allows programming the SVIN under voltage lockout threshold externally using a resistor divider. INTVCC Regulator and Bypass Capacitor An internal low dropout regulator produces the 3.6V supply that powers the drivers and internal bias circuitry. A 10μF ceramic capacitor should be used to bypass INTV cc to ground; 4.7 μF is the minimum value recommended. Good bypassing is necessary to supply the high transient currents required by the MOSFET drivers. For applications running high frequency and high output currents, increased switching currents may result in higher die temperatures due to higher power dissipation across the LDO. In such cases, consider shorting INTVcc to SVIN. SVIN can be a 3.3V or 5V rail, but be aware that 5V operation results in higher switching losses, which will be more critical at higher switching frequencies. PVIN and SVIN do not have to be tied to the same potential, so an external 3.3V supply can be used to power S VIN if one is available. When biasing SVIN and PVIN from different potentials, the two supplies are required to be sequenced such that SVIN is up before PVIN powers up and that PVIN is powered down first.

analog.com Rev 0 17 of 31 Adjustable Current Limit The current limit setting of the LT7153SP can be lowered to 70% or 55% of its full value for applications that do not require the full 25A capability. The state of the two-phase mode pins (PHSMD1/ISEL, PHSMD2/ILIM) determines the current limit setting. See Table 1 for details. Overcurrent and Short-Circuit Protection The LT7153SP has a cycle-by-cycle overcurrent protection scheme by sensing the inductor valley current. When the current limit is reached, the output begins to fall, decreasing the on -time of the top power MOSFET. If the short is prolonged enough for the on-time to reach its minimum, the off-time lengthens, lowering the switching frequency and preventing excess current from being drawn from VIN. After the overcurrent or short is removed, the regulator executes its soft-start function to prevent the output voltage from overshooting. Multiphase Operation For output loads that demand more than 25A of current, multiple the LT7153SP outputs can be tied together to run out of phase to provide more output current. See Table 1 and Figure 28 for more information. The LT7153SP not only varies the phasing between the internal oscillator and CLKOUT, but it also varies the phasing between the external clock and the internal oscillator, allowing shorted signal chains to minimize accumulating clock jitter. Power Good Status Output PGOOD open-drain output is pulled low if the regulator output feedback voltage, V FB, exits a ±6.5% window around the regulation point while the overvoltage (OV) or undervoltage (UV) comparator is tripped. This condition is released once regulation within a ±6.5% window is achieved. Continuous operation is forced during OV and UV conditions, except during start -up when the TRACK/SS pin is ramping up to 0.5V. VIN Overvoltage Protection To protect the internal power MOSFET devices against transient voltage spikes, the LT7153SP constantly monitors the PVIN pin for an overvoltage condition. When the PVIN rises above 8V, the regulator suspends operation by shutting off both power MOSFETs. Once PVIN drops below 7.5V, the regulator immediately resumes normal operation. During an overvoltage event, the internal soft-start voltage is clamped to a voltage slightly higher than the feedback voltage. Thus, the soft-start feature is present upon exiting an overvoltage condition. Selectable Load Line (AVPSEL) In order to minimize the amount of output capacitance needed, the LT7153SP allows to pick two different load line settings, in addition to a flat load line setting. Load line settings are accessed via the AVPSEL pin state: flat load line setting when this pin is tied to ground, 1% when floated, and 1.5% when tied to INTVcc. MODE, SYNC, Spread-Spectrum Operation Connecting the MODE pin to ground enables Burst Mode operation for superior efficiency at low load currents at the expense of slightly higher output voltage ripple. When the MODE pin is tied to INTVcc or floated, forced continuous mode operation is selected, creating the lowest fixed output ripple at the expense of light load efficiency. The SYNC/SPREAD pin is a dual -function pin. This pin allows the LT7153SP to sync to an external clock signal and also to activate or deactivate its spread spectrum feature. The LT7153SP detects the presence of the external clock signal on the SYNC/SPREAD p in and synchronizes the internal oscillator to the frequency of the incoming clock. Phasing between the SYNC input and the internal oscillator is determined by the states of the two phase mode pins (PHSMD1/ISEL, PHSMD2/ILIM). When the SYNC/SPREAD pin is tied to INTVcc or floated, spread-spectrum operation is enabled. The LT7153SP varies its frequency between the preset frequency and 20% higher than the preset value. When the SYNC/SPREAD pin is tied to ground, frequency spreading is disabled.

analog.com Rev 0 18 of 31 APPLICATIONS INFORMATION A simplified LT7153SP application circuit is shown on the first page of the data sheet. External component selection is largely driven by the target current ripple, load requirement, and switching frequency. Component selection typically begins with the selection of the inductor L and resistor R RT. Once the inductor is chosen, select the input capacitor, CIN, and the output capacitor, C OUT. Next, select the feedback resistors to set the desired output voltage. Finally, select the remaining optional external components for functions such as external lo op compensation, tracking/soft-start, input UVLO, and PGOOD. Silent Switcher Architecture The LT7153SP has integrated capacitors that allow it to operate at high switching frequencies efficiently. The internal VIN bypass capacitors allow the SW edges to transition extremely fast, effectively reducing transition loss. The capacitors also greatly reduce SW overshoot during top FET turn -on, which improves the robustness of the device over time. Programming Switching Frequency Selection of the switching frequency is a trade-off between efficiency and component size. High frequency operation allows the use of smaller inductors and capacitors. Operating at lower frequencies improves efficiency by reducing internal gate charge losses but requires larger inductances and capacitances to maintain low output ripple voltage. Connecting a resistor, R RT, from the RT pin to SGND programs the switching frequency, fSW, from 400kHz to 5MHz according to the following formula: fSW(Hz) = 1e11 RRT(Ω) The internal PLL has a synchronization range of ±30% around its programmed frequency. Therefore, during external clock synchronization be sure that the external clock frequency is within this ±30% range of the R RT programmed frequency. Output Voltage Programming Each regulator’s output voltage is set by an external resistive divider according to the following equation: VOUT = 0.5V • (1 + R1 R2) The desired output voltage is set by the appropriate selection of resistors R1 and R2, which allow the VFB pin to sense a fraction of the output voltage, as shown in Figure 27. Choosing large values for R1 and R2 results in improved zero/light load efficiency but may lead to undesirable noise coupling or phase margin reduction due to stray capacitances at the V FB node. Take care to route the V FB trace away from any noise source, such as SW trace. A feedforward compensation capacitor, CFF, can also be placed between VOUT and FB to improve transient performance. Figure 27.Setting the Output Voltage If the output voltage is outside the V ON sense range (0.5V ~ 4V), the output voltage stays in regulation, but the switching frequency may deviate from the programmed frequency. FB GND VOUT LT7153SP KELVIN TO POL GND CFF 033

analog.com Rev 0 19 of 31 Soft-Start and Output Voltage TRACK An internal 10µA pulls up the TRACK pin to INTVcc. Putting an external capacitor, CSS, from TRACK to ground enables soft starting the output to prevent a current surge on the input supply. The relationship between output rise time, TSS, and soft-start capacitance, CSS, is given by: TSS = 0.5e5 • CSS Upon start -up time, the LT7153SP operates in discontinuous mode until track voltage is higher than 0.5V. The regulator then operates in forced continuous mode until output is above the UV threshold (VFB > 0.475V). Once the output reaches this voltage, the operating mode of the regulator switches to the mode selected by the MODE pin as described above. The LT7153SP allows the user to program its output voltage ramp rate through the TRACK pin. From 0V to 0.5V, the TRACK voltage overrides the internal 0.5V reference input to the error amplifier, thus regulating the feedback voltage to that of the TRACK pin. When TRACK is above 0.5V, tracking is disabled, and the feedback voltage regulates to the internal reference voltage. Inductor Selection For a given input voltage, VIN, output voltage, VOUT, the inductor value, L, and operating frequency, f, determine the ripple current: ∆IL = VOUT fSW • L • (1 − VOUT VIN The inductor current ripple decreases with higher inductor value and higher operating frequency. Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors, and output voltage ripple. Highest efficiency operation is obtained at low frequency with small ripple current. However, achieving this requires a large inductor. There is a trade-off between component size, efficiency, and operating frequency. A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX). Exceeding 60% of IOUT(MAX) is not recommended. Note that the largest ripple current occurs at the highest VIN. To guarantee that ripple current does not exceed a specified maximum, the inductance should be chosen according to: L = VOUT fSW • ∆L(MAX)

• (1 − VOUT VIN(MAX) Once the value for L is known, the type of inductor must be selected. Actual core loss is independent of core size for a fixed inductor value, but is very dependent on the inductance selected. As the inductance or frequency increases, core losses decrease. Unfortunately, increased inductance requires more turns of wire leading to increased DCR and copper losses. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates hard, which means that inductance collapses abruptly when t he peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate. To avoid overheating and poor efficiency, choose an inductor with an RMS current rating that is greater than the maximum expected output load of the application. In addition, the saturation current (typically labeled I SAT) rating of the inductor must be higher than the load current plus 1/2 of inductor ripple current: IL(PEAK) = IOUT(MAX) + ∆IL Different core materials and shapes change the size/current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and do not radiate much energy, but generally cost

analog.com Rev 0 20 of 31 more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depends on the price versus size requirements and any radiated field/EMI requirements. Input Capacitor (CIN) Selection The input capacitance, C IN, is needed to filter the square wave current at the drain of the top power MOSFET. To prevent large voltage transients from occurring, use a low ESR input capacitor sized for the maximum RMS current. The maximum RMS current is given by: IRMS ≅ IOUT(MAX) • VOUT VIN

• √ 𝑉𝐼𝑁 𝑉𝑂𝑈𝑇 − 1 This formula has a maximum at VIN = 2VOUT, where: IRMS ≅ IOUT This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life, which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. For low input voltage applications, sufficient bulk input capacitance is needed to minimize transient effects during output load changes. Output Capacitor (COUT) Selection The selection of COUT is determined by the effective series resistance (ESR) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be check ed by viewing the load transient response. The output ripple, ∆V OUT, is determined by: ∆VOUT < ∆IL • ( 1 8 • fSW • COUT + ESR) The output ripple is highest at maximum input voltage since ∆I L increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic, and ceramic capacitors are all available in surface mount packages. Special polymer capacitors are very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density, but it is important to only use types that are surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long-term reliability. Ceramic capacitors have excellent low ESR characteristics and small footprints. Since the ESR of a ceramic capacitor is so low, it is more useful to choose the output capacitor value to fulfill a charge storage requirement. During a load step, the output capacitor must instantaneously supply the current to support the load until the f eedback loop raises the switch current enough to support the load. The time required for the feedback loop to respond is dependent on the compensation and the output capacitor size. Typically, five cycles are required to respond to a load step, but only in the first cycle does the output voltage drop linearly. The output droop, VDROOP, is usually about three times the linear drop of the first cycle. Thus, a good place to start with the output capacitor value is approximately. COUT = 3 • ( ∆IOUT fO•VDROOP

analog.com Rev 0 21 of 31 Using Ceramic Input and Output Capacitors Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating, and low ESR make them ideal for switching regulator applications. However, due to the self-resonant and high Q ch aracteristics of some types of ceramic capacitors, take care when these capacitors are used at the input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the VIN input. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. For a more detailed discussion, refer to Application Note 88. When choosing the input and output ceramic capacitors, choose the X5R and X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. Choose X8R for 150°C applications. Mor e capacitance may be required depending on the duty cycle and load step requirements. In most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. A 47μF ceramic capacitor is usually enough for these conditions. Place this input capacitor as close to the PVIN and GND pins as possible. Minimum Off-Time and Minimum On-Time Considerations The minimum off-time, tOFF(MIN), is the smallest amount of time that the LT7153SP is capable of turning on the bottom power MOSFET, tripping the current comparator and turning the power MOSFET back off. This time is generally about 30ns. The minimum off-time limit imposes a maximum duty cycle of tON/(tON + tOFF(MIN)). If the maximum duty cycle is reached due to a dropping input voltage, for example, then the output drops out of regulation. The minimum input voltage to avoid dropout is: VIN(MIN) = VOUT • tON + tOFF(MIN) tON Conversely, the minimum on-time is the smallest duration of time in which the top power MOSFET can be in its ON state. This time is typically 15ns. In continuous mode operation, the minimum on -time limit imposes a minimum duty cycle of DC(MIN) = fSW • tON(MIN) where t ON(MIN) is the minimum on -time. Reducing the operating frequency alleviates the minimum duty cycle constraint. In the rare cases where the minimum duty cycle is surpassed, the output voltage remains in regulation and the switching frequency decreases from its programmed value. This is an acceptable result in many applications. So, this constraint may not be of crit ical importance in most cases. High switching frequencies may be used in the design without any fear of output overvoltage. As the sections on inductors and capacitor selection show, high switching frequencies allow the use of smaller board components, thus reducing the size of the application circuit.

between the internal oscillator and CLKOUT and between the internal oscillator and SYNC. Figure 28. 2, 3, 4, 6, 8, 12 Multiphase Configuration Table 4. Multiphase Pin Configuration

analog.com Rev 0 24 of 31 The initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/DC ratio cannot be used to determine phase margin. The output voltage settling behavior is related to the stability of the closed -loop system and demonstrates the actual overall supply performance. For detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to Analog Devices Application Note 76. In some applications, a more severe transient can be caused by switching in loads with large (>47µF) input capacitors. The discharge input capacitors are effectively put in parallel with C OUT, causing a rapid drop in V OUT. No regulator can deliver enough current to prevent this problem if the switch connecting the load has low resistance and is driven quickly. The solution is to limit the turn -on speed of the load switch driver. A hot swap controller is designed specifically for this purpose and usually incorporates current limiting, short -circuit protection, and soft - starting. Thermal Conditions In some applications where the LT7153SP is operated at a combination of high ambient temperature, high switching frequency, high VIN, and high output load, the required power dissipation might push the part to exceed its maximum junction temperature. To avoid the LT7153SP from exceeding the maximum junction temperature, maximum current rating is derated depending on the operating condi tions. The temperature rise of the part varies depending on the thickness of copper on the PCB board, the number of layers of the board, and the shape of copper trace. In general, a thick continuous piece of copper on the top layer of the PCB for SW and GND pins greatly improves the thermal performance of the part. The LT7153SP offers exposed die back on the package top for heat sink mount. This option provides the capability to improve thermal performance for the same load if an appropriately sized heat sink is mounted correctly on the package. Figure 31 shows case temperature rise of the LT7153SP on a standard 6 -layer, 2oz copper per layer PCB board (standard demo board). Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change produces the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% − (L1 + L2 + L3 + ⋯ ) where L1, L2, etc., are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, three main sources usually account for most of the losses in LT7153SP circuits: 1) I2R losses, 2) switching and biasing losses, 3) other losses. 1. I2R losses are calculated from the DC resistances of the internal switches, R SW, and external inductor, R L. In continuous mode, the average output current flows through inductor L but is chopped between the internal top and bottom power MOSFETs. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 − DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus to obtain I2R losses: I2R losses = 𝐼𝑂𝑈𝑇 2(RSW + RL)

analog.com Rev 0 25 of 31 2. The switching current is the sum of the MOSFET driver and control currents. The power MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a power MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from PVIN to ground. The resulting dQ/dt is a current out of IN that is typically much larger than the DC control bias current. In continuous mode, I GATECHG = f(QT + QB), where QT and QB are the gate charges of the internal top and botto m power MOSFETs, and f is the switching frequency. The power loss is thus: Switching Loss = IGATECHG • PVIN The gate charge loss shows up as current through the INTVcc pin as well as frequency. Thus, their effects are more pronounced in applications with higher input voltage and higher frequency. 3. Other hidden losses such as transition loss, copper trace, and internal load resistances can account for additional efficiency degradations in the overall power system. It is very important to include these system level losses in the system design. Transit ion loss arises from the brief amount of time the top power MOSFET spends in the saturated region during switch node transitions. The LT7153SP internal power devices switch quickly enough that these losses are not significant compared to other sources. Other losses including diode conduction losses during dead-time and inductor core losses, which generally account for less than 2% total additional loss. Design Example As a design example, consider the LT7153SP in an application with the following specifications: VIN = 3.3V to 5V VOUT = 0.875V IOUT(MAX) = 25A fSW = 2MHz First, to program the output to 0.875V, set R2 to be 10kΩ and R1 to be 7.5kΩ, per Figure 27. For best accuracy, use a 0.1% resistor. For a typical soft-start time of 4ms (0% to 100% of final VOUT value), the CSS should be: 10μA = CSS • 0.875V 4ms CSS = 46nF Use a typical 47nF capacitor for CSS. Because efficiency is important at both high and low load current, discontinuous mode operation is utilized. Select from the characteristic curves the correct RT resistor for the 2MHz switching frequency. Based on that, RRT should be 50kΩ. Then calculate the inductor value to achieve a current ripple that is about 40% of the maximum peak current limit (25A) at maximum VIN: L = VOUT fSW • ∆L(MAX)

• (1 − VOUT VIN(MAX) L = 0.875V 2MHz • 10A • (1 − 0.875V 5V ) = 36nH The closest standard value inductor is 36nH.

needed for loop stability. For this design, use two 100µF and two 220µF ceramic capacitors.

• Sqrt ( VIN VOUT − 1) 1 2⁄ = 9.5A Decoupling VIN with two 47µF ceramic capacitor, as shown in Figure 30, is adequate for most applications. Board Layout Considerations When laying out the printed circuit board, use the following checklist to ensure proper operation of the LT7153SP (see Figure 30). Check the following in the layout: 1. Place the capacitors CIN connect to the PVIN and GND as close as possible. These capacitors provide the AC current to the internal power MOSFETs and their drivers. 2. Are COUT and L closely connected? The (–) plate of COUT returns current to GND and the (–) plate of CIN. 3. Place the FB dividers close to the part with kelvin connections to VOUT and GND at the point of load. 4. Keep sensitive components away from the SW pin. Route the FB resistors, RT resistor, the compensation component, and the INTVcc bypass caps away from the SW trace and the inductor. 5. A ground plane is preferred. 6. Flood all unused areas on all layers with copper, which reduces the temperature rise of power components. Connect these copper areas to GND.

Figure 30. Example of Top Layer PCB Design

analog.com Rev 0 28 of 31 OUTLINE DIMENSIONS 36-Terminal Land Grid Array [LGA] (7mm x 4mm x 1.02mm) (Reference DWG # CC-36-3) DETAIL B A PACKAGE TOP VIEW PIN 1 CORNER Y X E D 11-14-2023-A PKG-008034 PACKAGE IN TRAY LOADING ORIENTATION DETAIL B SUBSTRATE MOLD CAP Z DETAIL C 0.0000 1.2500 0.7500 0.2500 0.2500 1.2500 0.7500 PACKAGE BOTTOM VIEW SEE NOTES b 0.375 e e b 0.477 0.473 0.566 0.534 5.25 2.10 DETAIL A PIN 1 NOTCH 0.25 × 45° 31 36 18 13 0.427 0.423 0.516 0.484 0.25 ±0.05 0.70 ±0.05 TRAY PIN 1 BEVEL COMPONENT PIN 1 LTXXXXXX 36× 36b e Z DETAIL C DETAIL A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. PRIMARY DATUM -Z- IS SEATING PLANE METAL FEATURES UNDER THE SOLDER MASK OPENING NOT SHOWN SO AS NOT TO OBSCURE THESE TERMINALS AND HEAT FEATURES DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN 1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE

6 CORNER SUPPORT PAD CHAMFER IS OPTIONAL

L e/2 SUGGESTED PCB LAYOUT TOP VIEW 7.50 ±0.05 4.50 ±0.05 PACKAGE OUTLINE 0.375 0.375 SYMBOL A L b D E e aaa bbb ccc ddd eee fff MIN 0.92 0.30 0.22 NOM 1.02 0.40 0.25 4.00 7.00 2.10 5.25 0.50

0.32 REF

0.70 REF

1.12 0.03 0.50 0.28 0.10 0.10 0.10 0.10 0.15 0.08 NOTES DIMENSIONS SUBSTRATE THK MOLD CAP HT 5.7 ±0.025 1.84 ±0.025

0.65 REF

1.08 REF 1.08 REF 0.0000 0.2500 0.2500 0.7500 0.7500 1.2500 1.2500 1.7500 1.7500 2.7500 2.2500 2.7500 2.2500 2× aaa Z ddd Z // bbb Z M X YZeee M Zfff M X YZccc M X YZccc 2× aaa Z 5.25 2.10

analog.com Rev 0 29 of 31 ORDERING GUIDE TAPE AND REEL (MINI) TAPE AND REEL PART MARKING FINISH CODE PAD FINISH PACKAGE TYPE MSL RATING TEMPERATURE RANGE LT7153SPAV#TRMPBF LT7153SPAV#TRPBF 7153SPV E4 Au (RoHS) LQFN (Laminate Package with QFN Footprint) 3 -40°C to 125°C

• Parts ending with PBF are RoHS and WEEE compliant.
• Pad and ball finish code is per IPC/JEDEC J-STD-609.
• Temperature grades are identified by a label on the shipping container. Contact the factory for parts specified with wider operating temperature ranges.
• TRM = 500 pieces.
• Recommended PCB Assembly and Manufacturing Procedures.
• Package and Tray Drawings.

analog.com Rev 0 30 of 31 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT7200S 18V, Quad ±5A/Quad Phase ±20A Silent Switcher®2 Step-Down Regulator 2.9V < VIN < 18V, 0.5V < VOUT < 0.9VIN, 96% Maximum Efficiency, 5mm x 6mm LQFN-48 Package LTC7150S 20V, 20A Synchronous Step-Down Regulator 3.1V < VIN < 20V, 0.6V < VOUT < 5.5V, 96% Maximum Efficiency, 5mm × 6mm BGA Package LTC3605/ LTC3605A 20V, 5A Synchronous Step-Down Regulator 4V < VIN < 20V, 0.6V < VOUT < 20V, 96% Maximum Efficiency, 4mm × 4mm QFN-24 Package LTC3613 24V, 15A Monolithic Step-Down Regulator with Differential Output Sensing 4.5V < VIN < 24V, 0.6V < VOUT < 5.5V, 0.67% Output Voltage Accuracy, Valley Current Mode, Programmable from 200kHz to 1MHz, Current Sensing, 7mm × 9mm QFN-56 Package LTC3622 17V, Dual 1A Synchronous Step-Down Regulator with Ultralow Quiescent Current 2.7V < VIN < 17V, 0.6V < VOUT < VIN, 95% Maximum Efficiency, 3mm × 4mm DFN-14 and MSOP-16 Package LTC3623 15V, ±5A Rail-to-Rail Synchronous Buck Regulator 4V ≤ VIN ≤ 15V, 96% Maximum Efficiency, 3mm × 5mm QFN Package LTC3624 17V, 2A Synchronous Step-Down Regulator with 3.5µA Quiescent Current 2.7V < VIN < 17V, 0.6V < VOUT < VIN, 95% Maximum Efficiency, 3.5µA IQ, Zero-Current Shutdown, 3mm × 3mm DFN-8 Package LTC3633A/ LTC3633A-1 Dual Channel 3A, 20V Monolithic Synchronous Step-Down Regulator 3.6V < VIN < 20V, 0.6V < VOUT < VIN, 95% Maximum Efficiency, 4mm × 5mm QFN-28 and TSSOP-28 Package LTM4639 Low VIN 20A DC/DC µModule Step- Down Regulator Complete 20A Switch Mode Power Supply, 2.375V < VIN < 7V, 0.6V < VOUT < 5.5V, 1.5% Maximum Total DC Output Voltage Error, Differential Remote Sense Amp, 15mm × 15mm BGA Package LTM4637 20A DC/DC µModule Step-Down Regulator Complete 20A Switch Mode Power Supply, 4.5V < VIN < 20V, 0.6V < VOUT < 5.5V, 1.5% Maximum Total DC Output Voltage Error, Differential Remote Sense Amp, 15mm × 15mm BGA or LTC7130 20V, 20A Monolithic Buck Converter with Ultralow DCR Sensing 4.5V < VIN < 20V, 95% Maximum Efficiency, Optimized for Low Duty Cycle Applications, 6.25mm × 7.5mm BGA Package LT8642S 18V, 10A Synchronous Step-Down Silent Switcher 2 2.8V < VIN < 18V, 0.6V < VOUT < VIN, 96% Maximum Efficiency, 4mm × 4mm 0.94mm LQFN Package

ALL INFORMATION CONTAINED HEREIN IS PROVIDED “AS IS” WITHOUT REPRESENTATION OR WARRANTY. NO RESPONSIBILITY IS ASSUMED BY ANALOG DEVICES FOR ITS USE, NOR FOR ANY INFRINGEMENTS OF PATENTS OR OTHER RIGHTS OF THIRD PARTIES THAT MAY RESULT FROM ITS USE. SPECIFICATI ONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. NO LICENCE, EITHER EXPRESSED OR IMPLIED, IS GRANTED UNDER ANY ADI PATENT RIGHT, COPYRIGHT, MASK WORK RIGHT, OR ANY OTHER ADI INTELLECTUAL PROPERTY RIGHT RELATING TO ANY COMBINATION, MACHINE, OR PROCESS, IN WHICH ADI PRODUCTS OR SERVICES ARE USED. TRADEMARKS AND REGISTERED TRADEMARKS ARE THE PROPERTY OF THEIR RESPECTIVE OWNERS. ALL ANALOG DEVICES PRODUCTS CONTAINED HEREIN ARE SUBJECT TO RELEASE AND AVAILABILITY. analog.com Rev 0 31 of 31