LT5554

LT5554 - Broadband Ultra Low Distortion 7-Bit Digitally Controlled VGA

Document overview

• Manufacturer or author: Linear Technology Corporation
• PDF pages: 32

Technical content

FREQUENCY (MHz) SFDR (dBm/Hz) 132 130 128 126 OIP3 (dBm) 50 100 150

5554 TA01b

ROUT = 50Ω TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

Distortion 7-Bit Digitally Controlled VGA The L T®5554 is a 7-bit digitally controlled programmable gain (PG) amplifi er with 16dB gain control range. It consists of a 50Ω input variable attenuator , followed by a high linearity variable transconductance amplifi er . The coarse 4dB input attenuator step is implemented via 2-bits of digital control (PG5, PG6). The fi ne transconductance amplifi er 0.125dB step within 3.875dB gain control range is set via 5-bits digital control (PG0 to PG4). The L T5554 gain control inputs (PGx) and the STROBE input can be directly coupled to TTL or ECL drivers. The seven parallel gain control inputs time skew can be eliminated by using the STROBE input positive transition. The internal output resistor R O = 400Ω limits the maxi- mum overall gain to 36dB for open outputs. The internal circuitry of open output collectors enables the L T5554 to be unconditionally stable over any loading conditions (in- cluding external SAW fi lters) and provides –80dB reverse isolation at 300MHz. The L T5554 is internally protected during overdrive and has an on-chip power supply regulator . With 0.125dB step resolution and 5ns settling time, the L T5554 is suitable in applications where continuous gain control is required. n 1GHz Bandwidth at all Gains n 48dBm OIP3 at 200MHz, 2V P-P into 50Ω, ROUT = 100Ω n –88dBc IMD3 at 200MHz, 2V P-P into 50Ω, ROUT = 100Ω n 1.4nV/√ Hz Input-Referred-Noise (RTI) n 20dBm Output P1dB at 70MHz, R OUT = 130Ω n 2dB to 18dB Gain Range (R OUT = 50Ω) n 0.125dB Gain Step Size n 30ps Group Delay Variation n 5ns Fast Gain Settling Time n 5ns Fast Overdrive Recovery n –80dB Reverse Isolation n Differential ADC Driver n IF Sampling Receivers n VGA IF Power Amplifi er n 50Ω Driver n Instrumentation L, L T , L TC and L TM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. RF INPUT LO 0.1μF 0.1μF CDEC 0.1μF IF BPF BPF ADC IF AMPLIFIER L T5554DEC IN+ VCC MODE STROBE

5554 TA01PGx GAIN CONTROL

IN–

7 BITS

OIP3 and SFDR vs Frequency

PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Supply Voltage Pin Voltages and Currents Operating Ambient Temperature Range (Notes 1, 2) 32 31 30 29 28 27 26 25 9 10 11 12 TOP VIEW UH PACKAGE 32-LEAD (5mm s 5mm) PLASTIC QFN 13 14 15 16 1GND GND DEC IN+ IN– DEC GND GND V CC ENB GND OUT OUT+ GND MODE V CC PG1 GND PG2 PG3 GND PG4 GND GND PG5 GND PG6 PG0 GND STROBE GND GND TJMAX = 150°C, θJA = 34°C/W , θJC = 3°C/W EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE L T5554IUH#PBF L T5554IUH#TRPBF 5554 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C Consult L TC Marketing for parts specifi ed with wider operating temperature ranges. Consult L TC Marketing for information on non-standard lead based fi nish parts. For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear .com/tapeandreel/

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT Dynamic Performance BW Large Signal –3dB Bandwidth All Gain Settings (Note 7) LF – 1000 MHz OP1dB Output 1dB Compression Point All Gain Settings, R OUT = 130Ω, 70MHz 20 dBm GM Amplifi er T ransconductance at GMAX FIN = 100MHz 0.15 S CMRR Common Mode Gain to Single-Ended Output FIN = 100MHz, Figure 19 –6 dB S12 Reverse Isolation F IN = 100MHz FIN = 400MHz –86 –78 dB dB Overdrive Recovery Time 5ns Input Pulse, V OUT within ±10% 5 ns Noise/Linearity Performance T wo Tones, POUT = 4dBm/Tone (2VP-P into 50Ω), Δf = 200kHz IIP3 Input Third Order Intercept Point G MAX, FIN = 200MHz GMAX –3.875dB, FIN = 200MHz dBm dBm OIP3 Output Third Order Intercept Point for Max-Gain FIN = 100MHz FIN = 200MHz dBm dBm IMD3 Intermodulation Product for Max-Gain F IN = 100MHz FIN = 200MHz –82 –84 dBc dBc OIP3 Output Third Order Intercept Point for –3.875dB STEP FIN = 100MHz FIN = 200MHz dBm dBm OIP3 Output Third Order Intercept Point G MAX, F1 = 88MHz, F2 = 112MHz GMAX –3.875dB, F1 = 88MHz, F2 = 112MHz 40.5 dBm dBm HD3 Third Harmonic Distortion Pout = 10dBm, F IN = 100MHz, GMAX –62 dBc VONOISE Output Noise Noise Spectral Density G MAX, FIN = 200MHz GMAX –3.875dB, FIN = 200MHz 10.7 7.3 nV/√Hz nV/√Hz NF Noise Figure G MAX, FIN = 200MHz GMAX –3.875dB, FIN = 200MHz 10.5 dB dB RTI Input Referred Noise Spectral Density (RMS) (Note 5) GMAX, FIN = 200MHz GMAX –3.875dB, FIN = 200MHz 1.34 1.42 nV/√Hz nV/√Hz SFDR Spurious Free Dynamic Range in 1Hz BW . GMAX, FIN = 200MHz GMAX –3.875dB, FIN = 200MHz 128 129 dBm/Hz dBm/Hz Amplifi er Voltage Gain and Gain Step G MAX Maximum Voltage and Power Gain F IN = 112MHz 15.3 17.6 19.7 dB GMIN Minimum Voltage and Power Gain F IN = 100MHz 1.725 dB GSTEP Gain Step Size (Note 9) Except For –4dB, –8dB, –12dB Steps For –4dB, –8dB, –12dB Steps 0.125 0.25 0.35 dB dB GDERROR Group Delay Step Accuracy F IN = 100MHz 10 ps AMPLIFIER I/O Differential IMPEDANCE R IN Input Resistance F IN = 100MHz, GMAX to GMAX –3.875dB FIN = 100MHz, GMAX –4dB to GMIN Ω Ω C IN Input Capacitance F IN = 100MHz 2.8 pF RO Output Resistance F IN = 100MHz 400 Ω CO Output Capacitance F IN = 100MHz 1.9 pF AC ELECTRICAL CHARACTERISTICS (R OUT = 50Ω) Specifi cations are at TA = 25°C. VCC = 5V , VCCO = 5V , ENB = 3V , MODE = 5V , STROBE = 2.2V , VIH = 2.2V , VIL = 0.6V , maximum gain (Notes 3, 6), (Test circuits shown in Figure 16), unless otherwise noted.

AC ELECTRICAL CHARACTERISTICS (R OUT = 100Ω) Specifi cations are at TA = 25°C. VCC = 5V , VCCO = 5V , ENB = 3V , MODE = 5V , STROBE = 2.2V , VIH = 2.2V , VIL = 0.6V , maximum gain (Notes 3, 8), (Test circuits shown in Figure 16), unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT Noise/Linearity Performance T wo Tones, POUT = 4dBm/Tone (2VP-P into 50Ω), Δf = 200kHz IIP3 Input Third Order Intercept Point G MAX, FIN = 200MHz GMAX –3.875dB, FIN = 200MHz dBm dBm OIP3 Output Third Order Intercept Point for Max-Gain FIN = 100MHz FIN = 200MHz dBm dBm IMD3 Intermodulation Product for Max-Gain F IN = 100MHz FIN = 200MHz –88 –88 dBc dBc VONOISE Output Noise Noise Spectral Density G MAX, FIN = 200MHz GMAX –3.875dB, FIN = 200MHz 21.4 14.5 nV/√Hz nV/√Hz NF Noise Figure G MAX, FIN = 200MHz GMAX –3.875dB, FIN = 200MHz 10.5 dB dB RTI Input Referred Noise Spectral Density (RMS) (Note 5) GMAX, FIN = 200MHz GMAX –3.875dB, FIN = 200MHz 1.34 1.42 nV/√Hz nV/√Hz SFDR Spurious Free Dynamic Range in 1Hz BW . GMAX, FIN = 200MHz 128 dBm/Hz GVMAX Maximum Voltage Gain F IN = 100MHz 23.6 dB GPMAX Maximum Power Gain F IN = 100MHz 20.6 dB SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT PGx and Strobe Timing Characteristics T SU Setup Time PGx vs STROBE 0n s THOLD Hold Time PGx vs STROBE 1n s TPW STROBE Pulse Width 2n s TR STROBE Period 4n s TLATENCY Latency Time of the Previous Gain State Output Settles within 1% 4 ns TGLITCH Time Between Previous Stable Gain State to Next Stable State Output Settles within 1% 5 ns AGLITCH Max Glitch Amplitude V IN = 0 (No Signal or STROBE T ransition During Output Signal Zero Crossing) 1m V STROBE T ransition when Output Power is at Peak + 10dBm Power 3d B AC ELECTRICAL CHARACTERISTICS (Timing Diagram) (ROUT = 50Ω) Specifi cations are at TA = 25°C. VCC = 5V , VCCO = 5V , ENB = 3V , MODE = 5V , STROBE = 3V , VIH = 2.2V , VIL = 0.6V , maximum gain (Test circuit shown in Figure 16), unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT Normal Operating Conditions V CC Supply Voltage 4.75 5 5.25 V VCCO OUT+, OUT– Output Pin DC Common Mode Voltage (Note 4) 5 6 V Shutdown DC Characteristics, ENB = 0.6V VIN(BIAS) DEC, IN+, IN– Bias Voltage 2 2.15 V IIL(PG) PGx, STR Input Current V IN = 0.6V 0 μA IIH(PG) PGx, STR Input Current V IN = 5V 210 μA IOUT OUT+, OUT– Current 20 μA ICC VCC Supply Current 4 5.1 mA Enable Input DC Characteristics VIL(EN) ENB Input LOW Voltage Disable 0.6 V VIH(EN) ENB Input HIGH Voltage Enable 3 V CC V IIL(EN) ENB Input Current V IN = 0.6V 20 μA IIH(EN) ENB Input Current V IN = 3V 70 μA IIH(EN) ENB Input Current V IN = 5V 220 300 μA DC ELECTRICAL CHARACTERISTICS Specifi cations are at T A = 25°C. VCC = 5V , VCCO = 5V , ENB = 3V , MODE = 5V , unless otherwise noted. (Note 3) (Test circuit shown in Figure 16), unless otherwise noted. Timing Diagram INPUTS STROBE INPUTS

5554 TD01

STATE (i) DATA TRANSPARENT DATA LATCH STATE (i + 1) STATE (i + 2) THOLD TPW TGLITCH AC ELECTRICAL CHARACTERISTICS (Timing Diagram)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT DEC External Capacitor Charge/Discharge CURRENT I IH(DEC) DEC Pin Source Current V DEC = 4V 27 50 70 mA IIL(DEC) DEC Pin Sink Current V DEC = 1.8V –70 –38 –14 mA Mode Input Three-State DC Characteristics V IL(MODE) MODE Input LOW Voltage for AC-Couple PGx AC-Coupled, STROBE AC-Coupled 0 0.6 V VOPEN(MODE) MODE Input OPEN PGx AC-Coupled, STROBE DC-Coupled 1.7 OPEN 2.3 V VIH(MODE) MODE Input HIGH Voltage PGx DC-Coupled, STROBE DC-Coupled V CC – 0.4 V CC V IIL(MODE) MODE Input Current V MODE = 0V –42 –31 –23 μA IIH(MODE) MODE Input Current V MODE = 5V 43 72 100 μA PGx (MODE = VCC) and STROBE (MODE = OPEN or MODE = VCC) INPUTS for DC-Coupled VIL Input LOW Voltage 0.6 V VIH Input HIGH Voltage 2.2 V IIL(DC) Input Current V IN = 0.6V 30 μA IIH(DC) Input Current V IN = 5V 125 170 220 μA PGx (MODE = 0V or MODE = OPEN) and STROBE (MODE = 0V) INPUTS for AC-Coupled VIN(AC) Input Pulse Range Instantaneous Input Voltage 0 4.6 V VIN(AC)P-P Input Pulse Amplitude Rise and Fall Time <5ns Rise and Fall Time >80ns 600 300 mVP-P mVP-P VIN(AC)MAX Maximum Input Noise Amplitude No L T5554 Gain Update 100 mV P-P IIL(AC) Input Current V IN = 0V –210 –155 –100 μA IIH(AC) Input Current V IN = 5V 310 420 530 μA Amplifi er DC Characteristics V IN(DEC) DEC G MAX 1.85 2 2.25 V VIN(BIAS) IN+, IN– Bias Voltage G MAX 1.8 2.04 2.2 V RIN INPUT Differential Resistance G MAX GMIN Ω Ω GM Amplifi er T ransconductance G MAX 0.15 S IODC OUT+, OUT– Quiescent Current V OUT = 5V 33 47 57 mA IOUT(OFFSET) Output Current Mismatch IN +, IN– Open 200 μA ICC VCC Supply Current G MAX, MODE = 0V GMIN, MODE = 0V GMAX, MODE = 5V GMIN, MODE = 5V 110 109 106 106 132 131 127 127 mA mA mA mA I CC(TOTAL) Total Supply Current I CC + 2 • IODC (GMAX) 200 mA DC ELECTRICAL CHARACTERISTICS Specifi cations are at T A = 25°C. VCC = 5V , VCCO = 5V , ENB = 3V , MODE = 5V , unless otherwise noted. (Note 3) (Test circuit shown in Figure 16), unless otherwise noted. Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND ground. Note 3: R S = RIN = 50Ω Input matching is assumed. PIN is the available input power . POUT is the power into ROUT. ROUT = RO || RLOAD is the total output resistance at amplifi er open-collectors outputs (used in GV, GP gain calculation). RO = 400Ω is L T5554 internal output impedance. RLOAD is load resistance as seen at OUT+, OUT– pins. All dBm fi gures are with respect to 50Ω. Specifi cations refer to differential inputs and differential outputs. Note 4: An external power supply equal to VCCO is used for choke inductors or center-tap transformer output interfaces. Whenever OUT+, OUT– pins are biased via resistors, the voltage drop produced by the DC- output current (IODC = 45mA typical) may require a larger output external power supply. However , care must be taken not to exceed the OUT+, OUT– absolute maximum rating when the L T5554 is disabled.

FREQUENCY (MHz) GAIN (dB) 500 900300 700

5554 G01

Note 5: RTI (Referred-To-Input) stands for the total input-referred noise voltage source. RTI is close to output noise voltage divided by voltage gain (the exact equation is given in Defi nition of Specifi cation section). The equivalent noise source e N is twice the RTI value. Note 6: The external loading at L T5554 OUT+/OUT– pins is RLOAD = 57Ω. ROUT = RLOAD || RO = 50Ω. Note 7: The IN+, IN–, DEC pins are internally biased. The time-constant of input coupling capacitor sets the low frequency corner (LF) at input. The output coupling capacitors or the transformer sets the low frequency corner (LF) at the output. The L T5554 operates internally down to DC. Note 8: The external loading at OUT+/OUT– pins is RLOAD = 133Ω. ROUT = RLOAD || RO = 100Ω. Note 9: Depending on the actual input matching conditions and frequency of operation, the L T5554 steps involving the input attenuator tap change may show less than 0.125dB change. These steps are G MAX –4dB, GMAX –8dB, GMAX –12dB, and the code is given in the Programmable Gain Table. The L T5554 monotonic operation for 0.125dB step resolution can still be obtained by skipping any such code with a gain error excedding 0.125dB. TYPICAL PERFORMANCE CHARACTERISTICS Gain vs Frequency for 0.5dB Steps, Figure 17 Differential Gain Error vs Frequency at –40°C Differential Gain Error vs Frequency at 85°C

ELECTRICAL CHARACTERISTICS

(ROUT = 50Ω) TA = 25°C. VCC = 5V , VCCO = 5V , ENB = 3V , MODE = 5V , STROBE = 3V , VIH = 2.2V , VIL = 0.6V (Test circuit shown in Figure 16), unless otherwise noted. FREQUENCY (MHz) GAIN ERROR (dB) 0.3 0.2 0.1 –0.1 –0.2

5554 G02

FREQUENCY (MHz) GAIN ERROR (dB) 0.3 0.2 0.1 –0.1 –0.2

5554 G03

Differential Gain Error vs Attenuation at 50MHz Differential Gain Error vs Attenuation at 100MHz Differential Gain Error vs Attenuation at 200MHz ATTENUATION (dB) GAIN ERROR (dB) 0.3 0.2 0.1 –0.1 –0.2

5554 G04

–16–4 –12 –8 –40°C 25°C 85°C ATTENUATION (dB) GAIN ERROR (dB) 0.3 0.2 0.1 –0.1 –0.2

5554 G05

–16–4 –12 –8 –40°C 25°C 85°C ATTENUATION (dB) GAIN ERROR (dB) 0.3 0.2 0.1 –0.1 –0.2

5554 G06

–16–4 –12 –8 –40°C 25°C 85°C

ATTENUATION (dB) GAIN ERROR (dB) 0.4 0.3 0.2 0.1 –0.1

5554 G08

–16–4 –12 –8 –40°C 25°C 85°C TYPICAL PERFORMANCE CHARACTERISTICS Integral Gain Error vs Attenuation at 50MHz Integral Gain Error vs Attenuation at 100MHz Integral Gain Error vs Attenuation at 200MHz (ROUT = 50Ω) TA = 25°C. VCC = 5V , VCCO = 5V , ENB = 3V , MODE = 5V , STROBE = 3V , VIH = 2.2V , VIL = 0.6V (Test circuit shown in Figure 16), unless otherwise noted. Maximum Gain vs Temperature P OUT vs PIN at Maximum Gain P OUT vs PIN at GMAX – 3.875dB ATTENUATION (dB) GAIN ERROR (dB) 0.4 0.3 0.2 0.1 –0.1

5554 G07

–16–4 –12 –8 –40°C 25°C 85°C ATTENUATION (dB) GAIN ERROR (dB) 0.4 0.3 0.2 0.1 –0.1

5554 G09

–16–4 –12 –8 –40°C 25°C 85°C TEMPERATURE (°C) –40 GMAX (dB) 18.0 17.8 17.6 17.4 17.2 17.0

5554 G10

8020 6004 0–20 50MHz 100MHz 200MHz PIN (dBm) –35 POUT (dBm) –16

5554 G11

15–5–15 5–25 70MHz 140MHz 200MHz PIN (dBm) –35

5554 G12

15–5–15 5–25 70MHz 140MHz 200MHz POUT (dBm) –16 T wo-Tone OIP3 vs Frequency at Max Gain, Three Temperatures T wo-Tone IMD3 vs Frequency at Max Gain, Three Temperatures IIP3 vs Frequency at Max Gain, Three Temperatures FREQUENCY (MHz) 05 0 OIP3 (dBm) 100 150

5554 G13

–40°C 85°C 25°C FREQUENCY (MHz) 0 50 100 150

5554 G14

–40°C 85°C 25°C IMD3 (dBc) –76 –79 –82 –85 –88 FREQUENCY (MHz) 0 50 100 150

5554 G15

IIP3 (dBm) –40°C 85°C 25°C (ROUT = 50Ω) TA = 25°C. VCC = 5V , VCCO = 5V , ENB = 3V , MODE = 5V , STROBE = 3V , VIH = 2.2V , VIL = 0.6V (Test circuit shown in Figure 16) POUT = 4dBm/tone (2VP-P into 50Ω), Δf = 200kHz, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS (ROUT = 50Ω) TA = 25°C. VCC = 5V , VCCO = 5V , ENB = 3V , MODE = 5V , STROBE = 3V , VIH = 2.2V , VIL = 0.6V (Test circuit shown in Figure 16) POUT = 4dBm/tone (2VP-P into 50Ω), Δf = 200kHz, unless otherwise noted. T wo-Tone OIP3 vs Frequency for GMAX and Critical Gain Steps T wo-Tone IMD3 vs Frequency for GMAX and Critical Gain Steps IIP3 vs Frequency for GMAX and GMAX –3.875dB T wo-Tone IMD3 and OIP3 vs Attenuation at 50MHz T wo-Tone IMD3 and OIP3 vs Attenuation at 70MHz FREQUENCY (MHz) OIP3 (dBm) 100 150

5554 G16

GMAX – 15.875dB GMAX – 12dB GMAX – 3.875dB GMAX FREQUENCY (MHz) IMD3 (dBc) –70 –76 –82 –88 100 150

5554 G17

GMAX – 15.875dB GMAX – 12dB GMAX – 3.875dB GMAX FREQUENCY (MHz) IIP3 (dBm) 100 150

5554 G18

GMAX – 3.875dB ATTENUATION (dB) 0 –4 –8 –12

5554 G19

–16 IMD3 OIP3 IMD3 (dBc) –70 –74 –78 –82 –86 OIP3 (dBm) ATTENUATION (dB) 0 –4 –8 –12

5554 G20

–16 IMD3 OIP3 IMD3 (dBc) –70 –74 –78 –82 –86 OIP3 (dBm) T wo-Tone IMD3 and OIP3 vs Attenuation at 100MHz ATTENUATION (dB) 0 –4 –8 –12

5554 G21

–16 IMD3 IMD3 (dBc) –70 –74 –78 –82 –86 OIP3 (dBm) OIP3 T wo-Tone IMD3 and OIP3 vs Attenuation at 140MHz ATTENUATION (dB) 0 –4 –8 –12

5554 G22

–16 IMD3 OIP3 IMD3 (dBc) –70 –74 –78 –82 –86 OIP3 (dBm)

TYPICAL PERFORMANCE CHARACTERISTICS T wo-Tone OIP3 vs Tone Power at Min-Gain T wo-Tone OIP3 vs ROUT, for GMAX OIP3 vs Frequency for GMAX and GMIN, POUT = 10dBm (ROUT = 50Ω) TA = 25°C. VCC = 5V , VCCO = 5V , ENB = 3V , MODE = 5V , STROBE = 3V , VIH = 2.2V , VIL = 0.6V (Test circuit shown in Figure 16) POUT = 4dBm/tone (2VP-P into 50Ω), Δf = 200kHz, unless otherwise noted. T wo-Tone IMD3 and OIP3 vs Attenuation at 200MHz ATTENUATION (dB) 0 –4 –8 –12

5554 G23

–16 IMD3 OIP3 IMD3 (dBc) –70 –74 –78 –82 –86 OIP3 (dBm) T wo-Tone OIP3 vs Tone Power at Max-Gain OUTPUT TONE POWER (dBm) OIP3 (dBm)

5554 G24

OUTPUT TONE POWER (dBm) OIP3 (dBm)

5554 G25

FREQUENCY (MHz) OIP3 (dBm) 100 150

5554 G29

Attenuation, 50MHz, P OUT = 10dBm, Figure 17 ATTENUATION (dB) 0 –4 –8 –12

5554 G27

–16 HD3 HD5 HARMONIC DISTORTION (dBc) –70 –75 –80 –85 –90 –100 –95 –105 T wo-Tone OIP3 vs VCCO, for GMAX OUTPUT COMMON MODE VOL TAGE (V)

5554 G28

OIP3 (dBm) 3456 25MHz 70MHz 140MHz 200MHz T wo-Tone OIP3 vs VCCO, for GMAX –3.875dB OUTPUT COMMON MODE VOL TAGE (V)

5554 G30

OIP3 (dBm) 3456 25MHz 70MHz 140MHz 200MHz ROUT (Ω)

5554 G52

OIP3 (dBm) 75 100 25MHz 70MHz 140MHz 200MHz

TYPICAL PERFORMANCE CHARACTERISTICS (ROUT = 50Ω) TA = 25°C. VCC = 5V , VCCO = 5V , ENB = 3V , MODE = 5V , STROBE = 3V , VIH = 2.2V , VIL = 0.6V (Test circuit shown in Figure 16) POUT = 4dBm/tone (2VP-P into 50Ω), Δf = 200kHz, unless otherwise noted. Noise Figure vs Attenuation, 140MHz Input Referred Noise vs Attenuation, 140MHz Output Noise Density vs Attenuation, 140MHz Noise Figure vs Frequency Single-Ended Output NF vs Frequency, Figure 18 HD3 and HD5 vs POUT for GMAX, Figure 17 HD3 vs Frequency for GMAX and GMIN, POUT = 10dBm, Figure 17 HD5 vs Frequency for GMAX and GMIN, POUT = 10dBm, Figure 17 HARMONIC DISTORTION (dBc) –50 –68 –80 –62 –74 –56 FREQUENCY (MHz) 50 100 150

5554 G31

HARMONIC DISTORTION (dBc) –70 –88 –100 –82 –94 –76 FREQUENCY (MHz) 50 100 150

5554 G32

OUTPUT POWER (dBm) HARMONIC DISTORTION (dBc) –40 –60 –75 –80 –70 –65 –55 –50 –45 10 13

5554 G33

FREQUENCY (MHz)

5554 G34

NF (dB) 200 400 600 800 GMAX GMAX –3.875 GMAX GMAX –3.875 FREQUENCY (MHz) 0 200 400 600

5554 G35

NF (dB) ATTENUATION (dB) NF (dB)

5554 G36

–16–4 –12 –8 ATTENUATION (dB) RTI (nV/√Hz)

5554 G37

–16–4 –12 –8 ATTENUATION (dB) VONOISE (nV/√Hz)

5554 G38

–16–4 –12 –8 (ROUT = 50Ω) TA = 25°C. VCC = 5V , VCCO = 5V , ENB = 3V , MODE = 5V , STROBE = 3V , VIH = 2.2V , VIL = 0.6V (Test circuit shown in Figure 16), maximum gain, unless otherwise noted.

ATTENUATION (dB) VIN(BIAS) (V) 2.2 2.1 2.0

5554 G42

–16–4 –12 –8 –40°C 85°C 25°C ATTENUATION (dB) CURRENT (mA) 215 208 200 185 193

5554 G40

–16–4 –12 –8 –40°C 85°C 25°C TYPICAL PERFORMANCE CHARACTERISTICS Single-Ended Output Current vs Attenuation Total ICC Current vs Attenuation ICC Shutdown Current vs VCC, ENB = 0.6V ( ROUT = 50Ω) TA = 25°C. VCC = 5V , VCCO = 5V , ENB = 3V , MODE = 5V , STROBE = 3V , VIH = 2.2V , VIL = 0.6V (Test circuit shown in Figure 16), maximum gain, unless otherwise noted. VIN(BIAS) vs Attenuation ATTENUATION (dB) CURRENT (mA)

5554 G39

–16–4 –12 –8 –40°C 85°C 25°C VCC (V) 4.7 CURRENT (mA)

5554 G41

5.54.9 5.3 5.1 –40°C 85°C 25°C

GND (Pins 1, 2, 7, 8, 10, 13, 15, 16, 19, 22, 25, 26, 28, 31): Ground Pins. DEC (Pins 3, 6): Decoupling Pin for the Internal DC Bias Voltage for the Differential Inputs, IN+ and IN–. It is also connected to the ‘virtual ground’ of the input resistive attenuator . Capacitive de-coupling to ground is recom- mended in order to preserve linearity performance when IN +, IN– inputs are driven with up to 3dB imbalance. IN+ (Pin 4): Positive Signal Input Pin with Internal DC Bias to 2V . IN– (Pin 5): Negative Signal Input Pin with Internal DC Bias to 2V . PG5 (Pin 9): 4dB Step Amplifi er Programmable Gain Con- trol Input Pin. Input levels are controlled by MODE pin. PG6 (Pin 11): 8dB Step Amplifi er Programmable Gain Control Input Pin. Input levels are controlled by the MODE pin. PG0 (Pin 12): 0.125dB Step Amplifi er Programmable Gain Control Input Pin. Input levels are controlled by MODE pin. STROBE (Pin 14): Strobe Pin for the Programmable Gain Control Inputs (PGx). With STROBE in Low-state, the Amplifi er Gain is not changed by PGx state changes (latch mode). With STROBE in High-state, the Amplifi er Gain is asynchronously set by PGx inputs transitions (transpar- ent-mode). A positive STROBE transition updates the PGx state. Low-state and High-state depends on MODE pin level (Table1). V CC (Pins 17, 24): Power Supply Pins. These pins are internally connected together . MODE (Pin 18): PGx and STROBE Functionality and Level Control Pin. When MODE is higher than V CC – 0.4V , the PGx and STROBE are DC-coupled. When the MODE pin is lower than 0.6V , the PGx and STROBE are AC-coupled. 2dB-Step Response (PG4) 120MHz Signal 8dB-Step Response (PG6) 120MHz Signal 8dB-Step Response (PG6) 120MHz Pulse Signal TYPICAL PERFORMANCE CHARACTERISTICS (ROUT = 50Ω) TA = 25°C. VCC = 5V , VCCO = 5V , ENB = 3V , MODE = 5V , STROBE = 3V , VIH = 2.2V , VIL = 0.6V (Test circuit shown in Figure 16), maximum gain, unless otherwise noted. 8dB-Step (PG6) 120MHz Pulse Signal for 8dB Overdrive 8dB-Step (PG6) 120MHz Sinusoidal Signal for 2dB Overdrive 8dB-Step (PG6) 120MHz Sinusoidal Signal for 8dB Overdrive MODE = HIGH 1V/DIV

5554 G49

MODE = HIGH 1V/DIV

5554 G50

MODE = HIGH 1V/DIV

5554 G51

MODE = HIGH 0.1V/DIV

5554 G46

MODE = HIGH 0.1V/DIV

5554 G47

MODE = HIGH 0.2V/DIV

5554 G48

couple and the STROBE input is DC-coupled. sets a Low-state (for PGx and STROBE inputs). mended to conduct the DC quiescent current. mended to conduct the DC quiescent current. input voltage is higher than 3V , the amplifi er is turned on. the amplifi er is turned off. trol Input Pin. Input levels are controlled by MODE pin. trol Input Pin. Input levels are controlled by MODE pin. trol Input Pin. Input levels are controlled by MODE pin. Figure 1. Functional Block Diagram

FUNCTIONAL CHARACTERISTICS Programmable Gain Table STATE PG0 PG1 PG2 PG3 PG4 PG5 PG6 ATTENUATION Step Relative to Max Gain GAIN STATE NAME N Step Size in dB dB 0.125 0.25 0.5 1 2 4 8 (N – 127) • 0.125dB 1 2 7HHHHHHH 0.00dB G MAX (Max Gain) 1 2 6 LHHHHHH –0.125dB G MAX –0.125dB 1 2 5HLHHHHH –0.250dB G MAX –0.25dB 1 2 4 LLHHHHH –0.375dB G MAX –0.375dB 123 H H L H H H H –0.500dB G MAX –0.5dB 122 L H L H H H H –0.625dB G MAX –0.625dB 121 H L L H H H H –0.750dB G MAX –0.75dB 120 L L L H H H H –0.875dB 119 H H H L H H H –1.00dB G MAX –1dB 118 L H H L H H H –1.125dB G MAX –1.125dB 112 L L L L H H H –1.875dB G MAX –1.875dB 111 H H H H L H H –2.00dB G MAX –2dB 104 L L L H L H H –2.875dB G MAX –2.875dB 103 H H H L L H H –3.00dB G MAX –3dB 96 L L L L L H H –3.875dB G MAX –3.875dB 95 H H H H H L H –4.00dB G MAX –4dB 64 L L L L L L H –7.875dB G MAX –7.875dB 6 3 HHHHHHL –8.00dB G MAX –8dB 32 L L L L L H L –11.875dB G MAX –11.875dB 3 1 HHHHHLL –12.000dB G MAX –12dB 8 L L L H L L L –14.875dB G MAX –14.875dB 7 HHHLLLL –15.000dB G MAX –15dB 6 LHHLLLL –15.125dB G MAX –15.125dB 5 HLHLLLL –15.250dB G MAX –15.25dB 4 LLHLLLL –15.375dB G MAX –15.375dB 3 HHLLLLL –15.500dB G MAX –15.5dB 2 L H L L L L L –15.625dB G MAX –15.625dB 1 H L L L L L L –15.750dB G MAX –15.75dB 0 LLLLLLL –15.875dB G MIN (Min Gain)

Figure 2. Output Equivalent Circuit and Impedance Defi nitions

5554 F02

The L T5554 is a high dynamic range programmable-gain amplifi er . It consists of the following sections:

• An input variable attenuator with 50Ω input imped- ance (four 4dB steps, controlled by PG5, PG6 inputs)
• A differential programmable transconductance ampli- fi er (32 steps, 0.125dB each controlled by PG0, PG1, PG2, PG3, PG4 inputs)
• Programmable logic blocks
• Internal bias (voltage regulators)
• Enable/disable circuit
• Overdrive protection circuit Noise Defi nitions for 50Ω Matched Input e RS Source resistor RMS noise voltage: ek T R f o r R e nV Hz RS S S RS 2 45 0
• •• ; , Ω eN Equivalent short-circuit input RMS noise voltage source iN Equivalent open-circuit input RMS noise current source vN Equivalent total input RMS noise voltage source: v N2 = eN2 + iN2 • RS2 (RS = 50Ω) RTI Referred-to-input L T5554 noise voltage: RTI = ( e +e +i •R ) = v RS N N S N VONOISE L T5554 output noise voltage: V= R T I + e 2 •1 0ONOISE 2 RS 2 GV 220 NF Noise fi gure in dB according to any of the fol- lowing equations: NF ei R e NN S RS +()⎛ ⎟ = 10 1 10 1 22 2 2log log VV e RTI e N RS RS 210 1 ⎟ = + log Linearity Defi nitions for 50Ω Matched Input IMD3[dBc] Third-order intermodulation product (negative value) IIP3[dBm] IIP3 = P (per-tone) – IMD3 2IN SFDR[dBm/Hz] SFDR = 2 3 • 1 7 4+I I P 3–N F⎛ ⎠⎟ () OIP3[dBm] OIP P IMD IIP GOUT P3 3 2 3== + – APPLICATIONS INFORMATION DEFINITION OF SPECIFICATIONS Since no internal feedback network is used between ampli- fi er outputs and inputs, the L T5554 is able to offer:
• Unconditional stability for I/O reactive loading such as fi lters (no isolation output resistors required)
• High reverse isolation The L T5554 is a class-A transconductance amplifi er . An input signal voltage is fi rst converted to an output cur- rent via the L T5554 internal G M. And then, the output load (ROUT) converts the output current into an output voltage. ROUT sets the L T5554 gain and output noise fl oor . However , the SFDR performance is almost independent of ROUT for values of 25Ω to 100Ω.

range of user control interfaces. The L T5554 has internal overdrive protection circuitry. an input imbalance is less than 2dB. +, IN– inputs are imbalanced by 3dB. circuitry when DC input coupling is desired. examples are shown in Figures 5 and 6. Figure 3. Input Capacitively-Coupled to a Differential Source Figure 4. Input T ransformer-Coupled to Single-Ended Source Figure 5. Differential Output Interface Figure 6. Single-Ended Matched Output Interface

5554 F04

5554 F03

5554 F06

with about 30mA sourcing or sinking current capability.

5554 F05

shown in Figure 6 and Figure 16. when outputs OUT+, OUT– are open. and voltage limiting for maximum output power . (for ECL or low-voltage CMOS interfaces). STROBE transition (PGx latch control in strobed-mode). Figure 7. Maximum Voltage and Power Gain vs ROUT

5554 F07

8 and 9) depending on MODE input choice (Table1). transition rather than signal level. this amplifi er output glitch. circuit without external components. set the transparent-mode with all PGx inputs low. Figure 8. DC-Coupled PGx and STROBE Equivalent Inputs Figure 9. AC-Coupled PGx and STROBE Equivalent Inputs

5554 F08

5554 F09

RSADC = 50Ω is shown in Figures 10 through 13.

5554 F10

Figure 10. Noise, 140MHz, ROUT = 50Ω

5554 F12

Figure 12. Linearity, 70MHz, ROUT = 50Ω, 4dBm/Tone

5554 F11

Figure 11. Noise, 140MHz, ROUT = 50Ω Figure 13. Linearity, 140MHz, ROUT = 50Ω, 4dBm/Tone

pattern repeats for each 4dB gain step change. impact on the HD2 performance. when the output power is 10dBm at 140MHz. imbalance as shown in Figure 15. output interfaces to the L T5554 part are recommended. Figure 15. Not Recommended Single-Ended Input and Output Figure 14. Recommended Single-Ended Input and Output

5554 F14

5554 F15

Figure 16. Single-Ended T ransformer Test Board (Simplifi ed Schematic)

5554 F16

feedback). The evaluation board layout is a good example. soldered to PCB ground plane for thermal considerations. L T5554 internal, and part on board R5 and R6). Table 3. T ransformer Board ROUT Options

Figure 17. Single Ended Test Board (Simplifi ed Schematic) dependent) has been included in characterization. CCO for 5V on L T5554 outputs. Table 4. Balun Board ROUT Options

• • 1:1 ETC1-1-13 IN+ IN– 1μF L T5554 1, 3, 5, 7 9

5554 F17

Figure 18. Wideband Differential Output Test Board (Simplifi ed Schematic) formed with input circuit shown in Figure 19. Figure 19. Common Mode Input Interface to PG6 turret will set the PG6 DC-voltage in 0V to 5V range. plied at J7 connector as shown in Figure 20. tors shown in Figure 21, other PGx inputs can be evaluated.

5554 F18

5554 F19

Figure 20. Timing Test for PG6 and STROBE (Simplifi ed Schematic)

1 GND

2 GND

3 DEC

4 IN+

5 IN–

6 DEC

7 GND

8 GND

5554 F20

5554 F21

Figure 21. Evaluation Circuit Schematic

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION 32-Lead Plastic QFN (5mm × 5mm) (Reference L TC DWG # 05-08-1693 Rev D) 5.00 ± 0.10 (4 SIDES) NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (NOTE 6) 0.40 ± 0.10 BOTTOM VIEW—EXPOSED PAD

3.50 REF

(4-SIDES) 3.45 ± 0.10 3.45 ± 0.10 0.75 ± 0.05 R = 0.115 TYP 0.25 ± 0.05 (UH32) QFN 0406 REV D

0.50 BSC

0.200 REF

0.00 – 0.05 0.70 ±0.05 (4 SIDES) 4.10 ±0.05 5.50 ±0.05 0.25 ± 0.05 PACKAGE OUTLINE RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER R = 0.05 TYP 3.45 ± 0.05 3.45 ± 0.05

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com © LINEAR TECHNOLOGY CORPORATION 2008 LT 0708 • PRINTED IN USA RELATED PARTS PART NUMBER DESCRIPTION COMMENTS Infrastructure L T5514 Ultralow Distortion, IF Amplifi er/ADC Driver with Digitally Controlled Gain 850MHz Bandwidth, 47 dBm OIP3 at 100MHz, 10.5dB to 33dB Gain Control Range L T5517 40MHz to 900MHz Quadrature Demodulator 21dBm IIP3, Integrated LO Quadrature Generator L T5518 1.5GHz to 2.4GHz High Linearity Direct Quadrature Modulator 22.8dBm OIP3 at 2GHz, –158.2dBm/Hz Noise Floor , 50Ω Single-Ended RF and LO Ports, 4-Channel W-CDMA ACPR = –64dBc at 2.14GHz L T5519 0.7GHz to 1.4GHz High Linearity Upconverting Mixer 17.1dBm IIP3 at 1GHz, Integrated RF Output T ransformer with 50Ω Matchin g, Single-Ended LO and RF Ports Operation L T5520 1.3GHz to 2.3GHz High Linearity Upconverting Mixer 15.9dBm IIP3 at 1.9GHz, Integrated RF Output T ransformer with 50Ω Match ing, Single-Ended LO and RF Ports Operation Port Operation L T5522 600 MHz to 2.7GHz High Signal Level Downconverting Mixer 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 50Ω Single-Ended RF and LO Ports L T5524 Low Power , Low Distortion ADC Driver with Digitally Programmable Gain 450MHz Bandwidth, 40dBm OIP3, 4.5dB to 27dB Gain Control L T5525 High Linearity, Low Power Downconverting Mixer Single-Ended 50Ω RF and LO Ports, 17.6dBm IIP3 at 1900MHz, I CC = 28A L T5526 High Linearity, Low Power Downconverting Mixer 3V to 5.3V Supply, 16.5dBm IIP3, 100kHz to 2GHz RF , NF = 11dB, ICC = 28mA, –65dBm LO-RF Leakage L T5527 400MHz to 3.7GHz High Signal Level Downconverting Mixer IIP3 = 23.5dBm and NF = 12.5dBm at 1900MHz, 4.5V to 5.25V Supply, ICC = 78mA, Conversion Gain = 2dB L T5528 1.5GHz to 2.4GHz High Linearity Direct Quadrature Modulator 21.8dBm OIP3 at 2GHz, –159.3dBm/Hz Noise Floor , 50Ω, 0.5VDC Baseband Interface, 4-Channel W-CDMA ACPR = –66dBc at 2.14GHz L T5557 400MHz to 3.8GHz, 3.3V High Signal Level Downconverting Mixer IIP3 = 23.7dBm at 2600MHz, 23.5dBm at 3600MHz, ICC = 82A at 3.3V L T5560 Ultra-Low Power Active Mixer 10mA S upply Current, 10dBm IIP3, 10dB NF , Usable as Up- or Down-Converter. L T5568 700MHz to 1050MHz High Linearity Direct Quadrature Modulator 22.9dBm OIP3 at 850MHz, –160.3dBm/Hz Noise Floor , 50Ω, 0.5VDC Baseband Interface, 3-Ch CDMA2000 ACPR = –71.4dBc at 850MHz L T5572 1.5GHz to 2.5GHz High Linearity Direct Quadrature Modulator 21.6dBm OIP3 at 2GHz, –158.6dBm/Hz Noise Floor , High-Ohmic 0.5VDC Baseband Interface, 4-Ch W-CDMA ACPR = –67.7dBc at 2.14GHz L T5575 800MHz to 2.7GHz High Linearity Direct Conversion I/Q Demodulator 50Ω, Single-Ended RF and LO Inputs. 28dBm IIP3 at 900MHz, 13.2dBm P1dB, 0.04dB I/Q Gain Mismatch, 0.4° I/Q Phase Mismatch LO Leakage RF Power Detectors LT C 5505 RF Power Detectors with >40dB Dynamic Range 300MHz to 3GHz, Temperature Compensated, 2.7V to 6V Supply L TC5507 100kHz to 1000MHz RF Power Detector 100kHz to 1GHz, Temperature Compensated, 2.7 to 6V Supply L TC5508 300MHz to 7GHz RF Power Detector 44dB Dynamic Range, Temperature Compensated, SC70 Package L TC5509 300MHz to 3GHz RF Power Detector 36dB Dynamic Range, Low Power Consumption, SC70 Package L TC5530 300MHz to 7GHz Precision RF Power Detector Precision V OUT Offset Control, Shutdown, Adjustable Gain L TC5531 300MHz to 7GHz Precision RF Power Detector Precision V OUT Offset Control, Shutdown, Adjustable Offset L TC5532 300MHz to 7GHz Precision RF Power Detector Precision V OUT Offset Control, Adjustable Gain and Offset L T5534 50MHz to 3GHz Log RF Power Detector with 60dB Dynamic Range ±1dB Output Variation over Temperature, 38ns Response Time, Log Linear Response L TC5536 Precision 600Mhz to 7GHz RF Power Detector with Fast Comparator Output 25ns Response Time, Comparator Reference Input, Latch Enable Input, –26dBm to 12dBm Input Range L T5537 Wide Dynamic Range Log RF/IF Detector Low Frequency to 1GHz, 83dB Log Linear Dynamic Range L T5538 3.8GHz Wide Dynamic Range Log Detector 75dB Dynamic Range, ±1dB Output Variation Over Temperature L T5570 2.7GHz RMS Power Detector Fast Responding, up to 60dB Dynamic Range, ±0.3dB Accuracy Over Temperature