LT5524EFE

LT5524 AD | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 16

Technical content

FREQUENCY (MHz) OIP3 (dBm) 200

5524 TA02

1.5dB ATTENUATION STEP MAX GAIN Low Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain ■ Output IP3 at 100MHz: 40dBm ■ Maximum Output Power: 16dBm ■ Bandwidth: LF to 540MHz ■ Propagation Delay: 0.8ns ■ Maximum Gain: 27dB ■ Gain Control Range: 22.5dB ■ Gain Control Step: 1.5dB ■ Gain Control Settling Time: 500ns ■ Noise Figure: 8.6dB at 100MHz (Max Gain) ■ Output Noise Floor: –138dBm/Hz (Max Gain) ■ Reverse Isolation: –92dB ■ Single Supply: 4.75V to 5.25V ■ Shutdown Mode ■ Enable/Disable Time: 1µs ■ Differential I/O Interface ■ 20-Lead TSSOP Package ■ High Linearity ADC Driver ■ IF Sampling Receivers ■ VGA IF Power Amplifier ■ 50Ω Driver ■ Instrumentation Applications , LTC and LT are registered trademarks of Linear Technology Corporation. DESCRIPTIO UFEATURES APPLICATIO SU The LT 5524 is a programmable gain amplifier (PGA) with bandwidth extending from low frequency (LF) to 540MHz. It consists of a digitally controlled variable attenuator, followed by a high linearity amplifier. Four parallel digital inputs control the gain over a 22.5dB range with 1.5dB step resolution. An on-chip power supply regulator/filter helps isolate the amplifier signal path from external noise sources. The LT5524’s open-loop architecture offers stable opera- tion for any practical load conditions, including peaking- free AC response when driving capacitive loads, and excellent reverse isolation. The LT5524 may be operated broadband, where the out- put differential RC time constant sets the bandwidth, or it may be used as a narrowband driver with the appropriate output filter. TYPICAL APPLICATIO U LT5524 ADC 0.1µF 0.1 µF 100Ω CHOKE GAIN CONTROL CHOKE 0.1µF

5524 TA01

0.1µF IF AMP IF BPF LO RF INPUT

4 LINES

Output IP3 vs Frequency, ROUT = 200Ω Patents Pending.

(Notes 1, 2) Operating Ambient Temperature Range .. – 40°C to 85°C LT5524EFE TJMAX = 150°C, θJA = 38°C/W EXPOSED PAD (PIN 21) IS GND MUST BE SOLDERED TO PCB ABSOLUTE MAXIMUM RATINGSW WW U PACKAGE/ORDER INFORMATIONW UU Consult LTC Marketing for parts specified with wider operating temperature ranges. TOP VIEW EN V CC1 GND GND IN IN– GND GND PGA0 PGA1 NC V CC2 GND GND OUT OUT+ GND GND PGA3 PGA2 FE PACKAGE 20-LEAD PLASTIC TSSOP ATTENUATION STEP RELATIVE TO MAX GAIN PGA0 PGA1 PGA2 PGA3 POWER GAIN* 1 0dB High High High High 27.0dB 2 –1.5dB Low High High High 25.5dB 3 –3.0dB High Low High High 24.0dB 4 –4.5dB Low Low High High 22.5dB 5 –6.0dB High High Low High 21.0dB 6 –7.5dB Low High Low High 19.5dB 7 –9.0dB High Low Low High 18.0dB 8 –10.5dB Low Low Low High 16.5dB 9 –12.0dB High High High Low 15.0dB 10 –13.5dB Low High High Low 13.5dB 11 –15.0dB High Low High Low 12.0dB 12 –16.5dB Low Low High Low 10.5dB 13 –18.0dB High High Low Low 9.0dB 14 –19.5dB Low High Low Low 7.5dB 15 –21.0dB High Low Low Low 6.0dB 16 –22.5dB Low Low Low Low 4.5dB (Note 3) *ROUT = 200Ω PROGRA ABLE GAI SETTI GS U UWW

VCC = 5V, VCCO = 5V, EN = 3V, TA = 25°C, unless otherwise noted. (Note 7) (Test circuits shown in Figures 9 and 10) DC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Normal Operating Conditions VCC Supply Voltage (Pins 2, 19) (Note 4) 4.75 5 5.25 V VCCO OUT+, OUT– Output Pin DC Common Mode Voltage OUT +, OUT– Connected to VOSUP via 3 5 5.5 V Choke Inductors or Resistors (Note 5) Shutdown DC Characteristics, EN = 0.6V VIN(BIAS) IN+, IN– Bias Voltage Max Gain (Note 6) 1.15 1.3 1.5 V IIL(PGA) PGAO, PGA1, PGA2, PGA3 Input Current V IN = 0.6V 20 µA IIH(PGA) PGAO, PGA1, PGA2, PGA3 Input Current V IN = 5V 20 µA IOUT OUT+, OUT– Current All Gain Settings 20 µA ICC VCC Supply Current All Gain Settings (Note 4) 44 100 µA Enable and PGA Inputs DC Characteristics VIL EN and PGAx Input Low Voltage x = 0, 1, 2, 3 0.6 V VIH EN and PGAx Input High Voltage x = 0, 1, 2, 3 3 V IIL(PGA) PGAO, PGA1, PGA2, PGA3 Input Current V IN = 0.6V 20 µA IIH(PGA) PGAO, PGA1, PGA2, PGA3 Input Current V IN = 3V and 5V 15 30 µA IIL(EN) EN Input Current V IN = 0.6V 4 20 µA IIH(EN) EN Input Current V IN = 3V 18 µA VIN = 5V 38 100 µA DC Characteristics, EN = 3V VIN(BIAS) IN+, IN– Bias Voltage Max Gain (Note 6) 1.34 1.48 1.65 V RIN Input Differential Resistance All Gain Settings (DC) 122 Ω gm Amplifier Transconductance Max Gain 0.15 S IOUT OUT+, OUT– Quiescent Current All Gain Settings, V OUT = 5V 17 20 24 mA IOUT(OFFSET) Output Current Mismatch All Gain Settings, IN +, IN– Open 100 µA ICC VCC1 + VCC2 Supply Current Max Gain (Note 4) 34 40 mA Min Gain (Note 4) 36 43 mA ICC(TOTAL) Total Supply Current I CC + 2 • IOUT (Max Gain) 75 91 mA

VCC = 5V, VCCO = 5V, EN = 3V, TA = 25°C, ROUT = 200Ω. Maximum gain specifications are with respect to differential inputs and differential outputs, unless otherwise noted. (Note 7) (Test circuits shown in Figures 9 and 10) AC ELECTRICAL CHARACTERISTICS Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All voltage values are with respect to ground. Note 3: Default state for open PGA inputs. Note 4: VCC1 and VCC2 (Pins 2 and 19) are internally connected. Note 5: External VOSUP is adjusted such that VCCO output pin common mode voltage is as specified when resistors are used. For choke inductors or transformer, VOSUP = VCCO = 5V typ. Note 6: Internally generated common mode input bias voltage requires capacitive or transformer coupling to the signal source. Note 7: Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Gain always refers to power gain. Input matching is assumed. P IN is the available input power. POUT is the power into the external load, ROUT, as seen by the LT5524 differential outputs. All dBm figures are with respect to 50Ω. Note 8: High frequency operation is limited by the RC time constants at the input and output ports. The low frequency (LF) roll-off is set by I/O interface choice. Note 9: Limited by package and board isolation. Note 10: See “Clipping Free Operation” in the Applications Information section. Refer to Figure 7. Note 11: Although the instantaneous AC voltage on the OUT + or OUT– pins may in some situations safely exceed 8V (with respect to ground), in no case should the DC voltage on these pins be allowed to exceed the ABSMAX tested limit of 7V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Dynamic Performance BW Large-Signal –3dB Bandwidth All Gain Settings (Note 8), R OUT = 100Ω LF to 540 MHz VOUT(CLIP) Output Voltage Clipping Levels Each OUT +, OUT– with Respect to Ground 2 8 V (Note 11) POUT(MAX) Clipping Limited Maximum Sinusoidal All Gain Settings, Single Tone, 16 dBm Output Power f IN = 100MHz (Note 10) gm Amplifier Transconductance Max Gain, f IN = 100MHz 0.15 S S12 Reverse Isolation f IN = 100MHz (Note 9) –92 dB Distortion and Noise OIP3 Output Third Order Intercept Point for P OUT = 4dBm (Each Tone), 200kHz Tone Spacing, PGA0 = High (PGA1, PGA2, PGA3 Any State) f IN = 100MHz +40 dBm Output Third Order Intercept Point for P OUT = 4dBm (Each Tone), 200kHz Tone Spacing, PGA0 = Low (PGA1, PGA2, PGA3 Any State) f IN = 100MHz +36 dBm HD2 Second Harmonic Distortion P OUT = 5dBm (Single Tone), fIN = 50MHz –76 dBc HD3 Third Harmonic Distortion P OUT = 5dBm (Single Tone), fIN = 50MHz –72 dBc NFLOOR Output Noise Floor PGA1 = High, f IN = 100MHz –138 dBm/Hz (PGAO, PGA2, PGA3 Any State) PGA1 = Low, f IN = 100MHz –140 dBm/Hz NF Noise Figure Max Gain Setting, f IN = 100MHz 8.6 dB PGA Settling Time Output Settles within 10% of Final Value 500 ns Enable/Disable Time Output Settles within 10% of Final Value 600 ns Amplifier Power Gain and Gain Step GMAX Maximum Gain f IN = 20MHz and 200MHz 27 dB GMIN Minimum Gain f IN = 20MHz and 200MHz 4.5 dB GSTEP Gain Step Size f IN = 20MHz and 200MHz 0.8 1.5 2.2 dB Gain Step Accuracy f IN = 20MHz and 200MHz ±0.2 dB Amplifier I/O Impedance (Parallel Values, Specified Differentially) RIN Input Resistance f IN = 100MHz 122 Ω CIN Input Capacitance f IN = 100MHz 2 pF RO Output Resistance f IN = 100MHz 5 k Ω CO Output Capacitance f IN = 100MHz 1.7 pF

TYPICAL PERFOR A CE CHARACTERISTICS UW Frequency Response for All Gain Steps, ROUT = 200Ω TA = 25°C, VCC = 5V, VCCO = 5V, EN = 3V, control input levels VIL = 0.6V, VIH = 3V unless otherwise noted. (Test circuit shown in Figure 9) Gain Error vs Attenuation Step at 25MHz, ROUT = 200Ω Gain Error vs Attenuation Step at 100MHz, ROUT = 200Ω FREQUENCY (MHz) POWER GAIN (dB) 100 1000

5524 G01

ATTENUATION STEP (dB) GAIN ERROR (dB) 0.2 0.4 0.6

5524 G02

–0.2 –0.8 369 12 15 18 0.8 –0.4 –0.6 25°C –40°C 85°C ATTENUATION STEP (dB) GAIN ERROR (dB) 0.2 0.4 0.6

5524 G03

–0.2 –0.8 369 12 15 18 0.8 –0.4 –0.6 25°C –40°C 85°C PIN (dBm) –31 POUT (dBm) –25 –19 –13 –7

5524 G06

–28 –22 –16 –10 ROUT = 200Ω POUT vs PIN at 50MHz, Max Gain Minimum Gain vs VCC at 120MHz, ROUT = 200Ω VCC (V) 4.5 5.0 5.2 5.4 5.3

5524 G04

4.8 4.6 4.7 4.9 5.1 5.5 4.4 4.2 4.0 GAIN (dB) 25°C 85°C –40°C Maximum Gain vs VCC at 120MHz, ROUT = 200Ω VCC (V) 4.5 27.2 27.4 27.6 5.3

5524 G05

27.0 26.8 4.7 4.9 5.1 5.5 26.6 26.4

26.2 GAIN (dB)

25°C 85°C –40°C Harmonic Distortion vs POUT at 50MHz, Max Gain, ROUT = 200Ω OIP3 vs Frequency at Pin = –23dBm, Max Gain and 1.5dB Attenuation Step, ROUT = 200Ω FREQUENCY (MHz) OIP3 (dBm) 200

5524 G07

1.5dB ATTENUATION STEP MAX GAIN POUT (dBm) HD(dBc) –80 –50 –45 –40 0 6 9

5524 G08

–90 –60 –70 –85 –55 –100 –95 –65 –75 –3 3 12 15 HD2HD3 HD4HD5

ICC Shutdown Current vs VCC, EN = 0.6V TYPICAL PERFOR A CE CHARACTERISTICS UW Two tones, 200kHz spacing, TA = 25°C, EN = 3V, VCC = 5V, VCCO = 5V, control input levels VIL = 0.6V, VIH = 3V unless otherwise noted. (Test circuit shown in Figure 10) INPUT VCC (V) 4.5 25°C 85°C –40°C 5.3

5524 G16

4.7 4.9 5.1 5.5 CURRENT (µA) Total ICC vs Attenuation Step Single-Ended Output Current vs Attenuation Step V IN(BIAS) vs Attenuation Step Noise Figure vs Frequency FREQUENCY (MHz) 7.0 NF (dB) 7.5 8.0 8.5 9.0 100 200 300 400

5524 G09

9.5 10.0 50 150 250 350 MAX GAIN 1.5dB ATTENUATION STEP (PGA0 = LOW) 3dB ATTENUATION STEP (PGA1 = LOW) NF vs Attenuation Step at Freq = 100MHz ATTENUATION STEP (dB) NF (dB)

5524 G10

Output Noise Floor vs Attenuation Step, Freq = 100MHz, ROUT = 200Ω ATTENUATION STEP (dB) –142 NOISE FLOOR (dBm/Hz) –141 –140 –139 –138 –136 3 69 1 2

5524 G11

–137 PGA1 = HIGH PGA1 = LOW Pulse Response vs Output Level at Max Gain. Indicated Voltage Levels are into 50Ω External Load 2ns/DIV 5524 G12 2VP-P 1.5VP-P 1VP-P INPUTS COUT = 0.82pF ATTENUATION STEP (dB) CURRENT (mA) 3 69 1 2

5524 G15

78 85°C 25°C –40°C ATTENUATION STEP (dB)

19.0 CURRENT (mA)

20.0 19.5 20.5 21.0 3 69 1 2

5524 G13

85°C 25°C –40°C ATTENUATION STEP (dB)

1.40 VIN(BIAS) (V)

1.50 1.45 1.55 1.60 3 69 1 2

5524 G14

85°C 25°C –40°C

for example) may be required in some applications. pin is internally pulled to ground if not connected. pin is internally pulled to ground if not connected. pin is internally pulled to ground if not connected. pin is internally pulled to ground if not connected. mended to source the DC quiescent current. mended to source the DC quiescent current.

5524 F01

Figure 1. Functional Block Diagram

• An input variable attenuator “gain-control” block with 122Ω input impedance
• A differential transconductance amplifier, with enable input
• An internal bias block with internal voltage regulator
• A gain control logic block The LT5524 amplifier provides amplification with very low distortion using a linearized open-loop architecture. In contrast with high linearity amplifiers employing negative feedback, the LT5524 offers:
• Stable operation for any practical load
• A capacitive output reactance (not inductive) that pro- vides peaking free AC response to capacitive loads
• Exceptional reverse isolation of –100dB at 50MHz and –78dB at 300MHz (package and board leakage limited) The LT5524 is a transconductance amplifier and its opera- tion can be understood conceptually as consisting of two steps: First, the input signal voltage is converted to an output current. The intermodulation distortion (in dBc) of the LT5524 output current is determined by the input signal level, and is almost independent of the output load conditions. Thus, the LT5524’s input IP3 is also nearly independent of the output load. Next, the external output load (R OUT) converts the output current to output voltage (or power). The LT5524’s volt- age and power gain both increase with increasing R OUT. Accordingly, the output power and output IP3 also in- crease with increasing R OUT. The actual output linearity performance in the application will thus be set by the choice of output load, as well as by the output network. Maximum Gain Calculation The maximum power gain (with the 0dB attenuation step) is: GPWR(dB) = 10 • log(gm2 • RIN • ROUT) where: gm is the LT5524 transconductance = 0.15S. RIN is the LT5524 differential input impedance ≅ 122Ω. Input impedance matching is assumed. ROUT is the external differential output impedance as seen by the LT5524’s differential outputs. ROUT should be distinguished from the actual load impedance, RLOAD, which will typically be coupled to the LT5524 output by an impedance transformation network. The power gain as a function of ROUT is plotted in Figure 2. The ideal relationship is linear. The curved line indicates the roll-off due to the finite (noninfinite) output resistance of the LT5524. ROUT (Ω) GAIN (dB) 100 1000 2000

5524 F02

Figure 2. Power Gain as a Function of ROUT

• The insertion loss of the output impedance transforma- tion network (for example the transformer insertion loss in Figure 6)
• About –3dB loss if a matching resistor (R MATCH in Figure 6) is used to provide output load impedance back-matching (for example when driving transmis- sion lines)

sion applies to maximum gain operation. PIN(MAX) = –11.5dBm (assuming RIN = 122Ω). 17.8dBm. This calculation applies for a sinusoidal signal. equal to the gain reduction. unloaded, with instability as the undesirable consequence. The LT5524 has about 20GHz gain-bandwidth product. Figure 7. Maximum Output Power as a Function of ROUT

5524 F07

on the LT5524 package must be soldered to a good ground plane on the PCB. PGA Function, Linearity and NF As described in the Circuit Operation section, the LT5524 consists of a variable (step) attenuator followed by a high gain output amplifier. The overall gain of the LT5524 is digitally controlled by means of four gain control pins with internal pull-down. Minimum gain is programmed when the gain control pins are set low or left floating. In shutdown mode, these PGA inputs draw <10 µA leakage current, regardless of the applied voltage. The 6dB and 12dB attenuation steps (PGA2 and PGA3) are implemented by switching the amplifier inputs to an input attenuator tap. The 3dB attenuation step (PGA1) changes the amplifier transconductance. The output IP3 is approxi- mately independent of the PGA1, PGA2 and PGA3 gain settings. However, the 1.5dB attenuation step utilizes a current steering technique that disables the internal linear- ity compensation circuit, and the OIP3 can be reduced by as much as 6dB when PGA0 is low. Therefore, to achieve the LT5524’s highest linearity performance, the PGA0 pin should be set high. The LT5524 noise figure is 8.6dB at 100MHz in the maxi- mum gain state. For the –3dB attenuation setting, the NF is 9.2dB. The noise figure increases in direct proportion to the amount of programmed gain reduction for the 1.5dB, 6dB and 12dB steps. The output noise floor is proportional to the output load impedance, R OUT. It is almost constant for PGA1 = high and for any PGA0, PGA2, PGA3 state. When PGA1 = low, the output noise floor is 2dB lower (see Typical Perfor- mance Characteristics). Other Linearity Considerations LT5524 linearity is a strong function of signal frequency. OIP3 decreases about 13dB for every octave of frequency increase above 100MHz. As noted in the Circuit Operation section, at any given frequency and input level, the LT5524 provides a current output with fairly constant intermodulation distortion fig- ure in dBc, regardless of the output load value. For higher R OUT values, more gain and output power is available, and better OIP3 figures can be achieved. However, high ROUT values are not easily implemented in practice, limited by the availability of high ratio output impedance transforma- tion networks. Linearity can also be limited by the output RC time con- stant (bandwidth limitations), particularly for high R OUT values. A solution is outlined in the Bandpass Applications section. The LT5524 linearity degrades when common mode sig- nal is present. The input transformer center tap should be decoupled to ground to provide a balanced input differen- tial signal and to avoid linearity degradation for high attenuation steps. When the signal frequency is lower than 50MHz, and there is significant common mode signal, then high attenuation settings may result in degraded linearity. At signal frequencies below 100MHz, the LT5524’s inter- nal linearity compensation circuitry may provide “sweet spots” with very high OIP3, in excess of +52dBm. This almost perfect distortion correction cannot be sustained over the full operating temperature range and with varia- tions of the LT5524 output load (complex impedance Z OUT). Users are advised to rely on data shown in the Typical Performance Characteristics curves to estimate the dependable linearity performance. Wideband Applications At low frequencies, the value of the decoupling capacitors, choke inductors and choice of transformer will set the minimum frequency of operation. Output DC coupling is possible, but this typically reduces the LT5524’s output DC bias voltage, and thus the output swing and available power. At high frequencies, the output RC time constants set an upper limit to the maximum frequency of operation in the case of the wideband output networks presented so far. For example the LT5524 output capacitance, C OUT = 1.7pF, and a pure resistive load, ROUT = 200Ω, will set the –3dB bandwidth to about 400MHz. In an actual application, the R LOAD • CLOAD product may be even more restrictive. The use of wideband output networks will not only limit the APPLICATIO S I FOR ATIOWU UU

the available power is wasted driving the capacitive load. characterization setup schematic (Figure 9). but it provides no improvement in linearity performance. peaking due to the capacitive load can be removed. mation ratio is more flexible than in the wideband case. destabilized by reactive loading. gain is the only way to reduce the output noise floor.

5524 F08

Figure 8. Bandpass Output Transformation Network Example

reduction in the output noise floor with no loss of linearity.

5524 F09

Figure 9. Characterization Board (Simplified Schematic)

5524 F10

Figure 10. Output Transformer Application Board (Simplified Schematic)

ROUT = 100Ω, presented to the LT5524. back-matching is suitably remedied). inductor will limit the lowest signal frequency to 40MHz.

5524 F11

Figure 11. Wideband Differential Output Application Board (Simplified Schematic)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. UPACKAGE DESCRIPTIO 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation CB FE20 (CB) TSSOP 0204 0.09 – 0.20 (.0035 – .0079) 0° – 8° 0.25 REF RECOMMENDED SOLDER PAD LAYOUT 0.50 – 0.75 (.020 – .030) 4.30 – 4.50* (.169 – .177) 13 4 5 6 7 89 1 0 111214 13 6.40 – 6.60* (.252 – .260) 3.86 (.152) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) MAX 0.05 – 0.15 (.002 – .006) 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 2.74 (.108) 0.45 ±0.05

0.65 BSC

4.50 ±0.10 6.60 ±0.10 1.05 ±0.10 3.86 (.152) MILLIMETERS (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE SEE NOTE 4 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT 6.40 (.252) BSC

© LINEAR TECHNOLOGY CORPORATION 2004 LT/TP 0904 1K • PRINTED IN THE USA Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com RELATED PARTS PART NUMBER DESCRIPTION COMMENTS Infrastructure LT5511 High Linearity Upconverting Mixer RF Output to 3GHz, 17dBm IIP3, Integrated LO Buffer LT5512 DC-3GHz High Signal Level Downconverting Mixer DC to 3GHz, 21dBm IIP3, Integrated LO Buffer LT5514 Ultralow Distortion IF Amplifier/ADC Driver with Digitally 47dBm OIP3 at 100MHz, 33dB Maximum Gain, 22.5dB Gain Controlled Gain Control Range LT5515 1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator 20dBm IIP3, Integrated LO Quadrature Generator LT5516 0.8GHz to 1.5GHz Direct Conversion Quadrature Demodulator 21.5dBm IIP3, Integrated LO Quadrature Generator LT5517 40MHz to 900MHz Quadrature Demodulator 21dBm IIP3, Integrated LO Quadrature Generator LT5519 0.7GHz to 1.4GHz High Linearity Upconverting Mixer 17.1dBm IIP3 at 1GHz, Integrated RF Output Transformer with 50 Ω Matching, Single-Ended LO and RF Ports Operation LT5520 1.3GHz to 2.3GHz High Linearity Upconverting Mixer 15.9dBm IIP3 at 1.9GHz, Integrated RF Output Transformer with 50 Ω Matching, Single-Ended LO and RF Ports Operation –5dBm LO Drive, –42dBm LO-RF Leakage LT5522 600MHz to 2.7GHz High Signal Level Downconverting Mixer 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 50Ω Single-Ended RF and LO Ports LT5526 High Linearity, Low Power Downconverting Mixer 16.5dBm IIP3, 0.6dB Gain, 11dB NF at 900MHz, 28mA Supply Current RF Power Detectors LT5504 800MHz to 2.7GHz RF Measuring Receiver 80dB Dynamic Range, Temperature Compensated, 2.7V to 5.25V Supply LTC 5505 RF Power Detectors with >40dB Dynamic Range 300MHz to 3GHz, Temperature Compensated, 2.7V to 6V Supply LTC5507 100kHz to 1000MHz RF Power Detector 100kHz to 1GHz, Temperature Compensated, 2.7V to 6V Supply LTC5508 300MHz to 7GHz RF Power Detector 44dB Dynamic Range, Temperature Compensated, SC70 Package LTC5509 300MHz to 3GHz RF Power Detector 36dB Dynamic Range, Low Power Consumption, SC70 Package LTC5530 300MHz to 7GHz Precision RF Power Detector Precision V OUT Offset Control, Shutdown, Adjustable Gain LTC5531 300MHz to 7GHz Precision RF Power Detector Precision V OUT Offset Control, Shutdown, Adjustable Offset LTC5532 300MHz to 7GHz Precision RF Power Detector Precision V OUT Offset Control, Adjustable Gain and Offset LT5534 50MHz to 3GHz Wide Dynamic Range Log RF Power Detector 60dB Dynamic Range, Superb Temperature Stability and Accuracy, Low Supply Current, SC70 Package LTC5535 Precision RF Detector with 12MHz Baseband Bandwidth 600MHz to 7GHz Adjustable Gain, Precision V OUT Offset Control Low Voltage RF Building Blocks LT5500 1.8GHz to 2.7GHz Receiver Front End 1.8V to 5.25V Supply, Dual-Gain LNA, Mixer, LO Buffer LT5502 400MHz Quadrature IF Demodulator with RSSI 1.8V to 5.25V Supply, 70MHz to 400MHz IF, 84dB Limiting Gain, 90dB RSSI Range LT5503 1.2GHz to 2.7GHz Direct IQ Modulator and 1.8V to 5.25V Supply, Four-Step RF Power Control, Upconverting Mixer 120MHz Modulation Bandwidth LT5506 500MHz Quadrature IF Demodulator with VGA 1.8V to 5.25V Supply, 40MHz to 500MHz IF, –4dB to 57dB Linear Power Gain, 8.8MHz Baseband Bandwidth LT5546 500MHz Ouadrature IF Demodulator with 17MHz Baseband Bandwidth, 40MHz to 500MHz IF, 1.8V to 5.25V VGA and 17MHz Baseband Bandwidth Supply, –7dB to 56dB Linear Power Gain