LTC4381 AD | Alldatasheet
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Rev. 0For more information www.analog.com Document Feedback TYPICAL APPLICATION FEATURES DESCRIPTION Low Quiescent Current Surge Stopper with 9mΩ MOSFET The LT C®4381 is an integrated solution for low quiescent current surge stopper applications that protect loads from high voltage transients. Overvoltage protection is pro - vided by clamping the gate voltage of an internal 9mΩ N-channel MOSFET to limit the output voltage to a safe value during overvoltage events such as load dump in automobiles. The MOSFET safe operating area is pro - duction tested and guaranteed for the stresses during high voltage transients. Fixed output clamp voltages are selectable for 12V and 24V/28V systems. For systems of any voltage up to 80V, use the adjustable clamp versions. Overcurrent protection is also provided. An internal mul- tiplier generates a TMR pin current proportional to V DS and ID, so that operating time in both overcurrent and overvoltage conditions is limited in accordance with MOSFET stress. The GATE pin can drive back-to-back MOSFETs for reverse input protection, eliminating the voltage drop and dissipation of a Schottky diode solution. A low 6µA operating current permits use in always-on and battery powered applications. 12V System with 100V/0.5A/400ms Load Dump Overvoltage Protection 12V, 0.5A with 100V Overvoltage Protection
APPLICATIONS
n Withstands Surge Voltages Up to 100V n Internal 9mΩ N-Channel MOSFET n Guaranteed Safe Operating Area: 20ms at 70V, 1A n Low Quiescent Current: 6µA Operating n Operates Through Automobile Cold Crank n Wide Operating Voltage Range: 4V to 72V n Overcurrent Protection n Selectable Internal 28.5V/47V or Adjustable Output Clamp Voltage (Table 1) n Reverse Input Protection to –60V n Adjustable Turn-On Threshold n Adjustable Fault Timer with MOSFET Stress Acceleration n Latchoff and Retry Options (Table 1) n Low Retry Duty Cycle During Faults (Table 1) n 32-Lead DFN (7mm × 5mm) Package n Automotive 12V, 24V and 48V System n Avionic/Industrial Surge Protection n Hot Swap/Live Insertion n High Side Switch for Battery Powered Systems n Automotive Load Dump Protection All registered trademarks and trademarks are the property of their respective owners. 100V INPUT SURGE 100ms/DIV V OUT 20V/DIV V IN 20V/DIV
4381 TA01b
ILOAD = 0.5A
4381 TA01a
0.1µF 68V 10µF 80m/uni03A9 33/uni03A9 47nF 10/uni03A9 22µF IN DRN ON V CC SEL GND TMR SRC SNS OUT L TC4381-2 GATE GFET CMHZ5266B 12V/0.5A OUTPUT CLAMPED AT 28.5V V IN 12V (100V PK F LT
Rev. 0 For more information www.analog.com ABSOLUTE MAXIMUM RATINGS DRN (Note 3), SNS, OUT, SRC GATE, GFET (Note 4) GATE to OUT, GATE to VCC, Operating Junction Temperature Range ORDER INFORMATION PIN CONFIGURATION TUBE TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4381CDKE-2#PBF LTC4381CDKE-2#TRPBF 43812 32-Lead (7mm × 5mm) Plastic DFN 0°C to 70°C LTC4381IDKE-2#PBF LTC4381IDKE-2#TRPBF 43812 32-Lead (7mm × 5mm) Plastic DFN –40°C to 85°C LTC4381HDKE-2#PBF LTC4381HDKE-2#TRPBF 43812 32-Lead (7mm × 5mm) Plastic DFN –40°C to 125°C LTC4381CDKE-4#PBF LTC4381CDKE-4#TRPBF 43814 32-Lead (7mm × 5mm) Plastic DFN 0°C to 70°C LTC4381IDKE-4#PBF LTC4381IDKE-4#TRPBF 43814 32-Lead (7mm × 5mm) Plastic DFN –40°C to 85°C LTC4381HDKE-4#PBF LTC4381HDKE-4#TRPBF 43814 32-Lead (7mm × 5mm) Plastic DFN –40°C to 125°C Contact ADI Sales for LTC4381-1/LTC4381-3 option. Contact ADI Sales for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. (Notes 1, 2) 1TMR ON GND DRN NC VCC IN SRC SRC SRC SRC SRC SRC SRC SRC SRC SEL FLT OUT SNS NC GATE GFET IN SRC SRC SRC SRC SRC SRC SRC SRC TOP VIEW DKE PACKAGE 32-LEAD (7mm × 5mm) PLASTIC DFN TJMAX = 150°C, θJA = 23°C/W EXPOSED PAD (PIN 33) IS IN IN 24
Rev. 0For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = OUT = SNS = DRN = 12V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DC Characteristics VIN Input Voltage Range (Note 7) l 4 80 V VCC Operating Voltage Range LTC4381-1/LTC4381-2 (Note 7) LTC4381-3/LTC4381-4 (Note 7, 8) l l V V VOUT Operating Voltage Range VCC = OUT = SNS = DRN = 12V l 72 V IQ Total Supply Current, ON (Note 6) C-Grade and I-Grade H-Grade l l 6 12 µA µA VCC = OUT = SNS = DRN = 4V l 18 35 µA ICC VCC Current, Shutdown ON = OUT = SNS = 0V l 5 10 µA VCC Current, ON VCC = OUT = SNS = DRN = 12V l 4 12 µA VCC = OUT = SNS = DRN = 4V l 16 30 µA IIN IN pin Leakage Current VIN = 24V, VGFET = VSRC = 0V, ON = 0V l 10 µA IR Reverse Input Current VCC = –60V, ON Open, SEL = 0V VCC = ON = SEL = –60V l l mA mA RON MOSFET On-Resistance IN = VCC = 8V, 12V, ISRC = –1A, IGATE = –1µA l 9 13 mΩ SOA MOSFET Safe Operating Area VIN – VSRC = 70V, 1A, 10W√s 20 ms SNS, OUT , SEL, ON, DRN ISNS SNS Current, ON l 0.5 1.4 µA IOUT , ON OUT Current, ON l 1.5 5.5 µA IOUT , SD OUT Current, Shutdown C-Grade and I-Grade H-Grade l l 6 12 µA µA ∆VSNS Current Limit Sense Voltage (SNS – OUT) VCC = 12V, 24V, OUT = 6V, 12V VCC = 12V, 24V, OUT = 0V l l mV mV ISEL SEL Input Current SEL = 0V to 80V l ±0.1 µA VSEL SEL Input Threshold l 0.4 3 V ION ON Input Current VON = 1V l –1 –2 –4 µA VON ON Input Threshold ON Rising l 0.99 1.05 1.1 V VON(HYST) ON Input Hysteresis 45 mV ∆VDRN DRN Voltage (DRN – OUT) IDRN = 0.1mA l 0.7 2.25 2.6 V VDS(MAX) Overvoltage VDS Threshold (DRN – OUT) TMR = 0.8V, IDRN = 2µA l 0.58 0.3 0.7 0.8 1.0 V V SRC, GATE, FL T , TMR VSRC SRC Voltage Output Clamp VIN = VCC = 80V, SEL = 0V, IOUT = –10mA, LTC4381-1/LTC4381-2 VIN = VCC = 80V, SEL = VCC, IOUT = –10mA, LTC4381-1/LTC4381-2 VIN = 80V, VCC = 12V, IOUT = –10mA, LTC4381-3/LTC4381-4 VIN = 80V, VCC = 24V, IOUT = –10mA, LTC4381-3/LTC4381-4 l l l l 25.5 43.5 19.0 31.0 28.5 47.0 22.5 34.5 31.5 50.5 26.0 38.0 V V V VGFET(TH) MOSFET Threshold ISRC = –10mA l 1 3 4.6 V ∆VGATE GATE Drive (GATE – OUT) SEL = SNS = OUT = VCC, 8V ≤ VCC ≤ 30V l 10 11.1 14 V ∆VCLAMP GATE Clamp to VCC (GATE – VCC) SNS = OUT = 20V, IGATE = 0µA l 12 13.5 15.5 V
Rev. 0 For more information www.analog.com Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to GND unless otherwise specified. Note 3: Internal clamps limit the DRN pin to a minimum of 10V above the OUT and SNS pins. Note 4: Internal clamps limit the GATE pin to a minimum of 10V above the OUT pin or VCC pin, or 50V (SEL = VCC) or 31.5V (SEL = GND) above the GND pin (LTC4381-1/LTC4381-2). Driving this pin to voltages beyond the clamp may damage the device. Note 5: IN ABS MAX is rated at 25°C to 125°C only. Note 6: Total supply current is the sum of the current into the VCC, OUT , SNS and DRN pins. Note 7: The LTC4381 can operate through the cold crank down to 4V in automotive applications, wheres VCC is powered with a 12V supply initially and stays above 8V during the cold crank period. Note 8: Operating voltage is limited by the maximum GATE voltage of 86V.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VGATE GATE Clamp to GND VCC = 30V, SEL = 0V, LTC4381-1/LTC4381-2 VCC = 60V, SEL = VCC, LTC4381-1/LTC4381-2 l l 47.5 31.5 52.5 V V IGATE(UP) GATE Pull-Up Current VCC = GATE = OUT = 12V, 24V l –8.5 –20 –35 µA IGATE(DN) GATE Pull-Down Current Overcurrent Shutdown Input UV Fault Time Out ∆VSNS = 200mV, GATE = 12V, OUT = 0V ON = 0V, GATE = 20V VCC = 1.5V, GATE = 10V TMR = 2V, GATE = 10V l l l l 0.3 1.5 100 3.5 mA mA mA mA IF LT F LT Leakage Current F LT = 80V l 2 µA VF LT(LOW) F LT Output Low ISINK = 0.1mA ISINK = 3mA l l 0.1 0.5 V V ITMR(DN) TMR Pull-Down Current TMR = 0.8V l 1.2 1.6 2.75 µA ITMR(UP , COOL) TMR Pull-Up Current, Cool Down TMR = 2V l –1 –2 –3 µA ITMR(UP) TMR Pull-Up Current, Overvoltage Small OV , Light Load High OV , Light Load Small OV , Heavy Load High OV , Heavy Load TMR = 0.8V, OUT = 11V, VDS = 1.1V, ∆VSNS = 0mV OUT = 28V, TMR = 0.8V I DRN = 0.1mA, ∆VSNS = 10mV I DRN = 1mA, ∆VSNS = 10mV I DRN = 0.1mA, ∆VSNS = 40mV I DRN = 1mA, ∆VSNS = 40mV l l l l l –0.7 –3.5 –13 –10 –60 –1.6 –6.7 –30 –20 –120 –2.4 –12 –61 –30 –180 µA µA µA µA µA TMR Pull-Up Current, Overcurrent Small OV , Light Load High OV , Light Load Small OV , Heavy Load High OV , Heavy Load TMR = 0.8V I DRN = 0mA, OUT = 11V I DRN = 0mA, OUT = 0V I DRN = 0.1mA, OUT = 11V I DRN = 1mA, OUT = 11V I DRN = 0.1mA, OUT = 0V I DRN = 1mA, OUT = 0V l l l l l l –16 –16 –80 –35 –130 –24 –27 –142 –50 –170 –36 –38 –206 –60 –220 µA µA µA µA µA µA VTMR(F) TMR Gate Off Threshold TMR Rising l 1.178 1.215 1.251 V AC Characteristics D Retry Duty Cycle; Overvoltage, LTC4381-2/LTC4381-4 ∆VSNS = 40mV, IDRN = 5µA, OUT = 28V, VCC = 29V l 2.8 4.2 % ∆VSNS = 40mV, IDRN = 500µA, OUT = 28V, VCC = 80V l 0.1 0.2 % Retry Duty-Cycle; Overcurrent, LTC4381-2/LTC4381-4 IDRN = 500µA OUT = 0V OUT = 6V l l 0.1 0.35 0.2 0.7 tON(ON) Turn-On Propagation Delay ON Steps from 0V to 1.5V, OUT = SNS = 0V l 7.5 25 ms tOFF(ON) Turn-Off Propagation Delay ON Steps from 1.5V to 0V, OUT = SNS = VCC l 1 5 µs tOFF(OC) Overcurrent Turn-Off Propagation Delay ∆VSNS Steps from 0V to 250mV, OUT = 6V l 2 4 µs ∆VSNS Steps from 0V to 250mV, OUT = 0V l 2 4 µs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = OUT = SNS = DRN = 12V, unless otherwise noted.
Rev. 0For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Supply Current (ICC) vs Supply Voltage Supply Current (ICC) vs Temperature ISNS vs Temperature Output Pin Current vs Temperature Reverse Current vs Reverse Voltage Gate Pull-Up Current vs Temperature Total Supply Current (IQ) vs Input Voltage Total Supply Current (IQ) vs Gate Leakage Total Supply Current (IQ) vs Temperature VCC = 12V, unless otherwise noted. SEL = V CC I GATE = 0 SHUTDOWN V IN (V) I Q (µA)
4381 G01
SNS = OUT= SEL = V CC V CC (V) I CC (µA)
4381 G04
SNS = OUT = V CC ON SHUTDOWN TEMPERATURE (°C) –50 –25 100 125 150 100 I OUT (µA)
4381 G07
I GATE (µA) –0.001 –0.01 –0.1 –10 100 I Q (µA)
4381 G02
SNS = OUT = V CC V CC = 4V V CC = 12V TEMPERATURE (°C) –50 –25 100 125 150 100 I CC (µA)
4381 G05
SEL = ON = V CC V CC (V) –10 –20 –30 –40 –50 –60 –70 –80 0.1 I GND (mA)
4381 G08
SNS = OUT = V CC TEMPERATURE (°C) –50 –25 100 125 150 0.1 I SNS (µA)
4381 G06
GATE = 0V GATE = 12V TEMPERATURE (°C) –50 –25 100 125 150 –15 –20 –25 –30 –35 I GATE(UP) (µA)
4381 G09
I GATE = 0 I GATE = –1µA SHUTDOWN TEMPERATURE (°C) –50 –25 100 125 150 100 I Q (µA)
4381 G03
Rev. 0 For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS VSRC vs Temperature TMR Pin Current vs Temperature, Overcurrent Fault TMR Pin Current vs Temperature, Overvoltage Fault Current Limit vs Output Voltage DRN Voltage vs Current ON Pin Current vs Voltage Gate Drive vs Pull-Up Current Gate Drive vs Temperature Gate Drive vs Supply Voltage VCC = 12V, unless otherwise noted. V CC = 12V V CC = 4V I GATE (µA) –10 –15 –20 –25 GATE (V)
4381 G10
V CC = 24V TEMPERATURE (°C) –50 –25 100 125 150 VSRC (V) SRC
4381 G13
I DRN = 1mA SNS = 40mV SNS = 10mV TEMPERATURE (°C) –50 –25 100 125 150 –20 –40 –60 –80 –100 –120 –140 –160 I TMR(OV) (µA)
4381 G16
I GATE = –1µA V CC = 4V V CC = 12V TEMPERATURE (°C) –50 –25 100 125 150 GATE (V)
4381 G11
I DRN = 0.1mA OUT = 0V OUT = 6V TEMPERATURE (°C) –50 –25 100 125 150 –20 –25 –30 –35 –40 –45 –50 –55 –60 I TMR(OC) (µA)
4381 G14
= V DRN – V OUT I DRN (µA) 100 1.0 1.5 2.0 2.5 3.0 3.5 4.0 DRN (V)
4381 G17
I GATE = –1µA SEL = V CC V CC (V) GATE (V)
4381 G12
I DRN = 1mA SNS = 40mV SNS = 10mV TEMPERATURE (°C) –50 –25 100 125 150 –20 –40 –60 –80 –100 –120 –140 –160 I TMR(OV) (µA)
4381 G15
V ON (V) –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 –3.5 –4.0 I ON (µA)
4381 G18
Rev. 0For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS RON vs Temperature RON vs VCC MOSFET SOA Curve VCC = 12V, unless otherwise noted. PIN FUNCTIONS DRN: MOSFET Drain-Source Sense. The DRN pin voltage tracks the OUT pin. The resulting DRN pin current through external resistor RDRN is proportional to the MOSFET VDS. The DRN pin current and ∆ VSNS (SNS – OUT) are mul - tiplied internally to produce a TMR pin current approxi - mately proportional to the MOSFET’s power dissipation. This reduces the SOA requirement of the MOSFET by tim- ing out faster during more severe faults. Choose RDRN to limit the current to 1mA at the peak input voltage. Connect to OUT if unused. F LT: Fault Output. This open-drain logic output pin pulls low after the voltage at the TMR pin has reached the fault threshold of 1.215V. It indicates that the MOSFET is off because either the supply voltage has stayed at an ele - vated level for an extended period of time (voltage fault) or the device is in an overcurrent condition (current fault). The fault output is capable of sinking up to 3mA. Leave open or tie to GND if unused. GATE: Gate Drive for Internal N-Channel MOSFET . The GATE pin is pulled up by an internal 20µA charge pump that is regulated to 11.5V above the OUT pin. An amplifier controls the GATE pin to limit the current through the MOSFET . A minimum of 47nF of capacitance and 33Ω series resistor at the pin is necessary to compensate the current limit amplifier . To avoid damaging the MOSFET during an output short, GATE is also clamped internally to 17V above OUT . GFET: Gate of Internal N-Channel MOSFET . Connect this pin to the GATE pin through a 10Ω resistor . GND: Device Ground. IN: Input of MOSFET . This is the drain terminal of the inter- nal MOSFET . Connect this pin to the supply input. ON: Turn-On Control Input. The LTC4381 can be turned on by pulling this pin above 1.05V or by leaving it open to allow an internal 1MΩ resistor to turn the part on. Pulling the pin below the threshold puts the part in shutdown mode and reduces the supply current to 5µA. Limit the ON leakage current to less than 1µA if no external pull-up is used. The ON pin can be pulled up to 80V or below GND by 60V without damage. OUT: Output Voltage Sense. This pin senses the output voltage at the output terminal of the current sense resistor . An internal clamp limits the voltage in between the GATE and OUT pins to 17V. Bypass the OUT pin with a minimum of 22µF as close to the pin as possible. V CC = 4V V CC = 12V TEMPERATURE (°C) –50 –25 100 125 150 R ON (mΩ) ON
4381 G19
V CC (V) R ON (mΩ) ON CC
4381 G20
T A = 25°C SINGLE PULSE V IN SRC (V) 100 200 0.1 100 I OUT (A)
4381 G21
Rev. 0 For more information www.analog.com PIN FUNCTIONS SEL: Output Clamp Voltage Select for LTC4381-1 and LTC4381-2. Connect the SEL pin to GND to set the inter- nal output clamp voltage to 28.5V. Connect it to V CC or OUT for a 47V output clamp voltage. The SEL pin can be pulled up to 80V or below GND by 60V without damage. Connect SEL to GND for LTC4381-3 and LTC4381-4. SNS: Current Sense Input. Connect to the input terminal of the current sense resistor . The current limit amplifier controls the GATE pin to limit the current sense voltage to 50mV. This voltage increases to 62mV in a severe fault when OUT is below 1.5V. A fixed 6µA is added to the TMR pin current during an overcurrent condition to shorten the turn-off time. In a severe short condition when the output voltage is below 1.5V, the extra current increases to 24µA to reduce the power dissipation in the MOSFET . ∆ VSNS (SNS – OUT) must be limited to less than ±5V. Connect to OUT if unused. SRC: Output of MOSFET . This is the source terminal of the internal MOSFET , connect this pin to the sense resistor . The SRC pin and output is indirectly clamped through GATE pin during an overvoltage event. The LTC4381-1/ LTC4381-2 SRC pin is clamped at 28.5V above GND with SEL = 0 V , or 47V above GND when SEL = VCC. It is also clamped at 10.5V above V CC if the V CC voltage is low. The LTC4381-3/LTC4381-4 SRC pin does not have the 28.5V/47V clamp to GND, it is only clamped at 10.5V above VCC. TMR: Fault Timer Input. Connect a capacitor between this pin and ground to set the fault turn-off time and cool down period. The charging current during fault conditions varies depending on the power dissipation of the MOSFET . When TMR reaches 1.215V, the MOSFET turns off and F LT pulls low. Upon gate off, the part immediately enters a cool down period with a 2µA current pull up and pull down on the TMR pin. After the cool down period has concluded, the LTC4381-2 and LTC4381-4 immediately restart, while the LTC4381-1and LTC4381-3 remain off until the ON pin is pulled low momentarily for more than 100µs or power is cycled. A 10V rated X7R capacitor is recommended for CTMR. VCC: Positive Supply Voltage Input. The positive supply input ranges from 4V to 80V. For applications where the input voltage is expected to exceed 80V, the VCC pin may be protected by a Zener diode clamp or , in the case of short duration spikes, by a simple RC filter . Clamping the VCC pin with a Zener diode can also be used as a means of adjusting the output clamp voltage to a value less than the internal 28.5V/47V clamps for the LTC4381-1/LTC4381-2. For the adjustable versions, LTC4381-3/LTC4381-4, which have no internal clamp, a Zener diode at the V CC pin is the only way to limit the voltage at the output. The VCC pin can also be powered separately from the VIN pin.
Rev. 0For more information www.analog.com BLOCK DIAGRAM GATE 9mΩ 13.5V 17V RSNS RDRN 31.5V* 50mV/62mV 20µA GFET IN SRC SNS OUT OUTPUTINPUT VCC VCC SEL TMR DRN OUT SNS ON 3.5VIA 18.5V* *ONL Y IN L TC4381-1/L TC4381-2 2.2V3.4V 1.215V 0.1V ON CONTROL LOGIC VMAX IMUL T RST GOFF MUL TIPLIER CHARGE PUMP REGULATED TO VOUT + 11.5V (250kHz) UV GND F LT 6µA, 24µA OVERCURRENT 3.6µA4µA COOL DOWN 2µA OVERVOL TAGE 4381 BD 3.5V 3.5V 3.5V
the input surge is blocked from reaching the load. also limited to 10.5V above the VCC pin. 50mV, rising to 62mV when the output is less than 1.5V. an output overload or short circuit. MOSFET within its safe operating area (SOA). power or by pulling the ON pin low for at least 100µs. low for at least 10ms/µF of CTMR. Table 1. LTC4381 Options Contact ADI Sales for LTC4381-1/LTC4381-3 option.
tect the MOSFET from damage. MOSFET’s gate terminal with a fixed 20µA current source. in the load capacitance COUT is given by Equation 1. where IGATE(UP) is typically 20µA. its regulation point of 11.5V, fully enhancing the MOSFET . tects against short circuits and excessive load current. below the value previously calculated. VCC to between 4V and 61.5V. Figure 1. 12V/1A, Output Limited to 28.5V
4381 F01
Rev. 0 For more information www.analog.com APPLICATIONS INFORMATION voltage. Using a 68V Zener assures that D1 will not over- ride the internal GATE pin clamp in the LTC4381-1 and LTC4381-2 devices. For the LTC4381-3 and LTC4381-4, the VCC operating range extends from 4V to 72V. Since the SRC pin is regulated to VCC + 10.5V, D1 is chosen to achieve the desired output clamping effect while at the same time keeping the VCC pin within its 4V to 72V range. The LTC4381 can operate through the cold crank down to 4V in automotive applications, wheres VCC is powered with a 12V supply initially and stays above 8V during the cold crank period. Fault Timer Overview Overvoltage and overcurrent conditions, and high V DS conditions in MOSFET are limited in duration by an adjust- able fault timer . A capacitor at the TMR pin (CTMR) sets the delay time before a fault condition is reported at the F LT pin and MOSFET is turned off. CTMR also sets the cool down time before MOSFET is permitted to turn back on for the LTC4381-2 and LTC4381-4 auto retry versions. The LTC4381-1 and LTC4381-3 versions simply latch off at the end of the timer delay. A 10V or higher rated X7R capacitor is recommended for CTMR to minimize tempera- ture and voltage sensitivity. Fault timing starts as soon as the input power is applied with the part in the on condition, or when the part turns on after application of power . A 1.5µA current is gener - ated to pull up the TMR pin when the voltage across the MOSFET is higher than 0.7V. The timer speeds up with an additional current that varies with the power dissipated in the MOSFET. The power dissipation is the product of the voltage across the MOSFET (V DS) and the current flowing through it (I D). VDS is inferred from the voltage drop across the drain pin resistor , RDRN, while ∆VSNS rep- resents ID. At initial power-up, the 1.5µA pilot current charges the TMR pin capacitor because the input supply is, at least for a short time, more than 0.7V above the output voltage. When the output rises to within 0.7V of the input supply voltage, the pull-up current disappears and an internal 2µA current source discharges the TMR pin capacitor . The capacitor must be sized to ride through the initial start-up interval for successful power-up. In the presence of a sustained fault, the timer current charges the TMR pin to 1.215V. At this point, the F LT pin pulls low to indicate a fault condition and the GATE pin pulls low, shutting off the MOSFET . After faulting off, the timer enters the cool down phase. At the end of the cool down period, the LTC4381-1/LTC4381-3 remain off until manually reset, while the LTC4381-2/LTC4381-4 auto - matically restart. Fault Timer Operation in Overvoltage or Large VDS During start-up or an overvoltage condition, where the MOSFET’s VDS exceeds 0.7V, the TMR pin charges from 0V to 1.215V with a current that varies principally as a function of VDS and ID. VDS is inferred from the current flowing in the DRN pin resistor , RDRN, while the voltage difference between the SNS and OUT pins (∆V SNS) rep- resents the MOSFET current, ID. The TMR pin current is given by Equation 2. ITMR = 0.0917 A V (2) where 0.0917√A/V is the gain term of the multiplier . If IDRN is less than 70µA (for example during start-up), use ITMR of 1.5µA. Substituting for ∆VSNS and IDRN is given by Equation 3. ITMR = 0.0917 A V ⎥ • ID •RSNS • VDS RDRN −70 µA[ ] (3) If IDRN is less than 70µA (for example during start-up), use ITMR of 1.5µA. When TMR reaches 1.215V, the F LT pin pulls low and the MOSFET is turned off and allowed to cool for an extended period. The total elapsed time between the onset of output clamping and turning off is given by Equation 4. tTMR = VTMR(F) • CTMR ITMR (4) Because ITMR is a function of VDS and ID, the exact time spent in overvoltage before turning off depends upon the input waveform and the load current.
Rev. 0For more information www.analog.com APPLICATIONS INFORMATION Fault Timer Operation in Overcurrent TMR pin behavior in overcurrent is substantially the same as in overvoltage. In the presence of an overcurrent con- dition when the LTC4381 regulates the output current, the TMR pin charges from 0V to 1.215V with a current that varies principally as a function of the power dissipated in the MOSFET . In addition to the variable current, an addi- tional 24µA hastens timeout in a low impedance short where the output is less than 1.5V. This additional current is reduced to 6µA when VOUT is above 3V. The TMR pin current with V OUT less than 1.5V is given by Equation 5. ITMR = 0.0917 A V ⎥ • ID •RSNS • VDS RDRN −70 µA[ ] +24.5 µA[ ] (5) where 24.5μA is the extra TMR current during overcurrent condition. If IDRN is less than 70µA, use ITMR of 24µA. And with VOUT above 3V given by Equation 6. ITMR = 0.0917 A V ⎥ • ID •RSNS • VDS RDRN −70 µA[ ] +6 µA[ ] (6) where 6μA is the extra TMR current during overcurrent condition. If IDRN is less than 70µA, use ITMR of 6µA. When TMR reaches 1.215V, the F LT pin pulls low and the MOSFET is turned off and allowed to cool for an extended period. The total elapsed time between the onset of output clamping and turning off is given by Equation 7. tTMR = VTMR(F) • CTMR ITMR (7) Because ITMR is a function of VDS and ID, the exact time spent in overcurrent before turning off depends upon the input waveform, the output voltage and the time required for the output current to come into regulation. Cool Down Phase Cool down behavior is the same whether initiated by over- voltage or overcurrent. During the cool down phase, the timer continues to charge from 1.215V to 3.4V with 2µA, and then discharge back down to 1.215V with 2µA. This cycle repeats 14 times and at the 15th cycle the TMR pin is pulled all the way to ground. The total cool down time is given by Equation 8. tCOOL = CTMR •15 •4.37V +(1.215V – 0.1V) 2 µA[ ] = CTMR •33.3 s µF (8) where CTMR is in µF . Up to this point the operation of the LTC4381-1/LTC4381-3 and LTC4381-2/LTC4381-4 is the same. Behavior at the end of the cool down phase is entirely different. At the end of the cool down phase, when TMR crosses the 100mV reset threshold, the LTC4381-1/LTC4381-3 remain latched off and F LT remains low. They may be restarted by pulling the ON pin low for at least 100µs or by cycling the power supply. The cool down phase may be interrupted at anytime by pulling the ON pin low for at least 10ms/µF of C TMR; the LTC4381-1/LTC4381-3 will restart when ON goes high. The LTC4381-2/LTC4381-4 will automatically retry at the end of the cool down phase without cycling the ON pin and the cool down phase may be interrupted by pulling the ON pin low for at least 10ms/µF of CTMR. For both versions, the F LT pin goes high in shutdown and is cleared high when power is first applied to V CC. If F LT is set low, it can be reset during the cool down phase by pulling the ON pin low for at least 10ms/µF of CTMR. Supply T ransient Protection The LTC4381-1/LTC4381-2 is tested to operate to 80V and the LTC4381-3/LTC4381-4 to 72V. The IN and V CC pins are guaranteed to be safe from damage up to 100V and 80V, respectively. Voltage transients above these volt- ages may cause permanent damage. During a short-cir - cuit condition, the large change in current flowing through power supply traces and associated wiring can cause large inductive voltage transients. To minimize the voltage transients, minimize the power trace parasitic inductance
an effective measure against voltage spikes. current of the LTC4381 and the leakage current of D1. lytic or ceramic is required close to the OUT pin. output voltage and load current. lyzed by simulation using the MOSFET thermal model. type and rises to infinity under DC operating conditions. P√t is not the same for all combinations of I D and VDS. Figure 2. Prototypical T ransient Waveform
4381 F02tr
Figure 3. Safe Operating Area Required to Survive
4381 F03
using Equation 9 and Figure 3. 1A, P√t is 1.4W√s which can be handled by the MOSFET. condition. Short-circuit P√t is given by Equation 10. timer interval, given by Equation 5 and Equation 6. culated in the previous example. Figure 4. Automotive Cold Crank Ride Through itance by controlling the GATE pin voltage slew rate. turn-off time. The gate capacitor is set using Equation 11. lize the current limit amplifier during an overcurrent event. suppress parasitic oscillations. to ride through cold crank as shown in Figure 4.
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end of cold crank is given by Equation 12. crank, and t is the duration of the cold crank. MOSFET on to continue providing current to the output. Figure 5. Recommended PCB Layout
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1µA if no pull-up device is used to help turn on the part. tions to the current sense resistor (R SNS in Figure 5). at the expense of dissipation in the MOSFET pass device. SRC pins also conduct substantial heat from the MOSFET . Connect all the SRC pins to a plane of 1oz or 2oz copper .
Figure 6. Design Example 1: 12V/1A Application Survives 100V, 2ms OV T ransient to 3V for 40ms. Maximum load of 1A. voltage at the VOUT to less than 20V during a 100V surge. VIN is at 10V; the VCC pin input current is less than 30μA. We used R1 of 100k to cover all condition. sients is then calculated using Equation 15. C1 can be calculated by Equation 16. pin. Longer surges are suppressed by D1. (Equation 17). VOUT is clamped to 7.5V + 10.5V or 18V.
4381 F06
Rev. 0 For more information www.analog.com APPLICATIONS INFORMATION when VIN is minimum and load current is at its maximum when the input transient occur (Equation 18). P t = ILOAD • VDS • t P t = 4.02W s (18) Next calculate the sense resistor (R SNS) value with a current limit of greater than 1A with 10% tolerance (Equation 19). RSNS = 45mV 1.1•1A = 40.9mΩ (19) We will use 40mΩ, which gives a current limit of 1.25A. Next we select CTMR to shut off the MOSFET if the 100V transient is longer than 2ms at maximum load of 1A (Equation 20). ITMR = 0.0917 A V ⎥ • ID •RSNS • VDS RDRN −70 µA[ ] ITMR = 0.0917 A V 82.5k −70 µA[ ] = 117.2µA (20) Next the value is calculated using Equation 21 to achieve a fault time of greater than 2ms: CTMR = ITMR(UP) • tTMR VTMR CTMR = 0.193µF (21) So we choose a CTMR = of 0.22μF. Next, we need to make sure that the chosen CTMR allow enough time to power up the output (Equation 22). CTMR = ITMR(UP) •tINRUSH VTMR (22) where (Equation 23). tINRUSH = VIN • COUT IINRUSH = VIN • C2 IGATE(UP) = 14V • 47nF 20µA = 32.9ms ITMR(UP) ℵ 1.5µA at power up: VTMR = 1.5µA • 32.9ms 0.22µF ℵ 0.224V, (23) which is much lower than the 1.215V trip off threshold. Next, we need to check to make sure that in the case of a severe output short where V OUT = 0V, the power dis - sipation in the MOSFET is also within the safe operating area (Equation 24). tOC = 0.22µF • 1.215V 80.8µA = 3.31ms (24) The power dissipation in the MOSFET is given by Equation 25. P = 14V • 62mV 40mΩ = 21.7W P t = 1.248W s (25) During an output overload or soft short, the voltage at the OUT pin could stay at 3V or higher . The total overcurrent fault time when VOUT = 3V is given by Equation 26. tOC = 0.22µF • 1.215V 42.5µA = 6.29ms (26) The power dissipation in the MOSFET is given by Equation 27. P = (14V – 3V) • 50mV 40mΩ= 13.75W P t = 1.09W s (27) These conditions are within the 10W√ s safe operating area of the MOSFET .
Figure 7. Surge Stopper with Output Clamped Below 60V with 100V/1A/400ms Overvoltage Protection of more external components. sients is then calculated by Equation 28. Power dissipated in D1 is 22mW.
4381 F07
100kΩ is chosen to give enough margin. VPK = 100V and τ = 200ms (Equation 30). This is within the LTC4381 SOA limit of 10W√s.
Rev. 0 For more information www.analog.com APPLICATIONS INFORMATION Next calculate the sense resistor (RSNS) value with a current limit of greater than 1A with 20% tolerance (Equation 31). RSNS = 50mV ILIM = 50mV 1.2A = 41.67mΩ (31) We will use 40mΩ, which gives a current limit of 1.25A. The load dump waveform can be represented as an exponentially decaying waveform with a time constant of 0.2sec (Equation 32). VIN = 100 V[ ]e−t/0.2 s[ ] (32) The LTC4381 clamps the VOUT at 56.7V, which means that VDS and ITMR drops to zero when VIN drops to 56.7V. To find the time t1 when this happen, we use Equation 33. t1 = −0.2s •In 56.7V 100V ⎝⎜ ⎞ ⎠⎟ = 0.113s (33) VDS can be approximated as a triangular waveform with a peak of 100V – 56.7V or 43.3V and a time base of 0.113sec. We take half of the peak, 21.65V to calculate the ITMR (Equation 34). ITMR = 0.0917 A V ⎥ • ID •RSNS • VDS RDRN −70 µA[ ] ITMR = 0.0917 A V 100k −70 µA[ ] ITMR = 44µA CTMR = t1 •ITMR VTMR CTMR = 0.113s•44µA 1.215V CTMR = 4.1µF (34) We shall use a 4.7μF capacitor for more margin. Next, we need to make sure that the chosen CTMR allow enough time to power up the output (Equation 35). CTMR = ITMR(UP) • tINRUSH VTMR tINRUSH = VIN •COUT IINRUSH = VIN •C2 IGATE(UP) = 24V •47nF 20µA = 56.4ms ITMR(UP) ≈1.5µA at power up: VTMR = 1.5µA •56.4ms 4.7µF ≈18mV (35) Next, we need to check to makes sure that in the case of a severe output short where VOUT = 0V, the power dis- sipation in the MOSFET is also within the safe operating area (Equation 36). tOC = 4.7µF • 1.215V 98.1µA = 58.2ms (36) The power dissipation in MOSFET is given by Equation 37. P = 24V • 62mV 40mΩ = 37.2W P t = 8.97W s (37) During an output overload or soft short, the voltage at the OUT pin could stay at 3V or higher . The total overcurrent fault time when VOUT = 3V is given by Equation 38. tOC = 4.7µF • 1.215V 60.3µA = 94.8ms (38) The power dissipation in MOSFET is given by Equation 39. P = (24V – 3) • 50mV 40mΩ = 26.25W P t = 8.08W s (39) These conditions are within the safe operating area of the MOSFET .
Figure 8. 12V Hot Swap Controller with Input UV Detection with 60V/2A/3.5ms Overvoltage Protection Figure 9. 28V Surge Stopper with Output Clamped to Below 40V with 100V/1A/6ms Overvoltage Protection
4381 F08
4381 F09
Figure 10. –60V Reverse Battery Protection with 100V/1A/3ms Overvoltage Protection
4381 F10
Rev. 0For more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. PACKAGE DESCRIPTION 5.00 ±0.10 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE M0-220 VARIATION WHKD 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS PIN 1 TOP MARK (SEE NOTE 6) 2 BOTTOM VIEW—EXPOSED PAD 6.30 ±0.10 7.00 ±0.10 0.75 ± 0.05 R = 0.125 TYP 0.00 – 0.05 0.17 ±0.05 (DKE32) QFN 0819 REV A
0.40 BSC
0.200 REF
6.0 REF
RECOMMENDED SOLDER PAD LAYOUT APPL Y SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 REF
0.51 REF 0.40 ±0.10 0.70 ±0.05
6.00 REF
4.10 ±0.05 5.50 ±0.05 0.17 ±0.05 6.30 ±0.05 2.94 ±0.05 PACKAGE OUTLINE 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER 32-Lead Plastic DFN (7mm × 5mm) (Reference LTC DWG # 05-08-1789 Rev A) 2.94 ±0.10
Figure 11. 48V, 10A eFuse