LT4320

LT4320/LT4320-1 - Ideal Diode Bridge Controller

Document overview

• Manufacturer or author: Linear Technology Corporation
• PDF pages: 14

Technical content

For more information www.linear .com/L T4320 Features Description Ideal Diode Bridge Controller The LT®4320/LT4320-1 are ideal diode bridge controllers that drive four N-channel MOSFETs, supporting voltage rectification from DC to 600Hz typical. By maximizing available voltage and reducing power dissipation (see thermograph comparison below), the ideal diode bridge simplifies power supply design and reduces power supply cost, especially in low voltage applications. An ideal diode bridge also eliminates thermal design problems, costly heat sinks, and greatly reduces PC board area. The LT4320’s internal charge pump supports an all- NMOS design, which eliminates larger and more costly PMOS switches. If the power source fails or is shorted, a fast turn-off minimizes reverse current transients. The LT4320 is designed for DC to 60Hz typical voltage rectification, while the LT4320-1 is designed for DC to 600Hz typical voltage rectification. Higher frequencies of operation are possible depending on MOSFET size and operating load current.

applications

n Maximizes Power Efficiency n Eliminates Thermal Design Problems n DC to 600Hz n 9V to 72V Operating Voltage Range n IQ = 1.5mA (Typical) n Maximizes Available Voltage n Available in 8-Lead (3mm × 3mm) DFN, 12-Lead MSOP and 8-Lead PDIP Packages n Security Cameras n Terrestrial or Airborne Power Distribution Systems n Power-over-Ethernet Powered Device with a Secondary Input n Polarity-Agnostic Power Input n Diode Bridge Replacement L, LT, LT C, LT M, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Patent pending. TG1 IN1 L T4320 BG2 IN2 BG1 TG2 OUTN OUTP

4320 TA01a

DC TO 600Hz (TYP) Thermograph of Passive Diode Bridge Thermograph of LT4320 Driving Four MOSFETs SBM1040 (×4)

4320 TA01b

2.5mΩ DIODE SBM 1040 2A 0.6°C 15°C 4A 3.5°C 32°C 6A 6.7°C 49°C 8A 11°C 66°C 10A 16°C 84°C DC Input, On Same PCB L T4320+2.5m/uni03A9 FET (×4) CONDITIONS: 24V ACIN, 9.75A DC LOAD ON SAME PCB

4320 TA01c

4320fb For more information www.linear .com/L T4320 pin conFiguration absolute MaxiMuM ratings Supply Voltages Output Voltages (Note 3) (Notes 1, 2) TOP VIEW DD PACKAGE 8-LEAD (3mm × 3mm) PLASTIC DFN 1IN2 TG2 BG2 BG1 IN1 TG1 OUTP OUTN TJMAX = 150°C, θJC = 5.5°C/W EXPOSED PAD (PIN 9) MUST BE CONNECTED TO OUTN (PIN 5) IN2 TG2 NC NC BG2 BG1 IN1 TG1 NC OUTP NC OUTN TOP VIEW MSE PACKAGE 12-LEAD PLASTIC MSOP TJMAX = 150°C, θJC = 10°C/W EXPOSED PAD (PIN 13) MUST BE CONNECTED TO OUTN (PIN 7) TOP VIEW IN2 TG2 BG2 BG1 IN1 TG1 OUTP OUTN N8 PACKAGE 8-LEAD PLASTIC DIP TJMAX = 150°C, θJC = 45°C/W orDer inForMation LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION OPERATING JUNCTION TEMPERATURE RANGE LT4320IDD#PBF LT4320IDD#TRPBF LGCV 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LT4320HDD#PBF LT4320HDD#TRPBF LGCV 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT4320IDD-1#PBF LT4320IDD-1#TRPBF LGCW 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LT4320HDD-1#PBF LT4320HDD-1#TRPBF LGCW 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT4320IMSE#PBF LT4320IMSE#TRPBF 4320 12-Lead Plastic MSOP –40°C to 85°C LT4320HMSE#PBF LT4320HMSE#TRPBF 4320 12-Lead Plastic MSOP –40°C to 125°C LT4320MPMSE#PBF LT4320MPMSE#TRPBF 4320 12-Lead Plastic MSOP –55°C to 125°C LT4320IMSE-1#PBF LT4320IMSE-1#TRPBF 43201 12-Lead Plastic MSOP –40°C to 85°C LT4320HMSE-1#PBF LT4320HMSE-1#TRPBF 43201 12-Lead Plastic MSOP –40°C to 125°C LT4320MPMSE-1#PBF LT4320MPMSE-1#TRPBF 43201 12-Lead Plastic MSOP –55°C to 125°C LT4320IN8#PBF NA LT4320N8 8-Lead PDIP –40°C to 85°C LT4320HN8#PBF NA LT4320N8 8-Lead PDIP –40°C to 125°C LT4320IN8-1#PBF NA LT4320N8-1 8-Lead PDIP –40°C to 85°C LT4320HN8-1#PBF NA LT4320N8-1 8-Lead PDIP –40°C to 125°C Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LT C Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ Operating Junction Temperature Range Lead Temperature (Soldering, 10 sec)

For more information www.linear .com/L T4320 electrical characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS OUTP Voltage Range l 9 72 V OUTP Undervoltage Lockout (UVLO) Threshold INn = OUTP, Other IN = 0V l 6.2 6.6 7.0 V VINT INn Turn-On/Off Threshold OUTP = 9V, Other IN = 0V l 1.3 3.7 V IOUTP OUTP Pin Current INn = OUTP+ ∆VSD(MAX) + 5mV, Other IN = 0V l 1.0 1.5 mA IINn INn Pin Current at 9V at 72V INn = OUTP+ ∆VSD(MAX) + 5mV, Other IN = 0V l l 0.3 0.4 µA mA ∆VSD Topside Source-Drain Regulation Voltage (INn – OUTP) LT4320 LT4320-1 l l mV mV ∆VTGATE Top Gate Drive (TGn – INn) INn = OUTP+ ∆VSD(MAX) + 5mV, 10μA Out of TGn, Other IN = 0V l 6.6 10.8 V VBGATE Bottom Gate Drive (BGn) INn = OUTP, 10μA Out of BGn, Other IN = 0V l 7.0 12 V ITGUn Top Gate Pull-Up Current TGn – INn = 0V, INn = OUTP + 0.1V TGn – INn = 5V, INn = OUTP + 0.1V Current Flows Out of TGn, Other IN = 0V l l 425 120 µA µA ITGSn Top Gate Pull-Down Current to INn TGn – INn = 5V, INn = OUTP – 0.25V Current Flows Into TGn, Other IN = 0V l 1.25 mA ITGGn Top Gate Pull-Down Current to OUTN INn = 0V, Other IN = OUTP = 9.0V, TGn = 5V Current Flows Into TGn l 6.0 mA IBGUn Bottom Gate Pull-Up Current BGn = 5V; INn = OUTP = 9.0V, Other IN = 0V Current Flows Out of BGn l 1.9 mA IBGDn Bottom Gate Pull-Down Current BGn = 5V; INn = 0V, Other IN = OUTP = 9.0V Current Flows Into BGn l 12.5 mA Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Unless otherwise specified, exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltages are referenced to OUTN = 0V unless otherwise specified. Note 3: Externally forced voltage absolute maximums. The LT4320 may exceed these limits during normal operation.

4320fb For more information www.linear .com/L T4320 typical perForMance characteristics VBGATE vs OUTP TGn Pull-Up Strength TGn Pull-Down Strength to INn TGn Pull-Down Strength to OUTN BGn Pull-Up Strength BGn Pull-Down Strength IINn and IOUTP vs OUTP IOUTP vs OUTP ∆VTGATE vs OUTP INn = OUTP (V) CURRENT (µA) 200 400 600 800 1000 1200 20 40 60 80

4320 G01

OTHER IN = 0V OUTP (V) IOUTP (µA) 200 400 600 800 1000 1200 20 40 60 80

4320 G02

OUTP (V) ∆VTGATE (V)

4320 G03

∆VSD = 100mV ∆VSD = 40mV OTHER IN = 0V OUTP (V) VBGATE (V) 13 17 21 25

4320 G04

OTHER IN = 0V ∆VTGATE (V) ITGn (µA) 200 400 600 2 4 6 8

4320 G05

OUTP = 9V OUTP = 12V OUTP = 72V INn = OUTP + 100mV OTHER IN = 0V ∆VTGATE (V) ITGSn (mA) 2 4 6 8

4320 G06

OUTP = 9V OUTP = 72V INn = OUTP – 250mV OTHER IN = 0V TGn (V) ITGGn (mA) 2 4 6 8

4320 G07

INn = 0V OTHER IN = OUTP OUTP = 9V OUTP = 12V OUTP = 72V VBGATE (V) IBGUn (mA) 4 8 10 12

4320 G08

OTHER IN = 0V VINn = 9V VINn = 12V VINn = 72V VBGATE (V) 6 10

4320 G09

IBGDn (mA)

For more information www.linear .com/L T4320 pin Functions (DFN, PDIP/MSOP) IN2 (Pin 1/Pin 1): Bridge Rectifier Input. IN2 connects to the external NMOS transistors MTG2 source, MBG1 drain and the power input. TG2 (Pin 2/Pin 2): Topside Gate Driver Output. TG2 pin drives MTG2 gate. BG2 (Pin 3/Pin 5): Bottom-Side Gate Driver Output. BG2 pin drives MBG2 gate. BG1 (Pin 4/Pin 6): Bottom-Side Gate Driver Output. BG1 pin drives MBG1 gate. OUTN (Pin 5/Pin 7): OUTN is the rectified negative output voltage, and connects to the sources of MBG1 and MBG2. OUTP (Pin 6/Pin 9): OUTP is the rectified positive output voltage that powers the LT4320 and connects to the drains of MTG1 and MTG2. TG1 (Pin 7/Pin 11): Topside Gate Driver Output. TG1 pin drives MTG1 gate. IN1 (Pin 8/Pin 12): Bridge Rectifier Input. IN1 connects to the external NMOS transistors MTG1 source, MBG2 drain, and the power input. NC (Pins 3, 4, 8, 10, MSOP Only): No Connections. Not internally connected. Exposed Pad (Pin 9/Pin 13): Exposed Pad, DFN and MSOP. Must be connected to OUTN. OUTP L T4320 BD MTG1 OUTN BG1 IN1 L T4320 IN2 MBG1 BG2 MTG2 MBG2 TG1 TG2 CONTROL block DiagraM

power especially in low voltage applications. heat sinks, and greatly reduces PC board area. pins in an AC voltage rectification design.

4320 F01

4320 F02

Figure 1. LT4320 with Four N-Channel MOSFETS, Illustrating Current Figure 2. 24V AC Sample Waveform

For more information www.linear .com/L T4320 applications inForMation MOSFET Selection A good starting point is to reduce the voltage drop of the ideal bridge to 30mV per MOSFET with the LT4320 (50mV per MOSFET with the LT4320-1). Given the average output load current, IAVG, select RDS(ON) to be: RDS(ON) = 30mV IAVG for a DC power input or RDS(ON) = 30mV 3 •IAVG for an AC power input In the AC power input calculation, 3 • IAVG assumes the duration of current conduction occupies 1/3 of the AC period. Select the maximum allowable drain-source voltage, V DSS, to be higher than the maximum input voltage. Design Example For a 24W, 12V DC/24V AC application, IAVG = 2A for 12V DC. To cover the 12V DC case: RDS(ON) = 30mV 2A =15mΩ For the 24V AC operation, IAVG = 1A. To cover the 24V AC case: RDS(ON) = 30mV 3 • 1A =10mΩ This provides a starting range of RDS(ON) values to choose from. Ensure the MOSFET can handle a continuous current of 3 • IAVG to cover the expected peak currents during AC rec- tification. That is, select ID ≥ 3A. Since a 24V AC waveform can reach 34V peak, select a MOSFET with VDSS >>34V. A good choice of VDSS is 60V in a 24V AC application. Other Considerations in MOSFET Selection Practical MOSFET considerations for the LT4320-based ideal bridge application include selecting the lowest avail able total gate charge (Qg) for the desired RDS(ON). Avoid oversizing the MOSFET, since an oversized MOSFET limits the maximum operating frequency, creates unintended efficiency losses, adversely increases turn-on/turn-off times, and increases the total solution cost. The LT4320 gate pull-up/pull-down current strengths specified in the Electrical Characteristics section, and the MOSFET total gate charge (Qg), determine the MOSFET turn-on/off times and the maximum operating frequency in an AC applica- tion. Choosing the lowest gate capacitance while meeting RDS(ON) speeds up the response time for full enhancement, regulation, turn-off and input shorting events. V GS(th) must be a minimum of 2V or higher. A gate thresh- old voltage lower than 2V is not recommended since too much time is needed to discharge the gate below the threshold and halt current conduction during a hot plug or input short event. CLOAD Selection A 1μF ceramic and a 10μF minimum electrolytic capacitor must be placed across the OUTP and OUTN pins with the 1µF ceramic placed as close to the LT4320 as possible. Downstream power needs and voltage ripple tolerance determine how much additional capacitance between OUTP and OUTN is required. CLOAD in the hundreds to thousands of microfarads is common. A good starting point is selecting CLOAD such that: CLOAD ≥ IAVG/(VRIPPLE • 2 • Freq) where IAVG is the average output load current, VRIPPLE is the maximum tolerable output ripple voltage, and Freq is the frequency of the input AC source. For example, in a 60Hz, 24VAC application where the load current is 1A and the tolerable ripple is 15V, choose CLOAD ≥ 1A/(15V

• 2 • 60Hz) = 556µF. C LOAD must also be selected so that the rectified output voltage, OUTP-OUTN, must be within the LT4320/LT4320-1 specified OUTP voltage range. Transient Voltage Suppressor For applications that may encounter brief overvoltage events higher than the LT4320 absolute maximum rating, install a unidirectional transient voltage suppressor (TVS) between the OUTP and OUTN pins as close as possible to the LT4320.

Figure 3. Thermograph: B360B vs LT4320 +4 Compact FETs

Figure 4. Demonstration Circuit 1902A Used in Figure 3 Thermograph

4320fb For more information www.linear .com/L T4320 package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 3.00 ±0.10 (4 SIDES) NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE 0.40 ±0.10 BOTTOM VIEW—EXPOSED PAD 1.65 ±0.10 (2 SIDES) 0.75 ±0.05 R = 0.125 TYP 2.38 ±0.10 PIN 1 TOP MARK (NOTE 6)

0.200 REF

0.00 – 0.05 (DD8) DFN 0509 REV C 0.25 ±0.05 2.38 ±0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 1.65 ±0.05 (2 SIDES)2.10 ±0.05 0.50 BSC 0.70 ±0.05 3.5 ±0.05 PACKAGE OUTLINE 0.25 ±0.05

0.50 BSC

8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698 Rev C)

For more information www.linear .com/L T4320 package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MSOP (MSE12) 0213 REV G 0.53 ±0.152 (.021 ±.006) SEATING PLANE 0.18 (.007) 1.10 (.043) MAX 0.22 –/uni00A00.38 (.009 – .015) TYP 0.86 (.034) REF 0.650 (.0256) BSC 12 11 10 9 8 7 DETAIL “B” 1 6 NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED 0.254mm (.010") PER SIDE. 0.254 (.010) 0° – 6° TYP DETAIL “A” DETAIL “A” GAUGE PLANE RECOMMENDED SOLDER PAD LAYOUT BOTTOM VIEW OF EXPOSED PAD OPTION 2.845 ±0.102 (.112 ±.004) 4.039 ±0.102 (.159 ±.004) (NOTE 3) 1.651 ±0.102 (.065 ±.004) 1.651 ±0.102 (.065 ±.004) 0.1016 ±0.0508 (.004 ±.002) 1 2 3 4 5 6 3.00 ±0.102 (.118 ±.004) (NOTE 4) 0.406 ±0.076 (.016 ±.003) REF 4.90 ±0.152 (.193 ±.006) DETAIL “B” CORNER TAIL IS PART OF THE LEADFRAME FEATURE. FOR REFERENCE ONL Y NO MEASUREMENT PURPOSE

0.12 REF

0.35 REF 5.10 (.201) MIN 3.20 – 3.45 (.126 – .136) 0.889 ±0.127 (.035 ±.005) 0.42 ±0.038 (.0165 ±.0015) TYP 0.65 (.0256) BSC 12-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1666 Rev G)

4320fb For more information www.linear .com/L T4320 package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. N8 REV I 0711 .065 (1.651) TYP .045 – .065 (1.143 – 1.651) .130 ±.005 (3.302 ±0.127) .020 (0.508) MIN.018 ±.003 (0.457 ±0.076) .120 (3.048) MIN .008 – .015 (0.203 – 0.381) .300 – .325 (7.620 – 8.255) .325 +.035 –.015 +0.889 –0.3818.255 ( ) 1 2 3 4 8 7 6 5 .255 ±.015* (6.477 ±0.381) .400* (10.160) MAX NOTE: 1. DIMENSIONS ARE INCHES MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm) .100 (2.54) BSC N Package 8-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510 Rev I)

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revision history

REV DATE DESCRIPTION PAGE NUMBER A 11/13 Clarified that input frequency ranges use typical numbers (60Hz, 600Hz) Added PDIP package Reduced MOSFET drop to 30mV from 70mV in “MOSFET Selection” and “Design Example” sections Provided additional guidance in “Other Considerations in MOSFET Selection” section Updated MSE package drawing 1, 6 2, 12 B 2/14 Added H- and MP-grade information 2 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

4320fb For more information www.linear .com/L T4320 relateD parts typical application TG2 MTG2 MTG1 IN1 1µF C1L T4320 TO LOADINPUT IN2 OUTP OUTN BG2 MBG2 MBG1 TG1 BG1

4320 TA02

PART NUMBER DESCRIPTION COMMENTS LT4321 PoE Ideal Diode Bridge Controller Replaces 8 Diodes with 8 N-Channel MOSFETs, Reduces Heat, Maximizes Efficiency LTC4352 Low Voltage Ideal Diode Controller with Monitoring N-Channel, 0V to 18V, UV, OV, MSOP-12 and DFN-12 Packages LTC4353 Dual Low Voltage Ideal Diode Controller Dual N-Channel, 0V to 18V, MSOP-16 and DFN-16 Packages LTC4354 Negative Voltage Diode-OR Controller and Monitor Controls Tw o N-Channel MOSFETs, 1μs Turn-Off, –80V Operation LTC4355 Positive Voltage Diode-OR Controller and Monitor Controls Tw o N-Channel MOSFETs, 0.5μs Turn-Off, 9V to 80V Operation LTC4357 Positive High Voltage Ideal Diode Controller Controls Single N-Channel MOSFETs, 0.5μs Turn-Off, 9V to 80V Operation LTC4358 5A Ideal Diode Positive Voltage Ideal Diode with Integrated MOSFET, 9V to 26.5V Operation LTC4359 Ideal Diode Controller with Reverse Input Protection N-Channel, 4V to 80V, MSOP-8 and DFN-6 Packages LTC4370 2-Supply Diode-OR Current Balancing Controller Dual N-Channel, 0V to 18V, MSOP-16 and DFN-16 Packages LTC4415 Dual 4A ideal Diodes with Adjustable Current Limit 1.7V to 5.5V Operating Range LT4320 IDEAL BRIDGE DIODE BRIDGE MTG1,MTG2 MBG1, MBG2 OPERATING VOL TAGE LOAD CURRENT (MIN) POWER LOSS POWER LOSS BSZ110N06NS3 55V DC 3.5A 10µF 0.22W 4.2W 24V AC 1.5A 560µF 0.13W 1.9W BSC031N06NS3 55V DC 30A 10µF 4.5W 36W 24V AC 10A 3.3mF 1.6W 12W PSMN040-100MSE 72V DC 2A 10µF 0.24W 2.4W  LINEAR TECHNOLOGY CORPORATION 2013 LT 0214 REV B • PRINTED IN USA Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com/L T4320