LT4294

LT4294 (Rev. B)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 16

Technical content

Rev. BFor more information www.analog.comDocument Feedback TYPICAL APPLICATION FEATURES DESCRIPTION IEEE 802.3bt PD Interface Controller The LT®4294 is an IEEE 802.3af/at/bt-compliant powered device (PD) interface controller . The T2P output indicates the number of classification events received during IEEE 802.3bt-compliant mutual identification and negotiation of available power . The LT4294 utilizes an external, low R DS(ON) N-channel hot swap MOSFET and supports the LT4320/LT4321 ideal diode bridges, to extend the end-to-end power delivery efficiency and eliminate costly heat sinks. The LT4294 also includes a power good output, onboard signature resistor , undervoltage lockout, and thermal protection. Start-up inrush current is adjustable with an external capacitor . Auxiliary power override is supported as low as 9V with the AUX pin. The LT4294 can be configured to support all possible 802.3bt, 802.3at and 802.3af power levels with external component changes. Pin-for-pin compatibility with the LT4275 family of PD Interface Controllers enables easy migration between L TPoE ++ PDs and IEEE 802. 3bt- compliant PDs. IEEE 802.3bt Single-Signature Powered Device Interface

APPLICATIONS

n IEEE 802.3af/at/bt Powered Device (PD) Controller n Supports Up to 71.3W PDs n 5-Event Classification Sensing n Superior Surge Protection (100V Absolute Maximum) n Wide Junction Temperature Range (–40°C to 125°C) n Overtemperature Protection n Integrated Signature Resistor n External Hot Swap N-Channel MOSFET for Lowest Power Dissipation and Highest System Efficiency n Configurable Aux Power Support as Low as 9V n Easy Migration Between L TPoE++® PDs and IEEE 802.3bt PDs n Pin Compatible with LT4275A/B/C n Available in 10-Lead MSOP and 3mm × 3mm DFN Packages n High Power Wireless Data Systems n Outdoor Security Camera Equipment n Commercial and Public Information Displays n High Temperature Industrial Applications L T4294 VPORT HSGATE GND

4294 TA01a

0.1µFVPORT DATA PAIR SPARE PAIR RUN 47nF 3.3k PSMN040-100MSE VIN VOUT ISOLATED POWER SUPPL Y OPTO PSE TYPE (TO µP) CPORT VAUX (9V TO 60V) All registered trademarks and trademarks are the property of their respective owners. SINGLE-SIGNATURE POWER CLASSIFICATION (AT PD INPUT) CLASS POWER 0 13W 1 3.84W 2 6.49W 3 13W 4 25.5W 5 40W 6 51W 7 62W 8 71.3W

Rev. B For more information www.analog.com ORDER INFORMATION ABSOLUTE MAXIMUM RATINGS RCLASS, RCLASS++ (Notes 1, 3) LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT4294IDD#PBF LT4294IDD#TRPBF LHBX 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LT4294HDD#PBF LT4294HDD#TRPBF LHBX 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT4294IMS#PBF LT4294IMS#TRPBF L THBW 10-Lead Plastic MSOP –40°C to 85°C LT4294HMS#PBF LT4294HMS#TRPBF L THBW 10-Lead Plastic MSOP –40°C to 125°C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. TOP VIEW GND DD PACKAGE 10-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 150°C, θJC = 5°C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB GND

1 VPORT

TJMAX = 150°C, θJC = 45°C/W PIN CONFIGURATION Operating Junction Temperature Range (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VPORT Operating Input Voltage At VPORT Pin l 60 V VSIG VPORT Signature Range At VPORT Pin l 1.5 10 V VCLASS VPORT Classification Range At VPORT Pin l 12.5 21 V VMARK VPORT Mark Range At VPORT Pin, Preceded by VCLASS l 5.6 10 V ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)

Rev. BFor more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VPORT Aux Mode Range At VPORT Pin, AUX > VAUXT l 8 60 V Signature/Class Hysteresis Window l 1.0 V VRESET Reset Threshold At VPORT Pin, Preceded by VCLASS l 2.6 5.6 V VHSON Hot Swap Turn-On Voltage l 35 37 V VHSOFF Hot Swap Turn-Off Voltage l 30 31 V Hot Swap On/Off Hysteresis Window l 3 V Supply Current Supply Current VVPORT = VHSSRC = 57V l 2 mA Supply Current During Classification VVPORT = 17.5V, RCLASS and RCLASS++ Open l 0.4 0.7 0.9 mA Supply Current During Mark Event VVPORT = VMARK After 1st Classification Event l 0.5 2.2 mA Detection and Classification Signature Detection Signature Resistance VSIG (Note 2) l 23.7 24.4 25.2 kΩ Resistance During Mark Event VMARK (Note 2) l 5.8 8.3 11 kΩ RCLASS/RCLASS++ Operating Voltage –10mA ≥ IRCLASS ≥ –36mA, VCLASS l 1.32 1.40 1.43 V Classification Signature Stability Time VVPORT Step to 17.5V, 34.8Ω from RCLASS or RCLASS++ to GND l 2 ms Analog/Digital Interface VAUXT AUX Threshold l 6.1 6.3 6.5 V IAUXH AUX Pin Hysteresis Current VAUX = 6.1V l 3.2 5 7 µA T2P Output Low 1mA Load l 0.8 V PWRGD Output Low 1mA Load l 0.8 V PWRGD Leakage Current VPWRGD = 60V l 5 µA T2P Leakage Current T2P = 60V l 5 µA Hot Swap Control IGPU HSGATE Pull-Up Current VHSGATE – VHSSRC = 5V (Note 6) l –27 –22 –18 µA VGOC HSGATE Open Circuit Voltage –10µA Load, with Respect to HSSRC l 10 18 V HSGATE Pull-Down Current VHSGATE – VHSSRC = 5V l 200 µA Timing fT2P T2P Frequency After PWRGD Valid, if IEEE802.3bt PSE Is Mutually Identified l 690 840 990 Hz T2P Duty Cycle in PoE Operation (Note 5) After 4-Event Classification After 5-Event Classification (RCLASS++ Has Resistor to GND) T2P Duty Cycle in Auxiliary Supply Operation (Note 5) VAUX > VAUXT, and RCLASS++ Has Resistor to GND 25 % Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Signature resistance specifications do not include resistance added by the external diode bridge which can add as much as 1.1k to the port resistance. Note 3: All voltages with respect to GND unless otherwise noted. Positive currents are into pins; negative currents are out of pins unless otherwise noted. Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 150°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 5: Specified as the percentage of the period which T2P is low impedance with respect to GND. Note 6: IGPU available in PoE powered operation. That is, available after VVPORT > VHSON and VAUX < VAUXT , over the range where VVPORT is between VHSOFF and 60V.

Rev. B For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Detection Signature Resistance vs Input Voltage Reset Threshold PWRGD, T2P Output Low Voltage vs Current VPORT Classification Thresholds T2P Frequency Input Current vs Input Voltage 25k Detection Signature Range VPORT Hot Swap Thresholds Supply Current During Power-On VPORT VOL TAGE (V) VPORT CURRENT (mA) 0.2 0.3 0.4 0.5 0.1

4294 G01

T = –40°C T = 25°C T = 75°C T = 125°C TEMPERATURE (°C) –50 VPORT VOL TAGE (V)32 100

4294 G02

12575–25 50250 Hot Swap OFF Hot Swap ON VPORT VOL TAGE (V) SUPPL Y CURRENT (mA) 1.0 1.5 2.0 0.5

4294 G03

T = –40°C T = 25°C T = 75°C T = 125°C VPORT VOL TAGE (V) SIGNATURE RESISTANCE (k/uni03A9) 25.25 25.75 26.25 24.75 24.25 23.75

4294 G04

T = –40°C T = 25°C T = 75°C T = 125°C TEMPERATURE (°C) –50 VPORT VOL TAGE (V)3.6 4.1 5.1 4.6 5.6 3.1 2.6 100

4294 G05

12575–25 50250 CURRENT (mA) VOL TAGE (V)

4294 G06

T = –40°C T = 25°C T = 75°C T = 125°C TEMPERATURE (°C) –50 VPORT VOL TAGE (V) 11.0 11.5 12.0 12.5 10.5 10.0 100

4294 G07

12575–25 50250 DETECT OR MARK TO CLASS CLASS TO MARK TEMPERATURE (°C) –50 T2P FREQUENCY (Hz) 840 740 890 940 990 790 690 100

4294 G08

12575–25 50250

Rev. BFor more information www.analog.com PIN FUNCTIONS GND (Pins 1, 5, DFN Exposed Pad Pin 11): Device Ground. Exposed Pad must be electrically and thermally connected to pin 5 and PCB GND. AUX (Pin 2): Auxiliary Sense. A resistive divider from the auxiliary power input to AUX sets the voltage at which the auxiliary supply takes over . In auxiliary power operation, HSGATE pulls down, the signature resistor disconnects, classification is disabled, the PWRGD pin is high imped- ance and T2P indicates max available power . The AUX pin sinks IAUXH when below its threshold voltage of VAUXT to provide hysteresis. Connect to GND when not used. RCLASS (Pin 3): Configurable PoE Classification Resistor . See Table 2. RCLASS++ (Pin 4): Configurable PoE Classification Resis- tor . See Table 2. T2P (Pin 6): PSE Type Indicator , Open-Drain Output. See the T2P Output section for pin behavior . PWRGD (Pin 7): Power Good Indicator , Open-Drain Output. Pulls to GND during VCLASS and inrush. HSSRC (Pin 8): External Hot Swap MOSFET Source. Con- nect to source of the external MOSFET . HSGATE (Pin 9): External Hot Swap MOSFET Gate Control, Output. Connect to gate of the external MOSFET . VPORT (Pin 10): PD interface upper power rail and external Hot Swap MOSFET drain connection. BLOCK DIAGRAM 4294 BD CONTROL LOGIC CLASSIFICATION LOGIC VOL TAGE AND CURRENT REFERENCES CHARGE PUMP OVERTEMP ON GND VPORT VPORT VGOC 6.3V~6.5V 1.4V 1.4V EN EN VPORT VPORT AUX RCLASS RCLASS++ T2P HSSRC HSGATE PWRGD

power limit established by the IEEE 802.3at standard. mutual identification and negotiation of available power . to maximize efficiency and delivered power . Related Parts section for a list of L TPoE++ products. a ∆V/∆I measurement technique. Figure 1. Type 3 or 4 PSE, 1-Event Class Sequence LT4321-based ideal diode bridge. another classification probe voltage, or powering up the PD. as many as 5 events before powering up the PD.

4294 F01

Figure 2. Type 2 PSE, 2-Event Class Sequence Table 2. Single-Signature Classification, Power Levels and Resistor Selection Figure 3. Type 3 or 4 PSE, 3-Event Class Sequence operate in a lower power state. setting the RCLS and RCLS++ resistor values. Table 1. PSE Allocated Power Note: Bold indicates the PD has been demoted.

4294 F02

4294 F03

3 PD presents its class signature to the PSE and is then

higher PDs in order to demote those PDs to Class 3 (13W). event differentiates a Class 4 PD from a higher Class PD. class signature 2 or 3, respectively, on the remaining events. 1% resistor between the RCLASS, RCLASS++ pins and GND. port as required by the IEEE 802.3 specification. IINRUSH. Design I INRUSH to be approximately ~100mA. Figure 5. Type 4 PSE, 5-Event Class Sequence Figure 4. Type 3 or 4 PSE, 4-Event Class Sequence Figure 6. Configuring IINRUSH

4294 F04

4294 F05

4294 F06

heat dissipation, and eases thermal design. HSGATE charges up to approximately 7V above HSSRC. with the IEEE 802.3 standard. T2P pin indicates max available power . active only when the AUX pin voltage is less than VAUXT. limits the voltage on the AUX pin. PSE allocated power are shown in Table 3. Table 3. T2P Response to Determine PSE Allocated Power

1 Hi-Z

1 Hi-Z 13W

Figure 8. Response Example for 25% Low-Z, 75% Hi-Z

4294 F08

Figure 7. AUX Threshold and Hysteresis Calculation

4294 F07

be sized to provide at least the PD Requested Power . are configured using the RCLASS and RCLASS++ pins. PD Class is 0-4 or 5-8, as shown in Table 2. allocated power , and the number of classification events. overheats if this condition persists abnormally. HSGATE pin, and disables classification. **Table 4. LT4294 Interoperability (T2P Response*, PSE Allocated Power , Number of Classification Events)** Note 1. Shade of blue indicates the PD has been demoted or denied power .

• Specified as the percentage of the period which T2P is low impedance with respect to GND.

** Auxiliary Power Supply must be sized to provide PD Requested Power .

Rev. BFor more information www.analog.com silicon diodes, Schottky diodes, and ideal diodes. When silicon or Schottky diode bridges are used, the diode for- ward voltage drops affect the voltage at the VPORT pin. The LT4294 is designed to tolerate these voltage drops. Note, the voltage parameters shown in the Electrical Characteristics are specified at the LT4294 package pins. A silicon diode bridge consumes up to 4% of the avail - able power . In addition, silicon diode bridges exhibit poor pairset-to-pairset unbalance performance. Each branch of a silicon diode bridge shares source/return current, and thermal runaway can cause large, non-compliant current unbalances between pairsets. While using Schottky diodes can help reduce the power loss with a lower forward voltage, the Schottky bridge may not be suitable for high temperature PD applications. Schottky diode bridges exhibit temperature induced leakage currents. The leakage current has a voltage dependency that can invalidate the measured detection signature. In addition, these leakage currents can back-feed through the unpowered branch and the unused bridge, violating IEEE 802.3 specifications. For high efficiency applications, the LT4294 supports an LT4321-based PoE ideal diode bridge that reduces the forward voltage drop from 0.7V to 20mV per diode while maintaining IEEE 802.3 compliance. The LT4321 simpli- fies thermal design, eliminates costly heatsinks, and can operate in space-constrained applications. Auxiliary Input Diode Bridge Some PDs are required to receive AC or DC power from an auxiliary power source. A diode bridge is typically required to handle the voltage rectification and polarity correction. In high efficiency applications, or in low auxiliary input voltage applications, the voltage drop across the rectifier cannot be tolerated. The LT4294 can be configured with an LT4320-based ideal diode bridge to recover the diode voltage drop and ease thermal design. For applications with auxiliary input voltages below 10V, the LT4294 must be configured with an LT4320-based ideal diode bridge to recover the voltage drop and guarantee the minimum VPORT voltage is within the VPORT AUX Mode Range as specified in the Electrical Characteristics table. An example of a high efficiency typical application circuit is show in the Typical Application section. Input Capacitor A 0.1μF capacitor is needed from VPORT to GND to meet the input impedance requirement in IEEE 802.3 and to properly bypass the LT4294. When operating with the LT4321, locally bypass each with a 0.047μF capacitor , thus keeping the total port capacitance within specification. T ransient Voltage Suppressor The LT4294 specifies an absolute maximum voltage of 100V and is designed to tolerate brief overvoltage events due to Ethernet cable surges. To protect the LT4294 from an overvoltage event, install a unidirectional transient volt- age suppressor (TVS) such as an SMAJ58A between the VPORT and GND pins. For PD applications that require an auxiliary power input, install a TVS between VIN and GND. See Layout Considerations for TVS placement. For extremely high cable discharge and surge protection, contact Analog Devices Applications. Exposed Pad The LT4294 DFN package has an exposed pad that is internally electrically connected to GND. The exposed pad may only be connected to GND on the printed circuit board. LAYOUT CONSIDERATIONS Avoid excessive parasitic capacitance on the RCLASS and RCLASS++ pins and place resistors RCLS and RCLS++ close to the LT4294. It is strictly required for maximum protection to place the 0.1μF input capacitor , CPD, and transient voltage suppres- sor as close to the LT4294 as possible. When operating the LT4294 with the LT4321, place a 0.047μF capacitor , CPD1, as close as possible to the LT4294 VPORT and GND pins (pin 10 and pin 5, respectively), and a 0.047μF capacitor , CPD2, as close as possible to the LT4321 OUTP and OUTN pins. APPLICATIONS INFORMATION

Rev. B For more information www.analog.com TYPICAL APPLICATIONS

4294 TA03

PSMN075-100MSE ×4 BSZ110N06NS3 ×4 PSMN075-100MSE ×4 WURTH 749022017 BG36 IN36 IN45 IN78 IN12 DATA PAIRS SPARE PAIRS OUTN EN OUTP SMAJ58A VPORT 158k 931k PWRGD AUX RCLASS HSGATE PSMN075-100MSE VAUX 9V TO 57VDC OR 24VAC MMSD4148 LT4294 GND EN TG12 BG45TG78 TG45BG78 HSSRC ISOLATED POWER SUPPLY GND RUN VOUT VIN 150nF 680µF 34.8/uni03A9 3.3k BG1 BG2 IN2 IN1 TG1 TG2 OUTP OUTN LT4320 100k 1µF 0.1µFCPD2 0.047µF CPD1 0.047µF High Efficiency 25.5W PD Solution with 12VDC and 24VAC Auxiliary Input

Rev. BFor more information www.analog.com PACKAGE DESCRIPTION 3.00 ±0.10 (4 SIDES) NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.40 ±0.10 BOTTOM VIEW—EXPOSED PAD 1.65 ±0.10 (2 SIDES) 0.75 ±0.05 R = 0.125 TYP 2.38 ±0.10 (2 SIDES) 106 PIN 1 TOP MARK (SEE NOTE 6)

0.200 REF

0.00 – 0.05 (DD) DFN REV C 0310 0.25 ±0.05 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 1.65 ±0.05 (2 SIDES)2.15 ±0.05 0.50 BSC 0.70 ±0.05 3.55 ±0.05 PACKAGE OUTLINE 0.25 ±0.05

0.50 BSC

10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699 Rev C) PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER

Rev. B For more information www.analog.com PACKAGE DESCRIPTION MSOP (MS) 0213 REV F 0.53 ±0.152 (.021 ±.006) SEATING PLANE 0.18 (.007) 1.10 (.043) MAX 0.17 –/uni00A00.27 (.007 – .011) TYP 0.86 (.034) REF 0.50 (.0197) BSC 1 2 3 4 5 4.90 ±0.152 (.193 ±.006) 0.497 ±0.076 (.0196 ±.003) REF8910 7 6 3.00 ±0.102 (.118 ±.004) (NOTE 3) 3.00 ±0.102 (.118 ±.004) (NOTE 4) NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.254 (.010) 0° – 6° TYP DETAIL “A” DETAIL “A” GAUGE PLANE 5.10 (.201) MIN 3.20 – 3.45 (.126 – .136) 0.889 ±0.127 (.035 ±.005) RECOMMENDED SOLDER PAD LAYOUT 0.305 ±0.038 (.0120 ±.0015) TYP 0.50 (.0197) BSC 0.1016 ±0.0508 (.004 ±.002) 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661 Rev F)

Rev. BFor more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 09/18 Updated to IEEE 802.3af/at/bt (Draft 3.5) Revised T2P Output Applications Information Revised External Interface and Component Selection Applications Information 1-16 10, 11 11, 12 B 04/19 Removed Draft Number Added Table 4 – Interoperability 1-16

Rev. B For more information www.analog.com  ANALOG DEVICES, INC. 2017-2019 www.analog.com TYPICAL APPLICATION RELATED PARTS IEEE 802.3bt-Compliant > 99% Efficiency 71.3W Powered Device

4294 TA02

PSMN075-100MSE ×4 PSMN075-100MSE ×4 WURTH 749022016 BG36 IN36 IN45 IN78 IN12 DATA PAIRS SPARE PAIRS OUTN EN OUTP SMAJ58A VPORT PWRGD AUX RCLASS T2P RCLASS++ HSGATE PSMN040-100MSE LT4294 GND EN TG12 BG45TG78 TG45BG78 HSSRC ISOLATED POWER SUPPLY GND RUN VOUT VIN22µF RCLS 49.9/uni03A9 RCLS++ 118/uni03A9 47nF 3.3k 100kCPD2 0.047µF CPD1 0.047µF OPTO PSE TYPE (TO µP) PART NUMBER DESCRIPTION COMMENTS LT4293 L TPoE++/IEEE 802.3bt PD Interface Mutually Identified with L TPoE++ and IEEE 802.3bt PSEs LT4295 IEEE 802.3bt PD with Forward/Flyback Switching Regulator Controller External Switch, IEEE 802.3bt Support, Configurable Class, Forward or No-Opto Flyback Operation, Frequency, PG/SG Delays, Soft-Start, and Aux Support as Low as 9V, Including Housekeeping Buck, Slope Compensation LT4321 PoE Ideal Diode Bridge Controller Controls 8-NMOSFETs for IEEE-Required PD Voltage Rectification without Diode Drops LT4320/LT4320-1 Ideal Diode Bridge Controller 9V – 72V, DC to 600Hz Input. Controls 4-NMOSFETs, Voltage Rectification without Diode Drops LTC4292/LTC4291-1 4-Port IEEE 802.3bt PSE Controller T ransformer Isolation, Supports IEEE 802.3bt PDs LTC4279 Single PoE/PoE+/L TPoE++ PSE Controller Supports IEEE 802.3af, IEEE 802.3at, L TPoE++ and Proprietary PDs LTC4290/LTC4271 8-Port PoE/PoE+/L TPoE++ PSE Controller T ransformer Isolation, Supports IEEE 802.3af, IEEE 802.3at and L TPoE++ PDs LT4276A/B/C L TPoE++/PoE+/PoE PD with Forward/ Flyback Switching Regulator Controller External Switch, L TPoE++ Support, User-Configurable Class, Forward or No-Opto Flyback Operation, Frequency, PG/SG Delays, Soft-Start, and Aux Support as Low as 9V, Including Housekeeping Buck, Slope Compensation LT4275A/B/C L TPoE++/PoE+/PoE PD Controller External Switch, L TPoE++ Support LTC4269-1 IEEE 802.3at PD Interface with Integrated Flyback Switching Regulator 2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller , 50kHz to 250kHz, Aux Support LTC4269-2 IEEE 802.3at PD Interface with Integrated Forward Switching Regulator 2-Event Classification, Programmable Class, Synchronous Forward Controller , 100kHz to 500kHz, Aux Support LTC4278 IEEE 802.3at PD Interface with Integrated Flyback Switching Regulator 2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller , 50kHz to 250kHz, 12V Aux Support LTC4267/LTC4267-1/ LTC4267-3 IEEE 802.3af PD Interface with Integrated Switching Regulator Internal 100V, 400mA Switch, Programmable Class, 200/300kHz Constant Frequency PWM