LT4261-2

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Technical content

Rev. BFor more information www.analog.comDocument Feedback TYPICAL APPLICATION FEATURES DESCRIPTION High Power Negative Voltage Hot Swap Controller with Energy Monitor The LT C®4284 negative voltage hot swap controller drives external N-channel MOSFETs to allow a board to be safely inserted and removed from a live backplane. The dual- gate, multi-mode drivers optimize the MOSFET safe oper- ating area (SOA) for a variety of power levels. The SOA timer limits MOSFET temperature rise for reliable protec- tion against overstresses. An I2C interface and onboard gear-shift ADC allow moni- toring of board current, voltage, power , energy, and fault status. An available single-wire broadcast mode simplifies the interface by eliminating two isolators. The included EEPROM provides black-box capturing and nonvolatile configuration of fault behavior . Additional features respond to input UV/OV , interrupt the host when a fault has occurred, notify when output power is good, detect insertion of a board, turn off the MOSFETs if an external supply monitor fails to indicate power good within a timeout period, and auto-reboot after a program- mable delay following a host commanded turn-off. –52V/2500W Hot Swap Controller with Telemetry Startup Behavior

APPLICATIONS

n Drives T wo Gates for High Power Applications n Configurable Parallel, Staged Start or Single Modes n Protects MOSFET with SOA Timer n Programmable 15mV to 30mV Current Limit Sense Voltage with <3.3% Accuracy and Adjustable Foldback n 8-Bit to 16-Bit Gear-Shift ADC with 0.7% Accuracy n Monitors Voltages, Currents, Power and Energy n Nonvolatile Configuration and Fault Recording n Floating Topology for Rugged High Voltage Operation n Selectable Inrush Control: dV/dt or Current Limit n I2C/SMBus or Single-Wire Broadcast Interfaces n Min/Max ADC Measurement Logging with Alerts n Reboots on I2C Command with Programmable Delay n Adjustable Input UV/OV Thresholds and Hysteresis n 44-Pin 5mm × 8mm QFN Package n Telecom Infrastructure n –48V Distributed Power Systems n Servers and Data Centers n Power Monitors All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. patents, including 8230151, 7382167, 9634480, 9634481, 10263414. 402k 1µF 5m/uni03A9 4 × 1k IN SERIES 0.25W EACH 0.1µF 2 × IPT020N10N3 PSMN7R6-100BSE 100k 10k 316k 10.2k 316k 2.2nF 2000µF

4284 TA01a

0.33m/uni03A9 7.68k 470nF 10.2k RTN UVH UVL OV –52V INPUT ADIN TMR V EE MODE INTV CC SENSE1 GATE1 SENSE2 GATE2 DRAIN V Z V IN RTNS SCL SDAI SDAO ALERT# ADIO PGIO L TC4284 RTN (SHORT PIN) V EE DRNS SENSE2 EN# UV = 43.5V UV RELEASE AT 48.5V OV = 59V OV RELEASE AT 58V V EE V EE V EE V EE SENSE1 RAMP VOUT VLOAD GATE1 10V/DIV 100ms/DIV

4284 TA01b

–52V VOUT 50V/DIV IINRUSH 1A/DIV

Rev. B For more information www.analog.com TABLE OF CONTENTS A E O T Co D E xample 1: Design Procedure of Parallel Mode with E xample 2: Design Procedure of Low Stress Staged Start Mode with Single Capacitor on TMR Pin and L R D E Fa Di Bu S TART, REPEATED START and STOP Conditions ...56 ACK Tr C W R R B A S Da Sin R T T

Description

I T I P Tu O SO O C C FE I D Pa H Lo S Ov Und F P E C

Rev. BFor more information www.analog.com PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS Supply Voltage: Input Voltages ADC+ , ADC–, ADIN1-4, ADR0, ADR1, DRNS, OV, RTNS, SCL, SDAI, SENSE1+, SENSE1– , SENSE2+, SENSE2–, Output Voltages Input Currents: O perating Ambient Temperature Range C to 150°C (Notes 1 and 2) TOP VIEW UHG PACKAGE 44-LEAD (5mm × 8mm) PLASTIC QFN TJMAX = 150°C, θJA = 36°C/W EXPOSED PAD (PIN 45) IS VEE, CONNECTION OPTIONAL 44 44 43 42 41 40 39 38 37 15 16 17 18 19 20 21 22 EN# UVL UVH OV VREF VOUTTH ADIN1 ADIN2 ADIN3 ADIN4 V EE SENSE2– ADC– SENSE1– SDAI SDAO ALERT# VEE PGIO4 PGIO3 PGIO2 PGIO1 ADIO4 ADIO3 ADIO2 ADIO1 TMR RAMP VZ VIN INTVCC WP MODE ADR1 ADR0 SCL SENSE1 ADC+ SENSE2+ GATE1 GATE2 DRAIN DRNS RTNS VEE ORDER INFORMATION TUBE TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4284CUHG#PBF LTC4284CUHG#TRPBF 4284 44-Lead (5mm × 8mm) Plastic QFN 0°C to 70°C LTC4284IUHG#PBF LTC4284IUHG#TRPBF 4284 44-Lead (5mm × 8mm) Plastic QFN –40°C to 85°C LTC4284HUHG#PBF LTC4284HUHG#TRPBF 4284 44-Lead (5mm × 8mm) Plastic QFN –40°C to 125°C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

Rev. B For more information www.analog.com

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Supply VIN Shunt Regulated Voltage at VIN IIN + IVZ = 4mA l 10.8 11.5 12 V ∆VIN Load Regulation at VIN IIN + IVZ = 4mA to 35mA l 250 500 mV IIN VIN Supply Current VIN = 10.5V l 2.5 4 mA VIN(UVLO) VIN Undervoltage Lockout Threshold V IN Rising l 7.5 8.1 8.6 V ∆VIN(UVLO) VIN Undervoltage Lockout Hysteresis l 0.4 0.5 0.6 V IVZ VZ Input Current VIN = 10.5V, VZ = 15V l 20 µA INTVCC Internal 5V LDO Voltage ILOAD = 1mA to 30mA, IIN + IVZ = 35mA l 4.75 5.05 5.35 V VCC(UVLO) INTVCC Undervoltage Lockout Threshold INTV CC Rising l 3.65 4 4.3 V ∆VCC(UVLO) INTVCC Undervoltage Lockout Hysteresis l 0.12 0.2 0.3 V Gate Drive V GATE Gate Drive Voltage for GATE1,2 l VIN – 0.3 V IN VIN + 0.3 V VGATE(TH) Gate High Threshold for Asserting Power Good GATE1,2 Rising l VIN – 2.1 V IN – 1.8 V IN – 1.5 V VGATE(HYST) Gate High Hysteresis l 0.3 0.7 1.1 V IGATE(UP) GATE1,2 Pull-Up Current VGATE = 4V l –40 –50 –75 µA IGATE(DN) GATE1,2 Fast Pull-Down Current ∆V SENSE1,2 = VILIM(FAST) + 10mV, VGATE = 7V l 0.5 1.2 2 A GATE1,2 Current Limit Pull-Down Current ∆V SENSE1,2 = VILIM + 5mV, VGATE = 7V l 12.5 25 50 mA GATE1,2 Turn Off Pull-Down Current TMR, OV , EN# = High, UVL = Low, V GATE = l 4 9 20 mA On/Off Timing tPHL(SENSE) ∆VSENSE1,2 High to GATE1,2 Low Propagation Delay ILIM = 0000b, ∆VSENSE1,2 Steps from 0mV to 100mV, VGATE < 3V, GATE1,2 Open l 60 150 ns tPHL(GATE) GATE1,2 Turn Off Propagation Delay TMR, OV , EN# = High, UVL = Low, VGATE < 3V, GATE1,2 Open l 0.5 1 µs tDL(DB) Debounce Delay, Auto-Retry Delay Following Undervoltage or PGI Fault l 115 128 141 ms tDL(PG) Power Good Delay l 230 256 282 ms tDL(PGIWD) Power Good Input Watchdog Timer l 461 512 563 ms tDL(RTRY) Auto-Retry Delay Following Overcurrent, FET Bad or External Fault (Table 11) COOLING_DL = 000b – 111b l ±10 % tDL(RTCRST) Auto-Retry Counter Reset Delay OC_RETRY, FET_BAD_RETRY = 01b, 10b l 14.8 16.4 18 s tDL(FETBAD) FET Bad Fault Timer Delay (Table 11) FTBD_DL = 00b – 11b l ±10 % tDL(RBT) Auto-Reboot Delay (Table 23) After RBT_EN Bit is Set Via I2C Interface, RBT_DL = 000b – 111b l ±10 % dV/dt Control IRAMP RAMP Output Current Startup Only, dV/dt Control Enabled l –2.25 –2.5 –2.75 µA IRAMP(DN) RAMP Discharge Current VRAMP = 1.2V l 1 4 10 mA The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, IIN + IVZ = 4mA with VIN Connected to VZ. (Note 2)

Rev. BFor more information www.analog.com SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Drain Monitor VD,PG(TH) DRAIN Input Threshold for Power Good DRAIN Falling l 2 2.05 2.1 V ∆VD,PG(HYST) DRAIN Input Hysteresis for Power Good 20 mV VD,FET(TH) DRAIN Input Threshold for FET Bad Timer and TMR Pull-Up Current (Table 11) DRAIN Rising, VDTH = 00b – 11b l ±10 % ∆VD,FET(HYST) DRAIN Input Hysteresis with VD,FET(TH) 10 mV IDRAIN DRAIN Input Current VDRAIN = 200mV l 0 ±0.1 µA VDRAIN = 2 V l 0 ±1 µA Current Limit VILIM Current Limit Voltage DAC Zero-Scale ILIM = 0000b l 14.5 15 15.5 mV Current Limit Voltage DAC Full-Scale ILIM = 1111b l 29 30 31 mV Current Limit Voltage DAC INL l 0 ±50 µV ∆VILIM Current Limit Voltage Mismatch between Channel 1 and Channel 2 l 0 ±350 µV aSTARTUP Current Limit Foldback Factor at Startup RTNS = 1.8V, DRNS = 0, 1.8V FB = 01b l 45 50 55 % FB = 10b l 16 20 24 % FB = 11b l 7 10 13 % aNORMAL Current Limit Foldback Factor in Normal Operation RTNS = DRNS = 1.8V FB = 01b l 45 50 55 % FB = 10b l 15 20 26 % FB = 11b l 6 10 16 % VILIM(FAST) Fast Pull-Down Sense Threshold Voltage ILIM = 0000b l 20 30 40 mV ILIM = 1111b l 47 60 70 mV ISENSE+ SENSE1,2+ Input Current SENSE1,2+ = 33mV l 0 ±1 µA ISENSE– SENSE1,2– Input Current SENSE1,2– = SENSE1,2+ = 0 l –4 –10.5 –15 µA Circuit Breaker/SOA Timer ITMR(UP) TMR Pull-Up Current in Current Limit Onset DRNS = 0V, TMR = 1V l –1.5 –2 –2.5 µA Startup in Foldback dV/dt Control Disabled, DRNS = 1.8V, TMR = 1V FB = 00b l –192 –202 –212 µA FB = 01b l –96 –102 –108 µA FB = 10b l –39 –42 –45 µA FB = 11b l –20 –22 –24 µA Startup in dV/dt dV /dt Control Enabled, DRNS = 1.8V, TMR = 1V l –192 –202 –212 µA Hard Short in Normal Operation DRNS = 1.8V, TMR = 1V l –192 –202 –212 µA ITMR(DN) TMR Pull-Down Current DRAIN < VD,FET(TH) or Start into dV/dt Control, THERM_TMR = 0, TMR = 1V l 1.6 2 2.3 µA ITMR(RST) TMR Reset Current EN# = High, TMR = 1V l 3 5 8 mA VTMRH(TH) TMR Fault Threshold TMR Rising l 2.028 2.048 2.068 V VTMRH(HYST) TMR Fault Hysteresis 20 mV VTMRL(TH) TMR Low Status Threshold TMR Falling l 80 100 120 mV VTMRL(HYST) TMR Low Hysteresis 20 mV The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, IIN + IVZ = 4mA with VIN Connected to VZ. (Note 2)

Rev. B For more information www.analog.com SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Input Pins VMODE(TH) MODE Input Thresholds Threshold 1 l 0.4 0.7 1 V Threshold 2 l INTVCC – 0.85 INTVCC – 0.55 INTVCC – 0.25 V Threshold 3 l INTVCC + 0.5 INTVCC + 1.5 INTVCC + 2.5 V IMODE(IN) Allowable Leakage in Open State Mode 1 l ±10 µA VUVH(TH) UVH Input Threshold UVH Rising l 2.028 2.048 2.068 V VUVL(TH) UVL Input Threshold UVL Falling l 1.815 1.833 1.851 V ∆VUV(HYST) Built-In UV Hysteresis UVH and UVL Tied Together l 204 215 226 mV dVUV(HYST) UVH, UVL Minimum Hysteresis 11 mV VUVLR(TH) UVL Reset Threshold UVL Falling l 1 1.024 1.05 V ∆VUVLR(HYST) UVL Reset Hysteresis 21 mV VOV(TH) OV Input Threshold OV Rising l 1.392 1.406 1.42 V ∆VOV(HYST) OV Input Hysteresis l 10 24 38 mV VOUTL(TH) VOUT Low Threshold RTNS – DRNS Falling, VOUTTH = 0.8V l VOUTTH – 0.06 VOUTTH VOUTTH + 0.06 V ∆VOUTL(HYST) VOUT Low Hysteresis 40 mV VEN#(TH) EN# Input Threshold EN# Falling l 1.248 1.28 1.312 V ∆VEN#(HYST) EN# Input Hysteresis 18 mV VWP(TH) WP Input Threshold WP Rising l 1.2 1.65 2.1 V ∆VWP(HYST) WP Input Hysteresis 100 mV VINPUT(TH) ADIO1-4, PGIO1-4 Input Threshold ADIO1-4, PGIO1-4 Rising l 1.248 1.28 1.312 V ∆VINPUT(HYST) ADIO1-4, PGIO1-4 Input Hysteresis 18 mV IINPUT DRNS, EN#, OV , RTNS, UVL, UVH, VOUTTH, WP Input Current DRNS, EN#, OV , RTNS, UVL, UVH, VOUTTH, WP = 3V l 0 ±1 µA Output Pins VOL ADIO1-4, PGIO1-4 Output Low Voltage I = 5mA l 0.15 0.4 V ILEAK ADIO1-4, PGIO1-4 Leakage Current ADIO1-4 = INTV CC, PGIO1-4 = VIN l 0 ±1 µA VREF VREF Output Voltage IVREF = –200µA, 0, 400µA l 1.01 1.024 1.038 V rREF VREF to ADC VFS Ratio IVREF = –200µA, 0, 400µA l 0.495 0.5 0.505 ADC Resolution (No Missing Codes) (Note 6) RTNS, ADIN1-4, ADIO1-4, DRNS, DRAIN, (ADC+ – ADC–), Power ADC = 000b l 8 Bits ADC = 010b l 10 Bits ADC = 100b l 12 Bits ADC = 110b l 14 Bits ADC = xx1b l 14 16 Bits (SENSE1,2+ – SENSE1,2–), (ADIN2 – ADIN1), (ADIN4 – ADIN3), (ADIO2 – ADIO1), (ADIO4 – ADIO3) ADC = 000b l 7 Bits ADC = 010b l 9 Bits ADC = 100b l 11 Bits ADC = 110b l 13 Bits ADC = xx1b l 13 15 Bits The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, IIN + IVZ = 4mA with VIN Connected to VZ. (Note 2)

Rev. BFor more information www.analog.com SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VFS Full-Scale Voltage Single-Ended Inputs 2.048 V Differential Inputs 32.768 mV LSB LSB Step Voltage RTNS, ADIN1-4, ADIO1-4, DRNS, DRAIN ADC = 000b 8 mV ADC = 010b 2 mV ADC = 100b 0.5 mV ADC = 110b 0.125 mV ADC = xx1b 0.03125 mV ADC+ – ADC– ADC = 000b 128 µV ADC = 010b 32 µV ADC = 100b 8 µV ADC = 110b 2 µV ADC = xx1b 0.5 µV SENSE1,2+ – SENSE1,2–, ADIN2 – ADIN1, ADIN4 – ADIN3, ADIO2 – ADIO1, ADIO4 – ADIO3 ADC = 000b 256 µV ADC = 010b 64 µV ADC = 100b 16 µV ADC = 110b 4 µV ADC = xx1b 1 µV V OS Offset Error (Note 7) Single-Ended Inputs l 0 ±0.125 % V FS Differential Inputs l 0 ±0.25 % V FS INL Integral Nonlinearity (Note 7) ADIN1-4, ADIO1-4, RTNS, DRNS, DRAIN, ADC + – ADC– l ±0.01 ±0.06 % V FS SENSE1,2+ – SENSE1,2–, ADIN2 – ADIN1, ADIN4 – ADIN3, ADIO2 – ADIO1, ADIO4 – ADIO3 l ±0.02 ±0.12 % V FS FSE Full-Scale Error (Note 7) Single-Ended Inputs l ±0.7 % Differential Inputs l ±1.2 % Power l ±1.5 % Energy l ±5 % fCONV Refresh Rate in Continuous Mode (Table 12) l ±5 % IADC+ ADC+ Input Current ADC+ = 33mV l 0 ±1 µA IADC– ADC+ Input Current ADC– = ADC+ = 0 l –3 –7 µA RADIN(SE) ADIN1-4, ADIO1-4 Input Impedance, Single-Ended V = 3V l 3 MΩ IADIN(SE) ADIN1-4, ADIO1-4 Input Current, Single-Ended V = 3V l 0 ±1 µA IADIN(DIFF) ADIN1, ADIN3, ADIO1, ADIO3 Input Current, Differential Mode ADIN1, ADIN3, ADIO1, ADIO3 = 0, ADIN2, ADIN4, ADIO2, ADIO4 = 0 l –3 –7 µA ADIN2, ADIN4, ADIO2, ADIO4 Input Current, Differential Mode ADIN2, ADIN4, ADIO2, ADIO4 = 33mV l 0 ±1 µA The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, IIN + IVZ = 4mA with VIN Connected to VZ. (Note 2)

Rev. B For more information www.analog.com Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All Currents into device pins are positive and all currents out of device pins are negative. All voltages are referenced to V EE unless otherwise specified. Note 3: When VZ is connected to VIN, an internal shunt regulator limits the voltage to a minimum of 11V. Driving the pins above 11V may damage the part. These pins can be safely biased by a higher voltage using a resistor or current source that limits the current below 50mA. Note 4: An internal clamp limits DRAIN to a minimum of 3.2V. Driving this pin to voltages above the clamp may damage the part. The pin can SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I2C Interface VADR(H) ADR0, ADR1 Input High Threshold l INTVCC – 0.85 INTVCC – 0.55 INTVCC – 0.25 V VADR(L) ADR0, ADR1 Input Low Threshold l 0.4 0.7 1 V IADR(IN) Allowable Leakage Current l ±10 µA VALERT#(OL) ALERT# Output Low Voltage I = 5mA l 0.15 0.4 V VSDAO(OL) SDAO Output Low Voltage I = 20mA l 0.25 0.6 V ISDAO,ALERT# SDAO, ALERT# Input Current SDAO, ALERT# = INTVCC l 0 ±1 µA VSDAI,SCL(TH) SDAI, SCL Input Threshold l 1.5 1.75 2 V ISDAI,SCL SDAI, SCL Input Current SDAI, SCL = INTVCC l 0 ±1 µA I2C Interface Timing (Note 7) fSCL(MAX) Maximum SCL Clock Frequency 400 kHz tLOW Minimum SCL Low Period 0.65 1.3 µs tHIGH Minimum SCL High Period 50 600 ns tBUF(MIN) Minimum Bus Free Time Between Stop/ Start Condition 0.12 1.3 µs tHD,STA(MIN) Minimum Hold Time After (Repeated) Start Condition 140 600 ns t SU,STA(MIN) Minimum Repeated Start Condition Set-Up Time 30 600 ns t SU,STO(MIN) Minimum Stop Condition Set-Up Time 30 600 ns tHD,DATI(MIN) Minimum Data Hold Time Input –100 0 ns tHD,DATO(MIN) Minimum Data Hold Time Output 300 600 900 ns tSU,DAT(MIN) Minimum Data Set-Up Time Input 30 100 ns tSP(MAX) Maximum Suppressed Spike Pulse Width 50 110 250 ns tRST Stuck-Bus Reset Time SCL or SDAO Held Low 26 30 34 ms CX SCL, SDA Input Capacitance SDAI Tied to SDAO 5 10 pF Single-Wire Broadcast Timing fBC Broadcast Data Rate (Table 11) l ±10 % EEPROM Endurance 1 Cycle = 1 Write (Notes 8, 9) l 10,000 Cycles Data Retention (Notes 8, 9) l 20 Years tWRITE EEPROM Write Time per Byte l 1.2 2.2 3 ms The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, IIN + IVZ = 4mA with VIN Connected to VZ. (Note 2) be safely tied to higher voltages through a resistor that limits the current below 1.5mA. Note 5: An internal clamp limits EN# to a minimum of 6V. Driving this pin to voltages above the clamp may damage the part. The pin can be safely tied to higher voltages through a resistor that limits the current below 5mA. Note 6: Guaranteed by design and characterization. Not tested in production. Note 7: Tested at 12-bit resolution and guaranteed for other resolutions by design and characterization. Note 8: EEPROM endurance and retention are guaranteed by design, characterization and correlation with statistical process controls. Note 9: EEPROM endurance and retention will be degraded when T J > 85°C.

Rev. BFor more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Shunt Regulator Voltage vs Input Current VZ Input Current vs Temperature INTVCC Voltage vs Load Current GATE Output High Voltage vs Leakage Current GATE Pull-Down Current vs SENSE Input Voltage GATE Turn-Off Time vs SENSE Input Voltage I2C TIMING DIAGRAM tSP tBUF tSU,STO tSP tHD,STA START CONDITION STOP CONDITION tSU,STA tHD,DATI tHD,DATO REPEATED START CONDITION REPEATED START CONDITION tSU,DAT SDA SCL tHD,STA 4284 TD V IN INPUT CURRENT (mA) 11.0 11.2 11.4 11.6 11.8 12.0 V IN VOL TAGE (V)

4284 G01

I GATE (µA) –10 –20 –30 –40 –50 –60 –70 V GATE (V)

4284 G04

V Z = 15V V IN = 10.5V TEMPERATURE (°C) –50 –25 100 125 V Z INPUT CURRENT (µA)

4284 G02

V ILIM = 15mV V GATE = 7V FAST PULL-DOWN CURRENT LIMIT SENSE INPUT VOL TAGE (mV) 100 0.001 0.01 0.1 GATE PULL-DOWN CURRENT (A)

4284 G05

I IN = 35mA LOAD CURRENT (mA) 4.96 4.98 5.00 5.02 5.04 5.06 5.08 INTV CC VOL TAGE (V)

4284 G03

V ILIM = 15mV GATE FALLING FROM 11.5V TO 3V FAST PULL-DOWN C GATE = 100nF GATE OPEN SENSE INPUT VOL TAGE (mV) 100 0.01 0.1 100 GATE TURN-OFF TIME (µs)

4284 G06

Rev. B For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS GATE Fast Pull-Down Current vs GATE Voltage Current Limit Voltage Error vs ILIM Code Current Limit Foldback Profiles TMR Pull-Up Current vs DRNS Voltage TMR Pull-Up Current vs SENSE Input Voltage ADIO Output Low Voltage vs Load Current PGIO Output Low Voltage vs Load Current VREF Output Voltage vs Load Current ADC Full-Scale Error vs Temperature V ILIM(FAST) = 30mV SENSE INPUT = 40mV GATE VOL TAGE (V) 0.4 0.8 1.2 1.6 GATE FAST PULL-DOWN CURRENT (A)

4284 G07

100% V ILIM 98% V ILIM 50% V ILIM 20% V ILIM 10% V ILIM V DRNS (V) 0.6 1.2 1.8 2.4 100 200 300 400 TMR PULL–UP CURRENT (µA)

4284 G10

∆VSENSE1 = ∆VSENSE1 = ∆VSENSE1 = ∆VSENSE1 = ∆VSENSE1 = T A = –40°C T A = 25°C T A = 85°C T A = 125°C LOAD CURRENT (mA) 0.20 0.40 0.60 0.80 1.00 PGIO OUTPUT LOW VOL TAGE (V)

4284 G13

V ILIM1 AND V ILIM2

50 UNITS

V ILIM ERROR (%)

4284 G08

V ILIM = 15mV V DRAIN > V D,FET(TH) POWER GOOD LATCHED CURRENT LIMIT V DRNS = 1.8V V DRNS = 1.2V V DRNS = 0.6V V DRNS = 0V SENSE1 (mV) 100 150 200 250 TMR PULL-UP CURRENT (µA)

4284 G11

LOAD CURRENT (µA) –400 –200 200 400 600 1.022 1.023 1.024 1.025 1.026 VREF VOL TAGE (V)

4284 G14

V ILIM = 15mV V RTNS = 1.8V FB = 00 LPFB = 0 LPFB = 1 POWER GOOD LATCHED V RTNS – V DRNS (V) 0.3 0.6 0.9 1.2 1.5 1.8 CURRENT LIMIT VOL TAGE (mV)

4284 G09

T A = –40°C T A = 25°C T A = 85°C T A = 125°C LOAD CURRENT (mA) 0.20 0.40 0.60 0.80 ADIO OUTPUT LOW VOL TAGE (V)

4284 G12

TEMPERATURE (°C) –50 –25 100 125 –0.2 –0.1 0.1 0.2 0.3 ADC FULL-SCALE ERROR (%)

4284 G15

Rev. BFor more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS 12-Bit Voltage ADC DNL vs Code 12-Bit Current ADC INL vs Code 12-Bit Current ADC DNL vs Code 16-Bit Voltage ADC Noise Histogram 16-Bit Current ADC Noise Histogram 12-Bit ADC Input Signal Attenuation (Low Frequencies) Voltage ADC Total Unadjusted Error (TUE) vs Code Current ADC Total Unadjusted Error (TUE) vs Code 12-Bit Voltage ADC INL vs Code INPUT = VRTNS RESOLUTION = 12-BIT CODE 1024 2048 3072 4096 –0.10 –0.05 0.05 0.10 TUE (%)

4284 G16

INPUT = V RTNS CODE 1024 2048 3072 4096 –1.0 –0.8 –0.6 –0.4 –0.2 0.0 0.2 0.4 0.6 0.8 1.0 DNL (LSB)

4284 G19

V RTNS = 1.024V 1LSB = 31.25µV CODE VARIATION (LSB) 1000 2000 3000 4000 5000 6000 NUMBER OF READINGS

4284 G22

INPUT = V ADC – V ADC RESOLUTION = 12-BIT CODE 1024 2048 3072 4096 –0.10 –0.05 0.05 0.10 TUE (%)

4284 G17

INPUT = V ADC – V ADC CODE 1024 2048 3072 4096 –1.0 –0.8 –0.6 –0.4 –0.2 0.0 0.2 0.4 0.6 0.8 1.0 INL (LSB)

4284 G20

V ADC – V ADC = 16.4mV 1LSB = 500nV CODE VARIATION (LSB) 2000 4000 6000 8000 NUMBER OF READINGS

4284 G23

INPUT = V RTNS CODE 1024 2048 3072 4096 –1.0 –0.8 –0.6 –0.4 –0.2 0.0 0.2 0.4 0.6 0.8 1.0 INL (LSB)

4284 G18

INPUT = V ADC – V ADC CODE 1024 2048 3072 4096 –1.0 –0.8 –0.6 –0.4 –0.2 0.0 0.2 0.4 0.6 0.8 1.0 DNL (LSB)

4284 G21

INPUT = V RTNS FREQUENCY (Hz) 100 125 150 –50 –40 –30 –20 –10 REJECTION (dB)

4284 G24

Rev. B For more information www.analog.com PIN FUNCTIONS ADC+ (Pin 16): Positive Current Sense Kelvin Input to ADC. Connect to the tap of an external resistive divider between SENSE1+ and SENSE2+ to measure the average between those two pins. Connect to SENSE1+ when using a single sense resistor . Connect to VEE if unused. ADC− (Pin 13): Negative Current Sense Kelvin Input to ADC. Connect to the tap of an external resistive divider between SENSE1 − and SENSE2− to measure the average between those two pins. Connect to SENSE1− when using a single sense resistor . Connect to VEE if unused. ADIN1–ADIN4 (Pins 7–10): ADC Inputs. A single-ended voltage between 0V and 2.048V applied to each ADIN is measured by the on-chip ADC. T wo differential volt - ages ADIN2 – ADIN1 and ADIN4 – ADIN3, if enabled, are also measured by the ADC with a full scale of 32.768mV. Connect to V EE if unused. ADIO1–ADIO4 (Pins 25– 28): General Purpose Inputs/ Outputs and ADC Inputs. Configurable to logic inputs and general purpose outputs (open-drain). See Table 13 for details. The single-ended voltages at ADIOs are mea- sured by the ADC with a full scale of 2.048V. The dif- ferential voltages ADIO2 – ADIO1 and ADIO4 – ADIO3, if enabled, are also measured by the ADC with a full scale of 32.768mV. Connect to V EE if unused. ADR0, ADR1 (Pin 38, Pin 39): Serial Bus Address Inputs. Connecting to VEE, OPEN or INTVCC configures one of nine possible addresses, with one dedicated to the single-wire broadcast mode. Do not bias with an external supply. See Table 2 in Applications Information for address decoding. ALERT# (Pin 34): Fault Alert Output. Open-drain logic output that pulls to V EE when a fault occurs to alert the host controller . A fault alert is enabled by the FAULT_ ALERT and ADC_ALERT registers. See Tables 15 and 16 in Applications Information for details. Connect to V EE if unused. DRAIN (Pin 20): Drain Sense Input. Connect an external 100k resistor between this pin and the drain terminal of the N-channel MOSFET . A DRAIN voltage below 2.048V is one of the conditions to assert power good outputs and turn on GATE2 in the high stress staged start (Mode 3) or low stress staged start mode (Mode 4). When DRAIN voltage is above a voltage configurable between 72mV and 203mV, the FET Bad fault timer is started and the TMR output current is enabled when not in current limit. DRAIN is internally clamped to a minimum of 3.2V. INPUT = V RTNS REJECTION LIMITED BY QUANTIZATION NOISE FREQUENCY (kHz) 100 150 200 –80 –60 –40 –20 REJECTION (dB)

4284 G25

300 UNITS

260°C 3 CYCLES INPUT = V ADIN1 FSE SHIFT (%) –0.3 –0.2 –0.1 0.0 0.1 0.2 0.3 0.4 0.5 100 NUMBER OF UNITS

4284 G26

260°C 3 CYCLES V ILIM SHIFT (%) –1.2 –0.8 –0.4 0.0 0.4 0.8 1.2

4284 G27

TYPICAL PERFORMANCE CHARACTERISTICS 12-Bit ADC Input Signal Attenuation (Extended Frequencies) ADC FSE Shift Due to IR Reflow VILIM Shift Due to IR Reflow

Rev. BFor more information www.analog.com PIN FUNCTIONS DRNS (Pin 21): Attenuated Drain Sense Input. Connect to the tap of an external resistive divider between the drain terminal of the N-channel MOSFET and V EE to monitor the drain voltage. DRNS coupled with RTNS monitors the output voltage for the load, which controls dV/dt inrush current and current limit foldback. DRNS operates from 0 to 2.8V. Connect to V EE if unused. EN# (Pin 1): Device Enable Input. Pull low to enable the GATE outputs to turn-on after a startup debounce delay. When pulled high, both GATE1 and GATE2 are turned off. A high-to-low transition clears faults. T ransitions are recorded. Requires external pull-up. Debouncing with an external capacitor is recommended when used to monitor board present. Connect to VEE if unused. Exposed Pad (Pin 45): Exposed Pad may be left open or connected to device ground (V EE). GATE1, GATE2 (Pin 18, Pin 19): N-Channel MOSFET Gate Drive Outputs. The GATEs can be configured into single driver , parallel, high stress staged start, and low stress staged start modes. See Table 1 in Application Information for details. The GATEs are pulled high by internal current sources (>40μA) when V IN and INTVCC cross the UVLO thresholds, UV and OV conditions are satisfied, no other faults are present and the debounce delay expires. The GATE1 and GATE2 voltages higher than VIN – 1.8V satisfy one of the conditions to assert power good outputs. Upon a low impedance output short, a 1.2A fast pull-down cur- rent is immediately activated. INTVCC (Pin 42): 5V Internal Supply Output. The output of the internal linear regulator sources up to 30mA with an UVLO threshold of 4V. The supply powers the data con - verters, logic control circuitry, I2C interface and EEPROM. Bypass with 1μF capacitor to V EE. INTVCC is not current limited. When driving INTVCC with an external supply, VIN and VZ must be left open or connected to INTVCC. MODE (Pin 40): GATE Drive Mode Configuration Input. Its voltage decodes four operation modes of GATE1 and GATE2. Leaving MODE open enables the single driver mode (Mode 1): GATE1 and GATE2 drive a single chan- nel of MOSFETs. Connecting MODE to V EE enables the parallel mode (Mode 2): GATE1 and GATE2 drive two par- allel channels of MOSFETs that turn on simultaneously to share the load current and turn off simultaneously upon overload. Connecting MODE to VIN enables the high stress staged start mode (Mode 3): GAT E1 drives a high SOA MOSFET that turns on first for startup and withstands the stress under overload conditions, while GATE2 drives a low RDS(ON) MOSFET as a bypass switch that turns on after GATE1 is fully enhanced and turns off whenever overload occurs. Connecting MODE to INTV CC enables the low stress staged start mode (Mode 4): the turn-on behavior of GATE1 and GATE2 is the same as Mode 3, but GATE1 drives a low SOA trickle MOSFET and the low RDS(ON) bypass MOSFET driven by GATE2 stays on under overload to share the stress. See Applications Information for more details. OV (Pin 4): Overvoltage Detection Input. Connect to an external resistive divider from VEE. When OV is above its threshold of 1.406V, the GATE outputs pull low to turn off the MOSFETs and an overvoltage fault is recorded. The overvoltage fault does not affect the status of the power good outputs. Connect to V EE if unused. PGIO1, PGIO2 (Pin 29, Pin 30): General Purpose Inputs/Outputs. Configurable to sequenced, inverted and non-inverted power good outputs, general purpose logic inputs and open-drain outputs. See Table 12 in bit in CONTROL_1 register 0x0A is set, PGIO2 is config- ured as inverted current limit engagement indicator after startup. Connect to V EE if unused. PGIO3 (Pin 31): General Purpose Input/Output. Configurable to inverted and non-inverted power good watchdog input (PGI# and PGI), general purpose logic input and open-drain output. See Table 12 in Application Information for details. Connect to V EE if unused. PGIO4 (Pin 32): General Purpose Input/Output. Configurable to inverted and non-inverted external fault input (EXT_ FAUL TIN# and EXT_FAULTIN), general pur- pose logic input and open-drain output. See Table 12 in Application Information for details. Connect to INTV CC through a 10kΩ pull-up resistor if unused.

Rev. B For more information www.analog.com PIN FUNCTIONS RAMP (Pin 23): Ramp Control. Connect a capacitor between RAMP and V EE to set inrush current in dV/dt startup mode. During the dV/dt control, RAMP acts as an attenuated output and feeds a fixed 2.5μA current through the RAMP capacitor to set the slew rate of the output voltage. The dV/dt inrush control is disabled after startup when power good signals are asserted. Leave open if unused. RTNS (Pin 22): RTN Sense Input. Connect to the tap of an external resistive divider between RTN and VEE to monitor the board input voltage. When selected, the RTNS voltage is measured by the ADC and used to calculate the input power . Monitors the output voltage for the load when cou- pled with DRNS, which controls dV/dt inrush current and current limit foldback. Operates from 0V to 2.8V. Connect to INTVCC if unused. SCL (Pin 37): Serial Bus Clock Input. Data at SDAI is shifted in and data at SDAO is shifted out on rising edges of SCL. This is a high impedance input that is generally connected to the output of the incoming isolator driven by the SCL port of the master controller . An external pull-up resistor or current source is required. Pull up to INTV CC if unused. SDAI (Pin 36): Serial Bus Data Input. This is a high imped- ance input used for shifting in command bits, data bits, and SDAO acknowledge bits. An external pull-up resistor or current source is required. Normally connected to the output of the incoming isolator that is driven by the SDA port of the master controller . Pull up to INTV CC if unused. SDAO (Pin 35): Serial Bus Data Output. Open-drain out- put used for sending data back to the master controller or acknowledging a write operation. An external pull-up resistor or current source is required. Normally con - nected to the input of the outgoing isolator that outputs to the SDA port of the master controller . In the single-wire broadcast mode, SDAO sends out selected data that is Manchester encoded with an internal clock. The broadcast bit rate is configurable between 2Mbit/s and 32kbit/s. SENSE1+, SENSE2+ (Pin 15, Pin 17): Positive Current Sense Kelvin Inputs. Connect to the high side of the current sense resistors. The active current limit ampli- fiers control GATE1 and GATE2 independently to limit the sense voltages SENSE1 + – SENSE1– and SENSE2 + – SENSE2– from 15mV to 30mV, configurable in 1mV steps. When enabled, SENSE1+ – SENSE1– and SENSE2+ – SENSE2– are also measured by the ADC with a full scale of 32.768mV. Connect together when using a single sense resistor . Connect SENSE2+ to VEE in the high stress staged start mode (Mode 3). Connect both to VEE if unused. SENSE1–, SENSE2– (Pin 14, Pin 12): Negative Current Sense Kelvin Inputs. Connect to the low side of the cur - rent sense resistors. TMR (Pin 24): Circuit Breaker/SOA Timer Current Output. The current sourced out of TMR is proportional to the power dissipation in the MOSFET driven by GATE1. If an RC network that represents the thermal behavior of the MOSFET is connected between TMR and V EE, the voltage at TMR represents the real-time temperature rise of the MOSFET . When the TMR voltage reaches its threshold of 2.048V that corresponds to T J(MAX) of the MOSFET , both GATE1 and GATE2 pull low to turn off the MOSFETs and an overcurrent fault is logged. If a single capacitor is connected between TMR and V EE, TMR sets the delay for MOSFET turn-off based on the power dissipation in the MOSFET . In this mode the 2μA pull-down current must be enabled to discharge the capacitor when the MOSFET power drops to near zero. When EN# is low, TMR is dis- charged by a 5mA current. Connect to V EE if unused. UVH (Pin 3): Undervoltage High Level Input. Connect to an external resistive divider from V EE. If UVH rises above 2.048V and UVL is above 1.833V, the GATE outputs pull high to turn on the MOSFETs. A capacitor of at least 10nF between UVH and V EE prevents transients and switching noise from affecting the UV threshold. Connect to INTVCC if unused.

Rev. BFor more information www.analog.com PIN FUNCTIONS UVL (Pin 2): Undervoltage Low Level Input. Connect to an external resistive divider from V EE. If UVL drops below 1.833V and UVH is below 2.048V , the MOSFETs are turned off. Pulling below 1.024V resets faults and allows the MOSFET to turn back on when undervoltage is cleared. Connect to INTVCC if unused. VEE (Pin 11 and Pin 33): Negative Supply Voltage Input and Device Ground. Connect to the negative side of the power supply. The connection between any component and device ground must be made to a dedicated plane that connects directly to VEE, not to the main current-carrying trace of −48V on the board. VIN (Pin 43): Positive Supply Input to the Device. Connect to VZ directly or through an external buffer transistor driven by VZ. The voltage at VIN is internally regulated at 11.5V. An undervoltage lockout (UVLO) circuit holds the GATE1 and GATE2 outputs low until V IN is above 8.1V. Bypass with at least 0.1μF capacitor to VEE. If it is desired to log fault information into EEPROM upon brown-out, bypass V IN with at least 68μF capacitor to VEE (See Applications Information for details). VOUTTH (Pin 6): Output Low Threshold Input. Connect to an external reference voltage for output voltage low threshold. RTNS – DRNS below VOUTTH sets the V OUT low status bit. RTNS – DRNS above VOUTTH satisfies one of the conditions to assert power good outputs. Connect to V EE if unused. VREF (Pin 5): Reference Voltage Output. Regulated at 1.024V or half of the ADC full-scale. Sources up to 200μA and sinks up to 400μA. It can drive a capacitive load of up to 10nF. Leave open if unused. VZ (Pin 44): Shunt Regulator Input. Operates with a bias of 20μA to 30mA. Connect to the positive supply (RTN) through a dropping resistor . To supply external loads with VIN, use VZ to drive an external buffer transistor with the emitter or source connected to VIN. Bypass with a 0.1μF capacitor to VEE. WP (Pin 41): EEPROM Write Protect Input. All write oper- ations to the EEPROM except fault logging are blocked when the voltage at WP is above 1.65V.

Rev. B For more information www.analog.com BLOCK DIAGRAM PGIO1 TMR WP WP 1.65V MODEINTVCC 2µA VEE VEE INTVCC VEE 2.048V TMRH DRAIN ADR0 ADR1 SCL SDAI SDAO ALERT# VEE VIN RAMP 4284 BD 0.1VTMRL – 72mV TO 203mV DC2 2.048V DC1 VIN – 1.8V GATE1/GATE2 3.2V GC ENERGY 1.28VPGIC 50µA ∆VSENSE1 × VDRNS ADIO1 VEE VEE – 1.28VADIC ADIO2 ADIO3 ADIO4 PGIO2 PGIO3 PGIO4 EN# 1.28V EN OV 1.833V UVL –2.048V UVH –1.406V OV VRTNS – VDRNS VOUTL ADIN4 SENSE2– SENSE2+ SENSE1– ADIN1 ADIN2 ADIN3 SENSE1+ UVH UVL VREF 1.024V VOUTTH 62.5x ADC+ ADC– DECODER I2C INTERFACE REGISTERS UVLO: VIN = 8.1V INTVCC = 4V VZ VIN CONTROL LOGIC 11.5V EEPROM MUX/ PREAMP POWER ACC1OSC MUL TIPLIER TIME ACC2 MIN/ MAX LOG ADC2 VPWR (RTNS or DRNS) DRNS ADC1 DRNSGATE2 RTNS FOLDBACK dV/dt CONTROLFST2 30mV TO 60mV ACL2 15mV TO 30mV VIN 50µA GATE1 FST1 30mV TO 60mV +– +– +– ACL1 15mV TO 30mV + – + – VCC

Rev. BFor more information www.analog.com OPERATION The LTC4284 is designed to turn a board’s supply voltage on and off in a controlled manner , allowing the board to be safely inserted or removed from a live, high power sys - tem. The device features four distinct operation modes: single driver mode (Mode 1), parallel mode (Mode 2), high stress staged start mode (Mode 3), and low stress staged start mode (Mode 4). Each of these modes addresses specific application requirements for SOA (Safe Operating Area), RDS(ON), and cost. In normal operation after a startup debounce delay, the LTC4284 turns on the external N-channel MOSFETs, passing the power to the load. The inrush control dur - ing startup is configurable between two methods. One is programmable active current limiting with an adjustable foldback factor . The other is constant dV/dt ramp control of the output voltage using a capacitor connected between RAMP and V EE. The inrush current is a function of the RAMP capacitor , the load capacitor and the attenuated load voltage seen between RTNS and DRNS. An 11.5V shunt regulator on V IN powers the LTC4284 with an external dropping resistor from the system RTN node. It also provides gate drive for GATE1 and GATE2. An optional buffer transistor driven by VZ boosts sourcing capability to supply external loads. An internally generated 5V supply on INTVCC supplies the logic control circuits, communication interface, data con- verters and EEPROM. Prior to turning on the MOSFETs, both V IN and INTVCC voltages must exceed their under - voltage lockout thresholds. In addition, the control inputs UVH, UVL, OV , EN#, PGIO3 and PGIO4 are monitored by comparators. The MOSFETs are held off until all startup conditions are met. The DRAIN, RTNS − DRNS and GATE voltages are moni- tored to determine if power is available for the load. T wo power good signals are sequenced on PGIO1 and PGIO2, each with a delay that is twice the startup debounce delay. Additionally, PGIO3 serves as a watchdog input to monitor the output of the DC/DC module. If the module output fails to come up, the LTC4284 turns off the MOSFETs. PGIO4 defaults as an external fault input (inverted). PGIO1-4 can also be configured into general purpose inputs or outputs. An overcurrent fault at the output may result in exces - sive MOSFET power dissipation during Active Current Limiting (ACL). To limit this power in each channel, the ACL amplifiers regulate the SEN SE1+ – SEN SE1− and SENSE2+ – SENSE2− voltages at precise, programmable values (15mV to 30mV in 1mV steps). When the output voltage is low, power dissipation is further reduced by folding back the current limit, with the foldback ratio con- figurable to 10%, 20%, or 50% of nominal. In the event of a catastrophic output short when the sensed current is twice of the current limit, fast response comparators immediately pull the GATE pins down with 1.2A. When active current limiting is engaged, TMR is pulled up by a current that is proportional to the power dissipa- tion in the MOSFET (M1) driven by GATE1. With an RC network representing the thermal behavior of M1 con- nected between TMR and VEE, the TMR voltage is propor- tional to the temperature rise in M1. When TMR voltage reaches its threshold of 2.048V (representing T J(MAX) of the MOSFET), the overcurrent fault is logged and both GATE1 and GATE2 turn off, allowing protection of the MOSFETs based on true SOA. TMR can also be config - ured to drive a single capacitor . Following the overcurrent fault, the LTC4284 can either latch off the MOSFETs or auto-retry after a cooling delay. Both the retry delay and the number of retries are configurable, too. The LTC4284 also logs and responds to other faults including overvolt- age, undervoltage, FET bad, Power Good Input (PGI) fault, FET short and external fault. Included in the LTC4284 is a pair of analog to digital con- verters (ADCs). The ADCs are configurable from 8-bit at 1kHz to 16- bit at 1Hz in five settings. As shown in the Block Diagram, ADC1 continuously monitors the current sense voltage between ADC + and ADC −. ADC2 is syn - chronized to ADC1 and measures the attenuated input voltage at RTNS or the attenuated MOSFET drain voltage at DRNS plus one of the sixteen auxiliary inputs. Every time the ADCs finish taking a measurement, the current sense voltage is multiplied by the measurement of the RTNS or DRNS voltage to provide a power measurement. Every time power is measured, it is added to an energy accumulator that tracks the input energy or the energy consumption of the MOSFET . The energy accumulator

Rev. B For more information www.analog.com APPLICATIONS INFORMATION OPERATION can generate an optional alert upon overflow, and can be preset to allow it to overflow after a given amount of energy is reached. A time accumulator tallies energy increments; dividing the results of the energy accumulator by the time accumulator gives the average system power . The minimum and maximum of each ADC measurement and power are stored, and optional alerts may be gener- ated if a measurement is above or below user configurable 8-bit thresholds. An internal EEPROM provides nonvolatile configuration of the LTC4284 operation behaviors and parameters. It also records fault information and selected ADC data. Seven bytes of uncommitted memory are reserved for general purpose storage. An I 2C/SMBus interface accesses the ADC data registers and allows the host to poll the device and determine if The LTC4284 is ideally suited for high power , high avail- ability distributed power systems, allowing a board to be safely inserted or removed from a live negative voltage backplane. The device features two GATE drivers that can be configured into parallel mode, high stress staged start mode, low stress staged start mode and single driver mode, each to optimize SOA and R DS(ON) of MOSFETs for different application requirements. In the following sections, the parallel mode is first chosen to demonstrate the common functions and basic hot-swap applications. The unique features and applications of each operation mode are then described separately. Figure 1 shows a basic 1.2kW application circuit with the dual-gate drivers configured in parallel mode. Figure 2 shows a more complete application circuit in a dual-feed system with board insertion detection and opto-coupling. Input Power Supply The LTC4284 features a floating topology that allows a wide operating voltage range and is robust to faults. For a –48V system, supply to the LTC4284 is derived from a fault has occurred. If the ALERT# line is used as an interrupt, the host can respond to a fault in real time. A reboot command turns off the MOSFETs and automati - cally restarts after a configurable delay. The SDA line is divided into SDAI (input) and SDAO (output) to facili - tate opto-coupling with the system host. T wo three-state pins, ADR0 and ADR1, are used to decode eight device addresses. The communication interface can also be configured through ADR0 and ADR1 for a single-wire broadcast mode, sending ADC data and faults status through SDAO to the host without clocking the SCL line. This single- wire, one-way communication simplifies system design by eliminating two opto-couplers on SCL and SDAI that are required by an I 2C interface. The transmission speed is configurable from 32kHz to 2MHz with four settings. the –48V RTN through an external shunt resistor R IN to the VIN and VZ pins (Figure 1). An internal shunt regulator clamps VIN to 11.5V relative to VEE and provides power to the GATE drivers. VZ acts as the shunt path of the regula- tor . A bypass capacitor of at least 0.1μF is recommended between VIN/VZ and VEE. If EEPROM fault log is enabled (see Fault Log), the minimum bypass capacitance at VIN for the fault log operation to complete upon an undervolt- age or power loss condition is CIN 15 µF mA •(IIN(MAX)+IEXTERNAL) An internal 5V linear regulator that derives from the 11.5V supply powers data converters, logic control circuits, I2C interface and EEPROM. The 5V output is available at the INTV CC pin for driving external circuits. A bypass capaci- tor of 1μF is recommended between INTVCC and VEE. To only test data converters or program EEPROM, the main –48V supply is not needed. Instead, a 5V supply may be applied between INTV CC and V EE, with V IN and V Z con- nected to INTVCC.

Figure 1. –48V/1200W Hot Swap Controller with SOA Timer and Current Limited Inrush Control in Parallel Mode:

4284 F01

to achieve the desired standoff voltage or dissipation.

Rev. B For more information www.analog.com APPLICATIONS INFORMATION For applications at very high voltages (> 300V), a high voltage MOSFET can be used. Figure 3 shows an appli - cation circuit with a depletion mode N-channel MOSFET that can withstand up to 1000V drain-to-source voltage. In this case RZ is chosen according to RZ ≤ VS(MIN) –VIN(MAX) – VGS 20µA where VGS is the gate-to-source voltage of the MOSFET (positive for an enhancement mode and negative for a depletion mode transistor) . When using an enhancement mode transistor , VZ voltage must be kept lower than its absolute maximum of 16V: VZ(MAX) = VIN(MAX) + VGS < 16V In Figures 2b and 3, the voltage drop and power dissipa- tion in the NPN or the MOSFET may be augmented by the use of one or more resistors in series with the col - lector or drain. If an external 12V supply is available on the application board, it may be used to drive the VIN pin directly as shown in Figure 4. Turn-On Sequence The following conditions must be satisfied before the turn-on sequence is started. First the voltage at VIN must exceed the undervoltage lockout level of 8.1V. Next the internal supply INTV CC must cross its 4V undervoltage lockout level. This generates a 1.3ms power-on-reset delay. After the delay times out, the voltages at UVH, UVL and OV must satisfy UVH > 2.048V, UVL > 1.833V and OV < 1.406V to indicate that the input power is within the acceptable range, and EN# must be pulled low. All the above conditions must be satisfied throughout the dura- tion of the startup debounce delay of 128ms. If any of the above conditions is violated during the delay, the delay is reset and restarted. After the delay expires, if the ON bit in CONTROL_1 register 0x0A is high, the LTC4284 turns on the MOSFETs. Otherwise, the MOSFET will be turned Figure 2a. –48V/1200W Dual-Feed Hot Swap Controller with LTC4284 in Parallel Mode (Part One) R H 750/uni03A9 0.5m/uni03A9 R 0.5m/uni03A9 R 20k 10k C 4.7nF C 68nF R 18.2k R 1.13M C UV 100nF 2N5401 100k 100k 100A 10k 100k 100k C EN 1µF R10 100k HZS5C1 100A 100A 100A 10k R RT 200k R RB 5.11k 499k 2N5401 R11 5.62k R12 20k RTN A UVH UVL OV –48V B ADIN1-4 TMR V EE SENSE1 SENSE1 RAMP SENSE2 ADIO1-4 L TC4284 ADC SENSE2 ADC DVDT = 0 THERM_TMR = 1 PWRGD_RESET_CNTRL = 1 ILIM = 0001 FB = 11 FB_DIS = 1 LPFB = 1

4284 F02a

EN# UV = 32.4V UV RELEASE AT 35.3V OV = 74.5V OV RELEASE AT 73.2V V EE L TC4371 RTN B –48V A L TC4355 1N4148 RTNS A B C BACKPLANE PLUG-IN CARD MODE V EE 2m/uni03A9 2m/uni03A9 VOUTTH VREF V EE RA1– 1/uni03A9 RA2– 1/uni03A9 RA1+ 1/uni03A9 RA2+ 1/uni03A9 BATTERY OPERATED (SUBJECT TO –36V INPUT STEPS)

4284 F02b

4284 F03

4284 F04

Figure 3. The LTC4284 Can Operate to >300V Figure 4. Using an External 12V Supply

the data held in the corresponding EEPROM registers. reading indicates a power-on-reset has occurred. Inrush current control can be configured in two ways. CR while the inrush current charges load capacitor C L. Figure 5. LTC4284 Turn-On Sequence in Parallel Mode

4284 F05

Figure 6. dV/dt Inrush Control Using RAMP Capacitor

4284 F06

Rev. BFor more information www.analog.com APPLICATIONS INFORMATION and regulates the inrush current to a fixed value that is a function of the attenuation ratio, r and the ratio between load capacitance and RAMP capacitance: IINRUSH =2.5µA •r • CL CR The attenuation ratio r is set by the external resistive divid- ers at RTNS (RRT and RRB) and DRNS (RDT and RDB) in Figure 6: r= RRT +RRB RRB = RDT +RDB RDB RTNS and DRNS represent the attenuated input voltage and MOSFET drain voltage, respectively. The differential voltage between RTNS and DRNS therefore represents the attenuated load voltage. The operation range of VRTNS, VDRNS and VRTNS – VDRNS is from 0V to 2.8V. The dV/dt control is only active during initial startup. After the turn-on sequence is completed and power good signals are activated, the dV/dt inrush control mode is disabled and RAMP is discharged with a 4mA current. RAMP will also be discharged under any GATE turn-off conditions. In the dV/dt mode the inrush current must be set lower than the folded back current limit level to avoid triggering the current limit (see below). The second inrush control mechanism is active cur - rent limiting. This is enabled by clearing the DVDT bit in CONTROL_1 register 0x0A. In this mode the inrush cur- rent is regulated to the folded back current limit: IINRUSH = ILIM • aSTARTUP where ILIM is the current limit and aSTARTUP is the startup foldback factor . ILIM is determined by the current limit sense voltage VILIM and the sense resistance RS. ILIM = VILIM RS VILIM is configurable from 15mV to 30mV in 1mV steps. aSTARTUP is configurable to 10%, 20%, 50% and 100% (no foldback) of current limit. During startup the current limit foldback profile is flat and does not change with output voltage. See Current Limit Adjustment and Current Limit Foldback for details. In this mode the RAMP capaci- tor CR at the RAMP pin no longer takes effect. If C R is omitted, RAMP must be left open. In parallel mode or single driver mode, GATE1 and GATE2 are turned on simultaneously to charge the load capacitor . In staged start modes, GATE1 is turned on first to charge the load capacitor and GATE2 is turned on after the load capacitor is fully charged. See High Stress Staged Start Mode (Mode 3) and Low Stress Staged Start (Mode 4) for details. Power Good Monitors and PGI Fault After the MOSFETs are turned on, the following conditions must be met before the power good signals are activated. First, the DRAIN voltage must fall below 2.048V to indicate the MOSFET drain is low. Second, RTNS − DRNS must be higher than the external threshold voltage at VOUTTH to indicate the output voltage is high. Last, GATE voltages must satisfy the GATE high (>VIN – 1.8V) condition. For parallel mode, one GATE must be high and the other GATE must be either high or in current limit. When all three condi- tions are met, an internal power good signal is latched, the PG_STATUS bit in SYSTEM_STATUS register 0x00 is set, and a series of three delay cycles are started as illustrated in Figure 5. When the first delay of 256ms expires, the first power good signal PGIO1 turns on the first load. When the second delay of 256ms expires, the second power good signal PGIO2 can be used to turn on a second load. Following the two 256ms delays, a third delay of 512ms is started for monitoring PGIO3 as a power good input (PGI) watchdog. Before this delay expires, PGIO3 must be pulled low or high (polarity configurable by register 0x10) by an external supply monitor to indicate the load is working prop- erly. Otherwise, the MOSFETs are turned off and a PGI fault is logged in FAUL T register 0x04. The MOSFETs are allowed to auto-retry after a delay of 128ms following the PGI fault if the PGI_RETRY bit in CONTROL_2 register 0x0B is set to 1. Both power good signals and the power good input can be configured into inverted or non-inverted polarity using PGIO_CONFIG_1 register 0x10 (see Table 12). To disable the PGI watchdog, connect PGIO3 to VEE or INTVCC depending on the configured polarity, or configure PGIO3 as general purpose input or output using register 0x10.

Rev. B For more information www.analog.com APPLICATIONS INFORMATION Power good signals are reset in two configurable ways. If the PWRGD_RESET_CNTRL bit in CONTROL_1 reg - ister 0x0A is set to 1, power good signals are reset by an output low condition as indicated by RTNS − DRNS < VOUTTH. In Figure 2a VOUTTH is biased at 0.8V, so power good signals will be reset when RTNS – DRNS drops below 0.8V, which corresponds to V OUT < 32V. If the PWRGD_RESET_CNTRL bit is cleared, power good signals are reset by any GATE turn-off conditions except overvoltage fault. When the power good signals are reset, the power good delays and the PGI delay are also reset. Turn-Off Sequence In any of the following conditions, the MOSFETs are turned off by pulling down the GATE pins with 9mA cur- rent sources and the FET_ON_STATUS bit in SYSTEM_ STATUS register 0x00 is cleared. 1. VIN is lower than 7.6V (VIN undervoltage lockout). 2. INT V CC is lower than 3.8V (INTV CC undervoltage lockout). 3. EN# is high. 4. ON bit in CONTROL_1 register 0x0A is cleared. 5. OV is higher than 1.406V (over voltage fault). 6. UVL is lower than 1.833V a nd UVH is lower than 2.048V (undervoltage fault). 7. TMR reaches its 2.048V threshold (overcurrent fault). 8. DRAIN rises above 2.048V or GATE dips below V IN – 1.8V and this condition lasts longer than a pre- configured delay (FET bad fault). 9. PGIO3, when configured as PGI#/PGI input, is high/ low when the PGI check delay of 512ms expires (PGI fault). 10. PGIO4 pin, when configured as EXT_FAULT#/EXT_ FAULT, is low/high (external fault). 11. The RBT_EN bit in REBOOT register 0xA2 is set. For condition 8, if the FET_BAD_TURN_OFF bit in CONTROL_1 register 0x0A is cleared, the MOSFETs remain on following a FET bad fault. For condition 10, if the EXT_FAULT_TURN_OFF bit in CONFIG_3 register 0x0F is cleared, the MOSFETs remain on following an external fault. For condition 11, the LTC4284 will auto- matically reboot after a programmable delay. See Reboot on I 2C Command. For each independent GATE turn-off fault, the LTC4284 can be configured to latch off the MOSFETs or go into an auto-retry sequence after the fault occurs. In paral - lel mode or single driver modes, GATE1 and GATE2 are turned off simultaneously. In high stress or low stress staged start modes, GATE2 turn-off depends on GATE1 turn-off and other conditions. Refer to the sectors cover- ing high stress staged start mode and low stress staged start mode for details. Overcurrent Protection The LTC4284 features two levels of protection from short-circuit and overcurrent conditions. Load current is monitored by SENSE1,2+ and SENSE1,2− pins and sense resistors. There are two distinct thresholds for the sense voltages: VILIM and VILIM(FAST). VILIM is configurable from 15mV to 30mV in 1mV steps and V ILIM(FAST) is always twice VILIM. See Current Limit Adjustment for details. If the sense voltage of a channel reaches V ILIM, the cor- responding GATE is pulled down by 25mA current until the associated active current limit loop is engaged. In the event of a catastrophic short-circuit or a sudden input step, where the sense voltage of a channel reaches VILIM(FAST), the corresponding GATE is immediately pulled down by a 1.2A current to limit peak current through the MOSFET . When the sense voltage drops to V ILIM, the active current limit loop is engaged. SOA Timer During active current limit, the power dissipation in the MOSFET is large. If this power dissipation persists, the MOSFET can reach temperatures that cause damage. MOSFET manufacturers specify the safe limits on operat- ing voltage, current and time as a curve referred to as the Safe Operating Area (SOA). Commonly, a circuit breaker timer sets a maximum time for the MOSFET to operate in a current limit mode. When this timer expires, the MOSFET

complicates the design procedure and MOSFET selection. ing in a resistive short-circuit condition. the startup MOSFET from overstress. Figure 7. TMR Pull-Up Current vs ∆VSENSE1 and DRNS Voltage

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Rev. B For more information www.analog.com APPLICATIONS INFORMATION Case 3. If current limit is engaged during startup in current limit mode (DVDT bit in CONTROL_1 register 0x0A = 0), the TMR pull-up current is reduced by the foldback ratio: ITMR(UP) = αSTARTUP •111.1 µA V ⎦⎥• VDRNS +2µA where aSTARTUP is the startup foldback ratio that is con- trolled by the FB bits in CONFIG_1 register 0x0D (see Current Limit Foldback). The reduction keeps the trans - conductance unchanged compared to that in normal operation with foldback disabled. Case 4. If current limit is not engaged, either in normal operation or during startup in current limit mode, the TMR pull-up current is gated by the DRAIN voltage. If DRAIN is lower than its threshold, V D,FET(TH), the TMR pull-up current is disabled. V D,FET(TH) is programmable from 72mV to 203mV in geometric scale using the VDTH bits in CONFIG_2 register 0x0E. This is a typical case in normal operating conditions when MOSFETs are fully enhanced. If DRAIN is higher than V D,FET(TH), an internal multiplier charges up TMR with a current approximately propor - tional to power dissipation in the channel 1 MOSFET: If VSENSE1 0.1VILIM, ITMR(UP) =111.1 µA V • VDRNS • VSENSE1 VILIM – 0.1+ITMR(OS) If VSENSE1<0.1VILIM, ITMR(UP) =ITMR(OS) WhereITMR(OS) has an appropriate value of 2µA. Figure 7 shows the TMR pull-up currents vs VDRNS at four different VSENSE1+ − VSENSE1− levels below current limit. If using an RC network representing the MOSFET thermal model between TMR and V EE, the THERM_TMR bit in CONTROL_1 register 0x0A must be set to 1 to disable the internal 2μA pull-down current. The total resistance in the RC network provides the discharge path to TMR. The RC network connected to TMR should be configured to represent the electric model of the thermal behavior associated with the MOSFET (M1) driven by GATE1. M1 should be selected so that its SOA is equal to or worse than that of the MOSFET ( M2) driven by GATE2. Since GATE2 turns off when GATE1 turns off due to TMR time- out, M2 is automatically protected when M1 is turned off under overload conditions. The configuration of the RC network for a particular MOSFET starts with selection of a desired number of resistive and capacitive elements and their values in ther- mal domain based on the thermal impedance plot pro - vided by the MOSFET manufacturer . Three resistors and three capacitors are usually enough to fit the plot fairly well from 10μs to 100ms, which covers the timing range of typical operating and fault conditions. T wo resistors and two capacitors may provide an acceptable accuracy for some MOSFETs or conditions. If better fitting accuracy or wider fitting range is desired, more elements may be used. After the thermal RC network is configured, the thermal quantities are then converted to electric quanti- ties according to RE=k •Rθ CE= Cθ k where RE and CE are electric resistance and capacitance, respectively and R θ and C θ are thermal resistance and capacitance, respectively. The conversion constant k is given by k = VDS,MAX •ID,MAX ITMR(UP),MAX

• VTMR(TH) ΔTMAX where V DS,MAX and I D,MAX are the maximum drain- to-source voltage and maximum drain current of the MOSFET , respectively, ITMR(UP),MAX is the TMR pull-up current corresponding to the maximum power dissipa - tion PMAX = VDS,MAX • ID,MAX, VTMR(TH) is TMR threshold voltage (2.048V), and ∆TMAX is the maximum allowable temperature rise of the MOSFET . For example, if VDS,MAX = 72V, ID,MAX = 32A, ITMR(UP),MAX = 202μA (at V DRNS = 1.8V, in current limit) and ∆TMAX = 65°C (maximum junction temperature of MOSFET = 150°C and ambient temperature = 85°C), k = 3.6 • 105 [V2/°C]. An RC network consisting of two resistors and capacitors that represent the electric model for the thermal behavior of PSMN4R8- 100BSE is show in Figure 2a.

Rev. BFor more information www.analog.com APPLICATIONS INFORMATION The LTC4284 also allows a single capacitor connected between TMR and VEE (see Figure 13 and Figure 15). In this case, the THERM_TMR bit in the CONTROL_1 regis- ter must be cleared to enable the internal 2μA pull-down current. Once enabled, the 2μA pull-down current keeps TMR low in normal conditions when the pull-up current is disabled. When the pull-up current is enabled under fault conditions, the 2μA pull-down is switched off. A mini- mum capacitance must be selected to keep the MOSFETs on during worst-case operating conditions, and the MOSFETs must be selected to withstand the worst-case SOA condition during normal operating or fault conditions. Regardless of the value of the THERM_TMR bit, when EN# is higher than its 1.28V threshold, TMR is discharged by a 5mA current. When TMR is below 0.1V, the TMR_LOW bit in SYSTEM_STATUS register 0x00 is set to 1. Overcurrent Fault and Auto-Retry Under an overcurrent condition, when the active current limit loops are engaged and TMR is being charged up, the overcurrent present bit, OC_STATUS, in FAULT_STATUS register 0x03 is set. When the TMR voltage reaches its 2.048V threshold, the overcurrent fault bit, OC_FAULT, in the FAUL T register 0x04 is set and the GATE pins are pulled down to turn off the MOSFETs. After the MOSFETs are turned off, the OC_STATUS bit is cleared. The MOSFETs are allowed to turn on again after a cooling delay if the OC_RETRY bits in CONTROL_2 register 0x0B have not been cleared. The auto-retry cooling delay is configurable from 512ms to 65.5s in binary scale using the COOLING_DL bits in CONFIG_2 register 0x 0E (See Table 11). During the cooling delay the DELAY_STATUS bit in REBOOT register 0xA2 is set to 1 to indicate the delay timer is running. It will be cleared when the delay expires. The number of retries following an overcurrent fault can be configured to 1, 7 or infinity using the OC_RETRY bits (see Table 10). If a finite retry number is selected, a retry coun- ter reset timer of 16.4s is started upon the retry following an overcurrent fault. If the next overcurrent fault occurs before the timer times out, the retry counter increments and the timer is restarted. Otherwise the retry counter is restarted. When the programmed number of retries is reached, the MOSFETs will be latched off if the next over- current fault occurs before the counter reset timer times out. During startup when power good conditions are not met, the counter reset timer is disabled. The retr y counter and the counter reset timer for the overcurrent fault are independent of those for the FET bad fault. If the OC_RETRY bits in the CONTROL_2 register 0x0B have been cleared, the MOSFETs will remain off until the OC_FAULT bit is reset (see Resetting Faults). When the OC_FAULT bit is reset, the MOSFETs are allowed to turn on after the auto-retry delay expires. Current Limit Adjustment The current limit voltage, VILIM, is programmable between 15mV and 30mV in 1mV steps through the I2C interface using the ILIM bits in CONFIG_1 register 0x0D. The default values are stored in EE_CONFIG_1 register 0xAD in the onboard EEPROM. The fast GATE pull-down sense voltage, V ILIM(FAST), is set to twice of V ILIM through the whole configuration range. The fine scales are useful in adjusting the sense voltage to achieve a given current limit using the limited selection of standard sense resis- tor values available around 1mΩ. The adjustability allows the LTC4284 to reduce available current for light loads or increase it in anticipation of a surge. This feature also enables the use of board-trace as sense resistors by trim- ming the sense voltage to match measured copper resis- tance during final test. The measured copper resistance may be written to the undedicated scratch pad area of the EEPROM (0xE9-0x EF) so that it is available to scale ADC current measurements. Current Limit Foldback The LTC4284 current limit can be configured to fold back to four levels: 10%, 20%, 50% and 100% (no foldback) of full current limit using the FB bits in the CONFIG_1 register 0x0D. During the startup inrush control the fold- back profile is flat (Figure 8a), resulting in a constant current limit. This is to protect the MOSFETs more effec- tively upon a resistive output short during startup. With a traditional resistive foldback profile, if the output short resistance is the same as the slope of the foldback profile, the foldback has no effect and MOSFETs with larger SOAs must be selected to withstand the full stress, substantially increasing the MOSFET cost.

Rev. B For more information www.analog.com APPLICATIONS INFORMATION After the internal power good signal is latched (see Power Good Monitors and PGI Fault), the LTC4284 goes into normal operation and the foldback is determined by the attenuated output voltage for the load, RTNS – DRNS (Figure 8b). If the output voltage or RTNS – DRNS drops to 0V in an event such as a catastrophic output short, the current limit sense voltage is folded back to the ratio con- figured by the FB bits. As shown in Figure 8b, the foldback ratio increases linearly with RTNS – DRNS and reaches 100% when RTNS – DRNS reaches 0.9V, which corre- sponds to the minimum supply voltage of an application. Above 0.9V the current limit sense voltage stays constant unless the load power foldback (LPFB) bit in the CONFIG_1 register 0x0D is set. If the LPFB bit is set, the current Figure 8a. Current Limit Foldback During Startup Figure 8b. Current Limit Foldback in Normal Operation limit sense voltage decreases linearly to 50% when RTNS – DRNS reaches 1.8V (corresponding to the maximum supply voltage). This profile approximately tracks the load power when the output voltage increases with a constant power load. The LTC4284 foldback profile can differentiate an output short fault from an allowed input step. Upon an output short, RTNS – DRNS drops and current limit is folded back to protect the MOSFETs from overstress. In the event of an input step, RTNS – DRNS increases while the load is charged up. The current limit either stays constant or approximates constant load power (based on the LPFB bit) to approach the optimum output ramp and minimize the temperature rise of the MOSFETs (see Input Step and Optimum Output Ramp). This is superior to a foldback profile capacitance based upon VDS or power dissipation of the MOSFET . In that case, the output short and input step conditions cannot be differentiated, often resulting in unwanted turn-off upon an input step. Foldback in normal operation can be independently dis- abled by setting the FB_DIS bit in the CONFIG_1 register 0x0D. With this configuration foldback is only effective during startup, and it should only be used when an RC network representing the thermal model of the MOSFET is connected to TMR. If a single capacitor is used, it is recommended to enable foldback in normal operation by clearing the FB_DIS bit for more conservative protection of the MOSFET . Note that the load power foldback con - trolled by the LPFB bit is not affected by the FB_DIS bit. FET Bad Fault and Auto-Retry In a hot swap application several possible faults can prevent the MOSFETs from turning on fully. A damaged MOSFET may have leakage from gate to drain or have degraded R DS(ON). Debris on the board may also pro - duce leakage or a short from the GATE pins to VEE or the MOSFET drain. In these conditions the LTC4284 may not be able to pull the GATE pins high enough to fully enhance the MOSFETs, or the MOSFETs may not reach the intended RDS(ON) when the GATE pins are fully enhanced. This can put the MOSFETs in a condition where the power in the MOSFETs is higher than its continuous power capability, even though the current is below the current limit. The VRTNS – VDRNS (V) VRTNS = 1.8V VILIM (%) 100 0.9

4284 F08a

1.8 FB = 11 FB = 10 FB = 01 FB = 00 VRTNS – VDRNS (V) VILIM (%) 100 0.9

4284 F08b

1.8 LPFB = 0 LPFB = 1 FB = 00 VRTNS = 1.8V

Rev. BFor more information www.analog.com APPLICATIONS INFORMATION LTC4284 monitors the integrity of the MOSFETs in two ways, and acts on both of them in the same manner . First, the LTC4284 monitors the MOSFET drain voltage at the DRAIN pin. A comparator detects a DRAIN high condition whenever DRAIN is above a reference volt - age, VD,FET(TH) that can be configured to 72mV, 102mV, 143mV or 203mV (geometric scale) using the VDTH bits in the CONFIG_2 register 0x0E. Second, the LTC4284 monitors the GATE voltages. If the MOSFETs are turned on, but the GATE1 and/or GATE2 voltages are lower than VIN – 1.8V, a GATE low condition is detected. The logic that determines a GATE low condi- tion depends on the operation mode (see Table 1). For the parallel mode, in turn-on state, a GATE low condition is detected in either of the following two conditions: (1) both GATE1 and GATE2 are low; (2) One GATE is low but not in current limit. When either a DRAIN high or a GATE low condition is present when the MOSFETs are commanded on, the FET_BAD_STATUS bit in FAULT_STATUS register 0x03 is set and an internal FET bad fault timer is started. The FTBD_DL bits in CONFIG_2 register 0x0E configures the timer duration to 256ms, 512ms, 1.02s and 2.05s. If the DRAIN voltage falls below V D,FET(TH) and the GATE low conditions are cleared before the timer times out, the FET_BAD_STATUS bit is cleared and the timer is reset. If the timer does time out, the FET_BAD_FAULT bit in FAUL T register 0x04 is set and the MOSFETs are turned off if the FET_BAD_TURN_OFF bit in CONTROL_1 reg - ister 0x0A has been set. The DRAIN high condition also activates TMR pull-up current when not in current limit (see SOA Timer). Note that during startup while the load is being charged, the FET_BAD_STATUS bit is set and the FET bad fault timer is running. To avoid undesired turn-off, the timer duration must be configured long enough for the load to be fully charged. After the MOSFETs are turned off following a FET bad fault, the FET_BAD_STATUS bit is cleared. The MOSFETs are allowed to turn on again after a cooling delay if the FET_BAD_RETRY bits in CONTROL_2 register 0x0B have not been cleared. The cooling delay is the same as that for an overcurrent fault and is configurable from 512ms to 65.5s in binary scale using the COOLING_DL bits in CONFIG_2 register 0x0E (see Table 11). During the cool- ing delay the DELAY_STATUS bit in REBOOT register 0xA2 is set. It will be cleared when the delay expires. The FET_BAD_RETRY bits configures the number of retries following a FET bad fault to 1, 7 or infinity (see Table 10). If a finite retry number is selected, a retry counter reset timer of 16.4s is started upon the retry following a FET bad fault. If the next FET bad fault occurs before the timer expires, the retry counter increments and the timer is reset. Otherwise the retry counter is reset. The retry coun- ter and the counter reset timer for the FET bad fault are independent of those for the overcurrent fault. If the FET_BAD_RETRY bits in CONTROL_2 register 0x0B have been cleared, the MOSFETs will remain off until the FET_BAD_FAULT bit is reset (see Resetting Faults) or the FET_BAD_TURN_OFF bit is cleared through I 2C. In either of those two cases, the MOSFETs are allowed to turn on after the auto-retry delay expires. Input Step and Optimum Output Ramp In events such as battery hot swapping or supply surge, the input voltage may experience a sudden step. The mag- nitude of the input step, ∆V , can be as large as tens of volts. As long as the input voltage does not exceed the overvoltage limit, the input step is not a fault condition and the system should stay on and operate through it. In the presence of the load capacitor , the output does not follow the input immediately, but rather ramps up from the initial supply voltage to the new supply voltage while charging the load capacitor . The VDS of the MOSFET initially jumps to ∆V and then ramps down. Additionally, during the output ramp the MOSFET not only carries the load current, I L but also the capacitance charging cur - rent, ICL, so the total power dissipation in the MOSFET can be very large. If a large input step is possible, it is usually the worst-case operating condition for the SOA of the MOSFET , and proper MOSFETs must be selected to withstand the stress. In such a condition, the minimum temperature rise of the MOSFET is achieved when ICL matches IL, or the total cur- rent is twice the load current. In other words, the current

Figure 9. LTC4284 Responds to –36V to –72V Input Step rupted during an input step. behavior , power good signaling and fault detection logic. (Table 5) to indicate the mode is selected. withstand this worst-case operating condition for the SOA. See Input Step and Optimum Output Ramp for details.

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gate driver , they only provide the SOA of a single MOSFET . fully enhanced is 1W or less. GATE2 are low or one GATE is low but not in current limit. See FET Bad Fault and Auto-Retry for details. Table 1. Configuration of the LTC4284 Dual-Gate Operation Modes

• VOUT High is equivalent to VRTNS – VDRNS > VOUTTH.

† ACL1: Active current limit circuit associated with GATE1; ACL2: Active current limit circuit associated with GATE2.

related to power dissipation in the channel 1 MOSFET . logged in FAUL T register 0x04. each channel, not the sum of the two channels. to deliver the capacitive current to charge up the load. See Input Step and Optimum Output Ramp for details. is fully charged (V DRAIN < 2.048), GATE2 is turned on.

4284 F10

Figure 10. –48V/1800W Hot Swap Controller with SOA Timer and dV/dt Inrush Control in High Stress Staged Start Mode:

is turned off and an overcurrent fault is logged. Figure 11. Turn-On Sequence of High Stress Staged Start Mode Figure 12. –36V to –72V Input Step Response in High Stress be lower than the parallel mode.

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4284 F11

STATUS register 0x03 and starts the FET bad fault timer . Figure 13. –52V/2500W Hot Swap Controller in Low Stress Staged Start Mode with dV/dt Inrush Control: GATE1 Drives

4284 F13

(VGATE2 > VGATE(TH)), the power good signals are asserted. the thermal behavior of M1 should be connected to TMR. timeout in an overcurrent condition. applications where a second gate driver is not needed. Figure 14. Output-Short Protection in

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age fault occurs when OV rises above its 1.406V threshold. Figure 15. –48V/300W Hot Swap Controller in Single Driver Mode: GATE1 Drives MOSFET and GATE2 Is Open, with dV/dt Inrush Control

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Figure 16. –48V/600W Hot Swap Controller in Single Driver Mode: Both GATE1 and GATE2 Drive MOSFETs,

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clearing the OV_RETRY bit in CONTROL_2 register 0x0B. comparator output to change state. overvoltage shutdown threshold of 71.9V. the UV_RETRY bit in CONTROL_2 register 0x0B. Figure 17. Adjustment of Undervoltage Thresholds

Rev. B For more information www.analog.com APPLICATIONS INFORMATION Because of the compromises of selecting from a table of discrete resistor values (1% resistors in 2% increments, 0.1% resistors in 1% increments), best possible OV and UV accuracy is achieved using separate dividers for each pin, This increases the total number of resistors from three or four to as many as six, but maximizes accu - racy, greatly simplifies calculations and facilitates running changes to accommodate multiple standards or custom- ization without any board changes. To improve noise immunity, put the resistive divider to the UV and OV pins close to the chip and keep traces to RTN and V EE short. A 0.1μF capacitor from UVH or UVL (and OV through resistor R2 as in Figure 17) to VEE helps reject supply noise. FET Short Fault A FET short fault will be reported if the data converter measures a current sense voltage between ADC + and ADC− greater than 255μV while the MOSFETs are turned off. This condition sets the FET_SHORT_STATUS bit in FAULT_STATUS register 0x03 and the FET_SHORT_ FAULT bit in FAUL T register 0x04. Power Failed Fault The LTC4284 continuously monitors the output voltage for the load. The differential voltage between RTNS and DRNS represents the attenuated output voltage for the load. An output low status will be reported if RTNS – DRNS is lower than the external reference voltage at VOUTTH. This con- dition sets the VOUT_LOW status bit in FAULT_STATUS register 0x03. If this condition occurs after the internal power good signal is latched, the POWER_FAILED fault bit in FAUL T register 0x04 will also be set. This fault does not turn off the MOSFETs. After RTNS – DRNS rises above VOUTTH, the VOUT_LOW bit is cleared. External Fault and Auto-Retry PGIO4 can be configured as EXT_ FAUL T# or EXT_FAULT using PGIO_CONFIG_1 register 0x10 bits [7:6] to monitor an external fault condition. If the input polarity is con - figured as EXT_ FAUL T#, an external fault occurs when PGIO4 falls below its 1.28V threshold. This condition sets the EXT_FAULT_STATUS bit in FAULT_STATUS register 0x03 and the EXT_FAULT bit in FAUL T register 0x04. This condition also turns off the MOSFETs if the EXTFLT_TURN_OFF bit in CONFIG_3 register 0x0F has been set. When PGIO4 subsequently rises above 1.28V, the EXT_FAULT_STATUS bit is cleared. After an auto-retry delay, the MOSFETs will be allowed to turn on again unless the external fault auto-retry has been disabled by clearing the EXT_FAULT_RETRY bit in CONTROL_2 register 0x0B. The auto-retry delay for the external fault is configurable from 512ms to 65.5s in binary scale using the COOLING_ DL bits in CONFIG_2 register 0x0E. During the delay the DELAY_STATUS bit in REBOOT register 0xA2 is set to 1. It will be cleared when the delay expires. In Figure 18, PGIO4 is configured as EXT_FAULT and used to monitor MOSFET temperature. When the MOSFET temperature rises above 115°C , the EXT_FAULT bit in FAUL T register 0x04 is set and the MOSFET is turned off. If the EXTFLT_TURN_OFF bit in CONFIG_3 register 0x0F has been cleared, an external fault condition at PGIO4 will not turn off the MOSFETs. Regardless of the value of the EXTFLT_TURN_OFF bit, if the EXT_FAULT_ALERT bit in FAULT_ALERT register 0x15 is set, the high state of the EXT_FAULT bit in FAUL T register 0x04 will generate an alert by pulling ALERT# low. PGIO1-4 and ADIO1-4, when configured as general pur- pose inputs, can be used to monitor external conditions without turning the MOSFETs off or generating alerts. If any of these pins is pulled above the 1.28V threshold, the associated input status bit in INPUT_STATUS register 0x02 is set. Cooling Delay The cooling delay (configurable by the COOLING_DL bits, 0x0E [3:1]) after an overcurrent fault, FET bad or external fault, will not be interrupted by any other fault. If, before expiration of the cooling delay, another overcurrent, FET bad or external fault occurs, the cooling delay will restart and extend the total cooling time. During the cooling delay the DELAY_STATUS bit 0xA2 [1] is set to indicate the delay timer is running. This bit resets when the delay expires. The cooling delay can be terminated by initiating an I 2C reboot command, and is also terminated by UVLO (INTVCC < 3.8V).

Figure 18. Use PGIO4/EXT_FAULT to Turn Off 2.048V while toggling UVL to reset faults. delay expires, the MOSFETs are allowed to turn on again.

4284 F18

INTVCC below its undervoltage lockout voltage. low and remain low during the 128ms debounce delay. to monitor board present as shown in Figure 2. Resetting Faults) except pulling EN# from high to low. while clearing the entire FAUL T register 0x04.

EN#, UV/OV , PGIO3 or PGIO4 pins along with the I2C port. ured as power good input and external fault, respectively. On/off control is possible with or without I2C intervention. conditions in each operation mode as shown in Table 1. backplane and board resident applications. backplane and board resident applications. EE_CONTROL_1 register 0xAA) to 1 or 0, respectively. 1, the LTC4284 turns on the GATE outputs without a delay. 2C will not turn off the GATE outputs. Figure 19. On/Off Control of the LTC4284

Rev. BFor more information www.analog.com APPLICATIONS INFORMATION Configuring PGIO and ADIO Pins The LTC4284 has four PGIO pins and four ADIO pins, all of which can be configured as general purpose inputs/ outputs using PGIO_CONFIG_1 register 0x10 and ADIO_ CONFIG register 0x12. Additionally, PGIO1 and PGIO2 can be configured as two sequential inverted or non-inverted power good signals, PGIO3 can be configured as inverted or non-inverted power good input signal (see Power Good Monitors and PGI Fault), and PGIO4 can be configured as inverted or non-inverted external fault (see External Fault and Auto-Retry). When configured as general purpose outputs, the output data for PGIO1–PGIO4 and ADIO1– ADIO4 are stored in bits[7:4] in PGIO_CONFIG_2 register 0x11 and bits[3:0] in ADC_CONFIG register 0x12, respec- tively. When selected, ADIO1–ADIO4 are also monitored by the on-board ADC (see Data Converters). If the PGIO2_ACLB bit in CONTROL_1 register 0x0A is set, PGIO2 is configured as an inverted indicator of active current limit after startup. During startup PGIO2 is held low. After the internal power good signal is latched, if the OC_STATUS bit in FAULT_STATUS register 0x03 is 0, PGIO2 goes high impedance. If the OC_STATUS bit is set to indicate that active current limit is engaged, PGIO2 is pulled low. Regardless of the configurations, PGIO1– PGIO4 and ADIO1–ADIO4 all have comparators monitoring the volt- age on these pins with a threshold of 1.28V. The results are stored in INPUT_STATUS register 0x02. Design Examples The design flow starts with specifying the maximum load power and the operating voltage limits (line or battery operated). A line operated system usually has a tightly regulated supply voltage. A battery operated system usu- ally has wide supply range and can experience large input steps when replacing a dropping-out battery with a newly charged one. An operation mode is then selected based on the following guideline. Single Driver Mode (Mode 1): < 800W, line or battery operated. Parallel Mode (Mode 2): up to 1500W, line or battery operated. High Stress Staged Start Mode (Mode 3): >1500W, bat - tery operated. Low Stress Staged Start Mode (Mode 4): >1500W, line operated. This is a rough guide and the boundaries between dif - ferent modes may shift up or down depending upon the allowed budget of the MOSFETs. Example 1: Design Procedure of Parallel Mode with SOA Timer and Current Limit Startup Consider a battery operated system with maximum load power of 1200W, a supply voltage range of –36V to –72V (–36V to –72V input step is allowed), and a load capaci- tance of CL = 1000µF as shown in Figure 2. The parallel mode is chosen based on the above guideline. In the par- allel mode, GATE1 and GATE2 drive two parallel channels of MOSFETs to charge the load capacitor simultaneously at startup, share the load current after startup, and turn off simultaneously upon a fault condition such as output overload or short-cir cuit. The maximum load current is calculated as IL(MAX) = PL(MAX) VS(MIN) = 1200W 36V =33.3A Step 1. Configure current limit and select current sense resistors. Since a –36V to –72V input step is a valid oper- ating condition, the current limit should be twice the maxi- mum load current to minimize the temperature rise in the MOSFETs following a large input step: ILIM(OPT) = 2 ∙ IL(MAX) = 66.7A With a constant power load, when the load voltage ramps from 36V to 72V following the input step, the load cur - rent is halved. The LPFB (load power foldback) bit in CONFIG_1 register 0x0D is set to 1 so that the current limit will be maintained at approximately twice the load current during the output ramp. In parallel mode, the two channels share the current equally, so the maximum current each channel carries is ICH(MAX) =ILIM =33.3A

Rev. B For more information www.analog.com APPLICATIONS INFORMATION Sense resistors for each channel are selected assuming they will carry the maximum channel current, or 33.3A in this example. Selection is a matter of total cost, sense voltage (configurable from 15mV to 30mV in 1mV steps), allowable dissipation, availability of discrete resistance values, using multiple devices to reduce the sensing errors associated with high current density at the interface between the PCB and resistor , and using multiple devices to ballast current flow across a wide path, between 2 or more connectors, or between 2 or more MOSFETs. These factors are iterated until an acceptable solution is found. First, determine the number of resistors needed to handle the total sense power of each channel. Compute the total sense power starting with the minimum sense voltage or 15mV: PS(CH) = ∆VSENSE(MIN) • ICH(MAX) = 15mV • 33.3A = 500mW Second, compute the number of resistors needed to handle this power . For example, 1206 resistors are rated for 250mW dissipation. A conservative design is half as much, or 125mW. NRS(CH) = PS(CH) 125mW = 500mW 125mW Thus at least four parallel 1206 resistors are needed for each channel. Third, compute the resistance value: RS(CH)= VILIM(MIN) ICH(MAX) = 15mV 33.3A =450µΩ Four resistors of 1.8mΩ each would give the correct sense resistance. Fourth, use the closest next-larger avail- able sense resistor value and adjust the sense voltage as needed to restore the current. In this case, a 2mΩ sense resistor value is selected and the sense voltage is adjusted to 16mV. Recompute the numbers: RS(CH) = 2mΩ 4 =500µΩ ICH(MAX) = 16mV 500µΩ=32A PS(CH) = 16mV • 32A = 512mW The power dissipation of each resistor package is now 512mW/4 = 128mW. The total current limit is now 32A • 2 = 64A, close enough to the optimum value of 66.7A. The above process might be iterated for several combinations of different resistor counts, different package sizes, and even combinations of mixed resistor values. When a specific design is actually built, there can be small inaccuracies in the current sensing owing to contact and copper trace resistances. An immediate remedy without changing sense resistors is to readjust the sense voltage in 1mV steps. For instance, moving sense voltage from 16mV to 17mV gives a 6.25% increase in current. Step 2. Select resistive dividers for DRNS (drain sense), RTNS (RTN sense) and VOUTTH (output low threshold). DRNS and RTNS serve multiple purposes. First, they are the inputs to a differential amplifier that measures the attenuated load voltage for dV/dt control at startup (see Inrush Control). In the event of an output overload or short-circuit, the current limit foldback profile in normal operation depends upon the differential input between RTNS and DRNS that represents the output voltage across the load. The current limit starts to fold back when RTNS – DRNS drops below 0.9V and reaches the minimum when RTNS – DRNS drops to zero (see Current Limit Foldback). Additionally, in current limit the DRNS input monitors the MOSFET’s VDS and uses this information to scale the TMR pull-up current accordingly. When not in current limit, DRNS monitors V DS and serves as one input to a mul - tiplier which generates the TMR pull-up current. Finally, RTNS and DRNS also ser ve as inputs to the ADCs so that the input voltage and MOSFET drain voltage can be read remotely. RTNS and DRNS have a maximum useable input voltage of 2.8V, so resistive dividers are required. To select resistive dividers for RTNS and DRNS, compute the divider ratio r using the maximum supply voltage: r = VS(MAX) 1.8V = 72V 1.8V =40 where 1.8V is the operating point of DRNS at which the TMR pull-up current is tested and specified. The resulting

Rev. BFor more information www.analog.com APPLICATIONS INFORMATION ADC measurement full scale for input (at RTNS) and MOSFET drain (at DRNS) voltages is VFS(MEAS) = r • 2.048V = 40 • 2.048V = 81.92V which gives a LSB size of 20mV in 12-bit mode. If it was desired to measure gross overvoltage inputs, such as 100V, then a decision would have to be made to sacrifice control dynamic range in favor of ADC measurement range by using a higher divider ratio. An alternative approach is to use ADIN1–ADIN4 inputs for ADC measurements, leaving RTNS and DRNS for control purpose only. With 72V load voltage corresponding to RTNS – DRNS = 1.8V, in normal operation the current limit starts to fold back when load voltage drops below 36V (or RTNS – DRNS < 0.9V) in overload conditions. This means there is no foldback in normal operating input range between −36V and −72V, allowing the MOSFETs to pass the full load current. Standard values of 200k and 5.11k give a divider ratio of 40.1. DRNS and RTNS must use identical dividers. While the exact ratio is not important, matching between them is very important. For this reason, 1% resistor tolerance is the minimum requirement; 0.25% or 0.1% is better . VOUTTH pin sets the threshold of RTNS − DRNS that indicates the low limit of the output voltage to reset power good signals if the PWRGD_RESET_CNTRL bit in CONTROL_1 register 0x0A is set to 1. The low limit is set below the minimum input voltage, so 32V is selected in this example. With a divider ratio of 40 on DRNS and RTNS, the VOUTTH threshold is 32V/40 = 0.8V. This voltage may be realized with a resistive divider between INTV CC (5V) and V EE, or for a better tolerance, between VREF (1.024V) and V EE. For the latter case, a divider of 5.62k and 20k as shown in Figure 2a results in 0.8V at VOUTTH. The source current of VREF is 40μA, well within its specified limit of 200μA. Step 3. Design the overcurrent timer behavior . The TMR pin can be configured into a SOA timer or a single capaci- tor circuit breaker timer . The SOA timer requires an RC network representing the MOSFET thermal model to be connected to TMR (see SOA Timer). At least two resistors and two capacitors are needed for minimum accuracy of the thermal behavior . More RC elements are desired for better accuracy. Thus the cost and board area are larger than the single-capacitor timer . The benefit of the SOA timer is that the TMR voltage represents the temperature rise of the MOSFET and its trip threshold represents the maximum allowable peak temperature of the MOSFET . With the SOA timer , selection of MOSFETs is much sim- pler: they just need to meet the worst-case operation requirements. In fault conditions such as output short, the SOA timer automatically protects the MOSFETs by turning them off once the maximum allowable peak temperature is reached (TMR tripped). With the single capacitor timer , the minimum capacitor must first be selected to keep the MOSFETs on during worst-case operating conditions, then the MOSFETs must be selected to withstand the worst-case SOA conditions during normal operating and fault conditions. The cost of MOSFETs selected based on the single capacitor timer for parallel mode or high stress staged start mode may be substantially higher than that using the SOA timer . It is recommended to use the SOA timer for high power applications using parallel mode or high stress staged start mode, especially for those with large input steps. Therefore, in this example the TMR pin is configured as an SOA timer by setting the THERM_TMR bit in CONTROL_1 register 0x0A to 1, which disables the internal TMR pull-down current. With the SOA timer protecting the MOSFETs, current limit foldback may be disabled after startup. This can be done by setting the FB_DIS bit in CONTROL_1 register 0x0A to 1. The foldback during startup is not affected by the FB_DIS bit. Step 4. Select the MOSFETs. With the SOA timer , two operating requirements must be met: (1) the R DS(ON) must be low enough to carry maximum load current; (2) the SOA must be sufficient to stand the worst-case oper- ating condition. The selection for the RDS(ON) requirement is a combination of total MOSFET cost and maximum desired dissipation per package. For the maximum chan- nel current of 32A, two 5mΩ devices result in 1.28W per device. With air flow 1.28W dissipation is acceptable and a third device is unnecessary. The chosen MOSFETs are two PSMN4R8-100BSE devices (each R DS(ON) < 4.8mΩ) for each channel. The components selected so far are shown in Figure 1 and Figure 2a.

Rev. B For more information www.analog.com APPLICATIONS INFORMATION The worst-case MOSFET drain voltage with full load is VD(ON),MAX=ICH(MAX) •RDS(ON),MAX 2 = 32A • 4.8mΩ 2 =76.8mV The DRAIN threshold VD,FET(TH) must be set higher than this number with sufficient margin to account for com - ponent inaccuracies and temperature coefficient. When the MOSFET drain voltage is higher than this threshold, two things will happen. First, the FET_BAD_STATUS bit in FAULT_STATUS register 0x03 will be set and the FET bad timer will be started. When the timer expires the FET_ BAD_FAULT bit in FAUL T register 0x04 will be set and the MOSFETs will be turned off if the FET_BAD_TURN_OFF bit in CONTROL_1 register 0x0A has been set. Second, the TMR pull-up current will be enabled even if current limit is not engaged. This current is produced by an internal multiplier monitoring the power dissipation in channel 1. VD,FET(TH) has four discrete settings: 72mV, 102mV, 143mV and 203mV. In this example 143mV is selected by setting the VDTH bits in CONFIG_2 register 0x0E to 10b. A large input step is usually the worst-case operating condition for SOA. To verify the temperature rise of the MOSFET , it is necessary to run simulations in this con - dition. With the above selected components and con - figurations, the temperature rise of the MOSFET when riding through a –36V to –72V input step with full load (1200W and 1000μF) is 46°C (simulated with the L Tspice SOAtherm model). At worst-case operating temperature of 85°C, this translates to 131°C in the MOSFET , which has substantial margin from the manufacturer specified maximum temperature of 175°C. With a load capacitance of 2000μF, the temperature rise during the –36V to –72V input step increases to 64°C, still an acceptable figure. Step 5. Design the startup current and FET bad timer . First the startup mode is selected. As pointed out in Inrush Control, the startup current (or inrush current) can be controlled either by a RAMP capacitor in dV/dt mode or by startup foldback in current limit mode. The cur - rent limit mode is selected in this example based on two considerations. First, in the parallel mode, both channels charge the load capacitance during startup. Current limit will equalize the charging currents between the two chan- nels. In the dV/dt mode, the charging current may concen- trate on one channel due to MOSFET threshold mismatch. Second, the current limit mode is a better choice to work with the SOA timer that has been selected in Step 3. This is because if the dV/dt mode was selected, the TMR pull- up current would be disabled in normal startup conditions and the SOA timer would not be able to track the tempera- ture rise of the MOSFET during startup. Choice of the charging current is a trade-off between maximum charging time, maximum inrush current drawn from the backplane, and more importantly, peak power dissipated in the MOSFETs. When charging a capacitor from a voltage source, the charging process dissipates an energy in the pass MOSFET equal to the energy stored in the capacitor . The maximum input voltage results in the maximum energy: EMAX = CL • VS(MAX) = 1000µF •(72V) 2 =2.59 J This indirectly sets a limit on how quickly the load capaci- tor can be charged, since the average power dissipation in the MOSFETs is energy/time. In general, the faster the charge rate, the higher the peak temperature. For this reason, it is a good idea to lower the inrush current to no more than necessary to achieve the required startup time. Therefore, the smallest foldback ratio, 10%, is selected by setting the FB bits in CONFIG_1 register 0x0D to 11b, and the startup inrush current is IINRUSH = ILIM • aFB = 64A • 10% = 6.4A The maximum startup charging time of the load capacitor is then computed: tSTARTUP(MAX) = CL • VS(MAX) IINRUSH 1000µF • 72V 6.4A =11.25ms This charging time is short enough for most applications. Simulation shows the temperature rise of the MOSFET in this worst-case startup condition is 40°C, lower than that for the –36V to –72V input step calculated in Step 4.

Rev. BFor more information www.analog.com APPLICATIONS INFORMATION During startup the FET_BAD_STATUS bit is high and the FET bad timer is running and serves as a watchdog over the controlled startup. The load capacitor must be fully charged before this timer expires, or the GATE out- puts will be turned off if the FET_BAD_TURN_OFF bit in CONTROL_1 register 0x0A has been set. There is no con- cern with this example since the maximum charging time of 11.25ms is much shorter than the minimum FET bad timer delay (256ms). Step 6. Select the RC network for the SOA timer follow - ing the procedure as shown in the SOA Timer section. It was found that two thermal capacitors and two thermal resistors provide fairly good curve fitting for the ther - mal impedance plot of the chosen MOSFET , PSMN4R8- 100BSE in the range between 100μs and 100ms (wide enough for typical operating conditions of this applica- tion): Cθ1 = 0.002J/°C, Rθ1 = 0.05°C/W , Cθ2 = 0.03J/°C, Rθ2 = 0.35°C/W . The conversion constant is given by k = VDS,MAX •ID,MAX ITMR(UP),MAX

• VTMR(TH) ΔTMAX 72V •32A 202µA •2.048V 65°C = 3.6 •105 V2 where ∆TMAX is the maximum allowable temperature rise and chosen to be 65°C, which corresponds to a maximum MOSFET temperature of 150°C at an operating tempera- ture of 85°C , with 25°C margin from the manufacturer specified maximum temperature of 175°C. The thermal R and C values are then converted to electric R and C values as shown in SOA Timer . After the electrical R and C values are computed, choose the closest next-larger avail- able resistor value and the closest next-smaller available capacitor value. Then the resistance corresponding to the thermal resistance of the board is added to the termination resistance (the largest one). If the computed resistance for the board thermal resistance is over 1MΩ , choose 1MΩ. Assuming a 5°C/W board thermal resistance in this application, it is converted to 5 • 3.6 • 105 = 1.8MΩ. So 1MΩ is selected. This avoids accuracy degradation due to board leakage currents. The resulting electrical capacitors and resistors are C E1 = 4.7nF, R E1 = 18.2k, C E2 = 68nF, RE2 = 1.13MΩ, as shown in Figure 1 and Figure 2a. After the SOA timer is configured, rerun simulations to ensure TMR does not reach its 2.048V trip point in all operating conditions including startup and input step. When it trips in fault conditions such as output over - load or short-circuit, verify the peak temperature of the MOSFET matches the proposed maximum temperature. Iterations of the above procedure may be needed before the RC network is finalized. Step 7. Select resistive dividers for UV/OV inputs and ADC averaging resistors Select resistive dividers so that UV rising threshold is set just below the minimum input voltage and OV falling threshold is set just above the maximum input voltage. A single, 4-resistor divider as shown in Figure 2a gives UV shutdown at 32.4V, UV release at 35.3V, OV shutdown at 74.5V and OV release at 73.2V. This configured range is just wide enough to cover the full input voltage range between 36V to 72V. A 100nF bypass capacitor is selected to filter out noises at UVL/UVH and OV . Four 1Ω averaging resistors are chosen for the ADC+ and ADC− inputs to measure the average current between the two channels. The current ADC has a full scale of 32.768mV. The total sense resistance is 0.25mΩ, giving a full-scale current of 131.1A, with a 32mA LSB size in 12-bit mode. Example 2: Design Procedure of Low Stress Staged Start Mode with Single Capacitor on TMR Pin and dV/ dt Startup The second example is a line operated –52V system with supply tolerance of 10% (–46.8V to –57.2V) and maxi - mum load power of 2500W as shown in Figure 13. The load capacitance is specified as C L = 2000µF. The low stress staged start mode is chosen for this example since the power exceeds 1500W and the supply is line regulated, without the concern about a large input step. The low pass staged start mode features a small startup MOSFET , driven by GATE1 (channel 1) and designed to carry a low startup inrush current to charge the load capacitor . After successful startup, low resistance bypass MOSFETs are driven by GATE2 (channel 2) to supply the load current. The current in channel 1 is usually only a small fraction of

Rev. B For more information www.analog.com APPLICATIONS INFORMATION the maximum load current, such as 10% or less. For this reason, its current contribution during normal operation can be ignored for the first phase of the design. Later channel 1 can be accounted for or sized to make up for any shortfall in the high current (channel 2) path, so that full power (2500W) can be supplied at minimum input voltage (46.8V). The maximum load current is calculated as IL(MAX) = PL(MAX) VS(MIN) = 2500W 46.8V =53.4A Step 1. Select sufficient bypass MOSFETs to carry the maximum load current. The decision is a combination of total MOSFET cost and maximum desired dissipation per package. For the maximum channel current of 53.4A, two IPT020N10N3 (RDS(ON) < 2mΩ) devices result in 1.415W per package, an acceptable dissipation with air flow. As an option, the IPT015N10N5 (R DS(ON) < 1.5mΩ could be used, dissipating just 1.06W per package, at a slightly higher cost. With full load the worst-case drain voltage of the MOSFET is 53.4A • 1mΩ = 53.4mV. Select 102mV as the DRAIN threshold for starting FET bad timer and enabling TMR pull-up current, with sufficient margin to account for inac- curacies. Set the VDTH bits in CONFIG_2 register 0x0E to 01b for this configuration. See detailed design consider- ations in Example 1, Step 4. Step 2. Configure current limit and select current sense resistors. Since the input voltage is well regulated, there is no need to set the current limit to twice the load current to minimize temperature rise upon a large input step as in Example 1. The current limit in this example just needs to cover the maximum load current, with enough margin to account for device tolerances. Select sense resistors for channel 2 (bypass channel) first assuming it carries the maximum load current, then add a small current carried by the startup channel for the margin. Compute the sense power of channel 2 starting with the minimum sense volt- age or 15mV: PS2 = VILIM(MIN) • IL(MAX) = 15mV • 53.4A = 801mW With 250mW rated 1206 resistors, use 125mW for con- servative design and the minimum number of sense resis- tors to handle the power is NRS2 = PS2 125mW = 801mW 125mW =6.4 Thus at least 6 parallel 1206 resistors are needed for channel 2. The resistance of channel 2 is RS2 = VILIM(MIN) IL(MAX) = 15mV 53.4A =281 µΩ Six resistors of 1.69mΩ each would give the correct sense resistance. The closest next-larger available sense resistor value is 2mΩ: RS2= 2mΩ 6 =333µΩ Adjust the sense voltage to 18mV to restore the current: ILIM2 = VILIM RS2 = 18mV 333µΩ=54A and recompute the sense power: PS2 =18mV • 54A = 972mW The power dissipation of each resistor package is now 972mW/6 = 162mW, still an acceptable value for 1206 resistors. As a last step, a 5mΩ sense resistor is chosen for a channel 1 current of ILIM1= VILIM RS1 = 18mV 5mΩ =3.6A so that the total current limit is ILIM = ILIM1 + ILIM2 = 54A + 3.6A = 57.6A Taking all tolerances into account, this provides sufficient margin for the maximum load current of 53.4A. Sense voltage may need to be readjusted to account for current sensing inaccuracies such as contact and copper trace resistances, as explained in Example 1, Step 1. Step 3. Select resistive dividers for DRNS (drain sense), RTNS (RTN sense) and VOUTTH (output low reference).

Rev. BFor more information www.analog.com APPLICATIONS INFORMATION See Example 1, Step 2 for detailed design considerations. First compute the divider ratio r for RTNS and DRNS: r = VS(MAX) 1.8V = 57.2V 1.8V =31.78 which is rounded to 32. Standard values of 316kΩ and 10.2kΩ give a divider ratio of 31.98. The ADC measure - ment full-scale for input (at RTNS) and MOSFET drain (at DRNS) voltages is VFS(MEAS) = r • 2.048V = 32 • 2.048V = 65.5V which gives a LSB size of 16mV in 12-bit mode. With V LOAD = 32 • 1.8V = 57.6V corresponding to RTNS – DRNS = 1.8V, the current limit starts to fold back when VLOAD drops below 28.8V in overload conditions. There is no foldback at normal input between − 46.8V and −57.2V, allowing the MOSFETs to pass the full load current. If 44V is chosen as the output voltage threshold to reset power good signals, with a divider ratio of 32 on DRNS and RTNS, the VOUTTH threshold is 44V/32 = 1.375V. This voltage can be obtained with a resistive divider between INTVCC (5V) and V EE. The divider ratio is 5V/ 1.375V = 3.64. A divider of 26.7k and 10.2k as shown Figure 13 gives a close enough ratio of 3.62. Step 4. Design the TMR behavior . See Example 1, Step 3 for general design considerations. Since the inrush cur - rent in the low stress staged start mode is at such a low level that the temperature rise of the startup MOSFET is insignificant, there is no need to use an SOA timer for MOSFET protection during startup. After startup there is no concern about a large input step, thus a very short timer delay is needed for MOSFET turn-off upon a fault such as output short-circuit. Therefore, in the low stress staged start mode the TMR function is essentially a fil - tered circuit breaker and a single timer capacitor on TMR works just fine for this purpose. Channel 2 dictates the timer capacitor selection since it carries most of the load current. All of the channel 2 cur- rent could be concentrated into a single MOSFET . The current limit of channel 2 is 54A in this example, and the MOSFET chosen in Step 1 (IPT020N10N3) can handle 60V and 60A for 100μs. It has been found that 20μs of circuit breaker filtering is sufficient to reject noise encountered in most systems, so the chosen MOSFET is up to the task. The TMR pull-up current is 202μA at maximum overload, with a voltage threshold of 2.048V. Compute the timer capacitance, Ct, for 20μs filter delay: Ct = ITMR(UP),MAX • tFILTER VTMR(TH) = 202µA • 20µs 2.048V =2nF Select the closest next-larger available capacitance: Ct = 2.2nF. With single capacitor on TMR, the THERM_ TMR bit in CONTROL_1 register 0x0A must be cleared to enable the internal 2μA pull down current. Additionally, the FB_DIS bit in CONTROL_1 register 0x0A should be cleared to keep foldback enabled after startup to protect MOSFETs from damage upon a low impedance short-circuit. Step 5. Design the startup channel (channel 1) and FET bad timer . At startup in low stress staged start mode, channel 1 charges the load capacitance with a small trickle current. This is a good case to use the dV/dt startup mode (see discussions in Example 1, Step 5). The design pro - cedure involves selecting a RAMP capacitor to set the dV/ dt rate for desired charging current, selecting a proper startup current limit and checking the temperature rise of the startup MOSFET under a resistive short condition. Choice of the charging current is a trade-off between max- imum charging time and peak temperature of the startup MOSFET . As discussed in Example 1, Step 5, the charging current should be set to a low level that is just necessary to achieve the required charging time. Suppose an upper limit of 500ms charging time is desired for a 2000μF load capacitor at the maximum input of 57.2V. The necessary charging current is IINRUSH(MIN) = CL • VS(MAX) tSTARTUP(MAX) = 2000µF • 57.2V 500ms =229mA The RAMP capacitor is selected according to CR =IRAMP •r • CL IINRUSH =2.5µA • 32 • 2000µF 229mA =699n F

Rev. B For more information www.analog.com APPLICATIONS INFORMATION An acceptable value is 470nF, resulting in a nominal inrush of IINRUSH =IRAMP •r • CL CR =2.5µA • 32 • 2000µF 470nF =340mA and a maximum startup time of tSTARTUP(MAX) = CL • VS(MAX) IINRUSH = 2000µF • 57.2V 340mA =336ms which is well below the upper limit of 500ms. The FET bad timer must be set longer than the startup time for the load capacitor to be fully charged, so it is configured to 512ms by setting the FTBD_DL bits in CONFIG_2 register 0x0E to 01b. The startup current limit should also be configured to a low level to minimize the temperature rise of the startup MOSFET under a resistive short condition, but must be higher than the dV/dt inrush current to avoid current limit being triggered in normal startup conditions. With a fold- back ratio of 20%, the startup current limit of channel 1 is ILIM1(STARTUP) = 3.6A • 20% = 720mA which is more than twice of the inrush current of 340mA, with substantial margin to account for all inaccuracies. Select the 20% foldback ratio by setting the FB bits in CONFIG_1 register 0x0D to 10b. A 10% foldback ratio would result in 360mA current limit, too close to the inrush current. Since the inrush current is very low, RDS(ON) and SOA of the startup MOSFET are not critical, and a small, low cost device may be used. PSMN7R6-100BSE, with RDS(ON) < 7.6mΩ, is selected as the startup MOSFET . After startup with 3.6A current limit, the worst-case power dissipation in this channel is (3.6A) 2 • 7.6mΩ = 98.5mW, a very low figure that has no concern. Step 6. Run simulations to verify temperature rises in both the channel 1 and channel 2 MOSFETs under all operating and fault conditions are within the acceptable range. This is a necessary step when using a single capacitor circuit breaker timer as selected in Step 4. First, check temperature rise in channel 1 MOSFET (M1) during startup. The conditions include normal dV/dt startup to fully charge the 2000μF load capacitor and a fault condition in which M1 charges both the load capaci- tor and a parallel fault resistor , both at the maximum input voltage. If temperature rise is too high in normal startup condition, the inrush current may be reduced by select - ing a larger RAMP capacitor . If the inrush current must be reduced less than the value required to achieve the desired maximum charging time, a larger MOSFET has to be selected for channel 1. For the fault condition, the worst-case is found iteratively by changing the fault resis- tor value while monitoring the temperature rise. As a start- ing point, use a resistor of VS(MAX)/(4 • ILIM1(STARTUP)) or 57.2/(4 • 0.72) = 20Ω for this example. If the temperature rise is too high, startup current limit may be reduced by selecting a steeper foldback ratio or a larger sense resistor RS1. If the startup current limit must be reduced to less than or close to the dV/dt inrush required for the maxi - mum charging time, a larger MOSFET must be selected. Using the conditions of this example, it is found the worst- case temperature rise in M1 either in normal startup con- dition or with different fault resistors is lower than 10°C, an insignificant figure. This verifies the selected channel 1 MOSFET , PSMN7R6-100BSE, has more than enough SOA to handle the worst-case dissipation during startup. Second, check temperature rises in both channel 1 and channel 2 MOSFETs after startup when TMR times out under different overload conditions. The worst-case could be shorting the output to half of the available out - put voltage so there is no foldback while the V DS of the MOSFETs is still high. If the worst-case temperature rise in any channel is too high, larger MOSFET(s) must be selected for that channel. In this example, the worst-case temperature rise in channel 2 is an acceptable value of about 56°C and that in channel 1 is insignificant (<10°C). Step 7. Select resistive dividers for UV/OV inputs and ADC averaging resistors Although it is possible to use a single, four-resistor (or three-resistor if UVH and UVL connected together) divider as shown in Example 1, Step 7, two independent dividers

a LSB size of 25.6mA in 12-bit mode. copper for high current applications. plane, not the –48V input plane. reboot delay allows load capacitance to fully discharge. rent through a sense resistor between ADC + and ADC −. Figure 20. Layout Example of VEE Plane, –48V

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Rev. BFor more information www.analog.com APPLICATIONS INFORMATION CONFIG_3 register 0x0F is preset to 1. To measure cou- lombs, the energy meter may be configured to accumulate current rather than power by setting the INTEGRATE_I bit in CONFIG_3 register 0x0 F. The tick counter 0x80 to 0x83 keeps track of how many times power has been added into the energy meter . Dividing the energy by the tick count will yield the average power over the accumulation interval. The 4- byte tick counter will keep count for 9 years in the 12-bit mode before overflowing. When it overflows the TICK_OVERFLOW bit in METER_CONTROL register 0x 84 is set to 1 and an optional alert is generated if the TICK_OVERFLOW_ALERT bit in CONFIG_3 register 0x0F is preset to 1. Multiplying the value in the counter by the ADC conversion time yields the time that the energy meter has been accumulating. Both the energy accumulator and the tick counter are writ- able, allowing them to be preloaded with a given energy and/or time before overflow so that the LTC4284 will gen- erate an overflow alert after either a specified amount of energy has been delivered or time has passed. The following formulas are used to convert the values in the ADC data registers into physical units. Since the data are left justified, the same equations apply to all resolutions. To calculate single-ended voltages measured by ADC2: V = CODE(word) • 2.048V 216 To calculate currents in amperes measured by ADC1 and differential mode ADC2: I = CODE(word) • 32.768mV 216 •R SENSE To calculate power in watts: P = CODE(word) • 32.768mV • 2.048V 216 •R SENSE To calculate energy in joules: E = CODE(48 Bits) • 32.768mV • 2.048V • t CONV 224 •R SENSE where tCONV is the ADC conversion time depending upon the configured resolution (see Table 12). To calculate coulombs: Q = CODE(48 Bits) • 32.768mV • t CONV 216 •R SENSE To calculate average power over the energy accumulation period: PAVG = E tCONV • CODE(COUNTER) To calculate average current: IAVG = Q tCONV • CODE(COUNTER) To calculate voltage alarm thresholds: VALARM = CODE(byte) • 2.048V 256 To calculate current Alarm threshold in amperes: IALARM = CODE(byte) • 32.768mV 256 •R SENSE To calculate power Alarm threshold in watts: PALARM = CODE(byte) • 32.768mV • 2.048V 256 •R SENSE To synchronize multiple bytes of data from the tick coun- ter and energy meter , use the Read Page protocol (see Data Synchronization and Arbitration). An I2C read latches the tick counter and energy meter data in buffers while the tick counter and energy meter still increment. Alternatively one can set the METER_HALT bit in METER_CONTROL register 0x84 before reading the data. This will halt the ticker counter and energy meter . Clear the METER_HALT bit afterwards to reactivate incrementing. The LTC4284 ADCs also feature a snapshot mode that allows a one time measurement of a single data packet: ADC + − ADC−, VPWR (RTNS or DRNS), and an auxiliary input selected by the SNAPSHOT_SEL bits in ADC_ SNAPSHOT register 0x85. To enable the snapshot mode,

continuous mode, clear the ADC_HALT bit. input is –36V (VINPUT1) and the other is –72V (VINPUT2). Figure 22. Weighted Averaging Sense Voltages Figure 23. Feed Voltage and Open Fuse Monitoring

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Figure 24. Individual Feed Current and Channel Current Monitoring is monitored with the ADIN1 pin as shown in Figure 23. of 32.768mV (negative terminals are at VEE). shown in Figure 25 may be used. are denoted by EE_ in the first column of register Table 3. EEPROM is busy. See the Fault Log section for more detail. in the ADC_ALARM_LOG_1 register will be set. available. Any command code received will be NACKed. EEPROM locked. In this case the WP pin has no impact.

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The LTC4284’s EEPROM supports a fault logging feature. T welve bytes hold a log for a single fault event (Table 22). CONTROL, register 0x90, see Table 21). the EEPROM backup byte (EE_FAULT_LOG_CONTROL). CONTROL can’t be written until the busy condition clears. the ADC_ALARM_LOG_1 register (0x05).

1. VIN is above the UVLO limit.
2. FAULT_LOG_UNLOCK, FAULT_LOG_START and

log has been completely serviced). high while the LTC4284 is in single-wire broadcast mode.

1. Se t FAULT_LOG_START in the FAULT_LOG_
2. Write the 12 bytes of fault information as detailed in
3. Set FAULT_LOG_DONE in FAULT_LOG_CONTROL.
4. Set alert if FAULT_LOG_ALERT is set.
5. Unfreeze the shadow copy of fault bits.

The I2C bus is blocked for about 31ms (14 time tWRITE). quent fault bits set until after fault log writing finishes.

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Figure 25. Direct Monitoring of Load Voltage

Rev. BFor more information www.analog.com APPLICATIONS INFORMATION the first fault bit is set which leads to GATE1 and GATE2 low, the frozen copy of fault bits is closed and remains closed until after logging is complete. In the fault log, fault data comes from the frozen copy. During this time, fault information is still accumulated in the main fault registers. Servicing a Fault Log. After one fault log has been written, further fault log writes will be disabled until the first fault log has been serviced. The FAULT_LOG_START and FAULT_LOG_DONE bits can’t be set or cleared directly by I2C accesses. To prevent an accidental clearing of fault log information, a multi- byte sequence is required to fully service one fault log so another fault log can be written. The sequence is: 1. Write FAULT_LOG_CONTROL with FAULT_LOG_ UNLOCK set 2. Write a second time with FAULT_LOG_UNLOCK set and all other bits clear . This write will clear FAULT_ LOG_START and FAULT_LOG_DONE. 3. Write again with FAULT_LOG_UNLOCK, FAULT_LOG_ START and FAULT_LOG_DONE all clear . At this time, the FAULT_LOG_ENABLE and FAULT_LOG_ALERT bits may be set as desired. Additionally, to avoid inadvertently overwriting the logged data through I2C, bring WP high during servicing. Incomplete Fault Logs. A fault condition is a likely pre- cursor to an overall loss of power in the LTC4284. For accurate fault logging, the system design must provide sufficient external capacitance as described in Input Power Supply to hold INTVCC up during the time required to write 14 bytes to EEPROM. The fault log writing sequence described earlier provides a way to detect if the fault log doesn’ t complete suc - cessfully. The first EEPROM write saves FAULT_LOG_ CONTROL with the FAULT_LOG_START bit set. Then the final EEPROM write saves FAULT_LOG_CONTROL with both FAULT_LOG_START and FAULT_LOG_DONE bits set. After a loss of power , the FAULT_LOG_CONTROL reg - ister is loaded back from the saved EEPROM copy. If power was lost before a fault log completed, the FAULT_LOG_CONTROL register will have FAULT_LOG_ START set, but not FAULT_LOG_END. Also after a loss of power , if the FAULT_LOG_ALERT bit is set and FAULT_ LOG_START, FAULT_LOG_DONE or FAULT_LOG_ UNLOCK are set, the ALERT# pin will be pulled down to alert the system that an unserviced fault log remains in the chip. Digital Interface The LTC4284 communicates with a bus master using a serial 2-wire interface, compatible with both I 2C and SMBus. The 2-wire interface is supplemented by an SMBus-compatible ALERT# output. The LTC4284 is always a bus slave and doesn’t use clock stretching. Many LTC4284 applications require unidirectional isola - tors such as opto-couplers between the serial interface and the host system. For convenience of opto-coupling with the host, the SDA function is split into SDAI (input) and SDAO (output). For a conventional SDA line, tie SDAI and SDAO together. When using opto-couplers, connect the SDAI pin to the output of the incoming opto-coupler and connect the SDAO pin to the input of the outgoing opto-coupler (see Figure 2b). If the ALERT# line is used, connect it in the same way as the SDAO pin as shown in Figure 2b. Bus Compatibility The basic LTC4284 serial interface is compliant with I and SMBus AC and DC specifications. The timing is com- patible with 400Kbit operation for both. This includes the SMBus legacy tHD:DATO timing of 300ns minimum. In addition, the LTC4284 supports 1Mbit operation which is compatible with I 2C FastMode+ and SMBus 3.0. To use this timing, the FAST_I2C_EN bit in the CONFIG_3 register must be set. This bit may be set to 1 as default by EEPROM, or it can be manually written to 1. If the bit is 0 before writing, the write must be done at 400Kbit or less. With FAST_I2C_EN set, t HD:DATO is reduced to allow higher speed transfers. The LTC4284 SDAO output is guaranteed to pull down 20mA. This allows the use of a lower value pull-up resistor to reduce the low-to-high delay time.

Rev. B For more information www.analog.com APPLICATIONS INFORMATION START , REPEATED START and STOP Conditions When the bus is idle, SCL and SDA are high. A bus master signals the start of a transfer with a START condition. START is defined by a falling edge on SDA while SCL is high. The end of the transfer is signaled by a STOP condi- tion. STOP is defined by a rising edge on SDA while SCL is high (see Figure 26). In between START and STOP , data and handshake bits are transferred with a data value on SDA and a high pulse on SCL. For data or handshake bits, SDA changes only while SCL is low. A bus master may also signal a REPEATED START condi- tion in the middle of a transfer . Like START , REPEATED START is defined by a falling edge on SDA while SCL is high. REPEATED START is used in read transfers (see T ransfer Protocol Types). ACK/NACK Data is transferred as a series of 8-bit bytes. Following each data byte is a handshake bit driven by the receiver . SDA low during this bit is interpreted as acknowledge (ACK). SDA high is interpreted as not-acknowledge (NACK). In all cases, a transfer stops after a NACK bit. If the bus master is sending a data byte, a NACK from the slave indicates an error condition. If all bytes written are ACK’ed, the bus master may also terminate a write by making a STOP condition after the final byte. If the bus master is receiving a data, it returns NACK after the last byte it wants to receive. This is normal, no error condition is implied. I2C Device Addressing The bus master addresses a slave by sending a slave address byte after either a START or REPEATED START condition. Bit 0 of the slave address byte is high to select a read transfer and low to select a write. See T ransfer Protocol Types for more detail. The LTC4284 ADR1 and ADR0 pins can be configured to select its slave addresses as shown in Table 2. Single-wire broadcast mode replaces the normal serial- bus interface with a one-wire option which continuously broadcasts important status from the LTC4284. See more details in Single-Wire Broadcast. T ransfer Protocol Types Figure 26 shows basic elements of the I2C protocol. These are combined to form complete read and write transfers. Figures 27 to 32 show the transfer protocol types sup- ported by the LTC4284. Table 2. LTC4284 Device Addressing ADDRESS* BINARY DEVICE ADDRESS LTC4284 ADDRESS PINS 7-Bit 8-Bit a6 a5 a4 a3 a2 a1 a0 R/W ADR1 ADR0 Mass Write 1F 3E 0 0 1 1 1 1 1 0 X X Alert Response 0C 19 0 0 0 1 1 0 0 1 X X 0 10 20 0 0 1 0 0 0 0 X L L 1 11 22 0 0 1 0 0 0 1 X L NC 2 12 24 0 0 1 0 0 1 0 X H NC 3 13 26 0 0 1 0 0 1 1 X L H 4 14 28 0 0 1 0 1 0 0 X NC L 5 15 2A 0 0 1 0 1 0 1 X NC NC 6 16 2C 0 0 1 0 1 1 0 X H H 7 17 2E 0 0 1 0 1 1 1 X NC H

8 Single-Wire Broadcast Mode H L

H = Tie to INTVCC; L = Tie to VEE; NC = No connect or open; X = Don’t Care *8-bit hexadecimal address with LSB R/W bit = 0 7-bit hexadecimal address with MSB a7 = 0

Figure 26. General Data T ransfer over I2C

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Figure 27. Write Byte Protocol Figure 28. Write Word Protocol Figure 29. Write Page Protocol

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• • • 0 A

Figure 30. Read Byte Protocol Figure 31. Read Word Protocol Figure 32. Read Page Protocol Figure 33. Alert Response Protocol

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• • • ALERT RESPONSE ADDRESS DEVICE ADDRESS 0001100 S R 1 1

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Rev. B For more information www.analog.com APPLICATIONS INFORMATION Command Codes and Register Addressing The command byte in each transfer contains the register address for the first byte being accessed. If multiple bytes are accessed in a transfer , each comes from the address following the previous byte. For example, when reading the six-byte ENERGY register , the first byte comes from address 0x7A, the second byte from address 0x7B, up through the final byte from address 0x7F (see Table 3). It’s possible to access two different registers in one trans- fer . For example, the SYSTEM_STATUS and ADC_STATUS registers can be accessed using a read word transfer with COMMAND equal 0x00. This addressing method is common for I2C systems, but differs from SMBus. With SMBus, each register occupies a single command code, regardless of register size. Registers 0x41 to 0x79 are implemented in 16-bit RAM words as shown in Table 3. To save command codes, each occupies only one register address. Consider a four-byte read with command code of 0x41. Data will be returned in this order: Most significant byte of SENSE 2. Least significant byte of SENSE 3. Most significant byte of SENSE_MIN 4. Least significant byte of SENSE_MIN Write Protocols For writes, all data bytes come from the bus master and are acknowledged by the slave. Bit 0 of the slave address byte is clear to select write. The COMMAND byte contains the register address for the first byte being written. A special slave address can be used to implement mass writes. If multiple LTC4284 chips are on the same serial bus, the mass write technique can be used to write all of them at the same time. All LTC4284s respond to a slave address of 0011_111b with the R/W bit clear . Bit MASS_WRITE_ENABLE in register CONTROL_1 can be set to enable mass writes. Read Protocols Reads consist of two parts. First the master sends a slave address byte with bit 0 clear and a COMMAND byte to select the register to be read from. After this, a REPEATED START condition and second slave address byte are sent with bit 0 set (indicating read). The LTC4284 replies with data after the second slave address byte. Read Page and Write Page Protocols Read page and write page refer to transfers larger than two bytes. Page accesses are convenient for reading larger registers and for synchronizing data in multiple registers (see Data Synchronization and Arbitration for details). If page accesses are required, the PAGE_READ_ WRITE_ENABLE bit in the CONTROL_1 register should be set. If the bit is not set, accesses to more than two bytes of data will be terminated. For an attempted page write, the extra bytes would be NACK’ed. For an attempted page read, the LTC4284 would return 0xF F. Byte Ordering The LTC4284 uses big endian ordering for accessing multi-byte registers. That means when a 16-bit word register is accessed, the most significant byte is trans- ferred first, followed by the least significant byte. This is common in I2C systems. SMBus systems use little endian ordering, with least significant byte transferred first. ALERT# and Alert Response Protocol The LTC4284 fully supports the SMBus alert response mechanism. Refer to Figure 33: 1. If ALERT# is low , the LTC4284 will acknowledge the SMBus alert response address (ARA). 2. In the following data byte, the LTC4284 returns its own slave address, with bit 0 clear . Multiple slave devices on the bus may be responding to the same ARA. If a conflict is detected on any bit, the LTC4284 will back off and let the higher priority device continue. 3. If the LTC4284 successfully transfers its entire slave address, it will clear its ALERT_GENERATED bit, and stop pulling ALERT# low.

Rev. BFor more information www.analog.com APPLICATIONS INFORMATION There are 52 possible conditions to set ALERT_ GENERATED. Each condition (fault or event) has a cor - responding alert enable bit. Table 24 has the list of fault/ event bits and alert enable bits. For all cases, ALERT_GENERATED will only be set by a rising edge on the combination of fault/event logically and’ed with alert enable bit. ALERT_GENERATED is set whether a fault/event bit is set first or the corresponding alert enable bit is set first. Once a fault or event bit is set, it won’t contribute to ALERT_GENERATED again until the fault or event is cleared. One event, ADC conversion completed, doesn’ t have a latched status bit. There is a corresponding ADC_CONV_ ALERT bit to enable the ALERT_GENERATED. But when servicing ALERT#, software won’t have a way to verify that a completed ADC conversion caused the alert condition. Due to this limitation, the ADC conversion completed alert is not useful unless all other alert sources are masked off. Typically, software will read the event and fault regis - ters to check status, then write 0’ s to clear the bits that have been serviced. Event and fault bits can also be set directly by the I2C bus. A bit set this way leads to ALERT_ GENERATED set and ALERT# low in the same way as when the chip sets the bit. ALERT_GENERATED itself can also be set by an I2C write. These features may be helpful for software test. Stuck Bus Reset The LTC4284 has an SMBus-style stuck bus reset. If the serial bus remains stuck for about 30ms, the I2C control- ler block will reset itself. When the controller is reset, it stops pulling down SDAO and searches for a new ST ART condition. In the SMBus definition, the stuck bus timer is cleared by SCL high. Many existing L TC chips including previous hot swap controllers clear the timer when SCL and SDA are both high. This is more thorough because it can detect either SDA or SCL stuck low. The method presents a problem with the LTC4284. With read page or write page, very long transfers are possible. For each byte of 0x00 transferred, SDA will be low for the whole byte. A long sequence of 0x00 bytes may lead to false stuck bus timeouts. The LTC4284 uses a modified stuck bus mechanism to prevent false timeouts. The timer is cleared If SCL is high and the LTC4284 is not pulling down SDAO. As with other stuck bus timers, SCL stuck low causes a timeout. In addition, a timeout happens if the LTC4284 continuously pulls down SDAO for 30ms. This could hap- pen if the bus stops with SCL high while the LTC4284 is still pulling down on SDAO. Data Synchronization and Arbitration Several RAM locations and registers in the LTC4284 have control shared between ADC logic and the I 2C interface. ADC logic writes data and the I 2C interface reads from them. The RAM locations are at addresses between 0x41 and 0x79. Registers for ENERGY and TICK_COUNTER are at addresses between 0x7A and 0x83. These registers are also written by ADC logic. ADC writes to ENERGY, TICK_COUNTER and the ADC RAM locations are always done while the I 2C interface is idle. That ensures none of the locations can change in the middle of an I 2C read. For example, when reading a two-byte RAM location, the two bytes read will always be consistent with each other . The ENERGY and TICK_COUNTER registers are larger , but the same technique can be used. To ensure consistency, read all bytes of each register in a single I 2C operation. For energy calculations, you may also need ENERGY and TICK_COUNTER to be consistent with each other . This can be done by reading both registers together in a single 10-byte I2C read. The register locations are contiguous to facilitate this approach. Read 10 bytes starting at register location 0x7A. There are some limits on the length of I 2C transfers. If any one transfer takes longer than an ADC conversion time, some ADC data will be lost. This depends on the bus speed, transfer length and ADC conversion time. See the ADC[2:0] field in Table 12. As detailed above, the I 2C interface operates in parallel with ADC update logic. In some other cases, I 2C access will be disabled:

4284 F34

1. After a power-on reset or reboot, I 2C access is dis -
2. While a fault log is being written to EEPROM
3. After a write to the REBOOT register which sets the

the 4284 doesn’t ACK them in the three cases listed above. returned by the LTC4284 in place of the expected data. EEPROM to working registers after a power up or reboot. wire broadcast mode can reduce this to one isolator . nected to V EE, single-wire broadcast mode is selected. Figure 34. An Example of Manchester Encoding, Showing Both Conventions

for an explanation of the channel select sequence. bit cell. G.E. Thomas convention is used for the LTC4284. This is the same as for the LTC4261. using field BC in the CONFIG_3 register , see Table 11. Figure 35. Manchester Encoding for the Preamble Byte of 0x2A

4284 F350 0 1 0 1 0 1 0

Table 3. LTC4284 Register Address and Contents

Table 3. LTC4284 Register Address and Contents (Cont.)

Rev. BFor more information www.analog.com APPLICATIONS INFORMATION REGISTER NAME REGISTER ADDRESS* DESCRIPTION READ/ WRITE DATA LENGTH (BYTES) DEFAUL T VALUE Reserved 0xA3 Read only, always returns 0 R 1 N/A EE_FAULT 0xA4 Records fault register in EEPROM upon a fault R/W 1 0x00 EE_ADC_ALARM_LOG 0xA5-0xA9 Records ADC_ALARM_LOG registers in EEPROM upon a fault R/W 5 0x0000_0000_00 EE_CONTROL 0xAA-0xAB Stores default of CONTROL registers in EEPROM R/W 2 0xDB03 Reserved 0xAC Read only, returns 0xFF if EEPROM busy, otherwise returns 0 R 1 N/A EE_CONFIG 0xAD-0xAF Stores default of CONFIG registers in EEPROM R/W 3 0x0CC0_00 EE_PGIO_CONFIG 0xB0-0xB1 Stores default of PGIO_CONFIG registers in EEPROM R/W 2 0x0004 EE_ADIO_CONFIG 0xB2 Stores default of ADIO_CONFIG register in EEPROM R/W 1 0xF0 EE_ADC_SELECT 0xB3-0xB4 Stores default of ADC_SELECT registers in EEPROM R/W 2 0xFF0F EE_FAULT_ALERT 0xB5 Stores default of FAULT_ALERT register in EEPROM R/W 1 0x00 EE_ADC_ALERT 0xB6-0xBA Stores default of ADC_ALERT registers in EEPROM R/W 5 0x0000_0000_00 EE_SENSE_MIN_TH 0xBB Stores default of SENSE_MIN_TH register in EEPROM R/W 1 0x00 EE_SENSE_MAX_TH 0xBC Stores default of SENSE_MAX_TH register in EEPROM R/W 1 0xFF EE_VPWR_MIN_TH 0xBD Stores default of VPWR_MIN_TH register in EEPROM R/W 1 0x00 EE_VPWR_MAX_TH 0xBE Stores default of VPWR_MAX_TH register in EEPROM R/W 1 0xFF EE_POWER_MIN_TH 0xBF Stores default of POWER_MIN_TH register in EEPROM R/W 1 0x00 EE_POWER_MAX_TH 0xC0 Stores default of POWER_MAX_TH register in EEPROM R/W 1 0xFF EE_ADIN1_MIN_TH 0xC1 Stores default of ADIN1_MIN_TH register in EEPROM R/W 1 0x00 EE_ADIN1_MAX_TH 0xC2 Stores default of ADIN1_MAX_TH register in EEPROM R/W 1 0xFF EE_ADIN2_MIN_TH 0xC3 Stores default of ADIN2_MIN_TH register in EEPROM R/W 1 0x00 EE_ADIN2_MAX_TH 0xC4 Stores default of ADIN2_MAX_TH register in EEPROM R/W 1 0xFF EE_ADIN3_MIN_TH 0xC5 Stores default of ADIN3_MIN_TH register in EEPROM R/W 1 0x00 EE_ADIN3_MAX_TH 0xC6 Stores default of ADIN3_MAX_TH register in EEPROM R/W 1 0xFF EE_ADIN4_MIN_TH 0xC7 Stores default of ADIN4_MIN_TH register in EEPROM R/W 1 0x00 EE_ADIN4_MAX_TH 0xC8 Stores default of ADIN4_MAX_TH register in EEPROM R/W 1 0xFF EE_ADIO1_MIN_TH 0xC9 Stores default of ADIO1_MIN_TH register in EEPROM R/W 1 0x00 EE_ADIO1_MAX_TH 0xCA Stores default of ADIO1_MAX_TH register in EEPROM R/W 1 0xFF EE_ADIO2_MIN_TH 0xCB Stores default of ADIO2_MIN_TH register in EEPROM R/W 1 0x00 EE_ADIO2_MAX_TH 0xCC Stores default of ADIO2_MAX_TH register in EEPROM R/W 1 0xFF EE_ADIO3_MIN_TH 0xCD Stores default of ADIO3_MIN_TH register in EEPROM R/W 1 0x00 EE_ADIO3_MAX_TH 0xCE Stores default of ADIO3_MAX_TH register in EEPROM R/W 1 0xFF EE_ADIO4_MIN_TH 0xCF Stores default of ADIO4_MIN_TH register in EEPROM R/W 1 0x00 EE_ADIO4_MAX_TH 0xD0 Stores default of ADIO4_MAX_TH register in EEPROM R/W 1 0xFF EE_DRNS_MIN_TH 0xD1 Stores default of DRNS_MIN_TH register in EEPROM R/W 1 0x00 EE_DRNS_MAX_TH 0xD2 Stores default of DRNS_MAX_TH register in EEPROM R/W 1 0xFF EE_DRAIN_MIN_TH 0xD3 Stores default of DRAIN_MIN_TH register in EEPROM R/W 1 0x00 EE_DRAIN_MAX_TH 0xD4 Stores default of DRAIN_MAX_TH register in EEPROM R/W 1 0xFF EE_SENSE1_MIN_TH 0xD5 Stores default of SENSE1_MIN_TH register in EEPROM R/W 1 0x00 EE_SENSE1_MAX_TH 0xD6 Stores default of SENSE1_MAX_TH register in EEPROM R/W 1 0xFF x. LTC4284 Register Address and Contents (Cont.)

Table 4. SYSTEM_STATUS Registers (0x00) – Read Only

7 FET_ON_STATUS On/off status of GATE; 1 = GATE commanded on, 0 = GATE commanded off

6 EN# State of EN# pin; 1 = EN# high, 0 = EN# low

5 GATE2_HIGH State of GATE2 pin; 1 = GAT E2 high, 0 = GATE2 low

4 GATE1_HIGH State of GATE1 pin; 1 = GAT E1 high, 0 = GATE1 low

2 EEPROM _BUSY Status of EEPROM writing; 1 = EEPROM is being written, 0 = EEPROM writing is completed

1 PG_STATUS Power good status; 1 = power good condition met, 0 = power good condition not met

0 MODE1 Single driver mode (Mode 1) status; 1 = Mode 1 is enabled, 0 = Mode 1 is disabled

Table 5. ADC_STATUS Register (0x01) – Read Only

0000 ADIN1 0x4A

0001 ADIN2 0x4D

0010 ADIN3 0x50

0011 ADIN4 0x53

0100 ADIO1 0x56

0101 ADIO2 0x59

0110 ADIO3 0x5C

0111 ADIO4 0x5F

1000 DRNS 0x62

1001 DRAIN 0x65

1010 SENSE1 + – SENSE1– 0x68

1011 SENSE2 + – SENSE2– 0x6B

1100 ADIN2 – ADIN1 0x6E

1101 ADIN4 – ADIN3 0x71

1110 ADIO2 – ADIO1 0x74

1111 ADIO4 – ADIO3 0x77

2 MODE2 Parallel mode (Mode 2) status; 1 = Mode 2 is enabled, 0 = Mode 2 is disabled

1 MODE3 High stress staged start mode (Mode 3) status; 1 = Mode 3 is enabled, 0 = Mode 3 is disabled

0 MODE4 Low stress staged start mode (Mode 4) status; 1 = Mode 4 is enabled, 0 = Mode 4 is disabled

Table 6. INPUT_STATUS Register (0x02) – Read Only

7 PGIO1_INPUT State of PGIO1 pin; 1 = PGIO1 high, 0 = PGIO1 low

6 PGIO2_INPUT State of PGIO2 pin; 1 = PGIO2 high, 0 = PGIO2 low

5 PGIO3_INPUT State of PGIO3 pin; 1 = PGIO3 high, 0 = PGIO3 low

4 PGIO4_INPUT State of PGIO4 pin; 1 = PGIO4 high, 0 = PGIO4 low

3 ADIO1_INPUT State of ADIO1 pin; 1 = ADIO1 high, 0 = ADIO1 low

2 ADIO2_INPUT State of ADIO2 pin; 1 = ADIO2 high, 0 = ADIO2 low

1 ADIO3_INPUT State of ADIO3 pin; 1 = ADIO3 high, 0 = ADIO3 low

0 ADIO4_INPUT State of ADIO4 pin; 1 = ADIO4 high, 0 = ADIO4 low

Table 8. FAUL T Register (0x04) – Read/Write

7 EXT_FAULT External fault at PGIO4 pin; 1 = external fault detected, 0 = no external fault 0

6 FET_SHORT_FAULT FET short fault; 1 = FET short fault occurred, 0 = no FET short fault 0

4 PGI_FAULT PGI fault at PGIO3 pin; 1 = PGI fault occurred, 0 = no PGI fault 0

3 FET_BAD_FAULT FET bad fault; 1 = FET bad fault occurred, 0 = no FET bad fault 0

2 OC_FAULT Overcurrent fault; 1 = overcurrent fault occurred, 0 = no overcurrent fault 0

1 UV_FAULT Undervoltage fault; 1 = undervoltage fault occurred, 0 = no undervoltage fault 0

0 OV_FAULT Overvoltage fault; 1 = overvoltage fault occurred, 0 = no overvoltage fault 0

Table 7. FAULT_STATUS Register (0x03) – Read Only

6 FET_SHORT_STATUS FET short status; 1 = FET shorted, 0 = FET not shorted

5 VOUT_LOW V OUT low status; 1 = VOUT < VOUTTH, 0 = VOUT ≥ VOUTTH

3 FET_BAD_STATUS FET bad status; 1 = FET bad condition present, 0 = FET bad condition not present

1 UV_STATUS Input undervoltage status; 1 = UVH and UVL are low, 0 = UVH or UVL high

0 OV_STATUS Input overvoltage status; 1 = OV high, 0 = OV low

7 EN#_CHANGED EN# pin changed state; 1 = EN# changed state, 0 = EN# unchanged 0

3 VPWR_HIGH_ALARM VPWR was above VPWR_MAX_TH; 1 = VPWR was high, 0 = VPWR has not been high 0

2 VPWR_LOW_ALARM VPWR was below VPWR_MIN_TH; 1 = VPWR was low, 0 = VPWR has not been low 0

1 POWER_HIGH_ALARM POWER was above POWER_MAX_TH; 1 = POWER was high, 0 = POWER has not been high 0

0 POWER_LOW_ALARM POWER was below POWER_MIN_TH; 1 = POWER was low, 0 = POWER has not been low 0

7 ADIN1_HIGH_ALARM ADIN1 was above ADIN1_MAX_TH; 1 = ADIN1 was high, 0 = ADIN1 has not been high 0

6 ADIN1_LOW_ALARM ADIN1 was below ADIN1_MIN_TH; 1 = ADIN1 was low, 0 = ADIN1 has not been low 0

5 ADIN2_HIGH_ALARM ADIN2 was above ADIN2_MAX_TH; 1 = ADIN2 was high, 0 = ADIN2 has not been high 0

4 ADIN2_LOW_ALARM ADIN2 was below ADIN2_MIN_TH; 1 = ADIN2 was low, 0 = ADIN2 has not been low 0

3 ADIN3_HIGH_ALARM ADIN3 was above ADIN3_MAX_TH; 1 = ADIN3 was high, 0 = ADIN3 has not been high 0

2 ADIN3_LOW_ALARM ADIN3 was below ADIN3_MIN_TH; 1 = ADIN3 was low, 0 = ADIN3 has not been low 0

1 ADIN4_HIGH_ALARM ADIN4 was above ADIN4_MAX_TH; 1 = ADIN4 was high, 0 = ADIN4 has not been high 0

0 ADIN4_LOW_ALARM ADIN4 was below ADIN4_MIN_TH; 1 = ADIN4 was low, 0 = ADIN4 has not been low 0

7 ADIO1_HIGH_ALARM ADIO1 was above ADIO1_MAX_TH; 1 = ADIO1 was high, 0 = ADIO1 has not been high 0

6 ADIO1_LOW_ALARM ADIO1 was below ADIO1_MIN_TH; 1 = ADIO1 was low, 0 = ADIO1 has not been low 0

5 ADIO2_HIGH_ALARM ADIO2 was above ADIO2_MAX_TH; 1 = ADIO2 was high, 0 = ADIO2 has not been high 0

4 ADIO2_LOW_ALARM ADIO2 was below ADIO2_MIN_TH; 1 = ADIO2 was low, 0 = ADIO2 has not been low 0

3 ADIO3_HIGH_ALARM ADIO3 was above ADIO3_MAX_TH; 1 = ADIO3 was high, 0 = ADIO3 has not been high 0

2 ADIO3_LOW_ALARM ADIO3 was below ADIO3_MIN_TH; 1 = ADIO3 was low, 0 = ADIO3 has not been low 0

1 ADIO4_HIGH_ALARM ADIO4 was above ADIO4_MAX_TH; 1 = ADIO4 was high, 0 = ADIO4 has not been high 0

0 ADIO4_ LOW_ALARM

Table 9. ADC_ALARM_LOG Registers (0x05–0x09) – Read/Write

Rev. B For more information www.analog.com APPLICATIONS INFORMATION BIT NAME OPERATION DEFAUL T ADC_ALARM_LOG_4 (0x08) – Read/Write

7 DRNS_HIGH_ALARM DRNS was above DRNS_MAX_TH; 1 = DRNS was high, 0 = DRNS has not been high 0

6 DRNS_LOW_ALARM DRNS was below DRNS_MIN_TH; 1 = DRNS was low, 0 = DRNS has not been low 0

5 DRAIN_HIGH_ALARM DRAIN was above DRAIN_MAX_TH; 1 = DRAIN was high, 0 = DRAIN has not been high 0

4 DRAIN_LOW_ALARM DRAIN was below DRAIN_MIN_TH; 1 = DRAIN was low, 0 = DRAIN has not been low 0

3 SENSE1_HIGH_ALARM SENSE1+ – SENSE1– was above SENSE1_MAX_TH; 1 = SENSE1+ – SENSE1– was high, 0 = SENSE1+ – SENSE1– has not been high 2 SENSE1_LOW_ALARM SENSE1 + – SENSE1– was below SENSE1_MIN_TH; 1 = SENSE1+ – SENSE1– was low, 0 = SENSE1+ – SENSE1– has not been low 1 SENSE2_HIGH_ALARM SENSE2+ – SENSE2– was above SENSE2_MAX_TH; 1 = SENSE2+ – SENSE2– was high, 0 = SENSE2+ – SENSE2– has not been high 0 SENSE2_LOW_ALARM SENSE2 + – SENSE2– was below SENSE2_MIN_TH; 1 = SENSE2+ – SENSE2– was low, 0 = SENSE2+ – SENSE2– has not been low ADC_ALARM_LOG_5 (0x09) – Read/Write 7 ADIN12_HIGH_ALARM ADIN2 – ADIN1 was above ADIN12_MAX_TH; 1 = ADIN2 – ADIN1 was high, 0 = ADIN2 – ADIN1 has not been high 6 ADIN12_LOW_ALARM ADIN2 – ADIN1 was below ADIN12_MIN_TH; 1 = ADIN2 – ADIN1 was low, 0 = ADIN2 – ADIN1 has not been low 5 ADIN34_HIGH_ALARM ADIN4 – ADIN3 was above ADIN34_MAX_TH; 1 = ADIN4 – ADIN3 was high, 0 = ADIN4 – ADIN3 has not been high 4 ADIN34_LOW_ALARM ADIN4 – ADIN3 was below ADIN34_MIN_TH; 1 = ADIN4 – ADIN3 was low, 0 = ADIN4 – ADIN3 has not been low 3 ADIO12_HIGH_ALARM ADIO2 – ADIO1 was above ADIO12_MAX_TH; 1 = ADIO2 – ADIO1 was high, 0 = ADIO2 – ADIO1 has not been high 2 ADIO12_LOW_ALARM ADIO2 – ADIO1 was below ADIO12_MIN_TH; 1 = ADIO2 – ADIO1 was low, 0 = ADIO2 – ADIO1 has not been low

1 ADIO34_ HIGH_ALARM

ADIO4 – ADIO3 was above ADIO34_MAX_TH; 1 = ADIO4 – ADIO3 was high, 0 = ADIO4 – ADIO3 has not been high 0 ADIO34_LOW_ALARM ADIO4 – ADIO3 was below ADIO34_MIN_TH; 1 = ADIO4 – ADIO3 was low, 0 = ADIO4 – ADIO3 has not been low

Table 10. CONTROL Registers (0x0A-0x0B) – Read/Write

7 ON Turns MOSFET on and off; 1 = turn MOSFET on, 0 = turn MOSFET off 1

6 DVDT Enables dV/dt inrush control during startup; 1 = enabled, 0 = disabled 1

5 THERM_TMR Turns 2μa TMR pull-down off; 1 = TMR pull-down turned off, 0 = TMR pull-down turned on 0

3 PWRGD_RESET_ CNTRL Configures power good reset; 1 = reset by V OUT low, 0 = reset by MOSFET off 1

2 PGIO2_ACLB Configures PGIO2; 1 = PGIO2 as inverted output for active current limit engagement after

1 MASS_WRITE_ ENABLE Enables mass write to all LTC4284S on the I 2C bus; 1 = enabled, 0 = disabled 1

0 PAGE_READ_WRITE_ ENABLE Enables I 2C page read/write protocols; 1 = enabled, 0 = disabled 1

6 PGI_RETRY Enables auto-retry following a PGI_FAULT; 1 = unlimited retries, 0 = no retry (latch-off) 0

11 Unlimited

1 UV_RETRY Enables auto-retry following a UV_FAULT; 1 = unlimited retries, 0 = no retry (latch-off) 1

0 OV_RETRY Enables auto-retry following an OV_FAULT; 1 = unlimited retries, 0 = no retry (latch-off) 1

Table 11. CONFIG Registers (0x0D-0x0F) – Read/Write

0 LPFB Enables load power foldback after startup; 1 = enabled, 0 = disabled 0

Rev. BFor more information www.analog.com APPLICATIONS INFORMATION BIT NAME OPERATION DEFAUL T 5:4 FTBD_DL Configures FET_Bad fault filtering timer delay, tDL(FETBAD) FTBD_DL [5:4] t DL(FETBAD) [s] 00 0.256 01 0.512 10 1.02 11 2.05 3:1 COOLING_DL Configures cooling delay preceding each auto-retry following OC_FAULT, FET_BAD_FAULT or EXT_FAULT, tDL(RTRY) COOLING_DL [3:1] t DL(RTRY) [s] 000 0.512 001 1.02 010 2.05 011 4.10 100 8.19 101 16.4 110 32.8 111 65.5 000 0 PORB Resets to 0 upon power-on reset. Write this bit to 1 to use it as power-on reset indicator: 1 = power-on reset has not occurred, 0 = power-on reset occurred CONFIG_3 (0x0F) – Read/Write BIT NAME OPERATION DEFAUL T 7 EXTFLT_TURN_OFF Turns MOSFET off following an external fault; 1 = turn MOSFET off, 0 = keep MOSFET on 0 6 VPWR_SELECT Selects voltage for ADC power multiplication; 1 = selects DRNS (attenuated drain voltage for MOSFET power), 0 = selects RTNS (attenuated input voltage for input power)

5 FAST_I2C_EN Enables fast I

2C mode; 1 = fast I2C enabled, 0 = fast I2C disabled 0 4:3 BC Configures bit rate of single-wire broadcast mode, fBC BC [4:3] fBC [kbit/s] 00 2048 01 512 10 128 (Not available for 8-bit ADC) 11 32 (Not available for 8-bit ADC) 2 TICK_OVERFLOW_ ALERT Enables alert when tick counter overflows; 1 = alert enabled, 0 = alert disabled 0 1 METER_OVERFLOW_ ALERT Enables alert when energy meter overflows; 1 = alert enabled, 0 = alert disabled 0

0 INTEGRATE_I Enables integration of current; 1 = integrate current, 0 = integrate power 0

Table 12. PGIO_CONFIG Registers (0x10:0x11) – Read/Write

00 EXT_ FAUL T#

01 EXT_FAULT

10 General purpose output

11 General purpose input

00 PGI#

01 PGI

00 Power Good 2#

01 Power Good 2

00 Power Good 1#

01 Power Good 1

7 PGIO4_OUT Output data bit to PGIO4 pin when configured as general purpose output 0

6 PGIO3_OUT Output data bit to PGIO3 pin when configured as general purpose output 0

5 PGIO2_OUT Output data bit to PGIO2 pin when configured as general purpose output 0

4 PGIO1_OUT Output data bit to PGIO1 pin when configured as general purpose output 0

Table 13. ADIO_CONFIG Register (0x12) – Read/Write

3 ADIO4_OUT Output data bit to ADIO4 pin when configured as general purpose output 0

2 ADIO3_OUT Output data bit to ADIO3 pin when configured as general purpose output 0

1 ADIO2_OUT Output data bit to ADIO2 pin when configured as general purpose output 0

0 ADIO1_OUT Output data bit to ADIO1 pin when configured as general purpose output 0

Table 14. ADC_SELECT Registers (0x13-0x14) – Read/Write

7 ADIO4_SELECT Selects ADIO4 as input for ADC measurement; 1 = selected, 0 = not selected 1

6 ADIO3_SELECT Selects ADIO3 as input for ADC measurement; 1 = selected, 0 = not selected 1

5 ADIO2_SELECT Selects ADIO2 as input for ADC measurement; 1 = selected, 0 = not selected 1

4 ADIO1_SELECT Selects ADIO1 as input for ADC measurement; 1 = selected, 0 = not selected 1

3 ADIN4_SELECT Selects ADIN4 as input for ADC measurement; 1 = selected, 0 = not selected 1

2 ADIN3_SELECT Selects ADIN3 as input for ADC measurement; 1 = selected, 0 = not selected 1

1 ADIN2_SELECT Selects ADIN2 as input for ADC measurement; 1 = selected, 0 = not selected 1

0 ADIN1_SELECT Selects ADIN1 as input for ADC measurement; 1 = selected, 0 = not selected 1

7 ADIO34_SELECT Selects ADIO4 – ADIO3 as input for ADC measurement; 1 = selected, 0 = not selected 0

6 ADIO12_SELECT Selects ADIO2 – ADIO1 as input for ADC measurement; 1 = selected, 0 = not selected 0

5 ADIN34_SELECT Selects ADIN4 – ADIN3 as input for ADC measurement; 1 = selected, 0 = not selected 0

4 ADIN12_SELECT Selects ADIN2 – ADIN1 as input for ADC measurement; 1 = selected, 0 = not selected 0

1 DRAIN_SELECT Selects DRAIN as input for ADC measurement; 1 = selected, 0 = not selected 1

0 DRNS_SELECT Selects DRNS as input for ADC measurement; 1 = selected, 0 = not selected 1

Table 15. FAULT_ALERT Register (0x15) – Read/Write

7 EXT_FAULT_ALERT Enables alert for external fault; 1 = enable alert, 0 = disable alert 0

6 FET_SHORT_ALERT Enables alert for FET short fault; 1 = enable alert, 0 = disable alert 0

5 POWER_FAILED_ ALERT Enables alert for power failed fault; 1 = enable alert, 0 = disable alert 0

4 PGI_ALERT Enables alert for PGI fault; 1 = enable alert, 0 = disable alert 0

3 FET_BAD_ALERT Enables alert for FET bad fault; 1 = enable alert, 0 = disable alert 0

2 OC_ALERT Enables alert for overcurrent fault; 1 = enable alert, 0 = disable alert 0

1 UV_ALERT Enables alert for undervoltage fault; 1 = enable alert, 0 = disable alert 0

0 OV_ALERT Enables alert for overvoltage fault; 1 = enable alert, 0 = disable alert 0

7 EN#_CHANGED_ALERT Enables alert when EN# pin changed state; 1 = enable alert, 0 = disable alert 0

3 VPWR_HIGH_ALERT Enables alert when VPWR was above VPWR_MAX_TH; 1 = enable alert, 0 = disable alert 0

2 VPWR_LOW_ALERT Enables alert when VPWR was below VPWR_MIN_TH; 1 = enable alert, 0 = disable alert 0

Table 16. ADC_ALERT Registers (0x16-0x1A) – Read/Write

7 DRNS_HIGH_ALERT Enables alert when DRNS was above DRNS_MAX_TH; 1 = enable alert, 0 = disable alert 0

6 DRNS_LOW_ALERT Enables alert when DRNS was below DRNS_MIN_TH; 1 = enable alert, 0 = disable alert 0

3 SENSE1_HIGH_ALERT Enables alert when SENSE1 + – SENSE1– was above SENSE1_MAX_TH; 1 = enable alert,

2 SEN SE1_LOW_ALERT

1 SEN SE2_HIGH_ALERT

0 SEN SE2_LOW_ALERT

Table 17. ENERGY Registers (0x7A-0x7F) – Read/Write Table 18. TICK_COUNTER Registers (0x80-0x83) – Read/Write Table 19. METER_CONTROL Register (0x84) – Read/Write

7 METER_RESET Resets energy meter and tick counter until cleared; 1 = reset, 0 = reset cleared 0

6 METER_HALT Halts energy meter and tick counter from accumulating; 1 = halted, 0 = not halted 0

5 TICK_OVERFLOW Tick counter has overflowed; 1 = overflowed, 0 = not overflowed 0

4 METER_OVERFLOW Energy meter accumulator has overflowed; 1 = overflowed, 0 = not overflowed 0

2 EE_LOCK EEPROM lock status, read only; 1 = EEPROM is factor

Table 20. ADC_SNAPSHOT Register (0x85) — Read/Write

0000 ADIN1

0001 ADIN2

0010 ADIN3

0011 ADIN4

0100 ADIO1

0101 ADIO2

0110 ADIO3

0111 ADIO4

1000 DRNS

1001 DRAIN

1010 SENSE1+ – SENSE1–

1011 SENSE2+ – SENSE2–

1100 ADIN2 – ADIN1

1101 ADIN4 – ADIN3

1110 ADIO2 – ADIO1

1111 ADIO4 – ADIO3

3 ADC_HALT Enables ADC snapshot mode; 1 = snapshot, 0 = continuous conversion 0

Table 21. FAULT_LOG_CONTROL Register (0x90) – Read/Write

6 FAULT_LOG_UNLOCK Allows clearing of FAULT_LOG_START and FAULT_LOG_DONE bits to re-enable fault log

3 FAULT_LOG_ALERT Enables alert when a fault log is completed; 1 = enable alert, 0 = disable alert 0

Table 22. Registers Recorded to EEPROM During Fault Log Table 23. REBOOT Register (0xA2) – Read/Write

0 WP_STATUS WP pin status; 1 = WP is high, 0 = WP pin is low 0

Table 24. Mapping between Faults/Alarms and Alert Masks

Rev. B For more information www.analog.com PACKAGE DESCRIPTION 5.00 ±0.10 NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS PIN 1 TOP MARK (SEE NOTE 6) 43 44 BOTTOM VIEW—EXPOSED PAD 6.55 ±0.10 8.00 ±0.10 0.75 ± 0.05 0.75 ±0.05 R = 0.125 TYP 0.00 – 0.05 0.25 ±0.05 (UHG44) QFN 0417 REV 0

0.50 BSC

0.325 REF

0.200 REF

6.50 REF

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPL Y SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

3.50 REF

0.40 ±0.10 0.00 – 0.05 0.70 ±0.05 0.50 BSC1.00 BSC 3.50 REF4.10 ±0.05 5.50 ±0.05 0.25 ±0.05 6.55 ±0.05 3.55 ±0.05 7.10 ±0.05 8.50 ±0.05 PACKAGE OUTLINE 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER 44-Lead Plastic QFN (5mm × 8mm) (Reference LTC DWG # 05-08-1581 Rev Ø) 3.55 ±0.10 DETAIL A

0.08 REF

0.31 REF

Rev. BFor more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 01/20 Added patent number 10263414. Changed RTN to VZ resistor value from 1W to 0.25W in figure. Changed all register names with RTNS reference to VPWR (i.e. RTNS_MIN changed to VPWR_MIN). Corrected bit number for METER_CONTROL Reserved register . Added METER_CONTROL EE_LOCK register bit. 1 ,19, 32, 34, 36 62, 63, 65, 69, 76, 79 B 07/21 Updated Current Limit Voltage from 2% to <3.3%. Updated ADC accuracy from 0.5% to 0.7%. Pins in front cover Typical Application circuit: Changed EN to EN#, added ALERT#. Removed C-Grade specifications of Current Limit Voltage and ADC Full-Scale Error . Changed “TMR Pin Function” to “Circuit Breaker/SOA Timer”. Changed Power ADC Full-Scale Error from ±1.2% to ±1.5%. PGIO4 Pin Function: Added “through a 10kΩ pull-up resistor” in last sentence. TMR Pin Function: Added “Circuit Breaker/SOA” in first sentence. C IN equation: Corrected brackets and added right parenthesis. ITMR(UP) equations in Case 4: Changed 2μA to ITMR(OS) to differentiate it from the Onset TMR Pull-Up Current in Current Limit. Changed “VPWR(RTNS/DRNS)” to “VPWR (RTNS or DRNS)”. Changed “tHD:DATO” to “t HD:DATO”. Changed “Read/Write#” to “R/ W”. Changed “X8 + X2 + X + 1” to “X 8 + X2 + X + 1”. 5, 7 16, 50, 51, 62, 63 56, 57

4284 F36

Figure 36. –48V/1200W Hot Swap Controller Monitoring System Status, Faults, Currents, Voltages,