LT4239 AD | Alldatasheet

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Rev. 0For more information www.analog.com Document Feedback TYPICAL APPLICATION FEATURES DESCRIPTION High Current Hot Swap Controller with Current Monitor Output The LT®4239 hot swap controller allows a board to be safely inserted and removed from a live backplane. Using external N-channel pass transistors, board supply voltage and inrush current are ramped up at a controlled rate. Dual 12V gate drive supports high current loads by providing a two-stage start-up that first charges the load capacitance followed by enabling a low on-resistance path to the load. The supply output is protected against short-circuit faults with a fast-acting electronic circuit breaker . By placing the sense resistor on the output side and an RC filter at the device’s supply pin, the MOSFET avalanching can suppress the surge voltage when it is abruptly turned off without the additional TVS at the board supply input. The LT4239 features a current monitor that amplifies the voltage across an external sense resistor . It also provides undervoltage protection, and reports fault and power good status for the supply. A boost mode allows the cir- cuit breaker and current limit thresholds to be raised to ride through load surges without generating a fault.

APPLICATIONS

n Allows Safe Board Insertion into Live Backplane n Wide Operating Voltage Range: 4V to 20V n Dual Gate Drivers for High Current Applications n Withstands Surge Voltage without Protection TVS n Monitors VGS and VDS for MOSFET Health n Accurate 10mV ± 5% Circuit Breaker Threshold n Boost Mode for Load Surges n Current Monitor Output n 12V Gate Drive for Lower MOSFET RDS(ON) n Adjustable Start-Up and Overcurrent Fault Delay n Input Undervoltage Protection n Fault and Power Good Output n 16-Lead 4mm × 3mm DFN Package n Electronic Circuit Breaker n Enterprise Servers and Data Storage Systems n Network Routers and Switches All registered trademarks and trademarks are the property of their respective owners. Start-Up Waveforms START-UP FET BYPASS FET 100k 1µF 10m/uni03A9 0.16m/uni03A9 33nF 2.2µF 10/uni03A9 10/uni03A9 13.7k 10mF SENSE1 SENSE2 GATE1 DRAIN STMR UV CBTMR OUT OUTK GATE2 PG F LT L T4239 GND IBOOST IMON 12V 12V 100A 1/uni03A9 1/uni03A9 VCC 0.16m/uni03A9 1/uni03A9 1/uni03A9 10/uni03A9 BYPASS FET+ 47nF

4239 TA01a

4239 TA01b

∆VGATE1 10V/DIV ∆VGATE2 10V/DIV VOUT 10V/DIV

Rev. 0 For more information www.analog.com PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS Supply Voltages Input Voltages Output Voltages Operating Junction Temperature Range (Notes 1, 2) IMON IBOOST GND PG FLT CBTMR UV STMR OUT OUTK SENSE2 SENSE1 GATE2 GATE1 DRAIN VCC TOP VIEW DE PACKAGE 16-LEAD (4mm × 3mm) PLASTIC DFN θJA = 40°C/W (NOTE 4) EXPOSED PAD (PIN 17) PCB GND CONNECTION OPTIONAL ORDER INFORMATION LEAD FREE FINISH PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LT4239ADE#PBF 4239 16-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C Contact the factory for parts specified with wider operating temperature ranges.

Rev. 0For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 12V, IBOOST = 0V, RDRAIN = 100kΩ, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Supplies VCC Input Supply Range l 4 20 V ICC Input Supply Current VCC = 4V to 13.2V l 0.6 1 mA VCC(UVL) VCC Undervoltage Lockout VCC Rising l 3.3 3.6 3.8 V ∆VCC(HYST) VCC Undervoltage Lockout Hysteresis 100 mV Circuit Breaker and Current Limit ∆VSENSE2(CB) Circuit Breaker T rip Threshold (VSENSE2 – VOUTK) IBOOST = 0V, OUT = VCC IBOOST = 3V, OUT = VCC l l 9.5 10.5 mV mV ∆VSENSE2(ACL) Analog Current Limit Threshold (VSENSE2 – VOUTK) IBOOST = 0V IBOOST = 3V l l mV mV ∆VSENSE2(FAST) Fast Comparator T rip Threshold (VSENSE2 – VOUTK) IBOOST = 0V IBOOST = 3V l l 100 mV mV ∆VSENSE1(ACL) Analog Current Limit Threshold (VSENSE1 – VOUTK) l 45 50 55 mV ISENSE1 SENSE1 Current SENSE1 = SENSE2 = OUTK = 12V l 20 50 100 µA ISENSE2 SENSE2 Current SENSE1 = SENSE2 = OUTK = 12V l 20 70 140 µA IOUTK OUTK Current SENSE1 = SENSE2 = OUTK = 12V l 40 100 200 µA IOUT OUT Current OUT = 12V l 0.1 0.45 1 mA Gate Drive ∆VGATE Gate Drive IGATE1 = 0, –1µA l 10 12 14 V IGATE2 = 0, –5µA l 10 12 14 V ∆VGATE(TH) Gate Threshold for Start-Up and Power Good l 10 V IGATE1(UP) Gate Pull-Up Current Gate Drive On, ∆VGATE1 = 0V l –7 –10 –13 µA IGATE2(UP) Gate Pull-Up Current Gate Drive On, ∆VGATE2 = 0V l –35 –50 –65 µA IGATE1(DN) Gate Off Pull-Down Current Gate Drive Off, OUT=12V, ∆VGATE1 = 10V l 5 10 25 mA IGATE2(DN) Gate Off Pull-Down Current (UV Turn-Off) (Overcurrent Fault) Gate Drive Off, OUT=12V, ∆VGATE2 = 10V Gate Drive Off, OUT=12V, ∆VGATE2 = 10V l l mA mA IGATE1(FPD) Gate Fast Pull-Down Current Fast Turn-Off, OUT=12V, ∆VGATE1 = 10V l 50 130 300 mA IGATE2(FPD) Gate Fast Pull-Down Current Fast Turn-Off, OUT=12V, ∆VGATE2 = 10V l 0.3 0.6 1.5 A Comparator Inputs ∆VDS1 Voltage to Enable GATE2 Start-Up (VCC – VOUTK) Falling l 0.8 1 1.3 V ∆VDS2 Voltage to Start Power Good Delay (VCC – VOUTK) Falling l 80 100 130 mV ∆VDS(FET-BAD) FET-Bad Fault Threshold After Power Good (VCC – VOUTK) IBOOST = 0V IBOOST = 3V l l 160 100 200 120 240 mV mV ∆VDS(FETSHORT) FETShort Fault Threshold During Debounce (VCC – VOUTK) l 1.1 1.3 1.5 V VUV(TH) UV Threshold Voltage UV Rising l 1.207 1.232 1.257 V ∆VUV(HYST) UV Hysteresis 50 mV VUV(RESET) UV Fault Reset Threshold Voltage UV Falling l 0.45 0.6 0.65 V VIBOOST(TH) IBOOST High Threshold Voltage l 1.6 V IBOOST Low Threshold Voltage l 0.8 V

Rev. 0 For more information www.analog.com SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I(LEAK) UV , IBOOST Input Leakage Current V = 5V l 0 ±1 µA VOUT(G2OFF) OUT Voltage to Turn Off GATE2 After Power Good OUT Falling l 3.5 3.7 3.9 V Timer VTMR(H) STMR, CBTMR High Threshold Voltage Rising l 1.207 1.232 1.257 V VTMR(L) STMR, CBTMR Low Threshold Voltage Falling l 0.15 0.2 0.25 V ISTMR(UP) STMR Pull-Up Current STMR = 1V, GATE1 Start-Up l -8 -10 -12 µA ISTMR(DN) STMR Pull-Down Current STMR = 1V l 80 125 170 µA ICBTMR(UP) CBTMR Pull-Up Current CBTMR = 1V, In Overcurrent Fault l -8 -10 -12 µA ICBTMR(DN) CBTMR Pull-Down Current CBTMR = 2V, No Faults CBTMR = 2V, In Cool-Off Cycle l l µA µA DRETRY Retry Duty Cycle During Overcurrent Fault l 0.03 0.06 0.1 % Current Monitor ∆VSENSE2(FS) Input Sense Voltage Full-Scale (VSENSE2 – VOUTK) IBOOST = 0V, OUT = 12V IBOOST = 3V, OUT = 12V l l mV mV VIMON(OS) IMON Input Offset Voltage ∆VSENSE2 = 0V, OUT = 12V l ±800 µV AIMON IMON Voltage Gain ∆VSENSE2 = 1mV to 15mV, OUT = 12V l 97 100 103 V/V VIMON(MAX) IMON Maximum Output Voltage ∆VSENSE2 = 50mV, OUT = 12V l 4.5 4.9 5.5 V RIMON(OUT) IMON Internal Resistance ∆VSENSE2 = 0V, OUT = 12V l 15 20 25 kΩ BWIMON IMON Bandwidth 200 kHz Outputs VOL F LT, PG Output Low Voltage I = 5mA l 0.2 0.4 V IOH F LT, PG Input Leakage Current V = 5V l 0 ±1 µA Timing Delays tPHL(SENSE1) ∆VSENSE1 Voltage High to GATE1 Low ∆VSENSE1 = 0V Step to 300mV l 0.5 1 µs tPHL(SENSE2) ∆VSENSE2 Voltage High to GATE2 Low ∆VSENSE2 = 0V Step to 80mV l 0.5 1 µs tTMR(ACL) Overcurrent Fault Timer Delay ∆VSENSE1 = 0V Step to 100mV ∆VSENSE2 = 0V Step to 25mV l l 100 100 115 110 µs µs tTMR(FET-BAD) FET-Bad Fault Timer Delay l 17 20 23 ms tD(PG) Power Good Delay l 8 10 12 ms tD(GATE1) Debounced Turn-On Delay UV = 0V Step to 2V l 20 25 30 ms tOFF(GATE) GATE Turn-Off Propagation Delay UV = 2V Step to 0.8V l 170 220 270 µs tOFF(GATE2) GATE2 Turn-Off Delay After Power Good OUT = 12V Step to 0V l 1 2 µs tRST(UV) UV Low to F LT High UV = 2V Step to 0V l 20 40 µs ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 12V, IBOOST = 0V, RDRAIN = 100kΩ, unless otherwise noted. Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into device pins are positive; all currents out of the device pins are negative. All voltages are referenced to GND unless otherwise specified. Note 3: Limits on maximum rating is defined as whichever limit occurs first. Internal clamps limit the GATE pins to a minimum of 10V above OUT and a diode below OUT . Driving the GATE pins to voltages beyond the clamps may damage the device. Note 4: Thermal resistance is specified when the exposed pad is soldered to a 3-inch × 5-inch, four layer , FR4 board.

Rev. 0For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS VCC Supply Current vs Voltage OUT Current vs Voltage MOSFET Gate Drive vs VCC Voltage MOSFET Gate Drive vs Gate Leakage Current MOSFET Gate Drive Pull-Up Current vs Temperature Current Limit Propagation Delay vs Sense Voltage IMON Voltage vs Sense Voltage IMON Voltage Gain vs Temperature F LT and PG Output Low Voltage vs Load Current V CC (V) 500 550 600 650 700 750 I CC (µA)

4239 G01

V CC = V OUT V OUT (V) 200 300 400 500 600 700 I OUT (µA) 4239 G02 GATE2 GATE1 I GATE2 = –5µA I GATE1 = –1µA V CC (V) GATE (V) 4239 G03 GATE2 GATE1 I GATE (LEAKAGE) (µA) –10 –20 –30 –40 –50 –60 GATE (V)

4239 G04

I GATE2 I GATE1 TEMPERATURE (°C) –50 –25 100 125 –10 –20 –30 –40 –50 –60 I GATE (µA) 4239 G05 SENSE2 (mV) 100 0.1 100 T PHL(GATE2) (µs) 4239 G06 V CC = 12V V CC = 4V SENSE2 (mV) IMON VOL TAGE (V)

4239 G07

V CC = 12V V CC = 4V TEMPERATURE (°C) –50 –25 100 125 100 101 102 103 IMON VOL TAGE GAIN (V/V) 4239 G08 T A = 125°C T A = 25°C T A = –40°C I LOAD (mA) 0.2 0.4 0.6 0.8 V OL (V) 4239 G09 T A = 25°C, VCC = 12V, IBOOST = 0V, RDRAIN = 100kΩ, unless otherwise noted.

Rev. 0 For more information www.analog.com PIN FUNCTIONS OUT (Pin 1): MOSFET Gate Drive Return. Connect this pin to the output side of the current sense resistor . The gate fast pull-down current returns through this pin when gates are discharged. GATE2 is pulled low quickly when OUT falls below 3.7V after power good. OUTK (Pin 2): Negative Current Sense Input. Connect to the output terminal of the current sense resistor . SENSE1, SENSE2 (Pins 4, 3): Positive Current Sense Input. Connect to the input side of the current sense resis- tor . The current limit circuit controls GATE1 to limit the voltage between SENSE1 and OUTK to 50mV for 100µs before fault latched-off during start-up. After GATE2 turns on, the circuit breaker will trip when the voltage between SENSE2 and OUTK exceeds 10mV longer than the overcurrent fault timer period. During an overload condition, GATE2 is regulated to maintain 15mV of voltage drop across SENSE2 and OUTK for 100µs before fault latched-off. GATE2 (Pin 5): Gate Drive for External N-Channel MOSFETs. An internal 50µA current source starts charging up the gate of the Bypass MOSFET when ∆VGATE1 is higher than 10V and VIN – VOUT < 1V. GATE2 is limited to 12V above OUT by internal clamps. A 10mA current source keeps the MOSFET off when the part is in undervoltage condition. When a short-circuit condition is detected, GATE2 is pulled down to OUT by a 50mA current source. This current increases to 600mA when a severe output short is detected. GATE1 (Pin 6): Gate Drive for External N-Channel MOSFET . An internal 10µA current source charges up the gate of the Start-up MOSFET . The inrush current can be limited by the additional R-C network from GATE1 to GND by controlling its slew rate. GATE1 is limited to 12V above OUT by internal clamps. GATE1 turns off when power good condition, ∆VGATE2 ≥ 10V and VIN – VOUT < 100mV, are achieved. A 10mA current source keeps the MOSFET off when the part is in undervoltage condition. When a short-circuit condition is detected, GATE1 is pulled down to OUT by a 10mA current source. This current increases to 130mA when a severe output short is detected. DRAIN (Pin 7): External MOSFET’ s Drain Sense Input. Connect a 100k resistor between this pin and the drain of the external N-Channel MOSFET to monitor the differ- ence between MOSFET’s drain and OUTK voltages. The voltage sensed at this pin enables the GATE2 start-up and power good delay after GATE1 is fully enhanced. If the voltage between the MOSFET’s drain and OUTK rises above 100mV after power good, a 20ms FET-Bad fault timer will be activated. VCC (Pin 8): Positive Supply Input. If supply voltage spikes might exceed 25V, connect an RC filter at this pin. This pin has an undervoltage lockout threshold of 3.6V that will turn off all the MOSFETs. STMR (Pin 9): Start-Up Timer . Connect a capacitor between this pin and ground to set a 123ms/µF duration for start-up. If either the MOSFET gate drive at GATE1 remains below 10V or the voltage between MOSFET’ s drain and OUTK is greater than 100mV at the end of the start-up timer ramp-up, the start-up cycle is aborted. GATE1 pulls low turning off the MOSFET and F LT pulls low to indicate a start-up fault. UV (Pin 10): Undervoltage Comparator Input. Connect to an external resistive voltage divider from the input sup - ply to monitor the supply voltage. This pin has a 25ms debounce time on the rising edge before GATE1 start-up. If the voltage at this pin falls below 1.182V, an undervolt- age fault is detected and all the MOSFETs will be turned off. Pulling the UV pin below 0.6V resets the fault latch after a fault due to start-up failure, overcurrent, or FET short. Connect to VCC if unused. CBTMR (Pin 11): Overcurrent Fault Timer . Connect a capacitor between this pin and ground to set a 123ms/ µF duration for circuit breaker timeout, after which an overcurrent fault is generated and GATE2 is pulled low. The duration of the cool down time is 185s/µF when the device is configured for auto-retry, resulting in a 0.06% duty cycle.

Rev. 0For more information www.analog.com F LT (Pin 12): Open Drain Fault Output. Output that pulls low when a fault occurs. It can be a start-up fault, or a fault timer expired due to a FET-Bad or an overcurrent fault. Otherwise, it goes high impedance and requires an external pull-up resistor to a positive supply. Leave unconnected if unused. PG (Pin 13): Open Drain Power Good Status Output. The pin is kept low until a power good condition is valid for 10ms. To initiate the 10ms power good timer , ∆ VGATE2 needs to be above 10V and the voltage difference across the Bypass MOSFET is less than 100mV. Connect a resistor from this pin to a positive supply voltage. Leave unconnected if unused. GND (Pin 14): Device Ground. PIN FUNCTIONS IBOOST (Pin 15): Extra Loading Request Input. Pulls this pin high to double both the circuit breaker and active cur- rent limit thresholds. This allows the Bypass MOSFET to supply higher current without triggering either the circuit breaker or the current limit timers. Connect to GND to disable this function. IMON (Pin 16) : Current Sense Monitor Output. This voltage at the pin is proportional to the sense voltage monitored between the SENSE2 and OUTK pins with a voltage gain of 100. An internal 20k resistor is connected from this pin to ground. The measurement is valid only when OUT is above 3.7V and PG is pulled high, other - wise the pin is pulled low to ground. Leave unconnected if unused. Exposed Pad (Pin 17): May be left open or connected to device ground.

Rev. 0 For more information www.analog.com BLOCK DIAGRAM –4V LDO 10ms TIMER 20ms TIMER +– +– 100/uni03BCs TIMER GATE1 DRIVER ACL CHARGE PUMP + – 20k 10mV INTVCC 1.232V TM1 10/uni03BCA TM2 TM3 TM4 0.2V 1.232V 0.2V 6/uni03BCA 4/uni03BCA 10/uni03BCA 125/uni03BCA INTVCC 100/uni03BCs TIMER GATE2 DRIVER CB CM ACL FAST CB TIMER LOGIC PG F LT IBOOST UV VCC DRAIN SENSE1 GATE1 OUTK OUT GATE2 IMON SENSE2 CBTMR STMR GND EXPOSED PAD FAUL T RESET GATE ON UVLO UV RST 1.232V 3.6V 100mV 100mV 50mV FET-BAD PG G2START 50/uni03BCA 10/uni03BCACP1 CP2 12V 12V OUT OUT 10V 10V 3.7V G1HI OUTLO G2HI 15mV 40mV 200Ω LOGIC 0.6V INTVCC 4239 BD

Rev. 0For more information www.analog.com OPERATION The LT4239 is designed to turn a board’s supply voltage on and off in a controlled manner , allowing the board to be safely inserted or removed from a live backplane. Input protection devices such as T ransient Voltage Suppressors (TVS) are not required with this architecture. The avalanching of the MOSFET will limit the voltage spike on the input while the RC filter connected to the V CC pin protects it from this transitory voltage. LT4239 features a “Low Stress Staged Start” technique using two gate drives to sequence the turn-on of the external MOSFETs. At initial power-up, if UV is pulled above its turn-on threshold, a 25ms debounce cycle is initiated to ensure the input supply is firmly connected. After debounce, GATE1 is charged up with a 10µA current source. MOSFET M1 turns on and charges the output capacitor with a current level that is set by the slew rate at GATE1 and the output capacitance. Since the inrush cur- rent level is usually much smaller than the maximum load current, a small MOSFET can be chosen for M1. The cur- rent flowing through M1 is constantly monitored through the voltage drop on the sense resistor RS1. This voltage is regulated to 50mV lasting for 100µs before the part turns off and F LT pulls low during an overcurrent condition. When the output voltage rises to within 1V of the input’s and ∆VGATE1 is greater than 10V, M2 turns on with a strong gate pull-up current of 50µA. A lower SOA rated and lower RDS(ON) MOSFET can be used to keep the MOSFET’s cost down. For high current applications, multiple MOSFETs can be connected in parallel reducing the voltage drop and power dissipation. When the output voltage reaches within 100mV of the input supply and ∆V GATE2 is more than 10V, GATE1 turns off. Upon the completion of the 10ms power good timer , PG goes high impedance indicating to the system that M2 is fully enhanced and ready to supply the load. The total duration from the completion of the debounce time to the start of the power good timer is set by a capacitor connected from the STMR pin to ground. If due to any reasons, such as output soft short, bad MOSFET connec- tion or design mistake, PG timer does not start before the start-up timer expires, LT4239 latches off and pulls F LT low. Pull the UV pin below the 0.6V reset threshold to restart the part. At any time if the current flowing through M2 creates more than 10mV of voltage drop across sense resistor RS2, a circuit breaker timer will start with the duration set by a capacitor at the CBTMR pin. At the expiration of the CB timer , M2 turns off and F LT pulls low. If the current flowing through M2 is large, such as during an output short-circuit, the voltage drop across RS2 is regulated to 15mV for 100µs. Connecting the F LT pin to the UV pin will allow an automatic retry after a long cool-down period. LT4239 monitors the MOSFETs condition constantly even after PG goes high impedance. If during the operation the voltage drop from input to output is more than 100mV or ∆VGATE2 drops below 10V, a FET-Bad timer of 20ms starts. After the timer expires, GATE2 latches off and F LT pulls low. Restart the part by lowering the VCC pin below the 3.6V undervoltage lockout threshold momentarily as UV cannot reset such fault. A boost mode allowing extra current to flow through the pass transistors without triggering fault timers is included in the LT4239. Pull IBOOST pin above 1.6V to double both the circuit breaker and current limit thresholds. The FET- Bad fault threshold is also doubled to allow temporarily load surge. A current sense amplifier (CM) that is active during nor- mal operating condition provides accurate monitoring of current through the current sense resistor RS2. The sense voltage is amplified by 100 times and level shifted to a ground-referred output at the IMON pin. This analog out- put voltage can be digitized by an external ADC.

with enough SOA to withstand such events are needed. low RDS(ON) bypass the start-up for power distribution. to the load capacitance during start-up.

4239 F01

Figure 1. Typical Application

R2 divider , it initiates an internal 25ms debounce delay. capacitor CLOAD is limited to (10µA/CG1) • CLOAD. GATE2 charges up with a 50µA current source. reaching its fault threshold.

4239 F02

Figure 2. Normal Start-Up Waveforms 130mA and 600mA, respectively. be ≥ 470Ω and CG1 should be ≤ 100nF.

Rev. 0 For more information www.analog.com Parasitic MOSFET Oscillations Not all circuit oscillations can be ascribed to the cur - rent limit loop. Some higher frequency oscillations can arise from the MOSFETs themselves. (See Rarely Asked Questions— Issue 151, High-Side Current Sensing). There are two possible parasitic oscillation mechanisms. The first type of oscillation occurs at high frequencies, typically above 1MHz. This high frequency oscillation is easily damped with gate resistors R3 and R4 as shown in Figure 1. In some applications, one may find that these resistors help in short-circuit transient recovery as well. However , too large of a resistor will slow down the turn-off time. The recommended range for R3 and R4 is between 5Ω and 500Ω. 10Ω provides stability without affecting turn-off time. These resistors must be located next to the MOSFET gate pin with no other connections between them. Connect each of the gate resistors to every MOSFET when several MOSFETs are connected in parallel. A second type of parasitic oscillation occurs at frequencies between 200kHz and 800kHz when the MOSFET source is loaded with less than 10µF, and the drain is fed with an inductive impedance such as contributed by wiring induc- tance. To prevent this second type of oscillation, load the source with more than 10µF and bypass the input supply with a series 10Ω, 100nF snubber to ground. Overcurrent Fault During GATE1 Start-Up The LT4239 features an active current limit to protect the MOSFET M1 against short circuits or excessive cur - rent during start-up. A rail-to-rail active current limit (ACL) amplifier monitors the voltage across the sense resistor RS1 which is located on the source side of the MOSFET M1. When an overcurrent event appears, the ACL amplifier regulates the gate of the MOSFET to maintain 50mV across the sense resistor . At this point, an internal fault timer runs for 100µs until it times out. The MOSFET is turned off with GATE1 pulled to OUT by 10mA, and the fault latched-off with the F LT pin pulling low. In the event of a severe short-circuit fault occurring during start-up, the output current can momentarily surge to tens of amperes. The LT4239 responds within 1µs to bring the current under control by pulling the GATE1 to OUT . Almost immediately, the gate of the MOSFET M1 recovers due to the R G1 and C G1 network, and the current is actively limited until the 100µs fault timer expires. Overcurrent Fault After Power Good Once the load capacitor is fully charged up through MOSFET M1 after GATE1 start-up, MOSFET M2 will be turned on to pass the load current in the power path. There are three mechanisms to protect MOSFET M2 from damage when an overcurrent event develops after power good. The first one is the electronic circuit breaker (ECB) with an adjustable timer . The second is the active current limit (ACL) while the last one is a comparator detecting the output falling below 3.7V. An accurate electronic circuit breaker (ECB) and an active current limit (ACL) amplifier monitor the voltage across the sense resistor RS2 which is located on the source side of MOSFET M2. The electronic circuit breaker will turn off the MOSFET if the voltage across the sense resistor exceeds the ECB threshold ∆VSENSE2(CB) (10mV) for lon- ger than the fault filter delay configured at the CBTMR pin. The fault filter starts the timeout with a 10µA cur - rent charging the CBTMR pin capacitor . Otherwise, it dis- charges with 10µA if the sense voltage falls below the ECB threshold. If the CBTMR pin voltage exceeds its 1.232V threshold, the MOSFET turns off with GATE2 pulled to OUT by 50mA , and the fault is latched-off with the F LT pin pulling low. For a given circuit breaker time delay, tCB, the value for setting the external capacitor CFT is given by Equation 1. CFT = tCB •0.008[µF⁄ms] (1) After the MOSFET turns off, the CBTMR pin capacitor is discharged with a 4µA pull-down current until its threshold reaches 0.2V. This is followed by a cool-off cycle whereby the CBTMR pin will cycle up and down with 10µA and 4µA 512 times to allow the MOSFET to cool down. When configured in a circuit shown in Figure 8 for auto-retry, the resulting overcurrent duty cycle is 1:1280. During the cool-off period, the F LT pin remains low, and the output cannot be restarted by pulling the UV pin below 0.6V. Active current limiting begins when the sense voltage exceeds the ACL threshold ∆VSENSE2(ACL) (15mV), which is 1.5 times the ECB threshold ∆ VSENSE2(CB). The ACL APPLICATIONS INFORMATION

an internal fault timer runs for 100µs until it times out. 50mA, and the F LT pin also pulls low. the output can be restarted. following an overcurrent fault after power good.

4239 F03

Figure 3. Overcurrent Fault After Power Good pull-down current from both GATE1 and GATE2 to OUT . input supply is restored above its undervoltage threshold. the MOSFET’s gate to the source, the drain, or to ground. CBTMR pin for MOSFET cool-off.

Rev. 0 For more information www.analog.com terminals. If the GATE2 drive falls below its 10V threshold, a FET-Bad condition is detected. When either FET-Bad condition is present, an internal 20ms FET-Bad fault timer will be activated. The timer resets whenever the FET-Bad condition disappears. After the timer expires, the F LT pin pulls low and the GATE2 is pulled down to OUT with a 10mA current. A FET-Bad fault detection can only be cleared by lowering the VCC below its 3.6V undervoltage lockout threshold. FET Short Fault The LT4239 monitors the integrity of the MOSFETs during the debounce cycle. A FET short fault is detected if the voltage between the MOSFET’ s drain and OUTK pin remains below 1.3V at the end of the 25ms debounce cycle. The F LT pin will be pulled low after the debounce cycle. The LT4239 will enter a cool-off period of 512 timing cycles before the fault is cleared and the part can restart. Resetting Faults Faults generated during start-up or after power good will cause the LT4239 to latch-off and F LT pin to be pulled low. Pulling the UV pin below 0.6V will reset the latched fault. If UV is pulled low during the cool-off period, it will not reset the fault. But if UV continues to stay low until the cool-off cycle is over , the fault will be reset at the end of the cool-off period. If UV is pulled low after the cool-off period, it will reset the fault instantly. When UV goes high again after the fault latch is cleared, a debounce timing cycle is initiated followed by GATE1 start-up. The LT4239 can be configured for auto-retry by tying the F LT to UV in a circuit shown in Figure 8. Whenever the F LT pin is pulled low due to a fault, the UV pin will also be pulled below 0.6V to reset the fault latch. For faults that are followed by a cool-off cycle, the output will only restart again at the end of the cool-off period when the fault resets. However , for faults that don’t trigger the cool-off cycle, the fault will be reset instantly allowing the debounce timing cycle to restart. There is an exception for a FET-Bad fault detected after power good, the F LT pin will remain low prohibiting the debounce timing cycle from starting. Lowering the input supply until the V CC falls below its undervoltage lockout threshold (3.6V) shuts off all the MOSFETs and resets the fault latch. That includes reset- ting the fault while the device in cool-off cycle. Using IBOOST to Double the Circuit Breaker and Current Limit Thresholds The IBOOST pin can be used to double the circuit breaker , current limit thresholds and the FET-Bad fault threshold to ride through load surges after power good. It doesn’t increase the current limit threshold of the start-up chan- nel. Pulling the IBOOST pin above 1.6V will double those thresholds allowing large current to pass through the pass transistors without generating a fault. However , higher current limit settings will result in higher MOSFET power dissipation in the event of an output short. Proper choice of the MOSFET must accommodate high power dissipa - tion under the worst-case short-circuit if the IBOOST pin function is used. Monitor MOSFET Current The current through the sense resistor RS2 is monitored by LT4239’s current sense amplifier at the SENSE2 and OUTK pins. See Figure 4. The sense amplifier is supplied from the OUT voltage that must be greater than 3.7V for the IMON output to be valid. An internal resistor R IN of 200Ω is connected between the amplifier’s negative input terminal and SENSE2 pin. Another internal resistor ROUT of 20k is connected between the IMON and GND pins. The IMON output voltage is equal to (ROUT/RIN) • VSENSE. The resistor ratio ROUT/RIN defines the voltage gain of the sense amplifier and is set to 100. Full scale input sense voltage to the sense amplifier is 30mV, corresponding to an output of 3V at IMON pin. For input supply voltage greater than 5V, the output clamps at 4.9V if the allow - able input sense voltage range is exceeded. The IMON pin is held at ground potential if the OUT voltage is less than 3.7V. A capacitor connected from the IMON pin to GND will reduce noise at the output and may also be useful as a charge reservoir to keep the pin steady while driving a switching circuit such as an ADC. APPLICATIONS INFORMATION

be added from supply input to output for more protection.

4239 F04

Figure 4. Low Side Current Monitor with LTC2451 ADC

value with 1% tolerance are used for RS2.

4239 F05

Figure 5. Weighted Averaging Sense Voltages Choose a 10mΩ sense resistor with 1% tolerance for RS1. in the load capacitor , and is given by Equation 5. Calculate the time it takes to charge CLOAD (Equation 6). for 100ms, satisfying this requirement. ∆VSENSE1(ACL)(MAX) and minimum RS1 value.

Rev. 0For more information www.analog.com Thus, the maximum power dissipated in the MOSFET M1 during active current limiting is 5.6A • 12V = 67.2W for 100µs. The SOA curve of the PSM N6R1-30YLD shows 500W (50A at 10V) for 100µs, satisfying this requirement. The start-up timer capacitor (C ST) determines the total time allowed for a successful startup from the completion of the debounce to the start of the PG timer . For the STMR ramp-up time of 200ms which is 2 times longer than the time before the PG timer starts (Equation 9). CST = 200ms •0.008[µF⁄ms] ≅1.6µF (9) Since the MOSFET M2 turns on only after the load capaci- tor is fully charged through M1, the MOSFET is selected to handle the power dissipation during active current limiting for 100µs. Use Equation 10 to calculate the maximum short-circuit current using the maximum active current limit threshold, ∆VSENSE2(ACL)(MAX) and minimum RS2 value where there are 12 parallel 1mΩ sense resistors for RS2. ISHORT2(MAX) = ∆VSENSE2(ACL)(MAX) RS2(MIN) ⁄12 = 17mV 0.99mΩ⁄12 = 206A (10) If the output is shorted to a voltage below 3.7V, the MOSFET M2 will be turned off instantly without active current limit- ing and the fault is latched-off. Thus, the maximum power dissipated in the MOSFET during active current limiting if the 12V output collapsed to 4V is 206A • (12V – 4V) = 1648W for 100µs. Though the MOSFETs operate in par - allel during active current limiting, they only provide the SOA of a single MOSFET due to offset mismatch between the gate thresholds. The MOSFET with the lowest thresh- old may carry more current than the others and as it gets hotter , it carries even more current since threshold voltage has a negative temperature coefficient. The SOA curve of the PSMN1R0-25YLD shows 2500W (250A at 10V) for 100µs, satisfying this requirement. Another selection criterion is to use a smaller RDS(ON) of 1mΩ or less for the MOSFET to minimize the voltage drop keeping the power dissipation within limits at maximum load current. In the design, eight MOSFETs in parallel are used to reduce the dissipated power in each MOSFET . The effective RDS(ON) is kept low enough to avoid triggering the FET-Bad fault threshold. The fault timer capacitor (C FT) at CBTMR pin is used to prevent power dissipation in the MOSFET M2 from exceeding its SOA rating during an overcurrent fault. Use Equation 11 to calculate the worst-case short-circuit cur- rent during the fault timer period before active current limiting is activated. ISHORT2(WORST) = ∆VSENSE2(ACL)(MAX) – ∆VSENSE2(CB)(MIN) RS2(MIN) ⁄12 ISHORT2(WORST) = 17mV −9.5mV 0.99mΩ⁄12 = 91A (11) Assuming the short-circuit current is divided equally amongst the eight parallel MOSFETs, the maximum power dissipated in each MOSFET during the fault timer period if the 12V output collapsed to 4V is (91A/8) • (12V – 4V) = 91W. The SOA curve of the PSMN1R0-25YLD shows 200W (20A at 10V) for 10ms. The MOSFET’s SOA rating requirement is satisfied for a fault timer period of 5ms (Equation 12). CFT = 5ms •0.008[µF⁄ms] ≅47nF (12) Finally, select the values for the resistive voltage divider at the UV pin that defines the undervoltage threshold of 9.7V for the 12V supply. Since the leakage current for the UV pin can be as high as ±1µA, the total resistance in the divider should be low enough to minimize the resulting offset error . Calculate the bottom resistor R1 based on Equation 13 to obtain less than ±0.2% error due to leak- age current. R1= VUV(TH) I(LEAK) ⎠⎟ •0.2% = 1.232V 1µA ⎠⎟ •0.2% = 2.4k (13) Choose R1 to be 2kΩ to achieve less than ±0.2% error and then solving Equation 14 for R2, results in R2 = 13.7kΩ. R2 = VIN(UV) VUV(TH) ⎠⎟ •R1 R2 = 9.7V 1.232V −1⎛ ⎝⎜ ⎞ ⎠⎟ •2k = 13.7k (14) A 0.1µF capacitor C2 is placed on the UV pin to prevent supply glitches from turning off the MOSFETs. APPLICATIONS INFORMATION

ommended PCB layout is shown in Figure 6. resistances add up quickly in high current applications. shorted to ground when the insulation between them fails.

4239 F06

Figure 6. Recommended Layout

4239 F07

Figure 7. 12V, 100A Backplane Resident Application

4239 F08

Figure 8. 12V, 100A Application with Auto-Retry After a Fault

4239 F09

Figure 9. 12V, 50A Application with IBOOST Pin Control

4239 F10

Figure 10. 12V, 30A Card Resident Application

4239 F11

Figure 11. 12V, 100A Application with Parallel MOSFETs and Current Sense Resistor Averaging Network

Rev. 0For more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. PACKAGE DESCRIPTION 3.00 ±0.10 (2 SIDES) 4.00 ±0.10 (2 SIDES) NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.40 ±0.10 BOTTOM VIEW—EXPOSED PAD 1.70 ±0.10 0.75 ±0.05 R = 0.115 TYP R = 0.05 TYP

3.15 REF

1.70 ±0.05 169 PIN 1 TOP MARK (SEE NOTE 6)

0.200 REF

0.00 – 0.05 (DE16) DFN 0806 REV Ø PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 2.20 ±0.05 0.70 ±0.05 3.60 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 3.30 ±0.05 3.30 ±0.10

0.45 BSC

0.23 ±0.05 16-Lead Plastic DFN (4mm × 3mm) (Reference LTC DWG # 05-08-1732 Rev Ø)

Rev. 0 For more information www.analog.com  ANALOG DEVICES, INC. 2022 www.analog.com RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS LTC4210 Single Channel Hot Swap Controller Operates from 2.7V to 16.5V, Active Current Limiting, TSOT23-6 LTC4211 Single Channel Hot Swap Controller Operates from 2.5V to 16.5V, Multifunction Current Control, MSOP-8, SO-8 or MSOP-10 LTC4215 Single Channel Hot Swap Controller Operates from 2.9V to 15V, I2C Compatible Monitoring, SSOP-16 or QFN-24 LTC4216 Single Channel Hot Swap Controller Operates from 0V to 6V, Active Current Limiting, MSOP-10 or DFN-12 LTC4218 Single Channel Hot Swap Controller Operates from 2.9V to 26.5V, Active Current Limiting, SSOP-16 or DFN-16 LTC4221 Dual Channel Hot Swap Controller Operates from 1V to 13.5V, Multifunction Current Control, SSOP-16 LTC4222 Dual Channel Hot Swap Controller Operates from 2.9V to 29V, I2C Compatible Monitoring, SSOP-36 or QFN-32 LTC4223 Dual Supply Hot Swap Controller Controls 12V and 3.3V, Active Current Limiting, SSOP-16 or DFN-16 LTC4224 Dual Channel Hot Swap Controller Operates from 1V to 6V, Active Current Limiting, MSOP-10 or DFN-10 LTC4281 Positive Voltage Hot Swap Controller with I2C Compatible Monitoring Operates from 2.9V to 33V, 12-/16-Bit ADC Monitors Current, Voltage, Power and Energy, Internal EEPROM, QFN-28 LTC4282 High Current Positive Voltage Hot Swap Controller with I2C Compatible Monitoring Operates from 2.9V to 33V, Dual Gate Drive, 12-/16-Bit ADC Monitors Current, Voltage, Power and Energy, Internal EEPROM, QFN-32 RDRAIN 100k 2.2µF RS1 10m/uni03A9 RS2 0.5m/uni03A9 CG1 22nF RG1 CST 1µF 10/uni03A9 10/uni03A9 RVCC 475/uni03A9 5.36k CLOAD 4700/uni03BCF SENSE1 SENSE2 GATE1 DRAIN STMR UV CBTMR OUT OUTK GATE2 PG F LT L T4239 GND IBOOST IMON 30A R10 1/uni03A9 R11 1/uni03A9 VCC RS3 0.5m/uni03A9 R12 1/uni03A9 R13 1/uni03A9 10/uni03A9 0.1µF CFT 47nF

4239 TA02

M2, M3: PSMNR60-25YLH M1: PSMN6R1-30YLD 10k POWER GOOD 10k CONNECTOR1 CONNECTOR2 GND BACKPLANE PLUG-IN BOARD