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Rev. 0For more information www.analog.com Document Feedback TYPICAL APPLICATION FEATURES DESCRIPTION 50A Hot Swap E-Fuse with Guaranteed SOA The LT®4200 is an integrated solution for hot swap applications that allows a board to be safely inserted and removed from a live backplane. The part integrates a hot swap controller , power MOSFET and current sense resistor into a single package for small form-factor applications. The MOSFET safe operating area is production tested and guaranteed for the stresses in hot swap applications. The LT4200 allows 50A of continuous operation at up to 85°C ambient temperature. It provides separate inrush current control and a ±12% accurate 57A current limit with output dependent foldback. The current limit threshold can be adjusted dynamically using the ISET pin. Additional features include a current monitor output for ground referenced current sensing and a MOSFET temperature monitor output. Thermal limit, overvoltage, undervoltage and power good monitoring are also provided. 12V, 50A Card Resident Application with Auto-Retry Power-Up Waveform
APPLICATIONS
n Allows Safe Board Insertion into Live Backplane n Wide Operating Voltage Range: 2.9V to 15V n Guaranteed Safe Operating Area: 7.5W√s n 1.2mΩ MOSFET with Current Sense Element n ±4% Current Monitor Output n Adjustable Current Limit Threshold n Temperature Monitor Output n Overtemperature Protection n Adjustable Current Limit Timer Before Fault n Power Good and Fault Outputs n Adjustable Inrush Current Control n ±2.5% Accurate Undervoltage and Overvoltage Protection n Available in a 36-Pin (5mm × 8mm) QFN Package n High Availability Servers n Solid State Drives All registered trademarks and trademarks are the property of their respective owners. 12V VOUT 12V 50A
4200 TA01a
4700µF 10k VDD TIMER UV INTVCC OUT FB PG GND IMON L T4200 OV SENSE+ FL T# 20k 1µF *TVS: DIODES INC. SMCJ15A ADC 107k 10k 5.23k 150k 20k PINS NOT USED IN THIS CIRCUIT: GATE, ISET VIN 10V/DIV CONTACT BOUNCE VOUT 10V/DIV PG 10V/DIV 20ms/DIV
4200 TA01b
Rev. 0 For more information www.analog.com PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS Input Voltages Output Voltages Operating Junction Temperature Range (Note 4) C to 150°C (Notes 1 and 2) 16 17 18 TOP VIEW UHG PACKAGE 36-LEAD (5mm × 8mm) PLASTIC QFN θJA = 27°C/W (JEDEC PCB), 12°C/W (DC3024A) EXPOSED PAD (PIN 37) IS SENSE– AND MUST BE SOLDERED ONTO THE PCB SENSE– 20 21 36UV OV IMON TIMER INTVCC GATE OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT ISET FB FL T# PG SENSE GND V DD VDD VDD VDD VDD VDD VDD VDD VDD 15 22 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT4200RUHG#PBF LT4200RUHG#TRPBF 4200 36-Lead (5mm × 8mm) Plastic QFN –40°C to 150°C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Rev. 0For more information www.analog.com
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DC Characteristics VDD Input Supply Range l 2.9 15 V IDD Input Supply Current MOSFET On, No Load l 1.6 3 mA VDD(UVL) Input Supply Undervoltage Lockout VDD Rising l 2.63 2.73 2.85 V IOUT OUT Leakage Current VOUT = VGATE = 0V, VDD = 15V, l –700 700 µA OUT Operating Current VOUT = VGATE = 12V, VDD = 12V l 1 2 4 µA dVGATE/dt OUT Turn-On Ramp Rate GATE Open l 0.15 0.35 0.6 V/ms RON MOSFET On-Resistance Including Current Sense Resistor l 0.6 1.2 2.2 mΩ ILIM(TH) Current Limit Threshold VFB = 1.35V, ISET Open VFB = 0V, ISET Open VFB = 1.35V, RSET = 20k l l l 50.2 4.6 6.8 63.8 A A A SOA MOSFET Safe Operating Area 12.6V, 6.8A Folded Back, 7.5W√ s (Note 5) 7.7 ms Inputs IIN OV , UV , FB Input Current V = 1.2V l 0 ±1 µA ISENSE+(IN) SENSE+ Input Current VSENSE+ = 12V l 4 ±10 µA VTH OV , UV , FB Threshold Voltage VPIN Rising l 1.205 1.235 1.265 V ∆VOV(HYST) OV Hysteresis l 10 20 30 mV ∆VUV(HYST) UV Hysteresis l 50 80 110 mV VUV(RTH) UV Reset Threshold Voltage VUV Falling l 0.55 0.62 0.7 V ∆VFB(HYST) FB Power Good Hysteresis l 10 20 30 mV RISET ISET Internal Resistor l 19 20 21 kΩ Outputs V INTVCC INTVCC Output Voltage VDD = 5V,15V, ILOAD = 0mA, –10mA l 2.7 3.1 3.4 V VOL PG, FL T# Output Low Voltage I = 2mA l 0.4 0.8 V IOH PG, FL T# Input Leakage Current V = 30V l 0 ±10 µA VTIMER(H) TIMER High Threshold VTIMER Rising l 1.2 1.235 1.28 V VTIMER(L) TIMER Low Threshold VTIMER Falling l 0.1 0.21 0.3 V ITIMER(UP) TIMER Pull-Up Current VTIMER = 0V l –80 –100 –120 µA ITIMER(DN) TIMER Pull-Down Current VTIMER = 1.2V l 1.4 2 2.6 µA ITIMER(RATIO) TIMER Current Ratio ITIMER(DN)/ITIMER(UP) l 1.6 2 2.7 % AIMON IMON Current Gain 20A to 50A, TJ = 0°C to 125°C 1.92 2 2.08 µA/A BWIMON IMON Bandwidth 250 kHz IOFF(IMON) IMON Offset Current IOUT = 1.5A, TJ = 0°C to 125°C ±3 µA IGATE(UP) Gate Pull-Up Current Gate Drive On, VGATE = VOUT = 12V l –18 –24 –29 µA IGATE(DN) Gate Pull-Down Current Gate Drive Off, VGATE = 22V, VOUT = 12V l 165 500 µA IGATE(FST) Gate Fast Pull-Down Current Fast Turn Off, VGATE = 22V, VOUT = 12V 140 mA The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.
Rev. 0 For more information www.analog.com Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive; all voltages are referenced to GND unless otherwise specified. Note 3: An internal clamp limits the GATE pin to a minimum of 10V above OUT . Driving this pin to voltages beyond the clamp may damage the device. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS AC Characteristics tPHL(GATE) Input High (OV), Input Low (UV) to GATE Low Propagation Delay VGATE < 21.8V Falling l 8 25 µs tPHL(ILIM) Short-Circuit to GATE Low VFB = 0, Step SENSE+ – SENSE– to 50mV, VGATE < 15V Falling l 1 5 µs tD(ON) Turn-On Delay Step VUV to 2V, VGATE > 13V l 24 48 72 ms tD(FAUL T) UV Low to Clear Fault Latch Delay 1 µs tD(CB) Circuit Breaker Filter Delay Time (Internal) V FB = 0, Step SENSE+ – SENSE– to 50mV l 0.25 0.45 0.7 ms tD(COOL_DOWN) Cool Down Delay (Internal) TIMER = INTVCC l 600 900 1200 ms The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted. Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 150°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 5: SOA is tested with current limit folded back, V DD = 12V + 5% or 12.6V and output shorted to GND. This condition is near the Spirito region of the SOA curve. See the SOA Curve in the Typical Performance Characteristic section.
Rev. 0For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS UV Hysteresis vs Temperature Timer Pull-Up Current vs Temperature Current Limit Delay PHL(ILIM) vs Overdrive) Current Limit Threshold Foldback Current Limit Adjustment OUT vs RSET) RISET vs Temperature IDD vs VDD INTVCC Load Regulation UV Low-High Threshold vs Temperature T A = 25°C, VDD = 12V unless otherwise noted. 150°C 25°C –40°C V DD (V) 1.2 1.6 2.0 2.4 I DD (mA)
4200 G01
ILOAD (mA) 0.5 1.5
1.0 INTVCC (V)
3.5 2.0 2.5 3.0
4234 G02
VDD = 5V VDD = 3.3V TEMPERATURE (°C) –50 –25 100 125 150 1.230 1.232 1.234 1.236 1.238 1.240 UV LOW–HIGH THRESHOLD (V)
4200 G03
TEMPERATURE (°C) –50 –25 100 125 150 100 110 UV HYSTERESIS (mV)
4200 G04
TEMPERATURE (°C) –50 –25 100 125 150 –90 –95 –100 –105 –110 TIMER PULL-UP CURRENT (µA)
4200 G05
OUTPUT CURRENT (A) 100 125 150 175 200 0.1 100 1000 CURRENT LIMIT DELAY (/uni03BCs)
4200 G06
FB VOL TAGE (V) 0.2 0.4 0.6 0.8 1.0 1.2 CURRENT LIMIT VALUE (A)
4200 G07
R SET (Ω) 100 10k 100k CURRENT LIMIT VALUE (A)
4200 G08
TEMPERATURE (°C) –50 –25 100 125 150 R ISET (kΩ)
4200 G09
Rev. 0 For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICSTA = 25°C, VDD = 12V unless otherwise noted. GATE Pull-Up Current vs Temperature Gate Drive vs GATE Pull-Up Current Gate Drive vs V DD VISET vs Temperature Guaranteed MOSFET SOA CurveRON vs Temperature PG, FL T# VOUT Low vs ILOAD IMON vs Temperature TEMPERATURE (°C) –50 –25 100 125 150 0.5 1.0 1.5 2.0 2.5 3.0 RON (mΩ)
4200 G10
T EP = 25°C SINGLE PULSE V DS (V) 0.1 100 0.1 100 I D (A)
4200 G11
7.7ms SOA CURRENT (mA) 6 10
4234 G12
PG, FLT# VOL (V) V DD = 3.3V TO 12V I LOAD = 50A TEMPERATURE (°C) –50 –25 100 125 150 100 105 110 I MON (µA)
4200 G13
TEMPERATURE (°C) –50 –25 100 125 150 –23.0 –23.5 –24.0 –24.5 –25.0 I GATE PULL–UP (µA)
4200 G14
V DD = 3.3V V DD = 5V V DD = 12V I GATE (µA) –10 –15 –20 –25 –30 GATE GATE – V OUT ) (V)
4200 G15
V DD (V) GATE GATE – V OUT ) (V)
4200 G16
TEMPERATURE (°C) –50 –25 100 125 150 0.3 0.4 0.5 0.6 0.7 0.8 0.9 V ISET (V) ISET
4200 G17
Rev. 0For more information www.analog.com PIN FUNCTIONS UV (Pin 1): Undervoltage Comparator Input. Connect this pin to an external resistive divider from VDD. If the UV pin voltage falls below 1.15V, an undervoltage is detected and the switch turns off. Pulling this pin below 0.62V resets the overcurrent fault and allows the switch to turn back on (see Application Information section for details). If overcurrent auto-retry is desired, then tie UV to the FL T# pin. Tie UV to INTVCC if unused. OV (Pin 2): Overvoltage Comparator Input. Connect this pin to an external resistive divider from VDD. If the voltage at this pin rises above 1.235V, an overvoltage is detected, and the switch turns off. Tie to GND if unused. IMON (Pin 3): Current Monitor Output. The current in the internal MOSFET switch is divided by 500,000 and sourced from this pin. Placing a 20k resistor on this pin allows a 0V to 2V voltage swing when current ranges from 0A to 50A. TIMER (Pin 4): Current Limit Timer Input. Connect a capacitor between this pin and ground to set a 12ms/µF duration for current limit before the switch is turned off. If the UV pin is toggled low while the MOSFET switch is off, the switch will turn on again following cool down time of 4.14s/µF duration. Tie this pin to INTVCC for a fixed 0.5ms overcurrent delay and 900ms cool down time. INTVCC (Pin 5): Internal 3.1V Supply Decoupling Output. This pin must have a 1µF or larger bypass capacitor . Overloading this pin can disrupt internal operation. GATE (Pin 6): Gate Drive for Internal N-Channel MOSFET . An internal 24µA current source charges the gate of the N-channel MOSFET . At start-up, the GATE pin ramps up at a 0.35V/ms rate determined by internal circuitry. During an undervoltage or overvoltage condition, a 250µA pull- down current turns the MOSFET off. During a short-circuit or undervoltage lockout condition, a 140mA pull-down current source between GATE and OUT is activated. OUT (Pins 7– 21): Output of Internal MOSFET Switch. Connect this pin directly to the load. VDD (Pins 22– 30): Supply Voltage and Current Sense Input. These pins must be soldered to input power . VDD has an undervoltage lockout threshold of 2.73V. GND (Pin 31): Device Ground. SENSE– (Pin 32): Current Sense Node and MOSFET Drain. The exposed pad on the UHG package is connected to SENSE– and should be soldered to an electrically isolated printed circuit board trace to properly transfer the heat out of the package. SENSE+ (Pin 32): Current Limit and Current Monitor Amplifier Input. The current limit circuit controls the GATE pin to limit the voltage between the SENSE+ and SENSE– pin to 17mV (57A) or less depending on the voltage at the FB pin and ISET . This pin must be connected to V DD pin (connect Pin 32 to Pin 26). PG (Pin 33): Power Good Indicator . Open-drain output pulls low when the FB pin drops below 1.21V indicating the power is bad. If the voltage at FB rises above 1.235V and the GATE-to-OUT voltage exceeds 4.2V, the open- drain pull-down releases the PG pin to go high. FL T# (Pin 34): Overcurrent Fault Indicator . Open-drain output pulls low when an overcurrent fault has occurred and the circuit breaker trips. For overcurrent auto-retry tie FL T# to UV pin (see Applications Information section for details). FB (Pin 35): Foldback and Power Good Input. Connect this pin to an external resistive divider from OUT . If the voltage falls below 0.9V, the current limit is reduced using a fold- back profile (see the Typical Performance Characteristics section). If the voltage falls below 1.21V, the PG pin will pull low to indicate the power is bad. ISET (Pin 36): Current Limit Adjustment Pin. For 57A current limit value, open this pin. This pin is driven by a 20k resistor in series with a voltage source. The pin voltage is used to generate the current limit threshold. The internal 20k resistor (RISET) and an external resistor (RSET) between ISET and ground create an attenuator that lowers the current limit value. Due to circuit tolerance RSET should not be less than 2k. In order to match the temperature variation of the sense resistor , the voltage on this pin increases at the same rate as the sense resistance increases. Therefore the voltage at ISET pin is made pro- portional to temperature of the MOSFET switch.
Rev. 0 For more information www.analog.com FUNCTIONAL DIAGRAM 4200 BD RISET 20k VDD SENSE+ UV OUT FB PG GND IMON INTVCC INTVCC 100µA TIMER FL T# – ISET GATE 12V SENSE– (EXPOSED PAD) CLAMP 0.6V POSITIVE TEMPERATURE COEFFICIENT REFERENCE 0.9m/uni03A9 MOSFET 0.3m/uni03A9 SENSE RESISTOR CHARGE PUMP AND GATE DRIVER f = 2MHz 3.1V GEN LOGIC INRUSHCS CM 0.35V/ms FOLDBACK 0.9V 2.65V 1.235V PG 1.235V UV 0.21V TM1 1.235V – TM2 0.62V RST VDD VDD 2.73V + UVLO1 OV 1.235V – OV 2µA UVLO2
Rev. 0For more information www.analog.com OPERATION The Functional Diagram displays the main circuits of the device. The LT4200 is designed to turn a board’s supply voltage on and off in a controlled manner allowing the board to be safely inserted and removed from a live backplane. The LT4200 includes a 0.9mΩ MOSFET and a 0.3mΩ cur- rent sense resistor . During normal operation, the charge pump and gate driver turn on the pass MOSFET’s gate to provide power to the load. The inrush current control is accomplished by the INRUSH circuit. This circuit limits the GATE ramp rate to 0.35V/ms and hence controls the voltage ramp rate of the output capacitor . The current sense (CS) amplifier monitors the load cur - rent by using the voltage sensed across the current sense resistor . The CS amplifier limits the current in the load by reducing the GATE-to-OUT voltage in an active con- trol loop. It is simple to adjust the current limit threshold using the current limit adjustment (ISET) pin. This allows a different threshold during other times such as start-up. Note there must be a connection between SENSE + to VDD (Pin 32 to Pin 26) in order to monitor current. A short circuit on the output to ground causes significant power dissipation during active current limiting. To limit this power dissipation, the foldback amplifier reduces the current limit value from 57A to 6.8A in a linear manner as the FB pin drops below 0.9V (see the Typical Performance Characteristics). If an overcurrent condition persists, the TIMER pin ramps up with a 100µA current source until the pin voltage exceeds 1.235V (comparator TM2). This indicates to the logic that it is time to turn off the pass MOSFET to prevent overheating. At this point the TIMER pin ramps down using the 2µA current source until the voltage drops bel ow 0.21V (Comparator TM1 ) which completes one timer cycle. After eight TIMER pin cycles (ramping to 1.235V and then below 0.21V), the logic starts the 48ms debounce time. At this point, the pass transistor has cooled and it is safe to turn it on again. It is suitable in many applications to use an internal 0.5ms overcurrent timer with a 900ms cool down by tying the TIMER pin to INTVCC. Latchoff is the normal operating condition follow- ing overcurrent turnoff. Retry is initiated by pulling the UV pin low for a minimum of 1µs then high. Auto-retry is implemented by tying the FL T# to the UV pin. The output voltage is monitored using the FB pin and the PG comparator to determine if power is available for the load. The power good condition is signaled by the PG pin using an open-drain pull-down transistor . The Functional Diagram shows the monitoring blocks of the LT4200. The two comparators on the left side include the UV and OV comparators. These comparators are used to determine if the external conditions, typically input volt- age, are valid prior to turning on the MOSFET . But first, the undervoltage lockout circuits UVLO1 and UVLO2 must validate the input supply and the internally generated 3.1V supply (INTVCC), generating the power-up initialization to the logic circuits. If the external conditions remain valid for 48ms, the MOSFET is allowed to turn on. Other features include MOSFET current and temperature monitoring. The current monitor (CM) outputs a current proportional to the sense resistor current. This current can drive an external resistor or other circuits for moni- toring purposes. A voltage proportional to the MOSFET temperature is output to the ISET pin. The MOSFET is protected by a thermal shutdown circuit.
detail in the following sections.
4200 F01
Figure 1. 20A, 12V Card Resident Application, Auto-Retry
4200 F02
Figure 2. Supply Turn-On without CGATE
compensate the current limit.
- 24µA (2) When the GATE voltage reaches the MOSFET threshold voltage, the switch begins to turn on and the OUT volt - age follows the GA TE voltage as it increases. Once OUT reaches VDD, the GATE will ramp up until clamped by the 12V Zener between GATE and OUT . As the OUT voltage rises, so will the FB pin which is moni- toring it. Once the FB pin crosses its 1.235V threshold and the GATE to OUT voltage exceeds 4.2V, the PG pin will cease to pull low and indicate that the power is good. Parasitic MOSFET Oscillation When the N-channel MOSFET ramps up the output dur - ing power-up it operates as a source follower . The source follower configuration may self-oscillate in the range of 25kHz to 300kHz when the load capacitance is less than 10µF, especially if the wiring inductance from the supply to V DD pin is greater than 3µH. The possibility of oscil - lations will increase as the load current (during power- up) increases. There are two ways to prevent this type of oscillation. The simplest way is to avoid load capacitances below 10µF. For wiring inductances larger than 20µH, the minimum load capacitance may extend to 100µF. A second choice is to connect an external gate capacitor C P > 1.5nF as shown in Figure 3.
4200 F03
Figure 3. Compensation for Small CLOAD indicate output power is no longer good. 140mA current to the OUT pin.
the internally generated (circuit breaker) delay of 0.5ms. the timing capacitor’s value is given by Equation 3. if the overcurrent fault latch is cleared. a period determined by the capacitor on the TIMER pin. is 6.8A as the TIMER pin ramps up.
4200 F04
Figure 4. Short-Circuit Waveform corresponds to a 57A current limit at room temperature. calculated using the Equation 4.
Rev. 0For more information www.analog.com APPLICATIONS INFORMATION reduced running current while the maximum available current limit is used at start-up. Monitor MOSFET Temperature The voltage at the ISET pin increases linearly with increas- ing temperature. The temperature profile of the ISET pin is shown in the Typical Performance Characteristics section. Using a comparator or ADC to measure the ISET voltage provides an accurate indication of the MOSFET tempera- ture. The ISET voltage follows Equation 5. VISET = RSET RSET + RISET (5) The MOSFET temperature is calculated using RISET of 20k (Equation 6). T = RSET + 20k( ) • VISET RSET • 2.093 [mV/°C] – 273°C (6) When RSET is not present, T is given by Equation 7. T = VISET (7) There is an overtemperature circuit in the LT4200 that monitors an internal voltage similar to the ISET pin volt- age. When the die temperature exceeds 155°C the cir- cuit turns off the MOSFET until the temperature drops to 135°C. Monitor MOSFET Current The current in the MOSFET passes through an internal 0.3mΩ sense resistor . The voltage on the sense resistor is converted to a current that is sourced out of the IMON pin. The gain of ISENSE amplifier is 2µA/A referenced from the MOSFET current. This output current can be converted to a voltage using an external resistor to drive a comparator or ADC. The voltage compliance for the IMON pin is from 0V to INTV CC − 0.7V. A microcontroller with a built-in comparator can build a simple integrating single-slope ADC by resetting a capaci- tor that is charged with this current. When the capacitor voltage trips the comparator and the capacitor is reset, a timer is started. The time between resets will indicate the MOSFET current. Monitor OV and UV Faults Protecting the load from an overvoltage condition is the main function of the OV pin. In Figure 1 an external resis- tive divider (driving the OV pin) connects to a comparator to turn off the MOSFET when the V DD voltage exceeds 15.2V. If the VDD pin subsequently falls back below 14.9V, the switch will be allowed to turn on immediately. In the LT4200 the OV pin threshold is 1.235V when rising, and 1.215V when falling out of overvoltage. The UV pin functions as an undervoltage protection pin or as an “ON” pin. In the Figure 1 application the MOSFET turns off when VDD falls below 9.23V. If the VDD pin sub- sequently rises above 9.88V for 48ms, the switch will be allowed to turn on again. The LT4200 UV turn-on/off threshold are 1.235V (rising) and 1.155V (falling). In the case of an undervoltage or overvoltage, the MOSFET turns off and there is indication on the PG sta - tus pin. When the overvoltage is removed, the MOSFET’s gate ramps up immediately at the rate determined by the INRUSH circuit. Power Good Indication In addition to setting the foldback current limit threshold, the FB pin is used to determine a power good condition. The Figure 1 application uses an external resistive divider on the OUT pin to drive the FB pin. On the LT4200 the PG comparator drives high when the FB pin rises above 1.235V and low when it falls below 1.215V. Once the PG comparator is high the GATE pin voltage is monitored with respect to the OUT pin. Once the GATE minus OUT voltage exceeds 4.2V the PG pin goes high. This indicates to the system that it is safe to load the OUT pin while the MOSFET is completely turned “on”. The PG pin goes low when the GATE is commanded off (using the UV , OV or SENSE+ pins) or when the PG comparator drives low.
4200 F05
Figure 5. 50A, 12V Card Resident Application the LT4200 P√t spec of 7.5W√s. to prevent excessive energy dissipation in the MOSFET . the FB voltage is 1V, VOUT = 8.5V and MOSFET VDS = 3.5V. Performance Characteristics section to view this profile. maximum current limit timeout. using CT to be 0.8ms (Equation 11). fault, connect the FL T# to the UV pin. UV pin restart the power-up sequence. using Equation 12, Equation 13, and Equation 14.
voltage at a ratio given by Equation 15. perature. Using 0.02" per amp or wider is recommended. whole length of the V DD bar that connects pin 22 to 30. sible between INTVCC and GND.
4200 F06
Figure 6. Recommended Layout
Figure 7. 12V, 50A Backplane Resident Application with Insertion Activated Turn-On The LT4200 has a wide operating range from 2.9V to 15V. The UV , OV and PG thresholds are set with few resistors. All other functions are independent of supply voltage. Figure 8. 3.3V, 50A Card Resident Application with Auto-Retry
4200 F08
Rev. 0For more information www.analog.com PACKAGE DESCRIPTION 5.00 ±0.10 NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS PIN 1 TOP MARK (SEE NOTE 6) BOTTOM VIEW—EXPOSED PAD 6.95 ±0.10 8.00 ±0.10 0.75 ± 0.05 0.75 ±0.05 R = 0.125 TYP 0.00 – 0.05 0.22 ±0.05 (UHG36) QFN 0121 REV A
0.50 BSC
0.115 REF
0.200 REF 0.25 REF
7.0 REF
4.22 REF
0.28 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPL Y SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
2.50 REF
0.40 ±0.10 0.00 – 0.05 0.70 ±0.05 0.5 ±0.05 0.50 BSC1.00 BSC
7.00 REF
2.50 REF4.10 ±0.05 5.50 ±0.05 0.22 ±0.05 6.95 ±0.05 3.60 ±0.05 8.25 ±0.05 PACKAGE OUTLINE 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER 36-Lead Plastic QFN (5mm × 8mm) (Reference LTC DWG # 05-08-1790 Rev A) 3.60 ±0.10
Rev. 0 For more information www.analog.com RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS LTC4210 Single Channel Hot Swap Controller Operates from 2.7V to 16.5V, Active Current Limiting, SOT23-6 LTC4211 Single Channel Hot Swap Controller Operates from 2.5V to 16.5V, Multifunction Current Control, MSOP-8 or MSOP-10 LTC4215 Hot Swap Controller with I2C Compatible Monitoring Operates from 2.9V to 15V, 8-Bit ADC Monitors Current and Voltage LTC4217 2A Integrated Hot Swap Controller Operates from 2.9V to 26.5V, Adjustable 5% Accurate Current Limit LTC4218 Hot Swap Controller with 5% Accurate 15mV Current Limit Operates from 2.9V to 26.5V, Adjustable Current Limit, SSOP-16, DFN-16 LTC4219 5A Integrated Hot Swap Controller 12V and 5V Preset Versions, 10% Accurate Current Limit LTC4232 5A Integrated Hot Swap Controller Operates from 2.9V to 15V, Adjustable 10% Accurate Current Limit LTC4233 10A Guaranteed SOA Hot Swap Controller Operates from 2.9V to 15V, Adjustable 11% Accurate Current Limit LTC4234 20A Guaranteed SOA Hot Swap Controller Operates from 2.9V to 15V, Adjustable 11% Accurate Current Limit LTC4238 High Voltage High Current Hot Swap Controller Operates from 6.5V to 80V, Adjustable Current Limit: 6mV to 20mV LTC4283 –48V High Power Hot Swap Controller with Energy Monitor SOA Timer , 8- to 16-Bit ADC Monitors Current, Voltage, Power and Energy, Internal EEPROM, I2C or Single-Wire Broadcast LTC4284 –48V High Power Hot Swap Controller with Energy Monitor Dual Gate Drives, SOA Timer , 8- to 16-Bit ADC Monitors Current, Voltage, Power and Energy, Internal EEPROM, I2C or Single-Wire Broadcast LTC4381 Low Quiescent Current Surge Stopper Withstand Input Surge of Up to 100V 12V,100A Parallel Application
4200 TA02
5.23k 10k 1µF 0.1µF 0.1µF 4700µF VDD UV OUT FB PG GND L T4200 OV SENSE+ INTVCC TIMER FL T# VOUT 12V 100A 100k 1µF VDD UV FB OUT PG GND L T4200 OV SENSE+ INTVCC TIMER FL T# SMCJ15A 12V PINS NOT USED IN THIS CIRCUIT: GATE, IMON, ISET MMBT3906 ANALOG DEVICES, INC. 2021 www.analog.com