LT3967

LT3967 (Rev. 0)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 30

Technical content

Rev 0For more information www.analog.comDocument Feedback TYPICAL APPLICATION FEATURES DESCRIPTION 1.3A Eight-Switch Matrix LED Dimmer with CRC-8 The LT®3967 is an LED bypass switching device for dim- ming individual LEDs in a string using a common current source. It features eight individually controlled floating source 15V/110mΩ NMOS switches. The eight switches can be connected in parallel and/or in series to bypass current around LEDs in a string. The LT3967 uses the I2C serial interface to communicate with a microcontroller . Each of the eight channels can be independently pro - grammed to bypass the LED string in constant on or off, or PWM dimming with or without fade transition. Using the programmable fade option provides 11-bit resolution exponential transition between PWM dimming states. The LT3967 provides an internal clock generator and also sup- ports an external clock source for PWM dimming. The LT3967 reports fault conditions for each channel such as open LED and shorted LED. The four address pins allow

16 LT3967 devices to share the I

power-up state of the switches. 1A Matrix LED Dimmer Powered by a Buck LED Driver

APPLICATIONS

All registered trademarks and trademarks are the property of their respective owners. n Eight Independent 15V/110mΩ NMOS Switches n Controls LED Dimming of Strings Up to 54V n I2C Serial Interface with Programmable Address n I2C Packet Error Checking with CRC-8 n Programmable 256:1 (8-Bit) PWM Dimming n 11-Bit Precision Exponential Fade with Programmable Time n Independent On/Off Control for Each Switch n Programmable Shorted/Open LED Threshold with Fault Reporting n Internal PWM Signal Generator n Programmable Watchdog Timer n Accurate VIN Referred Enable Pin n User Defined Power-Up/Reset State of Switches n Thermally Enhanced TSSOP Package n Automotive LED Headlight Clusters n Large LED Displays n RGBW Color Mixing Lighting 22nF 33µH 1µF ×2 50V 255k 10.2k 2.2µF 2.2µF 10nF 330pF 287k 350kHz 267k 10k 100m/uni03A9 10k 10nF

3967 TA01

10µF 50V 10k 49.9k 10k 10k 1µF 50V 2.2µF 22nF 50V VIN EN/UVLO L T3932 VREF CTRL PWM INTVCC SS RT RP VC SYNC/SPRD ISN ISP FB VOUT SW BST VIN 32V TO 36V INTVCC GND VIN GND DRN6 SRC6 DRN5 SRC5 DRN4 SRC4 DRN3 SRC3 DRN2 SRC2 DRN1 SRC1 DRN8 DRN7 SRC8 SRC7 L T3967 LED+ LED+ ENH ADDR1 ADDR2 ADDR3 ADDR4 WDI VDD SCL SDA ALERT RTSYNC CLKIN CLKIN 3.3V 350kHz VDD UP TO 26V LED INTVCC D1: NEXPERIA BAT46WJ D2: NXP PMEG4010CEJ L1: WURTH 74437349330 PWMTG, FAUL T, AND ISMON NOT USED

Rev 0 For more information www.analog.com TABLE OF CONTENTS T

Description

T Over Power Dimming without Fade T ransition vs Dimming with Fade T W R Printed Cir T T

Rev 0For more information www.analog.com PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS 3V, 17V S A O perating Junction Temperature Range (Note 2) C to 150°C (Note 1) TOP VIEW FE PACKAGE 28-LEAD PLASTIC TSSOP θJA = 30°C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB DRN8 V IN ENH ALERT SCL SDA VDD RTSYNC ADDR1 ADDR2 ADDR3 ADDR4 WDI SRC1 SRC8 DRN7 SRC7 DRN6 SRC6 DRN5 SRC5 DRN4 SRC4 DRN3 SRC3 DRN2 SRC2 DRN1 GND ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3967EFE#PBF LT3967EFE#TRPBF LT3967FE 28-Lead Plastic TSSOP –40°C to 125°C LT3967JFE#PBF LT3967JFE#TRPBF LT3967FE 28-Lead Plastic TSSOP –40°C to 150°C Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

Rev 0 For more information www.analog.com

ELECTRICAL CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITS VDD Input Supply Voltage l 2.7 5.5 V VDD Operating IQ I2C Bus Idle, RTSYNC = 28k 1.5 2.2 mA VDD Shutdown IQ VIN - ENH < 1.15V, All Channels LED ON VIN - ENH < 1.15V, All Channels LED OFF 0.5 0.6 mA mA V IN Operating Voltage All Channels VOTH = VSTH = 0 (Note 3) l 8 60 V VIN Operating IQ (Channel Not Switching) All Channels VOTH = VSTH = 0, LED ON 1.3 1.8 mA All Channels VOTH = VSTH = 1, LED OFF 2.5 3.5 mA All Channels VOTH = 1, VSTH = 0, LED ON 1.8 2.5 mA VIN Shutdown IQ VIN - ENH < 1.15V, All Channels LED ON VIN - ENH < 1.15V, All Channels LED OFF 0.9 1.4 mA mA DRN[8:1] Operating Voltage l VIN – 1V V SRC[8:1] Operating Voltage l VIN – 6V V Current Out of SRC[8:1] Pins (Each Channel) Channel LED Is On (Channel Switch Is Off) Channel LED Is Off (Channel Switch Is On) l l µA µA Switch On-Resistance 110 mΩ Switch Leakage Current DRN = 8V, SRC = 0V, VOTH = 1 1 µA Switch Transition Time (t r/tf) DRN to 5V Through a 50Ω Resistor, VOTH = 1 1.0 1.6 2.2 µs DRN[8:1] to SRC[8:1] Overvoltage Protection Clamp Voltage LED or Switch Bypass Current is 1.3A l 15 17 V Response Time from Switch Overvoltage Protection to Switch Turn On LED or Switch Bypass Current is 1.3A l 5.2 6.6 µs Programmable Open LED Threshold (VOTH) SRC = 0V, VOTH = 0 (Note 3) SRC = 0V,VOTH = 1 SRC = 2V, VOTH = 0 SRC = 2V,VOTH = 1 l l l l 5.2 10.4 5.0 10.1 6.1 11.4 5.5 10.8 7.0 12.4 6.0 11.5 V V V V Programmable Shorted LED Threshold (V STH) VSTH = 0 (Note 3) VSTH = 1 l l 0.85 3.6 1.15 4.4 V V ENH Threshold Voltage Falling ENH(V TH) (VIN - ENH) l 1.1 1.22 1.34 V ENH Threshold Voltage Rising Hysteresis 50 mV ENH Pin Input Bias Current VIN – ENH = 1.5V, Current Out of ENH Pin 40 100 nA RTSYNC Programmable Internal Oscillator or External Clock Source LED PWM Dimming Frequency (= RTSYNC Programmed Oscillator Frequency/2048 or External Clock Frequency/2048) R TSYNC = 80.6kΩ RTSYNC = 28kΩ RTSYNC = 10kΩ l l l 170 450 880 198 500 1010 220 550 1130 Hz Hz Hz RTSYNC Output Voltage (Using Internal Oscillator) R TSYNC = 28kΩ 0.83 0.88 0.93 V Programmable LED PWM Dimming Frequency Range (Using Internal Oscillator) 100 1000 Hz Standby Fixed LED PWM Dimming Frequency RTSYNC = Float 32 45 58 Hz The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 40V, ENH = 38.5V, VDD = 5V, SRC[8:1] = 0V, ADDR[4:1] are tied to GND through a 100kΩ resistor respectively, SDA and SCL are pulled up to VDD by a 4.99kΩ resistor respectively, unless otherwise noted.

Rev 0For more information www.analog.com PARAMETER CONDITIONS MIN TYP MAX UNITS RTSYNC Input Clock Frequency Range 200 2000 kHz RTSYNC Input Low Threshold (RTVIL) l 0.4 V RTSYNC Input High Threshold (RTVIH) l 1.5 V RTSYNC Input Clock Pulse Width High (TRTH) 100 ns RTSYNC Input Clock Pulse Width Low (TRTL) 100 ns RTSYNC Input Clock Ramp Time Between RTVIL and RTVIH (TRTR) TRTH + TRTL > TRTR 2.5 µs Watchdog Timer Watchdog Upper Boundary (Timeout) A 10nF Capacitor Between WDI and GND l 15 17.5 20 ms WDI Pin Pull-Up Current WDI = 0.8V l 9 10 11 µA WDI Pin Pull-Down Current WDI = 2.2V 200 µA WDI Low Threshold Voltage 1 V WDI High Threshold Voltage 2 V Address Select and ACMREG Register Power-On Reset ADDR[4:1] Input Low Resistance to GND, ACMREG[M:N] = "00" at V DD Power-Up M:N=7:6 for ADDR[4], M:N=5:4 for ADDR[3], M:N=3:2 for ADDR[2], M:N=1:0 for ADDR[1] l 5 kΩ ADDR[4:1] Input Low Resistance to GND, ACMREG[M:N] = "11" at V DD Power-Up M:N=7:6 for ADDR[4], M:N=5:4 for ADDR[3], M:N=3:2 for ADDR[2], M:N=1:0 for ADDR[1] l 50 150 kΩ ADDR[4:1] Input High Resistance to VDD, ACMREG[M:N] = "11" at VDD Power-Up M:N=7:6 for ADDR[4], M:N=5:4 for ADDR[3], M:N=3:2 for ADDR[2], M:N=1:0 for ADDR[1] l 50 150 kΩ ADDR[4:1] Input High Resistance to VDD, ACMREG[M:N] = "00" at VDD Power-Up M:N=7:6 for ADDR[4], M:N=5:4 for ADDR[3], M:N=3:2 for ADDR[2], M:N=1:0 for ADDR[1] l 5 kΩ Alert Status Output ALERT Output Low Voltage IALERT = 3mA 0.3 0.4 V ALERT Output High Leakage Current ALERT = 5.5V 0.1 µA I2C Port (See Note 5 for I2C Timing Diagram) SDA and SCL Input Threshold Rising l 0.7VDD V SDA and SCL Input Threshold Falling l 0.25VDD V SDA and SCL Input Hysteresis l 0.05VDD V SDA and SCL Input Current SDA = SCL = 0V to 5.5V –250 250 nA SDA Output Low Voltage ISDA = 3mA l 0.4 V SCL Clock Operating Frequency l 400 kHz ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 40V, ENH = 38.5V, VDD = 5V, SRC[8:1] = 0V, ADDR[4:1] are tied to GND through a 100kΩ resistor respectively, SDA and SCL are pulled up to VDD by a 4.99kΩ resistor respectively, unless otherwise noted.

Rev 0 For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 40V, ENH = 38.5V, VDD = 5V, SRC[8:1] = 0V, ADDR[4:1] are tied to GND through a 100kΩ resistor respectively, SDA and SCL are pulled up to VDD by a 4.99kΩ resistor respectively, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS (Repeated) Start Condition Hold Time (tHD_STA) l 0.6 µs Repeated Start Condition Set-Up Time SU_STA) l 0.6 µs Stop Condition Setup Time (tSU_STO) l 0.6 µs Data Hold Time Output (tHD_DAT(O)) l 0 900 ns Data Hold Time Input (tHD_DAT(I)) l 0 ns Data Set-Up Time (tSU_DAT) l 100 ns SCL Clock Low Period (tLOW) l 1.3 µs SCL Clock High Period (tHIGH) l 0.6 µs Data Rise Time (tr) CB = Capacitance of One BUS Line (pF) (Note 4) 20+0.1CB 300 ns Data Fall Time (tf) CB = Capacitance of One BUS Line (pF) (Note 4) 20+0.1CB 300 ns Input Spike Suppression Pulse Width (tSP) 50 ns Bus Free Time (tBUF) l 1.3 µs Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3967E is guaranteed to meet performance specifications from the 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3967I is guaranteed over the full –40°C to 125°C operating junction temperature range. The LT3967H is guaranteed over the full –40°C to 150°C operating junction temperature range. High junction temperatures degrade operating lifetimes. Operating lifetime is derated at junction temperatures greater than 125°C. tSP tBUF tSU,STO tSP tHD,STA START CONDITION STOP CONDITION tSU,STA tHD,DATI tHD,DATO REPEATED START CONDITION REPEATED START CONDITION tSU,DAT SDA SCL tHD,STA 3967 TD Note 3: VOTH and VSTH register bits are set by a LT3967 I2C command. VOTH/VSTH programmed by VOTH/VSTH register bits refer to the open/ shorted LED threshold between DRN and SRC of a channel. For a channel, V IN > VSRC + VOTH + 1V is required for accurate open LED detection. Note 4: Rise and fall times are measured at 30% and 70% levels. Note 5: I2C interface timing diagram (see below).

Rev 0For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS VDD Quiescent Current vs Temperature VIN Quiescent Current vs Temperature Enable Threshold ENH(VTH) vs Temperature RTSYNC vs PWM Dimming Frequency PWM Dimming Frequency vs Temperature Switching T ransition Time vs Temperature SWITCHES ARE ON SWITCHES ARE OFF V DD = 5V TEMPERATURE (°C) –50 –25 100 125 150 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 V DD I Q (mA)

3967 G01

V DD = 5V , V IN = 40V VOTH = 1, VSTH=0, SWITCHES ARE ON VOTH = VSTH=1, SWITCHES ARE ON VOTH = VSTH=0, SWITCHES ARE OFF VOTH = 1, VSTH=0, SWITCHES ARE OFF TEMPERATURE (°C) –50 –25 100 125 150 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 V IN I Q (mA)

3967 G02

R TSYNC = 28kΩ TEMPERATURE (°C) –50 –25 100 125 150 460 470 480 490 500 510 520 530 540 DIMMING FREQUENCY (Hz)

3967 G05

DIMMING FREQUENCY (Hz) 200 400 600 800 1000 100 120 140 160 R TSYNC (kΩ)

3967 G04

TEMPERATURE (°C) –50 –25 100 125 150 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 TRANSITION TIME (µs)

3967 G06

TEMPERATURE (°C) –50 –25 100 125 150 1.16 1.18 1.20 1.22 1.24 1.26 1.28 1.30 ENH THRESHOLD (V)

3967 G03

Rev 0 For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Switch Open LED Protection Response Time Scope Photo Open LED Threshold vs VIN, for SRC = 0V Open LED Threshold vs VIN, for SRC ≥ 2V SRC = 0 VOTH = 1 VOTH = 0 T A = –50°C T A = 25°C T A = 150°C V IN (V) 5.0 5.7 6.4 7.1 7.8 8.5 9.2 9.9 10.6 11.3 12.0 OPEN LED THRESHOLD (V)

3967 G11

VOTH = 1 VOTH = 0 SRC ≥ 2V T A = –50°C T A = 25°C T A = 150°C V IN (V) OPEN LED THRESHOLD (V)

3967 G12

5µs/DIV V(DRN-SRC) 5V/DIV I(DRN) 500mA/DIV ALERT 5A/DIV

3967 G10

Standby Dimming Frequency vs Temperature WDI Pin Pull-Up/Pull-Down Current vs Temperature TEMPERATURE (°C) –50 –25 100 125 150 100 110 120 130 140 150 160 170 SWITCH ON–RESISTANCE (mΩ)

3967 G07

V DD = 5V TEMPERATURE (°C) –50 –25 100 125 150 STANDBY DIMMING FREQUENCY (Hz)

3967 G08

PULL-DOWN CURRENT AT WDI = 2.2V PULL-UP CURRENT AT WDI = 0.8V TEMPERATURE (°C) –50 –25 100 125 150 100 120 140 160 180 200 220 PULL-UP/DOWN CURRENT (µA)

3967 G09

Rev 0For more information www.analog.com Open LED Threshold vs SRC Shorted LED Threshold vs VIN, Temperature Current Out of SRC Pin vs Temperature RTSYNC vs Fading Time for FTM[2:0] = 001 RTSYNC Input Clock Frequency vs Fading Time for FTM[2:0] = 001 Switch Slew Rate Scope Photo VOTH = 1 VOTH = 0 V IN = 40V T A = –50°C T A = 25°C T A = 150°C SRC VOL TAGE (V) 0.4 0.8 1.2 1.6 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 OPEN LED THRESHOLD (V)

3967 G13

VSTH = 0 VSTH = 1 SRC = 0V V IN (V) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 SHORTED LED THRESHOLD (V)

3967 G14

TA = 150°C TA = 25°C TA = –50°C SWITCH IS ON SWITCH IS OFF TEMPERATURE (°C) –50 –25 100 125 150 CURRENT OUT OF SRC (µA)

3967 G15

0% AND 100% FADING UP FADING TIME (ms) 100 250 400 550 700 850 1000 100 120 140 160 180 R TSYNC (kΩ)

3967 G16

0% AND 100% FADING TIME (ms) 100 250 400 550 700 850 1000 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 RTSYNC INPUT CLOCK FREQUENCY (MHz)

3967 G17

2µs/DIV LED CURRENT 500mA/DIV V(DRN-SRC) 1V/DIV

3967 G18

TYPICAL PERFORMANCE CHARACTERISTICS

Rev 0 For more information www.analog.com ADDR[4:1]: Programmable Address Select and Initial Switch State Set Pins. The device address is 010xxxx0 for all channel mode (ACMODE) write, 010xxxx1 for all channel mode (ACMODE) read, 101x xxx0 for single channel mode (SCMODE) write, and 101xxxx1 for single channel mode (SCMODE) read, where xxxx represents the input logic value from ADDR[4:1] pins. The input logic value is 0/1 if the pin is connected to GND/V DD through a 150kΩ resistor or less. A total of 16 LT3967 devices can be connected to the same I 2C bus. Resistor values at ADDR[4:1] pins are also used to determine the V DD Power on Reset (POR) default value of ACMREG. A low value resistor (≤5k) to GND or VDD signals the LED should be off at start-up. A high value resistor (≥50k) to GND or V DD signals the LED should be on at start-up. ALERT: Alert Output for Fault Condition Report. ALERT pin is asserted (pulled low) to indicate any of the following fault conditions: an open LED, a shorted LED, overheat fault condition or a RTSYNC clock fault. The ALERT pin is deasserted (released to high) after the part sends its alert response address successfully or the fault condition is cleared by an I2C write command. The alert function is disabled when ENH is undervoltage. DRN[8:1]: Floating N-Channel FET Drain Side Pins. Tie to VDD with a 100kΩ resistor if not used. ENH: Shutdown and Undervoltage Detect Pin for V IN. When ENH pin is 1.22V (nominal) lower than VIN pin, PWM dimming and fault reporting are enabled. ENH undervolt- age is reported through the I2C interface. Typically this pin is tied to a resistor divider to ensure the part is enabled only when V IN is at least 6V higher than channel source voltage. GND: Exposed Pad Pin. Solder the exposed pad directly to ground plane (GND). RTSYNC: External PWM Clock Input and Internal Oscillator Frequency Programming Pin. Set the internal oscillator frequency using a resistor to GND if the internal oscillator is used for PWM dimming. An external clock source able to sink 500µA at 0.4V can be used for PWM dimming by driving RTSYNC above and below RTVIH and RTVIL respec- tively to override the internal oscillator . Do not leave the RTSYNC pin open. Place the resistor close to the IC if a resistor is used to set the internal oscillator frequency. LED PWM dimming frequency equals the programmed inter- nal oscillator frequency divided by 2048 or the external clock frequency divided by 2048. If the programmed inter- nal oscillator frequency or the external clock frequency becomes slower than 100kHz (nominal), the PWM clock setting LED dimming will switch to a 100kHz (nominal) internal standby clock. If the external clock connection is lost, the PWM clock setting LED dimming will switch to the R TSYNC programmed internal oscillator frequency if a programming resistor RTSYNC is connected between the RTSYNC pin and GND. Otherwise the PWM clock setting LED dimming will switch to the 100kHz (nominal) internal standby clock. This selection can be reset by V DD POR, watchdog timeout or an I2C BCMODE write command. SCL: Clock Input Pin for the I2C Serial Port. The I2C logic levels are scaled with respect to VDD. SDA: Data Input and Output Pin for the I2C Serial Port. The I2C logic levels are scaled with respect to VDD. PIN FUNCTIONS

Rev 0For more information www.analog.com PIN FUNCTIONS SRC[8:1]: Floating N-Channel FET Source Side Pins. The channel source voltage (SRC[8:1] ) must be at least 6V lower than VIN for proper channel switch bypass opera - tion. Tie to GND if not used. VIN: Input Supply Pin for LED Bypass Switches and Fault Detectors. Must be locally bypassed with a 1µF (or larger) capacitor placed close to this pin. For proper channel switch bypass operation, VIN must be at least 6V higher than the channel source voltage. V DD: Supply Voltage for I2C Serial Port and Input Supply Pin for Internal Bias and Logic. This pin sets the logic reference level of I 2C SCL and SDA pins. SCL and SDA logic levels are scaled to VDD. When the VDD supply tran- sitions above 2.5V (nominal), ACMREG and SCMREG are reset to the default value, and the I 2C interface is active. The LT3967 will acknowledge communications to its address and data can be written to and read back from the registers. This is true even if the part is disabled. The data in ACMREG and SCMREG will not change unless it is updated by an I 2C command, VDD POR or a watchdog timeout. Connect a 0.1μF (or larger) decoupling capacitor from this pin to ground. WDI: Watchdog Timer Input Pin. This pin is used to set the watchdog upper boundary using a capacitor to GND. The watchdog starts monitoring I 2C communications when VDD transitions above 2.5V. A timeout occurs when the time between VDD POR or START and STOP reaches the programmed watchdog upper boundary. The timeout resets all LT3967 registers to the default value, resets channel switches to the default state determined by resis- tor settings at ADDR[4:1] pins, and resets the PWM clock to the RTSYNC input clock. Do not leave this pin open. To disable the watchdog function, tie this pin to GND.

Figure 1. Block Diagram

3967 F01

Rev 0For more information www.analog.com APPLICATIONS INFORMATION OVERVIEW The LT3967 is an 8-channel LED bypass switching device with I 2C serial interface, designed for dimming LED strings using a common current source. Each of the eight channels can be independently programmed to bypass the LED string in constant on or off, or dimming with or without fade transition. Operation can be best understood by referring to the Block Diagram in Figure 1. The LT3967 operates over the V DD input supply range of 2.7V to 5.5V. The eight channel switches are powered by the VIN input supply and can be connected in parallel and/or in series. Each of the eight channel switches can bypass one or multiple series LEDs up to 10.1V. Each channel has an LED fault detector which can be pro- grammed to detect an open LED fault at one of the two threshold levels: 6.1V/5.5V and 11.4V/10.8V (default set- ting). When an open LED fault is detected in a channel, the channel switch will be turned on to bypass the faulty LED to maintain the continuity of the string and for self protec- tion. The PWM dimming for this channel is interrupted until reset by the serial interface. Each channel LED fault detector can also be programmed to detect a shorted LED fault at one of the two threshold levels: 1V (default setting) and 4V. The 1V and 4V threshold levels may be used to differentiate a 2-shorted LED fault from a 1-shorted LED fault in a multi-LED segment. When a shorted LED fault is detected in a channel, the channel switch will continue with the programmed PWM dimming. Besides LED faults, the LT3967 also detects and reports an overheat fault condition (≥170°C) and a RTSYNC clock fault condition. The LT3967 asserts (pulls down) the ALERT pin to inter- rupt the bus master when an LED fault and/or an overheat fault and/or a RTSYNC clock fault is detected. The master can use the alert response address (ARA) to determine which device is sending the alert. The LT3967 I 2C serial interface contains nine command registers for configuring channel switches and LED fault detectors and programming logarithmic fade time. It also contains two read-only fault status registers for reporting the LED and overheat faults. The I2C serial interface supports random addressing of any register . The LT3967 address select pins ADDR4, ADDR3, ADDR2 and ADDR1 allow up to 16 LT3967 devices to share the I2C bus. Resistor values at the address select pins are also used to determine the VDD POR default state of LEDs. If a resistor is connected between the RTSYNC pin and the ground, the internal oscillator is chosen and the LED dim- ming frequency is set by the resistor . If the RTSYNC pin is driven by an external clock source, the external clock source is used to override the internal oscillator and the dimming frequency equals the external clock frequency divided by 2048. Details of the LT3967 operation are found in the following sections. POWER-ON RESET AND DIMMING CYCLE INITIALIZATION The channels are set in pairs with ADDR4 setting the two MSBs and ADDR1 setting the two LSBs. See Table 1 for an overview of the ACMREG register . When V DD transi- tions above 2.5V, an internal power-on reset (POR) signal is generated to reset all LT3967 registers to the default value. Resistor values at ADDR[4:1] pins are used to determine the POR default state of ACMREG register bits which set each channel switch state at start-up. The POR also initializes each channel’ s PWM dimming counter with one-eighth dimming cycle shift, which can avoid simultaneous channel switching at the beginning of dimming cycle to reduce switching transients (see Figure 2). When using PWM dimming (with or without fade transition), the channel LED string is always turned on at the beginning of its dimming cycle. The channel LED string will be turned off if the value of the channel counter , which is clocked by the PWM clock, equals the dimming value stored in the channel SCMREG command register . Once the channel LED string is turned off, it remains off until its next dimming cycle starts. OPERATION IN SHUTDOWN CONDITION The ENH pin is used to enable the IC. When ENH pin is undervoltage for the V IN supply, the part is in shutdown condition, in this mode PWM dimming, ALERT pin assert- ing and fault reporting are disabled, and the IC does not respond to the broadcast read command. The LT3967 sets all OLFREG and SLFREG register bits high with

only by ACMREG register bits in shutdown condition. PWM dimming, ALERT pin asserting and fault reporting. Figure 1 can be used to generate ENH input signal. Figure 2. POR Dimming Cycle Initialization Diagram

1 DIMMING CYCLE = 2048 RTCLK CLOCK CYCLES

3967 F02

channel LED dimming functions without fade transition. isters are used to store the LED/overheat fault status bits. can be found in the Watchdog Timeout Reset section. Figure 4. LT3967 Down T ransition Dimming Curve from

3967 F04

Table 1. All Channel Mode (ACMODE) Command Register (8 Bits Long. See All Channel Mode (ACMODE) Command section for how to Figure 3. LT3967 Up T ransition Dimming Curve from LED

3967 F03

Table 2. Single Channel Mode (SCMODE) Command Registers (16 Bits Long. See Single Channel Mode (SCMODE) Command section

10000100 DDDDDDDD

10000100 CCCCCCCC

10000100 BBBBBBBB

10000100 AAAAAAAA

GND/VDD is 5kΩ or less, or is set to 1 if the values resistor to GND/VDD is between 50kΩ and 150kΩ.

Table 3. Read-Only Fault Status Register (See All Channel Mode (ACMODE) Command section for how to access these register bits) (See Operation in Shutdown Condition section for detail). If the two conditions are concurrent, the shutdown condition dominates. Figure 5. LT3967 Command Registers and Channel Control Diagram

3967 F05

Rev 0 For more information www.analog.com APPLICATIONS INFORMATION or transmit register contents. The serial clock line (SCL) is always an input to the LT3967 and the serial data line (SDA) is bidirectional. The LT3967 can only pull the serial data line (SDA) LOW and can never drive it HIGH. SCL and SDA are required to be externally connected to the V DD supply through a pull-up resistor . When the data line is not being driven LOW , it is HIGH. Data on the I 2C bus can be transferred at rates up to 100kbits/s in the standard mode and up to 400kbits/s in the fast mode. THE START AND STOP CONDITIONS When the bus is idle, both SCL and SDA must be HIGH. A bus master signals the beginning of a transmission with a START condition by transitioning SDA from HIGH to LOW while SCL is HIGH. When the master has finished communicating with the slave, it issues a STOP condi - tion by transitioning SDA from LOW to HIGH while SCL is HIGH. The bus is then free for another transmission. However , if the master still wishes to communicate on the bus, it can generate a repeated START condition (Sr) and address the same or another slave without first generating a STOP condition. When the bus is in use, it stays busy if a repeated START (Sr) is generated instead of a STOP condition. The repeated START (Sr) conditions are func- tionally identical to the START (S). Various combinations of read/write commands are then possible within such a transfer , except that the BCMODE write command for dim- ming cycle synchronization and the BCMODE read com- mand for alert inquiry and the ACMODE write command for clearing the overheat fault bits must be self contained with a terminating STOP condition. I 2C SERIAL PORT DATA TRANSFER After the START condition, the I2C bus is busy and data transfer can begin between the master and the addressed LT3967 slave. Data is transferred over the bus in group of nine bits, one byte followed by one acknowledge (ACK) bit. The acknowledge signal is used for handshaking between the master and the slave. A Packet Error Checking (PEC) mechanism is imple - mented in the LT3967 to improve I 2C communication reliability. This mechanism requires that a PEC byte (or CRC-8 checksum), which is calculated over the entire message frame including the address and read/write bit, is always appended at the end of each ACMODE or SCMODE command. The polynomial used for the PEC byte calculation is x8 + x2 + x + 1 (initialized to zero). Both the transmitter and the receiver need to calculate a PEC byte. The transmitter sends its PEC byte derived from the read/write address and subsequent outgoing data bytes. The receiver calculates its own PEC byte from the read/ write address and subsequent incoming data bytes, and compares it with the received one. A PEC-byte mismatch guarantees that an error has occurred during the transac- tion. A PEC-byte match suggests a reasonable likelihood of the command being received correctly, as long as the same polynomial is used. Example Linduino code for cal- culating CRC-8 PEC is provided (see next page). When the LT3967 is written to, it acknowledges its device write address and subsequent data bytes. It acknowledges the PEC byte if the PEC bytes match. Otherwise it does not acknowledge it. The received data bytes are validated and transferred to internal holding latches upon the return of the acknowledgment of the PEC byte by the LT3967. The received data bytes are regarded as void by the LT3967 in case of mismatch. If desired, a repeated START (Sr) con- dition may be initiated by the master to address another device on the I 2C bus or another register in the same device for data transfer . The LT3967 remembers the valid data it has received. Once selected channels of the devices on the I2C bus have been addressed and sent valid data, the master issues a STOP condition to finish the commu- nication. The LT3967 will update its command registers with the data it has validated upon the STOP condition, except that the VOTH and VSTH bits are updated in the channel SCMREG command register upon the return of the acknowledgment of the PEC byte by the LT3967. When reading from the LT3967 , the master initiates the command by issuing a read address. The LT3967 acknowledges its device read address and responds with subsequent data bytes plus a PEC byte. The master is not required to acknowledge the data/PEC bytes. The master can free the I 2C bus by issuing a STOP condi- tion after the data transfer . If desired the master can verify the data bytes written to the internal holding latches prior to updating them to the command registers by reading them back before sending a STOP condition.

Rev 0For more information www.analog.com APPLICATIONS INFORMATION // Bytewise CRC-8 for LT3967 using X8 + X2 + X + 1 // Takes a running sum (or 0) as <in>, and current byte to CRC as <data> // Returns the CRC-8 of <in> and <data> for sending or further CRC’ing int8_t doCRC(int8_t in, int8_t data){ int8_t crc; int8_t crc = in ^ data; // XOR the incoming bytes for(i = 0; i < 8; i++){ // Step through each bit if (crc & 0x80) { // If MSB is set crc <<= 1; // Shift up, then crc ^= 0x07; // XOR with the low byte of polynomial } else { // If MSB is unset crc <<= 1; // Simply shift up // Repeat for rest of bits return crc; // Finally, send back the result // Usage of ACMODE Write Protocol, // where CHIPADDR and DATA are the bytes to send to LT3967 int8_t myCRC; myCRC = doCRC(0, CHIPADDR); myCRC = doCRC(myCRC, DATA); // myCRC now holds the completed PEC byte for sending to LT3967 // Usage of SCMODE Write Short Format Protocol, // where CHIPADDR and DATA are the bytes to send to LT3967 int8_t myCRC; myCRC = doCRC(0, CHIPADDR); myCRC = doCRC(myCRC, DATA); // myCRC now holds the completed PEC byte for sending to LT3967 // Usage of SCMODE Write Long Format Protocol, // where CHIPADDR, DATA1, and DATA2 are the bytes to send to LT3967 int8_t myCRC; myCRC = doCRC(0, CHIPADDR); myCRC = doCRC(myCRC, DATA1); myCRC = doCRC(myCRC, DATA2); // myCRC now holds the completed PEC byte for sending to LT3967 Example Linduino ® Code for Calculating CRC-8 PEC

for the purpose of dimming without flicker . ister and the SLFREG register . mission (the master reads from the addressed LT3967) . address select pins ADDR4, ADDR3, ADDR2 and ADDR1. connected to GND/VDD through a 150kΩ resistor or less. about 70µs to transmit if 400kHz SCL clock is chosen. and channel switching off (LED turning on) is about 2µs. Figure 7. LT3967 I2C Serial Port ACMODE Read Protocol

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Figure 6. LT3967 I2C Serial Port ACMODE Write Protocol

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makes one channel switch at a time. of the channel SCMREG register you want to configure. off or constant on immediately with AO (B[9]) set to 0 or 1. Figure 8. LT3967 I2C Serial Port SCMODE Write Short Format Protocol Figure 9. LT3967 I2C Serial Port SCMODE Write Long Format Protocol

0 CA 3 CA2 CA1 B[15]B[14]B[9] B[8]

3967 F08

3967 F09

is the dimming value DV[7:0]. 11.4V/10.8V (default) respectively. respectively (refer to Table 2, Figure 9 and Figure 5).

• TSTEP = N • M • TPWM = N • M • TRTSYNC • 2048, where N is the number of transitional steps determined by the distance between the initial dimming value and the target dimming value. M is the programmed fade time multiplier which sets the number of PWM dimming cycles running for each transitional step. T STEP, TPWM and T RTSYNC represent the run time for one transitional step, one PWM dimming cycle and one RTSYNC input clock cycle respec- tively. When M is set to 0, the channel LED performs PWM dimming without fade transition. The SCMODE read command (see Figure 10 and Figure 11) is used to read back the addressed channel SCMREG reg- ister bits. The SCMODE read command is four bytes long including the PEC byte. The first byte is the SCMODE device read address. The second byte comprises (from MSB to LSB) the open LED threshold bit VOTH, the shorted LED threshold bit VSTH, the fade time multiplier FTM[2:0], the fading done indicator FDI which is a read-only bit used to indicate whether the fade process has ended or not, the asynchronous on/off bit AO and the asynchronous enable bit AE from the addressed SCMREG register . The third byte is the dimming value DV[7:0] from the addressed SCMREG register . Unlike the SCMODE write command, the SCMODE read command does not contain the channel address. Actu- ally the channel address received from the last SCMODE

Figure 10. LT3967 I2C Serial Port SCMODE Read Protocol

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Figure 11. LT3967 I2C Serial Port SCMODE Write Short Format Followed by SCMODE Read

3967 F11

(SLAVE ACK IF PEC HAS NO ERRORS.

received, the default channel address 000 (CH1) is used. mission (the master reads from the addressed LT3967). address select pins ADDR4, ADDR3, ADDR2 and ADDR1. connected to GND/VDD through a 150kΩ resistor or less. and to reset the PWM clock to the RTSYNC input clock. command does not modify any register bits. select pins ADDR4, ADDR3, ADDR2 and ADDR1. determine which device initiated the interrupt. Figure 12. LT3967 I2C Serial Port BCMODE Write Protocol Figure 13. LT3967 I2C Serial Port BCMODE Read Protocol

3967 F12

3967 F13

Rev 0For more information www.analog.com APPLICATIONS INFORMATION if another device is sending an address at the same time using standard I2C bus arbitration. If the LT3967 is send- ing a 1 and reads a 0 on the SDA pin on the rising edge of SCL, it assumes another device with a lower address is sending and the LT3967 immediately aborts its transfer and waits for the next ARA cycle to try again. If transfer is successfully completed, the LT3967 will deassert its ALERT pin and will not respond to further ARA requests until a new alert event occurs. Please note that the suc - cessfully completed ARA cycle deasserts the ALERT pin only. It does not clear the fault status bit set in the OLFREG/SLFREG register . WATCHDOG TIMEOUT RESET The LT3967 has a programmable watchdog timer designed to monitor I 2C communications to make sure reliable connection between the master and the LT3967 slave. The WDI pin is used to set the watchdog upper boundary with a capacitor to GND. The watchdog starts monitoring the serial interface when V DD transitions above 2.5V. A timeout occurs when the time between VDD POR or START and STOP reaches the programmed watchdog upper boundary. Like the VDD POR, the timeout event resets all LT3967 registers to the default value, and resets the PWM clock to the RTSYNC input clock. Each channel switch state is determined by resistor settings at ADDR[4:1] pins. In other words, watchdog timeout reset has the same initialization effect as V DD POR reset. For the customer who wants to know if the IC was reset by unexpected V DD POR or watchdog timeout during normal operation, the following procedure is suggested: 1) Upon V DD powered on, a unique data byte such as 10101010, which is different from the default determined by ADDR[4:1] resistor settings, should be immediately written to ACMREG register by using an ACMODE write command followed by 8 SCMODE write commands which configure channel dimming operation, and a STOP condi- tion. 2) By reading ACMREG register periodically using an ACMODE read command at intervals less than the watch- dog upper boundary (nominal 16ms with a 10nF capaci- tor), the customer is able to know if VDD POR or watchdog timeout reset has unexpectedly occurred during normal operation. ACMREG register reset to the default indicates VDD POR or watchdog timeout has occurred. Otherwise it indicates the IC has been operating with neither VDD POR nor watchdog timeout reset. Please note that the ACMODE write command mentioned in the procedure above should be used exclusively for detecting V DD POR or watchdog timeout reset. It will not be used to set channel switch state in this case. RTSYNC INPUT CLOCK FAUL T DETECTION AND ALERT ASSERTION The PWM clock is required by the LT3967 to perform PWM dimming. The PWM clock is disabled as long as the LT3967 is disabled (ENH pin is undervoltage for V IN supply). When the IC is being enabled, the PWM clock is set to the RTSYNC input clock coming either from the external clock source or from the R TSYNC programmed internal oscillator . Besides the RTSYNC programmed inter- nal oscillator , the LT3967 provides an internal standby clock (100kHz nominal). When a RTSYNC clock fault is triggered upon the RTSYNC clock running slower than the internal standby clock, the PWM clock will be switched from the RTSYNC clock to the standby clock. If the exter- nal clock connection is lost, the PWM clock setting LED dimming will switch to the RTSYNC programmed internal oscillator frequency without asserting ALERT pin if a pro- gramming resistor RTSYNC is connected between RTSYNC pin and GND. Otherwise the PWM clock will switch to the internal standby clock and ALERT pin will be asserted. Once switched, the PWM clock remains with the standby clock until reset by V DD POR, watchdog timeout or a BCMODE write command. The LT3967 asserts ALERT pin to indicate the RTSYNC clock fault condition. ALERT pin can be deasserted by V DD POR, watchdog timeout, a BCMODE write command or a BCMODE read command which successfully sent the alert response address to the master . LED/OVERHEAT FAUL T DETECTION AND REPORTING The LT3967 detects and reports open LED, shorted LED and overheat fault conditions via ALERT pin and I2C serial interface. (See the following sections for detail.)

Rev 0 For more information www.analog.com APPLICATIONS INFORMATION OPEN LED FAUL T DETECTION AND ALERT ASSERTION An open LED fault will be triggered when the voltage between the channel DRN pin and the channel SRC pin exceeds 13V (nominal) or when the voltage between the channel DRN pin and the channel SRC pin exceeds the programmed open LED threshold but less than 13V (nominal) for more than 15µs (nominal). Once an open LED fault is triggered in a channel, the fault status bit matching the channel will be set in the OLFREG status register , which will cause the ALERT pin to be asserted (pulled down) and the channel switch to be turned on for the switch protection and to maintain continuity of the string for good LEDs. The switch can be turned off and PWM dimming reestablished by updating its registers with the serial interface. SHORTED LED FAUL T DETECTION AND ALERT ASSERTION A shorted LED fault will be triggered when the voltage between the channel DRN pin and the channel SRC pin falls below the programmed shorted LED threshold for more than 15µs (nominal). Once a shorted LED fault is triggered in a channel, the fault status bit matching the channel will be set in the SLFREG status register , which will cause the ALERT pin to be asserted (pulled down). However , unlike the open LED fault, the channel switch will continue with the programmed PWM dimming. LED FAUL T STATUS BIT CLEARANCE The fault status bit set in the OLFREG/SLFREG register by an open/shorted LED fault can only be cleared by an ACMODE write command or a SCMODE write command accessing the channel. If the open/shorted LED fault no longer exists when the write command is updating the command register at the I 2C STOP condition, the fault status bit matching the channel will be cleared and the ALERT pin will be deasserted. Otherwise, the fault status bit will remain set, and the ALERT pin will remain asserted or be asserted again if previously deasserted. OVERHEAT FAUL T DETECTION AND ALERT ASSERTION An overheat fault will be triggered when the IC tempera - ture exceeds 170°C (nominal). Once an overheat fault is triggered, all status bits in both the OLFREG register and the SLFREG register will be set, which will cause the ALERT pin to be asserted (pulled down) and all eight channel switches to be turned on (LEDs to be turned off) for cooling down the system. OVERHEAT STATUS BITS CLEARANCE The fault status bits set in the OLFREG register and the SLFREG register by an overheat fault can only be cleared by an ACMODE write command with all 1s in its data byte. If the IC temperature is below 160°C (nominal) when the ACMODE write command is updating the ACMREG regis- ter at the I2C STOP condition, the fault status bits will be cleared and the ALERT pin will be deasserted. Otherwise, the fault status bits will remain set, and the ALERT pin will remain asserted or be asserted again if previously deasserted. ALERT DEASSERTION The LT3967 deasserts the ALERT pin in either of the fol- lowing two situations: The LT3967 has successfully completed the ARA pro- cedure initiated by the master . Please note that the successfully completed ARA procedure does not clear fault status bits. It only deasserts the ALERT pin. 2) The LT3967 has received an ACMODE or SCMODE command which cleared the fault status bits, result - ing in the ALERT pin deassertion. PRINTED CIRCUIT BOARD LAYOUT When laying out the printed circuit board, the following checklist should be followed to ensure proper operation of the LT3967: 1. Connect the exposed pad of the package (Pin 29) di- rectly to a large ground plane to minimize thermal and electrical impedance.

Figure 14. RC Snubbers in Long Wire Application

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1. Keep the LED connection traces as short as possible.
2. Place power supply bypass capacitors as close as pos-

IC if a resistor is used to set LED dimming frequency.

1. Place the WDI capacitor as close as possible to the IC

if the watchdog function is used. maximum rating VIN – SRC ≥ –0.3V is met.

Rev 0 For more information www.analog.com TYPICAL APPLICATIONS Matrix LED Dimmer Powered by a Dual Buck Mode LED Driver with a Boost Pre-Regulator 1µF 5.7k GND 10k RT SW1 BOOST INTV CC INTVCCINTVCC FBH1-2SW2PWM1-3 CTRL1-2VREF CTRL3 47.5k 28k 22k 0.22µF L4 47µH F LT1-3SS3 SS1-2 10µF 50V 10µF 50V 1µF 50V 0.1µF 10µF

3967 TA02

2.2nF 499k 69.8k ISP1-2 EN/UVLO VIN ISN1-2 GATE3 SENSEP3 SENSEN3 GATE1SENSEP1SENSEN1ISP3 ISN3 L T3797 GATE2 SENSEP2 SENSEN2 TG1-2 0.25/uni03A9 0.25/uni03A9 0.05/uni03A90.05/uni03A9 M5M4 D3L3 11.3µH M2M1M3 TG2TG1 FBH2 44.2k1M FBH1 1M44.2k ISN2 LED2+ LED2– LED1+ LED1– D2D1 33µH 33µH 40.2k ISP2 ISN1 ISP1 0.01/uni03A9 FBH3 SYNC 10µF 50V 0.1µF 50V VIN 9V TO 30V 33µF 50V PIN NOT USED IN L T3797 CIRCUIT : TG3 D1, D2: DIODES DFLS260 D3: DIODES PDS760 D4, D5, D10, D11: CENTRAL SEMI CMPD6263S

2 IN 1 PACKAGE

D6, D7: NXP SEMI PMEG6010CEH D8, D9: NXP SEMI PMEG4010CEH L1, L2: WURTH ELECTRONICS 7447789133 L3: WURTH ELECTRONICS 7443551111 L4: COOPER BUSSMANN SD25-470-R M1, M2: VISHAY Si7308DN M3: INFINEON BSC097N06 M4, M5: VISHAY Si7309DN VC1-2 15k 22nF 1nF VC3 0.1µF 50V D5D4 INTVCC 0.1µF 16V 0.1µF 16V D11D10 SYNC 22µF 22µF VLED 26V SDAALERT5V SCL GND L T3967 CH1 ENH SCL SDA ALERT RTSYNC ADDR1 ADDR2 ADDR3 ADDR4 WDI DRN8 DRN7 SRC8 DRN6 SRC7 DRN5 SRC6 DRN4 SRC5 DRN3 SRC4 DRN2 SRC3 DRN1 SRC2 SRC1 V IN VDD 10k 10k 10k 1µF 10V 1µF 50V VLED 26V 1µF 50V1µF 28k SET PIN NOT USED IN L TC6900 CIRCUIT : DIV VIN GND 350kHz SYNC OUT L TC69000.1µF 10V 10nF 49.9k 191k 10nF 10µF 50V 60.4k GND L T3967 CH2 ENH SCL SDA ALERT RTSYNC ADDR1 ADDR2 ADDR3 ADDR4 WDI DRN8 DRN7 SRC8 DRN6 SRC7 DRN5 SRC6 DRN4 SRC5 DRN3 SRC4 DRN2 SRC3 DRN1 SRC2 SRC1 V INVDD BIAS = VOUT + INTVCC + 5V VOUT + 22k

Rev 0For more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. PACKAGE DESCRIPTION FE28 (EB) TSSOP REV L 0117 0.09 – 0.20 (.0035 – .0079) 0° – 8° 0.25 REF 0.50 – 0.75 (.020 – .030) 4.30 – 4.50* (.169 – .177) 1 3 4 5 6 7 8 9 10 11 12 13 14 19 20 22 21 15 16 18 17 9.60 – 9.80* (.378 – .386) 4.75 (.187) 2.74 (.108) 28 27 26 2524 23 1.20 (.047) MAX 0.05 – 0.15 (.002 – .006) 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 2RECOMMENDED SOLDER PAD LAYOUT EXPOSED PAD HEAT SINK ON BOTTOM OF PACKAGE0.45 ±0.05

0.65 BSC

4.50 ±0.10 6.60 ±0.10 1.05 ±0.10 4.75 (.187) 2.74 (.108) MILLIMETERS (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE SEE NOTE 4 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT 6.40 (.252) BSC 28-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663 Rev L) Exposed Pad Variation EB

Rev 0 For more information www.analog.com  ANALOG DEVICES, INC. 2020 www.analog.com RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS LT3965/LT3965-1 Eight-Switch Matrix LED Dimmer with Programmable 256:1 PWM Dimming and Fault Reporting Through I2C VDD: 2.7V to 5.5V, VIN: 8V to 60V, Eight Independent 17V/330mΩ NMOS Switches, 11-Bit Resolution Logarithmic State T ransition, TSSOP-28E Package LT3932 36V, 2A Synchronous Step-Down LED Driver V IN: 3.6V to 36V, 0V to 36V LED String Voltage, 128:1 Internal PWM Dimming, 5000:1 External PWM Dimming, 20:1 Analog Dimming, 4mm × 5mm QFN-28 Package LT3952 60V, 4A LED Driver with 4000:1 P WM Dimming with Spread Spectrum VIN: 3V to 42V, VOUT(MAX) = 60V, 4000:1 PWM, 20:1 Analog, ISD < 1µA, LT3964 Dual 36V, Synchronous 1.6A Buck LED Driver with I2C V IN: 4V to 36V, 8192:1 Internal PWM Dimming, 1000:1 External PWM Dimming, 10:1 External Analog Dimming, 5mm × 6mm QFN-36 Package LT3756/LT3756-1/ LT3756-2 High Side 100V, 1MHz LED Controller with 3000:1 PWM Dimming V IN: 6V to 100V, VOUT: 5V to 100V, 3000:1 PWM, 20:1 Analog, ISD < µA, 3mm × 3mm QFN-16 and MSOP-16E Packages Matrix LED Dimmer Powered by a Boost-Buck LED Driver IVINP L T3952A VIN VC IVINCOMP SYNC/SPRD TG TG ISN ISMON ISP ISN ISMON ISP PIN NOT USED IN L TC6900 CIRCUIT : DIV PIN NOT USED IN L T3952 CIRCUIT : DIM PWM CTRL VREF FB GNDEN/UVLO OVLO SS RT INTVCC INTVCC

3967 TA03

2.2µF 4.7µF 50V 0.1µF6.8nF 340k 60.4k 14.7k 365k 249k 64.9k 1.5k IVINN SW SW 22µH 10µF 25V VIN 6V TO 18V ILED DERATES AT VIN < 9V 1µF 25V SHORTLED OPENLED SHORTLED OPENLED 100k100k 350kHz SYNC 499k 76.8k L T3470 5V REGULATOR 0.33/uni03A9 750mA TG ISPISN LED+ LED– 22µF D2 D6

8 LEDs

1µF 50V SW 0.1µF 100V GND L T3967 RTSYNC350kHz SYNC (170Hz PWM) SDA SCL ALERT ADDR1 ENH D1, D6: DIODES DFLS260 D2, D3: NXP SEMI PMEG6010CEH D4, D5: CENTRAL SEMI CMSD6263S L1: WURTH 74437349220 22µH L2: WURTH 74408943330 33µH Q1: ZETEX FMMT591 M1: VISHAY Si7415DN VDD ADDR2 ADDR3 ADDR4 WDI BIAS 191k49.9k 10V DRN8 DRN7 SRC8 DRN6 SRC7 DRN5 SRC6 DRN4 SRC5 DRN3 SRC4 DRN2 SRC3 DRN1 SRC2 SRC1 V IN 10k 10k 10k100k100k100k100k100k SDA SCL ALERT 10µF 10V 33µH INTVCC L TC6900 OUT SET GND 0.1µF 10nF