Power Management

LT3966

Analog Devices

I2C Programmable Quad Monolithic Boost LED Driver

Manufacturer: Analog Devices

Document: 36 Pages / 2Mb

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LT3966 (Rev. 0)

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Manufacturer or author: Analog Devices, Inc.
PDF pages: 36

Technical content

Rev. 0For more information www.analog.com Document Feedback TYPICAL APPLICATION FEATURES DESCRIPTION I2C Programmable Quad Monolithic Boost LED Driver

APPLICATIONS

The LT®3966 is an I 2C programmable monolithic boost LED driver with four independent channels. Each chan - nel provides a 60V current mode boost converter with an internal 1.6A DMOS power switch, as well as inter - nal and external analog and PWM dimming features. I2C programmable features include a 13-bit (8192:1) digital PWM generator , 8-bit analog dimming DAC, and flexible fault reporting and handling. An onboard 8-bit ADC allows measurement of each channel’s output voltage and output current, as well as chip input voltage and two external measurements. In addition, independent shutdown and standby con - trol of each channel provides flexible solutions for multitopology applications. The LT3966 is available in a thermally enhanced 6mm × 6mm 40-Lead QFN package. n Four Independent DC/DC Channels n I2C Programmable n 8192:1 T rue Color PWM™ Dimming n 8-Bit Analog Dimming Pin Scaled by DAC n 11-Channel, 8-Bit ADC with 2 External Inputs n 1.6A, 60V Internal DMOS Switches n Input Voltage: 3V to 60V n Output Voltage and Current Monitoring to 60V n High Side PMOS Disconnect and PWM Switch Driver n Adjustable Frequency: 300kHz to 4MHz with Optional Frequency Synchronization n Thermally Enhanced 6mm × 6mm 40-Lead QFN Package n AEC-Q100 Qualification in Progress n Backlighting n Heads Up Displays All registered trademarks and trademarks are the property of their respective owners. 4.7/uni03BCF ISP1 ISN1 TG1 330mΩ 1/uni03BCF 68/uni03BCH VIN 44V TO 52V ISP2 ISN2 TG2 330mΩ 1/uni03BCF 68/uni03BCH ISP3 ISN3 TG3 330mΩ 1/uni03BCF 68/uni03BCH SW1 ISP4 ISN4 TG4 330mΩ 1/uni03BCF 68/uni03BCH SW2 SW3 SW4VIN EN/UVLO EXT1 GND ISP1–4 ISN1–4 FB1–4 TG1–4 EXT2 SDA SCL RT SYNC ADR1–2 INTV CCALERT CTRL/ PWM1–4 4.7/uni03BCF 97.6k 22.1k 150k 360kHz MUL TI- PHASE I2C BUS L T3966 1M/uni03A9 33k INTVCC

3966 TA01a

100W Buck Mode LED Driver with I2C Dimming Efficiency f SW = 360kHz V IN = 48V V OUT = 34V 0.0 0.5 1.0 1.5 2.0 2.5 3.0 100 EFFICIENCY (%)

3966 TA01b

LED CURRENT (A) (4 × 750mA/4 CH)

Rev. 0 For more information www.analog.com PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS (Note 1) VIN, EN/UVLO, SW1, SW2, SW3, SW4, ISP1, ISP2, ISP3, ISP4, ISN1, ISN2, ISN3, ISN4 ISP–ISN (Any Channel) TG1–4 FB1–4, EXT1–2, CTRL/PWM1–4, ADR1–2, ALERT, RT Operating Junction Temperature Range (Notes 4, 5) LT 3966E LT Storage Temperature Range 3940 38 37 36 35 34 33 32 31 11 2012 13 14 15 TOP VIEW GND QFN PACKAGE 40-LEAD (6mm × 6mm) PLASTIC QFN 16 17 18 19 ISP1 TG1 SW1 SW1 SW3 SW3 TG3 ISP3 ISN3 FB3 ISP2 TG2 SW2 SW2 SW4 SW4 TG4 ISP4 ISN4 FB4 ISN1 FB1 V IN INTVCC EN/UVLO EXT2 SYNC RT FB2 ISN2 CTRL/PWM1 CTRL/PWM2 CTRL/PWM3 CTRL/PWM4 EXT1 ADR1 ADR2 SDA SCL ALERT TJMAX = 150°C, θJA = 33°C/W EXPOSED PAD (PIN 41) IS GND AND MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LT3966EUJ#PBF LT3966EUJ#TRPBF LT3966UJ 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C LT3966JUJ#PBF LT3966JUJ#TRPBF LT3966UJ 40-Lead (6mm × 6mm) Plastic QFN –40°C to 150°C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Operating Range l 3 60 V VIN Quiescent Current CTRL/PWM = 0V, EN/UVLO = 1.3V 2.7 3.3 mA VIN Shutdown Current EN/UVLO = 0V EN/UVLO = 1.15V, CTRL/PWM = 0V 190 230 µA µA EN/UVLO Shutdown Threshold Falling l 1.20 1.23 1.26 V EN/UVLO Rising Hysteresis EN/UVLO Rising 15 mV EN/UVLO Input Low Voltage IVIN < 1μA 0.4 V ELECTRICAL CHARACTERISTICS The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V unless otherwise noted.

Rev. 0For more information www.analog.com

ELECTRICAL CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITS EN/UVLO Bias Current Low EN/UVLO = 1.15V 2 µA EN/UVLO Bias Current High EN/UVLO = 1.3V 10 100 nA LDO Regulator INTVCC Regulation Voltage IINTVCC = –1mA, Not Switching l 2.9 3 3.1 V INTVCC Line Regulation 3V ≤ VIN ≤ 60V 0.03 %/V INTVCC Load Regulation –20mA ≤ IINTVCC ≤ 0mA, Not Switching 0.04 %/mA INTVCC Undervoltage Lockout INTVCC Falling l 2.6 2.7 2.8 V INTVCC Undervoltage Lockout Hysteresis INTV CC Rising 75 mV INTVCC Current Limit VIN = 12V, INTVCC = 2.8V 36 mA INTVCC Dropout Voltage VIN = 3V, IINTVCC = –15mA 320 mV Analog-to-Digital Converter Converter Resolution 8 Bits Converter Full-Scale Voltage 1.266 1.275 1.284 V Converter LSB Size 4.95 5 5.05 mV Conversion Time (t CONV) Rt = 100kΩ, MPHASE = 0, AUTO = 0 20 µs EXT1, EXT2 Input Impedance VEXT1 = VEXT2 = 1V 10 100 MΩ EXT1, EXT2 Internal Voltage Clamp IEXT1 = IEXT2 = 100μA l 1.4 1.7 1.9 V EXT1, EXT2 Internal Voltage Clamp Impedance VEXT1 = VEXT2 = 2V to 5.5V 2.2 kΩ Channel 1–4 LED Current Sense Amplifiers ISP Common Mode Voltage Range l 3 55 V Full-Scale Current Sense Threshold (VISP–VISN) ISP = 55V, CTRL/PWM =1.5V, ADIM[7:0] = 0xFF ISP = 3V, CTRL/PWM = 1.5V, ADIM[7:0] = 0xFF l l 242 242 250 250 255 255 mV mV Externally Adjusted Half-Scale Threshold (VISP–VISN) ISP = 55V, CTRL/PWM = 0.7V, ADIM[7:0] = 0xFF ISP = 3V, CTRL/PWM = 0.7V, ADIM[7:0] = 0xFF l l 122 122 125 125 128 128 mV mV Externally Adjusted 1/10th Scale Threshold ISP–VISN) ISP = 55V, CTRL/PWM = 0.3V, ADIM[7:0] = 0xFF ISP = 3V, CTRL/PWM = 0.3V, ADIM[7:0] = 0xFF l l mV mV Internally Adjusted Half-Scale Threshold (VISP–VISN) ISP = 55V, CTRL/PWM = 1.5V, ADIM[7:0] = ISP = 3V, CTRL/PWM = 1.5V, ADIM[7:0] = 0x7F l l 121 121 125 125 129 129 mV mV Internally Adjusted 1/10th Scale Threshold (VISP–VISN) ISP = 55V, CTRL/PWM = 1.5V, ADIM[7:0] = 0x19 ISP = 3V, CTRL/PWM = 1.5V, ADIM[7:0] = 0x19 l l mV mV Over current Protection Threshold (VISP–VISN) ISP = 60V 370 mV C/10 Threshold ISP = 60V 14 22 30 mV ISP/ISN Input Bias Current (Combined) CTRL/PWM = 3V (Active), ISP = ISN = 55V CTRL/PWM = 0V (Standby), ISP = ISN = 55V 440 µA µA P WM Threshold CTRL/PWM Falling l 90 103 115 mV The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V unless otherwise noted.

Rev. 0 For more information www.analog.com PARAMETER CONDITIONS MIN TYP MAX UNITS ISP Voltage Regulation Threshold 62 V Channel 1–4 Voltage Feedback Amplifiers FB Regulation Threshold (VFB) CTRL/PWM = 2V l 1.188 1.170 1.200 1.200 1.208 1.218 V V FB Over voltage Threshold VFB + 50mV VFB + 60mV VFB + 70mV V FB Open LED Threshold VFB – 40mV VFB – 50mV VFB – 60mV V FB Shorted LED Threshold l 280 300 320 mV FB Input Bias Current Current Out of Pin, FB = 1V 10 100 nA FB Line Regulation 3.3V ≤ VIN ≤ 60V 0.0004 %/V Oscillator RT Pin Voltage 1.0 V Switching Frequency in Single-Phase Mode R T = 261kΩ RT = 100kΩ RT = 47.5kΩ l l l 370 0.93 1.85 400 1.00 2.00 430 1.07 2.15 kHz MHz MHz Switching Frequency in Multiphase Mode R T = 174kΩ RT = 47.5kΩ RT = 21kΩ l l l 279 0.93 1.85 300 1.00 2.00 321 1.07 2.15 kHz MHz MHz Minimum Off T ime 30 50 65 ns Minimum On Time 35 60 75 ns SYNC Input High (SYNC In Mode) SYNCOUT = 0 1.5 V SYNC Input Low (SYNC In Mode) SYNCOUT = 0 0.4 V SYNC Input Duty Cycle 10 90 % SYNC Resistance to GND (SYNC In Mode) SYNCOUT = 0 95 kΩ SYNC Output Mode Duty Cycle SYNCOUT = 1 45 55 65 % SYNC Output Voltage High (SYNC Out Mode) SYNCOUT = 1, Load = 3kΩ l 2.4 V SYNC Output Voltage Low (SYNC Out Mode) SYNCOUT = 1, Load = 3kΩ l 0.4 V Channel 1–4 Power Switch SW On-Resistance ISW = 200mA 200 mΩ SW Current Limit l 1.6 2 2.4 A SW Leakage Current VSW = 62V 3 μA External PMOS Gate Driver TG ON Voltage (V ISP–VTG) ISP = 24V 7.4 8.2 9 V TG OFF Voltage (VISP–VTG) ISP = 24V 0 0.3 V TG Turn-On Time CLOAD = 470pF, ISP = 24V 50 ns TG Turn-Off Time CLOAD = 470pF, ISP = 24V 60 ns I2C Port I2C Address Programmed by ADR2, ADR1 Pins 101XXXX[R/W] ADR1, ADR2 Input High Voltage l 0.9 • VINTVCC V ADR1, ADR2 Input Low Voltage l 0.1 • VINTVCC V ADR1, ADR2 Pull-Down Current in HIGH State V ADR1, VADR2 = 3V, Current Into Pin l 9 13 17 µA ADR1, ADR2 Pull-Up Current in LOW State V ADR1, VADR2 = 0V, Current Out of Pin l 9 13 17 µA SDA, SCL Input High Voltage l 1.5 V SDA ,SCL Input Low Voltage l 0.4 V The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V unless otherwise noted.

Rev. 0For more information www.analog.com PARAMETER CONDITIONS MIN TYP MAX UNITS SDA, SCL Input Low Leakage Current Out of Pin, SDA = SCL = 0V 50 nA SDA, SCL Input High Leakage Current Into Pin, SDA = SCL = 3V 50 nA SDA Output Low Voltage ISDA = 3mA 0.4 V ALERT Output Low Voltage IALERT = 3mA 0.4 V I2C Clock Operating Frequency 400 kHz Bus Free Time Between Stop and Start Condition (tBUF) 1.3 µs Hold Time After Repeated Start Condition (tHD_SDA) 0.6 µs Repeated Start Condition Set-Up Time (tSU_STA) 0.6 µs Stop Condition Set-Up Time (tSU_STO) 0.6 µs Data Hold Time Output (tHD_DAT(O)) 0 900 ns Data Hold Time Input (tHD_DAT(I)) 0 ns Data Set-Up Time (tSU_DAT) 100 ns SCL Clock Low Period (tLOW) 1.3 µs SCL Clock High Period (tHIGH) 0.6 µs Clock/Data Fall Time CB = Capacitance of One Bus Line (pF) 20 + 0.1CB 300 ns Clock/Data Rise Time CB = Capacitance of One Bus Line (pF) 20 + 0.1CB 300 ns Input Spike Suppression Pulse Width (tSP) 50 ns Watchdog Timeout Period WDTEN = 1 75 100 125 ms The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V unless otherwise noted. Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Do not apply a positive or negative voltage source to TG pins, otherwise permanent damage may occur . Note 3: Do not apply a positive or negative voltage source to INTV CC pin, otherwise permanent damage may occur . IINTVCC = 2mA is the maximum external load that can be applied. Note 4: The LT3966E is guaranteed to meet performance specifications from the 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3966J is guaranteed to meet performance specifications over the full –40°C to 150°C operating junction temperature range. High junction temperatures degrade operating lifetimes. Operating lifetime is derated at junction temperatures greater than 125°C. Note 5: The LT3966 includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed the maximum operating junction temperature when overtemperature is active. Continuous operating above the specified maximum operating junction temperature may impair device reliability. Note 6: Guaranteed by a combination of design, testing, and characterization over the operating temperature range, and automated testing at ambient temperature. tSP tBUF tSU,STO tSP tHD,STA START CONDITION STOP CONDITION tSU,STA tHD,DATI tHD,DATO REPEATED START CONDITION REPEATED START CONDITION tSU,DAT SDA SCL tHD,STA 3966 TD

Rev. 0 For more information www.analog.com TA = 25°C, unless otherwise noted. Shutdown and Standby Current vs Input Voltage Shutdown and Standby Current vs Temperature EN/UVLO Thresholds vs Temperature EN/UVLO Hysteresis Current vs Temperature Quiescent Current vs Input Voltage INTV CC Voltage vs Input Voltage INTVCC Voltage vs Temperature INTVCC Current Limit vs Temperature INTVCC Dropout vs Temperature SHUTDOWN STANDBY EN/UVLO = 0V EN/UVLO = 1.15V V IN (V) 100 150 200 250 V IN CURRENT (µA) vs Input Voltage

3966 G01

EN/UVLO = 2V , CTRL/PWM1 –4 = 0V , FB1-4 = 1.3V VIN (V) 2.2 2.4 2.6 2.8 3.0 3.2 3.4 VIN IQ (mA)

3966 G05

IINTVCC = –15mA VIN (V) 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 INTVCC (V) INTVcc Voltage vs Input Voltage

3966 G06

EN/UVLO = 0V EN/UVLO = 1.15V TEMPERATURE (°C) –50 –25 100 125 150 100 150 200 250 V IN CURRENT (µA) vs Temperature

3966 G02

TEMPERATURE (°C) –50 –25 100 125 150 1.20 1.22 1.24 1.26 1.28 1.30 V EN/UVLO (V) vs Temperature

3966 G03

EN/UVLO = 1.15V TEMPERATURE (°C) –50 –25 100 125 150 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 I EN/UVLO (µA)

3966 G04

TEMPERATURE (°C) –50 –25 100 125 150 2.90 2.92 2.94 2.96 2.98 3.00 3.02 3.04 3.06 3.08 3.10 INTV CC (V) vs Temperature

3966 G07

V IN = 12V INTV CC = 2.8V TEMPERATURE (°C) –50 –25 100 125 150 I INTVCC (mA)

3966 G08

I INTV CC = –15mA TEMPERATURE (°C) –50 –25 100 125 150 100 200 300 400 500 600 INTV CC DROPOUT (mV)

3966 G09

TYPICAL PERFORMANCE CHARACTERISTICS

Rev. 0For more information www.analog.com TA = 25°C, unless otherwise noted. INTVCC Dropout vs Temperature Load Switching Frequency vs RT Switching Frequency vs Temperature VFB vs Temperature ISP Voltage Limit vs Temperature V ISP–ISN vs Temperature VISP–ISN vs VISP VISP–ISN Threshold vs Temperature Overcurrent Protection VISP–ISN vs ADIM VCTRL/PWM I INTV CC (mA) 100 150 200 250 300 350 400 INTV CC DROPOUT (mV) vs Load

3966 G10

R T (kΩ) 100 0.1 SWITCHING FREQUENCY (MHz) vs R T

3966 G11

R T = 100k TEMPERATURE (°C) –50 –25 100 125 150 900 920 940 960 980 1000 1020 1040 1060 SWITCHING FREQUENCY (kHz) vs Temperature

3966 G12

TEMPERATURE (°C) –50 –25 100 125 150 1.16 1.17 1.18 1.19 1.20 1.21 1.22 1.23 1.24 V FB (V) FB

3966 G13

TEMPERATURE (°C) –50 –25 100 125 150 ISP VOL TAGE LIMIT (V)

3966 G14

ISP = 48V TEMPERATURE (°C) –50 –25 100 125 150 240 242 244 246 248 250 252 254 256 258 260 V ISP–ISN (mV) ISP–ISN

3966 G15

V ISP (V) 246 247 248 249 250 251 252 253 254 V ISP–ISN (mV) ISP–ISN ISP

3966 G16

ISP = 48V TEMPERATURE (°C) –50 –25 100 125 150 350 355 360 365 370 375 380 385 390 V ISP–ISN OCP (mV) Threshold vs Temperature

3966 G17

ISP = 48V V CTRL/PWM (V) 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 2.0 100 125 150 175 200 225 250 275 V ISP–ISN (mV) ISP–ISN CTRL/PWM

3966 G18

TYPICAL PERFORMANCE CHARACTERISTICS

Rev. 0 For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICSTA = 25°C, unless otherwise noted. VISP–ISN vs ADIM VFB VISP–ISN vs VFB ILED Measured Code vs VISP–ISN FB Measured Code vs VFB Switch On-Resistance vs Temperature Switch Current Limit vs Temperature Switch Current Limit vs Duty Cycle TG Rise/Fall Time vs C LOAD Minimum On/Off Time vs Temperature ISP = 48V ADIM CODE 128 160 192 224 256 100 125 150 175 200 225 250 V ISP–ISN (mV) ISP–ISN

3966 G19

ISP = 48V V FB (V) 1.10 1.12 1.14 1.16 1.18 1.20 1.22 100 125 150 175 200 225 250 275 V ISP–ISN (mV) ISP–ISN FB

3966 G20

ISP = 48V V ISP–ISN (mV) 128 160 192 224 256 288 320 128 160 192 224 256 I LED MEASURED CODE ISP–ISN

3966 G21

V FB (V) 0.255 0.510 0.765 1.020 1.275 128 160 192 224 256 FB MEASURED CODE FB Measured Code vs V FB

3966 G22

TEMPERATURE (°C) –50 –25 100 125 150 100 150 200 250 300 350 400 SWITCH ON–RESISTANCE (mΩ) vs Temperature

3966 G23

TEMPERATURE (°C) –50 –25 100 125 150 1.7 1.8 1.9 2.0 2.1 2.2 2.3 SWITCH CURRENT LIMIT (A) vs Temperature

3966 G24

DUTY CYCLE (%) 100 1.7 1.8 1.9 2.0 2.1 2.2 2.3 SWITCH CURRENT LIMIT (A) vs Duty Cycle

3966 G25

ISP = 24V RISE FALL C LOAD (pF) 200 400 600 800 1000 100 120 140 TG RISE/FALL TIME (ns) LOAD

3966 G26

TEMPERATURE (°C) –50 –25 100 125 150 MINIMUM ON/OFF TIME (ns)

3966 G27

Rev. 0For more information www.analog.com PIN FUNCTIONS FB1, FB2, FB3, FB4 (Pins 39, 32, 10, 21): Voltage Feedback Pin. The FB pin is used for output voltage regu- lation and limiting. Tie to a resistor divider from the output voltage. When FB reaches 1.2V, the switch current will reduce in order to maintain the output voltage at this level. If ISP/ISN senses less than 10% of full output current when FB reaches regulation, an OPENLED condition will be flagged for that channel. If FB is driven above 1.26V, the external PMOS will be switched off and an OVFB con- dition will be flagged. If FB remains below 0.3V after the internal soft start has completed, a SHOR TLED condition will be flagged. See the Applications Information section for more information on faults and fault handling. ISP1, ISP2, ISP3, ISP4 (Pins 1, 30, 8, 23): Positive Terminal of the LED Current Sense Amplifier . Also serves as the positive supply of the TG gate driver . Connect to positive side of LED current sense resistor and minimize resistance in this path. ISN1, ISN2, ISN3, ISN4 (Pins 40, 31, 9, 22): Negative Terminal of the LED Current Sense Amplifier . Kelvin con- nects to negative side of LED current sense resistor . T G1, TG2, TG3, TG4 (Pins 2, 29, 7, 24): Top Gate Driver Output. Connect to gate of external PMOS pass transistor . TG is an inverted and level-shifted version of the PWM dimming signal, and drives between VISP (OFF) and VISP– 8.2V (ON) for LED PWM dimming as well as fault mode disconnect. Leave unconnected if not used. Power DMOS Drain. Connect to switching end of the inductor . Minimize copper area to increase efficiency and reduce EMI. CTRL/PWM1, CTRL/PWM2, CTRL/PWM3, CTRL/PWM4 (Pins 11, 12, 13, 14): Combination Analog/PWM Dimming Input. Drive from below 100mV to above 1.5V for full- scale PWM dimming. Or drive with an analog voltage from 0.2V to 1.2V for 0% to 100% analog dimming. Do not leave these pins floating, tie to INTVCC if unused. EXT1, EXT2 (Pins 15, 35): External Input to ADC. The working range of the EXT input is 0V (Code 0) to 1.275V (Code 255). These pins are internally clamped to 1.7V. Tie to GND if unused. ADR1, ADR2, (Pins 16, 17): I 2C Address Select. These pins are configured as three-state inputs (HIGH, LOW , FLOAT). See Table 1 for address selection. ALERT (Pin 20): Chip Status Reporting Pin. Depending on channel configuration, the ALERT pin can be pulled low due to any of the following faults: FB Overvoltage, Open LED, Shorted LED, and LED Overcurrent. See the Applications Information section for more information on faults and fault handling. SDA (Pin 18): Serial Data Line for I 2C Communications. Combination input and open-drain output. SCL (Pin 19): Serial Clock for I 2C Communications. SYNC (Pin 34): Oscillator Synchronization Pin. By default, this pin acts as an input for an external clock to define the switching frequency of the LT3966. By setting the SYNCOUT configuration bit, the input function is disabled and instead SYNC becomes a clock output for driving other external circuits. RT (Pin 33): Timing Resistor Set Pin. Set the master clock frequency using a resistor to GND. Do not leave the RT pin open. EN/UVLO (Pin 36) : Enable/Undervoltage Lockout Pin. This pin is used for general ON/OFF control and to enable the LT3966 at a specific input voltage. Drive with a logic level greater than 1.5V for simple ON/OFF control, or tie to a resistor divider of input voltage for precision shutdown threshold. This pin has a falling threshold of 1.23V, rising hysteresis of roughly 15mV, and a 2µA hysteresis current when below threshold. Tie this pin to VIN if unused. INTVCC (Pin 37): Internal 3V LDO Output. This pin is the LDO output and power supply for all internal circuitry. Place a 4.7μF filter capacitor to GND as close to this pin as possible. Do not drive this pin externally. Users may apply a load of up to 2mA to this pin. V IN (Pin 38): Input Voltage Supply. This pin is the power supply input to the LDO and the rest of the internal cir - cuitry. It must be locally bypassed with a capacitor to GND as close to the pin as possible.

Rev. 0 For more information www.analog.com BLOCK DIAGRAM CHANNEL DUPLICATED 4 TIMES PWM1 ISP1 –8.2V ISP1 FAUL T1 PWINT1 DIMMING GENERATOR SEL1[2:0] DIM1[12:0] ADIM1[7:0] DIMEN1 BAM1 PWEXT1 TG1 IREF IOUT DAC8 CTRL/ PWM1 ISN1 ISP1 FB1 SW1 SLOPE COMP LATOFFSOFT- START DATA R/W ADC MUX ADC8EXT2 EXT1 EXT2 EXT1 INTVCC BANDGAP OSCILLATOR VIN MCLK RT SYNC CLK1–4 I2C INTERFACE AND GLOBAL LOGIC RT VIN FB1–4 VLED1–4 VLED1 CURRENT SENSOR SHORT1 TSD VCCUV 1.7V 1.6A 1.2V –0.1V ++– 50mV 1.2V RQ S PWM1 CLK1 FB1 1.15V FB1 1.26V FB1 0.3V VLED1 1.5V VLED1 0.1V CHANNEL LOGIC & FAULT HANDLING VC1 OVFB1 OPENLED1 LEDOC1 RUN1 SSDONE1 FAUL T1 SS1 1.08V VCCUV ENUV 1.2V EN/UVLO FAUL T1–4 ADR1 ADR2 SCL SDA ACK/SDA0 ALERT SCL SDA ALERT INTVCC 3966 BD RISP

Rev. 0For more information www.analog.com OPERATION OVERVIEW The LT3966 is a 4-channel monolithic boost LED driver with I2C programmability and onboard ADC. The 4 inde- pendent LED driver channels each consist of a 1.6A monolithic boost converter with high side LED current sensing and high side gate driver for PWM dimming and fault protection. The analog LED current setpoint can be controlled externally and also programmed through I 2C. The LED dimming can be controlled with an external PWM signal or through I2C using the internal PWM generator . Additionally, the LT3966 contains an 11-input, 8-bit ADC used to measure regulation parameters of each of the LED driver channels as well as input voltage, die temperature, and two external inputs. LT3966 operates from input voltages of 3V to 60V. The 1.23V EN threshold allows programmable external UVLO using a resistor divider from the input voltage. All inter - nal circuitry is powered from an onboard LDO regulator supplying 3V at the INTVCC pin. Although the internal cir- cuitry operates at 3V, all I/O pins are 5V tolerant. The LDO is current limited to 36mA and should not be externally loaded, and the device provides an internal UVLO to pre- vent switching when INTVCC falls below 2.7V. Bypass and filtering of the LDO require a capacitor of at least 4.7μF from INTV CC to GND located close to the pins. The boost converters are internally compensated current mode converters with a 1.6A power FET each. The boost converters can operate from 300Hz to 4MHz, and switch- ing can be synchronized to an external clock. Through I2C, the LT3966 allows the options of multiphase switching for lower input ripple as well as clock sync output. The LED drivers use high side current sensing with a 250mV threshold. This analog threshold is externally adjustable by using the CTRL/PWM pin, and is also inter- nally programmable through I2C. A high side gate driver for an external PMOS transistor allows accurate PWM dimming, fast fault protection, and output disconnect. PWM dimming can be controlled externally by toggling CTRL/PWM, or internally programmed using the LT3966 onboard PWM generator . This PWM generator offers res- olution from 6-bit (64:1) to 13-bit (8192:1), as well as the choice between standard PWM modulation and optional BAM (Bit Angle Modulation) control. The LED drivers have detection and protection from overvoltage, overcurrent, open LED, and shorted LED conditions. Fault handling is autonomous, with optional readback, fault reporting, and latchoff functions using I2C. The device I2C address is programmable to one of eight different addresses or standalone mode using the two tri- mode ADR pins. Reliable and robust I2C communication is ensured by use of CRC error checking and an optional watchdog timer . I 2C OPERATION I2C T ransactions and Error Correction Operation I2C communication revolves around read and write trans- actions. In LT3966, Packet Error Checking (PEC) is used to guarantee reliable communication between the host system and the device. This consists of a trailing byte on both the read and write transactions that offers a CRC check of all bytes since the last start. The CRC polyno - mial used in LT3966 is identical to that used in SMBus: X8 + X2 + X1 + 1. The structure of an I 2C write is shown in Figure 1. Data being written to LT3966 must follow this format. The PEC code (Figure 2) should be computed by the host system using the CRC formula on the Chip Address, Sub Address, and Data Bytes. If a valid PEC is received, the LT3966 will acknowledge (ACK) on the 9th clock of the PEC transfer , and the data will be transferred to the LT3966 register . If an invalid PEC is received, the LT3966 will not ACK, and the data will be discarded.

Figure 1. I2C Write T ransaction with PEC Figure 2. Example Linduino® Code for Calculating CRC-8 PEC

3966 F01

simultaneously upon execution of the stop signal.

Figure 3. I2C Read T ransaction with PEC Table 1. I2C Address Settings

3966 F03

will start up and immediately begin soft-start switching. latched, but are indicated on the ALERT line.

LED current, ILED, Equation 1. block diagram is shown in Figure 4. current sense threshold over the range of 0.2V to 1.2V. Figure 4. Figure 5.

3966 F04

3966 F05

sense threshold is given by Equation 2. WM voltage is shown in Figure 5. ADIM-adjusted threshold can be computed by Equation 3. be too tiny for the amplifier to accurately regulate.

Figure 6. Figure 7.

3966 F06

3966 F07

reporting is enabled by the channel’s OC_EN bit. CTRL/PWM pin or ADIM register . logical representation is shown in Figure 7.

Rev. 0 For more information www.analog.com Figure 8. Figure 9. COUNTER DIM[12:0] VARIABLE LENGTH (6–13 BITS) COMPARE SCL[2:0] BAM

3966 F09

3966 F10

Figure 10.

3966 F08

It is important to note that both the DIMEN signal and the CTRL/PWM pin have the ability to clear the dimming generator’s counter . This is advantageous when using a combination of internal dimming and external ON/OFF control with CTRL/PWM. By restarting the dimming gen- erator’s counter in sync with the external ON/OFF signal, light output remains flicker free from full duty cycle to zero. The CTRL/PWM threshold for PWM dimming is 0.1V. For simple on/off control, the PWM pin can be driven with any standard logic signal between 1.5V and 5V. For dimming with analog control, drive the pin with a DAC providing output shutdown, or simply shunt a resistor divider using a small NMOS transistor (Figure 8). The internal dimming generator is based on a vari - able-length counter updated at the master clock rate, deter- mined by RT. An overview of the logic is shown in Figure 9. The scale (SCL[2:0]) bits set the compare length and cycle length of the dimming generator , from 6-bit at SCL = 000b, to 13-bit at SCL = 111b. This cycle length determines the dimming resolution, and also the dimming frequency based on the MCLK value set by R T, Equation 4. fDIM = fSW 2(6+SCL) (4) For example, a 13-bit dimming cycle using SCL = 111b would provide 8192:1 resolution at a dimming frequency of 244Hz using a 2MHz MCLK frequency (R T = 47.5k). The DIM[ 12:0] and BAM registers control the duty cycle and modulation strategy of the dimming genera- tor . In PWM (Pulse-Width Modulation) dimming mode (BAM = 0), the PWMOUT signal is high while the value in the DIM register is greater than the Counter . In BAM (Bit-Angle Modulation) mode, the PWMOUT signal is high anytime the MSB of the Counter matches the position of a 1 in the value in the DIM register . A comparison of the resulting waveforms of each of these strategies is shown in Figure 10. For a DIM value of 13, PWM mode provides a single pulse of 13 clock cycles starting at the 1st counter cycle. BAM mode provides pulses of duration 1, 4, and 8 cycles at the 1st, 4th, and 8th counter cycle, respectively. The total pulse duration in BAM mode still equals 13-clock cycles. The duty cycle of the dimming generator can be com- puted using Equation 5. Duty = DIM 2(6+SCL) (5) The system should be aware of the counter scale as defined by SCL, and avoid writing DIM values larger than the maximum value of counter . In the case where a DIM value is larger than the counter range, the DIM value will be truncated below bit (6+SCL). A DIM value of 0 0000 0000 0001 would be interpreted as 0 in all cases except SCL = 111b.

Figure 11. I2C Broadcast Write

3966 F12

3966 F11

value may not be synchronized to the other channels. device clears the counter and loads the latest DIM code. voltage limit can be set (see Figure 12). process and temperature variation. state of the faulted channel’s LATOFF bit. device’s ALERT pin will also assert if OVFB_EN is set. while regulating FB to 1.2V.

3966 F13

3966 F14

for generating programmable external UVLO. amount of current when driven to a voltage greater than 6V. pin to a resistor divider between VIN and GND (Figure 13). due to the 2µA hysteresis current source, Equation 7. A common choice is 487k for roughly 1V total hysteresis. and the 1.23V EN falling threshold, Equation 8. The UVLO rising threshold will therefore be given by Equation 9. internal clocks and the switching clocks are derived. Table 2. Single-Phase Switching Frequency vs RT Value frequency using Table 2 or Table 3.

3966 F15

Table 3. Multi-Phase Switching Frequency vs RT Value frequency of roughly 7.5MHz. details on this setting are available in the ADC section.

Rev. 0 For more information www.analog.com CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4 IN PHASE DIMMING (INPH = 1) OUT OF PHASE DIMMING (INPH = 0)1/4 DIMMING CYCLE

3966 F16

Figure 16. APPLICATIONS INFORMATION IN PHASE/OUT OF PHASE DIMMING To reduce input ripple current, each channel’s dimming operation can be independently programmed in one of the two modes: in-phase mode and out-of-phase mode (see Figure 16). When operating in in-phase mode, the start of CH2/CH3/CH4’ s dimming cycle is aligned with CH1’s. When operating in out-of-phase mode, the start of CH2/CH3/CH4’s dimming cycle is behind of CH1’s by a quarter/a half/three quarters of CH2/CH3/CH4’s dimming cycle. To enable the in-phase/out-of-phase operation, set the INPH register bit to 1/0. Please note that after the INPH bit change, an I2C broadcast write (see Figure 11) is required to reset all dimming generators for this function to work properly. POWER COMPONENT SELECTION Since the LT3966 is an internally-compensated converter , the external power components are selected to ensure system stability. By following a few simple guidelines, this process can be made simple and streamlined. Inductor Selection Inductor selection consists of two parameters: saturation current rating, and inductance value. Higher switching frequency allows the use of smaller inductance value at the expense of increased switching loss. The saturation current rating of the inductor should be selected appropriately for the 2.4A current limit of the LT3966. An approximation for maximum inductor cur - rent (efficiency = 100%) is based on the maximum LED current and the input-output ratio, Equation 10. IL = VOUT VIN

ILED (10) The desired inductance is determined by the steady-state current ripple. A typical rule of thumb is to set the inductor current ripple to a maximum of 20% of the maximum induc- tor current, Equation 11, Equation 12 and Equation 13. Boost LBOOST ≥ VIN(MIN) •(VOUT(MAX) – VIN(MIN) ) VOUT(MAX) • 0.45A • fSW (11) Buck LBUCK ≥ VOUT(MAX) •(VIN(MIN) – VOUT(MAX) ) VIN(MIN) • 0.45A • fSW (12)

able 4 provides some recommended inductor vendors. Table 4. Inductor Manufacturers low currents, and lowest at the maximum drive current. LED, where n is the number of LEDs in the strand. frequency of the output pole > 2kHz, Equation 14. In most cases, a 2.2µF output capacitor is a suitable choice. voltage will be driven to the limit defined by the FB divider . ance when no faults are detected in standalone mode. waits for a 7168-cycle cooldown period. OFF bit, or by clearing the LATOFF bit itself. cup” mode (see Figure 17 and Figure 18).

Figure 19. I2C Broadcast Alert Response

3966 F19

1 NACK

If the LT3966 fails arbitration, it will stop and wait for

timer is enabled through the WDTEN bit in register 0x00. required to reset the watchdog timer . bit (WDTFLAG) will be set in register 0x00. encoded values 03, 96 and 60, respectively. Figure 17. Scope Shot – HICCUP Figure 18. Scope Shot – LATOFF

3966 F17

3966 F18

Figure 20. Scope Shot – LATOFF

3966 F18SCL

enabled targets at any given time. appropriate timing is shown in Figure 21. for an I2C Stop to begin the next round of conversions. and ILED measurements for that channel will be skipped. pauses in the ADC converter’s measurement sequence.

Rev. 0 For more information www.analog.com APPLICATIONS INFORMATION When switching from manual to automatic mode, con - version will start from the target specified by TGT[3:0]. ADC Target 0 – VIN/48 The first target (TGT = 000) is a 1/48th scaled version of the chip input voltage, suitable for monitoring input voltage or battery state. The resolution of 5mV/LSB and 48× scale results in a resolution at the input of roughly 240mV/LSB. Input range for V IN is 3V to 60V, resulting in a code range of roughly 12 to 250 decimal. To determine the input voltage from the conversion data, use Equation 15. ADC T argets 2–3 – External Inputs LT3966 provides two external analog inputs to the ADC, on EXT1 and EXT2. The working range of these inputs are 0V to 1.275V, and the conversion resolution is 5mV/LSB. The EXT1 and EXT2 inputs are internally clamped to 1.7V with a 2k series resistance, but the pins are rated up to 5.5V ABSMAX. If the clamp voltage of 1.7V is exceeded, the EXT1 and EXT2 inputs will draw current but no dam- age will occur . For any voltage above 1.275V , the ADC conversion will read full scale, 0xF F. ADC Targets 4–11 – LED Driver Parameters The final 8 targets are FB voltage, and LED current for each of the 4 channels in turn. The FB measurement is a direct representation of the voltage at the FB pin, and the LED current measurement is a 4× multiplied version of the sense voltage between ISP and ISN. ADC Clock Selection The ADC clock is derived from the system master clock, MCLK, programmed by RT. For best results, an ADC clock between 1μs and 2μs is recommended. Scaling down of MCLK to ADC clock is accomplished through the use of the CLKSEL[1:0] bits. CLKSEL[1:0] ADC CLOCK

00 MCLK

01 MCLK/2

10 MCLK/4

11 MCLK/8

Rev. 0For more information www.analog.com REGISTER TABLE ADDR NAME DESCRIPTION b7 b6 b5 b4 b3 b2 b1 b0 Global Registers 0x00 GLBCFG Global Config WDTFLAG WDTEN MPHASE CLKOUT OFF4 OFF3 OFF2 OFF1 Channel 1 0x10 STAT1 Status/Status CFG OC_EN 1 SHORT_EN1 OPEN_EN1 OVFB_EN1 OC1 SHORT1 OPEN1 OVFB1 0x11 CFG1 Channel 1 Config x x x x INPH1 FLAT1 BAM1 DIMEN1 0x12 DIM1H PWM Dim Value CH1 SCL12 SCL11 SCL10 DIM14 DIM13 DIM12 DIM11 DIM10 0x13 DIM1L PWM Dim Value CH1 DIM112 DIM111 DIM110 DIM19 DIM18 DIM17 DIM16 DIM15 0x14 ADIM1 Analog Dimming CH1 ADIM17 ADIM16 ADIM15 ADIM14 ADIM13 ADIM12 ADIM11 ADIM10 Channel 2 0x20 STAT2 Status/Status CFG OC_EN 2 SHORT_EN2 OPEN_ EN2 OVFB_EN2 OC2 SHORT2 OPEN2 OVFB2 0x21 CFG2 Channel 2 Config x x x x INPH2 FLAT2 BAM2 DIMEN2 0x22 DIM2H PWM Dim Value CH2 SCL22 SCL21 SCL20 DIM24 DIM23 DIM22 DIM21 DIM20 0x23 DIM2L PWM Dim Value CH2 DIM212 DIM211 DIM210 DIM29 DIM28 DIM27 DIM26 DIM25 0x24 ADIM2 Analog Dimming CH2 ADIM27 ADIM26 ADIM25 ADIM24 ADIM23 ADIM22 ADIM21 ADIM20 Channel 3 0x30 STAT3 Status/Status CFG OC_EN3 SHORT_EN3 OPEN_EN3 OVFB_EN3 OC3 SHORT3 OPEN3 OVFB3 0x31 CFG3 Channel 3 Config x x x x INPH3 FLAT3 BAM3 DIMEN3 0x32 DIM3H PWM Dim Value CH3 SCL32 SCL31 SCL30 DIM34 DIM33 DIM32 DIM31 DIM30 0x33 DIM3L PWM Dim Value CH3 DIM312 DIM311 DIM310 DIM39 DIM38 DIM37 DIM36 DIM35 0x34 ADIM3 Analog Dimming CH3 ADIM37 ADIM36 ADIM35 ADIM34 ADIM33 ADIM32 ADIM31 ADIM30 Channel 4 0x40 STAT4 Status/Status CFG OC_EN4 SHORT_EN4 OPEN_EN4 OVFB_EN4 OC4 SHORT4 OPEN4 OVFB4 0x41 CFG4 Channel 4 Config x x x x INPH4 FLAT4 BAM4 DIMEN4 0x42 DIM4H PWM Dim Value CH4 SCL42 SCL41 SCL40 DI M44 DIM43 DIM42 DIM41 DIM40 0x43 DIM4L PWM Dim Value CH4 DIM412 DIM411 DIM410 DIM49 DIM48 DIM47 DIM46 DIM45 0x44 ADIM4 Analog Dimming CH4 ADIM47 ADIM46 ADIM45 ADIM44 ADIM43 ADIM42 ADIM41 ADIM40 Analog-to-Digital Converter 0x50 ADCCFG ADC Config RUN AUTO CLKSEL1 CLKSEL0 TGT3 TGT2 TGT1 TGT0 0x51 VIN Scaled Input Voltage VIN7 VIN6 VIN5 VIN4 VIN3 VIN2 VIN1 VIN0 0x53 EXT1 External Voltage 1 EXT17 EXT16 EXT15 EXT14 EXT13 EXT12 EXT11 EXT10 0x54 EXT2 External Voltage 2 EXT27 EXT26 EXT25 EXT24 EXT23 EXT22 EXT21 EXT20 0x55 VFB1 Ch 1 FB Voltage VFB17 VFB16 VFB15 VFB14 VFB13 VFB12 VFB11 VFB10 0x56 ILED1 Ch 1 LED Current ILED17 ILED16 ILED15 ILED14 ILED13 ILED12 ILED11 ILED10 0x57 VFB2 Ch 2 FB Voltage VFB27 VFB26 VFB25 VFB24 VFB23 VFB22 VFB21 VFB20 0x58 ILED2 Ch 2 LED Current ILED27 ILED26 ILED25 ILED24 ILED23 ILED22 ILED21 ILED20 0x59 VFB3 Ch 3 FB Voltage VFB37 VFB36 VFB35 VFB34 VFB33 VFB32 VFB31 VFB30 0x5A ILED3 Ch 3 LED Current ILED37 ILED36 ILED35 ILED34 ILED33 ILED32 ILED31 ILED30 0x5B VFB4 Ch 4 FB Voltage VFB47 VFB46 VFB45 VFB44 VFB43 VFB42 VFB41 VFB40 0x5C ILED4 Ch 4 LED Current ILED47 ILED46 ILED45 ILED44 ILED43 ILED42 ILED41 ILED40

Rev. 0 For more information www.analog.com ADDR NAME DESCRIPTION b7 b6 b5 b4 b3 b2 b1 b0 Part ID (BCD Encoded, “03 96 60”) 0xFD ID0 Part ID High 0 0 0 0 0 0 1 1 0xFE ID1 Part ID Mid 1 0 0 1 0 1 1 0 0xFF ID2 Part ID Low 0 1 1 0 0 0 0 0 GLOBAL CONFIGURATION REGISTER Default Value: 0000 0000 ADDR NAME DESCRIPTION b7 b6 b5 b4 b3 b2 b1 b0 0x00 GLBCFG Channel Config WDTFLAG WDTEN MPHASE CLKOUT OFF3 OFF2 OFF1 OFF0 Bit Description b[7] WDTFLAG: Watchdog Timer Status. This bit indicates if the device has been reset by the WDT . It is cleared by disabling the WDT . b[6] WDTEN: Watchdog Timer Enable. When set, LT3966 requires an I2C start condition every 100ms to verify the communication interface is good. If the WDT expires without an I2C start being detected, the chip will force a power-on-reset to the default state. b[5] MPHASE: Multiphase DC/DC Converter Clocking. When MPHASE is set, the 4 DC/DC channels operate at MCLK/2, with 90° of phase shift between each channel. b[4] CLKOUT: SYNC Pin Direction. Default = 0, SYNC = Input. When set, the SYNC pin becomes an output and drives the MCLK signal, for synchronizing other devices. The output frequency is always that of MLCK, regardless of the state of MPHASE. This allows a slave LT3966 to run at equal frequency to the master LT3966 even in multiphase mode. b[3:0] OFF[3:0]: OFF/ON Control for Each Channel. Channels are all on by default, and controlled by EN. Set the OFF bit to disable a channel. REGISTER TABLE

Rev. 0For more information www.analog.com LED DRIVER CHANNEL REGISTERS Each of the 4 LED driver channels is configured through its 4-register bank. The channel registers are located at address 0x10–0x13, 0x20–0x23, 0x30–0x33, and 0x40–0x43 for the 4 channels, respectively. Default Values: 0000 0000, 0000 0000, 0000 0000, 1111 1111 OFFSET NAME DESCRIPTION b7 b6 b5 b4 b3 b2 b1 b0 0x00 STAT Status/Status CFG OC_EN SHORT_EN OPEN_EN OVFB_EN OC SHORT OPEN OVFB 0x01 CFG Channel Config x x x x INPH LATOFF BAM DIMEN 0x02 DIMH PWM Dim Value SCL2 SCL1 SCL0 DIM4 DIM3 DIM2 DIM1 DIM0 0x03 DIML PWM Dim Value DIM12 DIM11 DIM10 DIM9 DIM8 DIM7 DIM6 DIM5 0x04 ADIM Analog Dimming ADIM7 ADIM6 ADIM5 ADIM4 ADIM3 ADIM2 ADIM1 ADIM0 Bit Descriptions STAT OFFSET NAME DESCRIPTION b7 b6 b5 b4 b3 b2 b1 b0 0x00 STAT Status/Status CFG OC_EN SHORT_EN OPEN_EN OVFB_EN OC SHORT OPEN OVFB b[7] OC_EN: LED Overcurrent Reporting Enable. Set this bit high to enable LED overcurrent fault reporting on the ALERT pin. If clear , ALERT is not triggered during an LED overcurrent event. b[6] SHORT_EN: Shorted LED Reporting Enable. Set this bit high to enable SHORTLED fault reporting on the ALERT pin. If clear , ALERT is not triggered during a SHORTLED event. b[5] OPEN_EN: Open LED Reporting Enable. Set this bit high to enable OPENLED fault reporting on the ALERT pin. If clear , ALERT is not triggered during an OPENLED event. b[4] OVFB_EN: FB Overvoltage Reporting Enable. Set this bit high to enable FB overvoltage fault reporting on the ALERT pin. If clear , ALERT is not triggered during an OPENLED event. b[3] OC: LED Overcurrent Status. This bit is asserted when a differential of 375mV or greater is detected at the ISP–ISN sense amplifier . If the corresponding OC_EN bit is enabled, ALERT is asserted and the status bit is latched until either OC or OC_EN is written to 0 by the host. If the corresponding enable bit is clear , the status is not latched and will reflect the present state of the LED overcurrent detector . If the channel’s LATOFF (latchoff) bit is set, an LED overcurrent fault will result in latched shutdown of the faulted channel until either OC or LATOFF is written to 0 by the host. If the channel’s LATOFF bit is not set, the faulted channel will enter the hiccup cycle of shutdown and attempted restart. REGISTER DETAILS

Rev. 0 For more information www.analog.com b[2] SHORT: Shorted LED Status. This bit is asserted when the corresponding channel’s FB pin is below 300mV and the internal soft start has completed. If the corresponding SHORT_EN bit is enabled, ALERT is asserted and the fault status is latched until either SHORT or SHORT_EN is written to 0 by the host. If the correspond- ing enable bit is clear , the status is not latched and will reflect the present state of the Shorted LED detector . If the channel ’s LATOFF (latchoff) bit is set, a Shorted LED fault will result in latched shutdown of the faulted channel until either SHORT or LATOFF is written to 0 by the host. If the channel’s LATOFF bit is not set, the faulted channel will enter the hiccup cycle of shutdown and attempt to restart. b[1] OPEN: OPENLED Status. This bit is asserted when the corresponding channel’s FB pin is above 1.15V and ISP–ISN is less than 25mV. If the corresponding OPEN_EN bit is enabled, ALERT is asserted and the fault status is latched until either OPEN or OPEN_EN is written to 0 by the host. If the corresponding enable bit is clear , the status is not latched and will reflect the present state of the open LED detector . Open LED does not generate a hiccup or latchoff event. b[0] OVFB: FB Overvoltage Status. This bit is asserted when the corresponding channel’s FB pin is above 1.26V. If the corresponding OVFB_EN bit is enabled, ALERT is asserted and the status bit is latched until either OVFB or OVFB_EN is written to 0 by the host. If the corresponding enable bit is clear , the status is not latched and will reflect the present state of the FB overvoltage detector . FB overvoltage does not generate a hiccup or latchoff event. LED Driver Configuration OFFSET NAME DESCRIPTION b7 b6 b5 b4 b3 b2 b1 b0 0x01 CFG Channel Config x x x x INPH LATOFF BAM DIMEN Bit Description b[7:4] RFU: Reserved for Future Use. Bits read as 0, writes do nothing. b[3] INPH: In Phase Mode Select. When set to 1, the dimming is in phase, which means that the start of the channel’s dimming cycle is aligned with CH1’s. When set to 0, the dimming is out of phase. In this case, the start of CH2/CH3/CH4’s dimming cycle is behind of CH1’s by a quarter/a half/three quarters of CH2/ CH3/CH4’s dimming cycle. b[2] LATOFF: Latchoff Mode. When set, OC or SHORT fault cause channel to latchoff until the fault bit is cleared by master . When LATOFF is clear , channel will enter hiccup mode to retry. b[1] BAM: Bit Angle Modulation Select. When set to 1, the dimming generator outputs Bit-Angle-Modulation. When set to 0, the dimming generator outputs Pulse Width Modulation. b[3:0] DIMEN: Dimming Generator Enable Bits. PWM dimming is the logical AND of the dimming generator output and the CTRL/PWM comparator output. When DIMEN = 0, the PWM generator is disabled and bypassed and dimming is controlled solely by the CTRL/PWM comparator . REGISTER TABLE

Rev. 0For more information www.analog.com LED Driver Dimming Generator OFFSET NAME DESCRIPTION b7 b6 b5 b4 b3 b2 b1 b0 0x02 DIMH PWM Dim Value SCL2 SCL1 SCL0 DIM4 DIM3 DIM2 DIM1 DIM0 0x03 DIML PWM Dim Value DIM12 DIM11 DIM10 DIM9 DIM8 DIM7 DIM6 DIM5 Bit Description b[7] SCL[2:0]: PWM Cycle Length Select. Value from 0 to 7 chooses PWM counter length from 6 to 13 bits. This sets the period of the PWM generator to n = 2(6 + SEL) counts of the master clock. In the case where a DIM value is larger than the counter length, the DIM value will be truncated below bit (6+SCL). A DIM value of 0 0000 0000 0001 would be interpreted as 0 in all cases except SCL = 111b. b[4] DIM[12:0]: PWM Dimming Setpoint. Specifies the on time of the PWM generator , where period is defined by SEL. PWM duty cycle is therefore: DIM/n and ranges from 0 to (n-1)/n. To reach 100% on time, simply disable the dimming generator using the DIMEN bit. LED Driver Analog Dimming Offset Name Description b7 b6 b5 b4 b3 b2 b1 b0 0x04 ADIM Analog Dimming ADIM7 ADIM6 ADIM5 ADIM4 ADIM3 ADIM2 ADIM1 ADIM0 Bit Description b[7] ADIM[7:0]: Modulates the external current sense threshold set by CTRL by the value in the ADIM register . The default value for ADIM[7:0] is 255. ANALOG-TO-DIGITAL CONVERTER REGISTERS ADC Configuration Default Value: 0000 0000 ADDR NAME DESCRIPTION b7 b6 b5 b4 b3 b2 b1 b0 0x50 ADCCFG ADC Config RUN AUTO CLKSEL1 CLKSEL0 TGT3 TGT2 TGT1 TGT0 REGISTER TABLE

Rev. 0 For more information www.analog.com Bit Description ADCCFG1 b[7] RUN: Set to 1 to start conversion. b[6] AUTO: Set to 0 for single conversion on a target specified by TGT[3:0]. Set to 1 for automatic continuous conversion. In automatic continuous mode, all active inputs will be repeatedly measured in a round-robin fashion. Any channels that are disabled (OFF) will be skipped, but channels that are enabled yet in PWM low will cause the ADC to wait for the next PWM high. Upon PWM high, a conversion will take place and the sequence will continue. Data is double-buffered so result registers will always contain valid data. b[5:4] CLKSEL[1:0]: Choose ADC clock divider . For best results, set ADC bit time >1μs. CLKSEL[1:0] ADC CLOCK b[3:0] TGT[3:0]: Only used in single conversion mode. Sets conversion target as shown in the table below. TGT[3:0] TARGET TGT[3:0] TARGET 0x00 Scaled VIN 0x08 CH3 VFB 0x01 Not Valid 0x09 CH3 ILED 0x02 External 1 0x0A CH4 VFB 0x03 External 2 0x0B CH4 I LED 0x04 CH1 VFB 0x0C Not valid 0x05 CH1 ILED 0x0D Not valid 0x06 CH2 VFB 0x0E Not valid 0x07 CH2 ILED 0x0F Not valid REGISTER TABLE

Rev. 0For more information www.analog.com ADC Result Registers Default Value: Indeterminate Until Written by ADC ADDR NAME DESCRIPTION b7 b6 b5 b4 b3 b2 b1 b0 0x51 VIN VIN/48 VIN7 VIN6 VIN5 VIN4 VIN3 VIN2 VIN1 VIN0 0x53 EXT1 External Voltage 1 EXT17 EXT16 EXT15 EXT14 EXT13 EXT12 EXT11 EXT10 0x54 EXT2 External Voltage 2 EXT27 EXT26 EXT25 EXT24 EXT23 EXT22 EXT21 EXT20 0x55 VFB1 Ch 1 FB Voltage VFB17 VFB16 VFB15 VFB14 VFB13 VFB12 VFB11 VFB10 0x56 ILED1 Ch 1 LED Current ILED17 ILED16 ILED15 ILED14 ILED13 ILED12 ILED11 ILED10 0x57 VFB2 Ch 2 FB Voltage VFB27 VFB26 VFB25 VFB24 VFB23 VFB22 VFB21 VFB20 0x58 ILED2 Ch 2 LED Current ILED27 ILED26 ILED25 ILED24 ILED23 ILED22 ILED21 ILED20 0x59 VFB3 Ch 3 FB Voltage VFB37 VFB36 VFB35 VFB34 VFB33 VFB32 VFB31 VFB30 0x5A ILED3 Ch 3 LED Current ILED37 ILED36 ILED35 ILED34 ILED33 ILED32 ILED31 ILED30 0x5B VFB4 Ch 4 FB Voltage VFB47 VFB46 VFB45 VFB44 VFB43 VFB42 VFB41 VFB40 0x5C ILED4 Ch 4 LED Current ILED47 ILED46 ILED45 ILED44 ILED43 ILED42 ILED41 ILED40 Registers 0x51 and 0x53–0x5C hold the ADC results for the 11 channels. They are read-only registers. All measurements are 5mV per LSB 0x51: V IN. A scaled (1/48) measurement of the chip input voltage. 0x55, 0x57, 0x59, 0x5A: FB1–4. Channel feedback voltage measurement. 0x56, 0x58, 0x5A, 0x5C: VLED1–4. LED current measurement. Equal to 4× the sensed voltage on ISP–ISN. REGISTER TABLE

Rev. 0 For more information www.analog.com TYPICAL APPLICATIONS Efficiency 8192:1 DimmingMultiphase 100W, Quad 750mA × 12 LED Buck Mode Driver with I2C Dimming 4.7/uni03BCF ISP1 ISN1 TG1 330mΩ 10/uni03BCF 68/uni03BCH VIN 44V TO 52V ISP2 ISN2 TG2 330mΩ 10/uni03BCF 68/uni03BCH ISP3 ISN3 TG3 330mΩ 10/uni03BCF 68/uni03BCH SW1 ISP4 ISN4 TG4 330mΩ 10/uni03BCF 68/uni03BCH SW2 SW3 SW4VIN EN/UVLO EXT1 GND ISP1–4 ISN1–4 FB1–4 TG1–4 EXT2 SDA SCL RT SYNC ADR1–2 INTV CCALERT CTRL/ PWM1–4 4.7/uni03BCF 97.6k 22.1k I2C BUS L T3966 1M/uni03A9 33k INTVCC D1 D2 D3 D4 M1 M2 M3 M4 150k 360kHz MUL TI- PHASE

3966 TA03a

D1, D2, D3, D4: PMEG6020 M1, M2, M3, M4: SI7309 L1, L2, L3, L4: WURTH 744 373 49680 f SW = 360kHz V IN = 48V V OUT = 34V 0.0 0.5 1.0 1.5 2.0 2.5 3.0 100 EFFICIENCY (%)

3966 TA03b

LED CURRENT (A) (4 × 750mA/4 CH) MPHASE 0.5µs/DIV

3966 TA03c

VIN = 40V VOUT = 23V CH 1 50V/DIV CH 2 50V/DIV CH 3 50V/DIV CH 3 50V/DIV 2µs/DIV

3966 TA03d

T pwm = 3µsec VIN = 48V VOUT = 34V ILED = 0.75A VSWITCH 50V/DIV ILED 500mA/DIV IINDUCTOR 1A/DIV

Rev. 0For more information www.analog.com Efficiency 8192:1 Dimming 2.2MHz, 4 × 150mA × 12 Boost White LED Backlight with 8192:1 Dimming Ratio TYPICAL APPLICATIONS 4.7/uni03BCF VIN 7V TO 25V SW1 SW2 SW3 SW4VIN EN/UVLO EXT1 GND ISP1–4 ISN1–4 FB1–4 TG1–4 EXT2 SDA SCL RT SYNC ADR1–2 INTV CCALERT CTRL/ PWM1–4 INTVCC INTVCCI2C BUS L T3966 6.8/uni03BCH 4.7/uni03BCF 1MΩ 21.5k ISP1 ISN1 TG1 1.67Ω4.7/uni03BCF 6.8/uni03BCH ISP2 ISN2 TG2 1.67Ω4.7/uni03BCF 6.8/uni03BCH ISP3 ISN3 TG3 1.67Ω4.7/uni03BCF 6.8/uni03BCH ISP4 ISN4 TG4 1.67Ω4.7/uni03BCF I2C–8192:1 PWM DIMMING ISP1–4 1MΩ 220k M1 M2 M3 M4 D1 D2 D3 D4

3966 TA04a

D1, D2, D3, D4: PMEG6020 M1, M2, M3, M4: SI2309 L1, L2, L3, L4: WURTH 744 778 5006 42.2k 2.2MHz SINGLE- PHASE f SW = 2.2MHz V IN = 12V V OUT = 33V VIN = 24V VIN = 12V 100 200 300 400 500 600 100 EFFICIENCY (%) L T3966 Boost Efﬁciency

3681 TA04b

LED CURRENT (mA) (4mA × 150mA/4 CH) 250ns/DIV

3966 TA04c

T pwm = 500nsec VIN = 12V VOUT = 33V ILED 100mA/DIV IINDUCTOR 500mA/DIV

Rev. 0 For more information www.analog.com Efficiency Hiccup Mode8192:1 Dimming TYPICAL APPLICATIONS 5V to 40V Buck-Boost Mode Driver for 4 Series 330mA LEDs 4.7/uni03BCF ISN1 ISP1 750mΩ VIN = 5V TO 40V SW1 SW2 SW3 SW4VIN EN/UVLO EXT1 GND ISP1–4 ISN1–4 FB1–4 TG1–4 EXT2 SDA SCL RT SYNC ADR1–2 INTV CCALERT CTRL/ PWM1–4 INTVCC EXTERNAL POTENTIOMETER MEASUREMENT I2C BUS L T3966 TG1 21.5k 4.7/uni03BCF FB1 47/uni03BCH ISN2 ISP2 750mΩ TG2 21.5k 4.7/uni03BCF FB2 47/uni03BCH ISN3 ISP3 750mΩ TG3 21.5k 4.7/uni03BCF FB3 47/uni03BCH ISN4 ISP4 750mΩ TG4 21.5k 4.7/uni03BCF FB4 47/uni03BCH 4.7/uni03BCF 1MΩ D1, D2, D3, D4: PMEG6020 M1, M2, M3, M4: SI2309 L1, L2, L3, L4: WURTH 744 373 49470 M1 M2 M3 M4 D1 D2 D3 D4

3966 TA05a100k

f SW = 1MHz V IN = 12V V OUT = 12V LED CURRENT (A) (4mA × 330mA/4 CH) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 100 EFFICIENCY (%) L T3966 Buck–Boost Efﬁciency

3966 TA05b

T pwm = 1µsec VIN = 12V , VOUT =12V , ILED = 0.33A 1.0µs/DIV

3966 TA05c

0.2A/DIV IINDUCTOR 0.5A/DIV VSWITCH 20V/DIV SHORTED OUTPUT HICCUPS 2ms/DIV

3966 TA05e

V IN = 12V V OUT = 12V I LED = 0.33A V SWITCH 20V/DIV I LED 5A/DIV ALERT 5V/DIV

Rev. 0For more information www.analog.com PACKAGE DESCRIPTION 6.00 ±0.10 (4 SIDES) NOTE: 1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (SEE NOTE 6) PIN 1 NOTCH R = 0.45 OR 0.35 × 45° CHAMFER 0.40 ±0.10 40 39 BOTTOM VIEW—EXPOSED PAD

4.50 REF

(4-SIDES) 4.42 ±0.10 4.42 ±0.10 4.42 ±0.05 4.42 ±0.05 0.75 ±0.05 R = 0.115 TYP 0.25 ±0.05

0.50 BSC

0.200 REF

0.00 – 0.05 (UJ40) QFN REV Ø 0406 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 4.50 ±0.05 (4 SIDES) 5.10 ±0.05 6.50 ±0.05 0.25 ±0.05 R = 0.10 TYP 40-Lead Plastic QFN (6mm × 6mm) (Reference LTC DWG # 05-08-1728 Rev Ø) Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Rev. 0 For more information www.analog.com  ANALOG DEVICES, INC. 2020 www.analog.com RELATED PARTS TYPICAL APPLICATIONS PART NUMBER DESCRIPTION COMMENTS LT3964 Dual 1.5A/40V Sync Buck LED Driver with I2C VIN: 4V to 40V, VOUT(MAX) = 40V, 3000:1 T rue Color PWM Dimming, ISD < 1μA, 5mm × 6mm QFN-36 Package LT3492 60V, T riple Output 750mA, 1MHz High Current LED Driver with 3000:1 Dimming with PMOS Disconnect FET Drivers VIN: 3V to 30V, VOUT(MAX) = 60V, 3000:1 T rue Color PWM Dimming, ISD < 1μA, TSSOP-28 and 4mm × 5mm QFN-28 Packages LT3476 Quad Output 1.5A, 2MHz High Current LED Driver with 1,000:1 T rue Color PWM Dimming V IN: 2.8V to 16V, VOUT(MAX) = 36V, ISD< 10μA, 5mm × 7mm 30W Boost RGBW Digital Color Blending Circuit Featuring BAM Modulation Efficiency BAM Modulation 3.3/uni03BCF VIN = 7V TO 17V SW1 SW2 SW3 SW4VIN EN/UVLO EXT1 GND ISP1–4 ISN1–4 FB1–4 TG1–4 EXT2 SDA SCL RT SYNC ADR1–2 INTV CCALERT CTRL/ PWM1–4 INTVCC I2C BUS L T3966 RED 250mA 4.7/uni03BCF 1MΩ 34k ISP1 ISN1 TG1 4.7/uni03BCF GREEN 156mA ISP2 ISN2 TG2 BLUE 180mA ISP3 ISN3 TG3 WHITE 200mA ISP4 ISN4 TG4 NOTE: CURRENTS SET USING ADIM CODE. M1 M2 M3 M4 4.7/uni03BCF 4.7/uni03BCF 4.7/uni03BCF D1 D2 D3 D4 6.8/uni03BCH 6.8/uni03BCH 6.8/uni03BCH 6.8/uni03BCH ISP1–4 1MΩ 221k

3966 TA02a

D1, D2, D3, D4: PMEG6020 M1, M2, M3, M4: SI2309 L1, L2, L3, L4: WURTH 744 778 5006 69.8k 1.4MHz SINGLE- PHASE LED CURRENT (A) (4 × 250mA/4 CH) 0.2 0.4 0.6 0.8 100 EFFICIENCY (%) f SW = 1.4MHz V IN = 12V V OUT = 30V V IN = 12V V OUT = 30V 2µs/DIV

3966 TA02c

Product Information

LT3966 specifications and overview.

Summary

I2C Programmable Quad Monolithic Boost LED Driver

Description

I2C Programmable Quad Monolithic Boost LED Driver

Source title LT3966 Datasheet(PDF) - Analog Devices

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