LT3964 – Dual 36V Synchronous 1.6A Buck LED Driver with I2C
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 36
Technical content
For more information www.linear .com/L T3964 3964fb TYPICAL APPLICATION FEATURES DESCRIPTION Dual 36V Synchronous 1.6A Buck LED Driver with I2C The LT®3964 is a dual synchronous step-down DC/DC converter with I 2C interface designed to operate as a constant-current and constant-voltage source and is ideal for driving LEDs. The fixed frequency and peak current mode topology result in stable operation over a wide range of supply and output voltages. The ground referred volt- age FB pin serves as the input for several LED protection features, and also allows the converter to operate as a constant-voltage source. The maximum output current is set by an external resistor, and the output current ampli- fier has a rail-to-rail common mode range. LT3964 uses an I2C interface to communicate with a microcontroller to read LED faults, write PWM and analog dimming reg- isters and set fault masking. The I2C PWM input provides LED dimming ratios up to 8192:1. The I2C programmable CTRL register sets the gain of the external CTRL pin, and maximum current sense threshold, providing additional analog dimming capability. 50W Dual Buck 1A LED Driver
APPLICATIONS
n Wide Input Voltage Range: 4V to 36V n T wo Independent 1.6A/40V Synchronous Bucks n I2C Interface for Internal T rue Color PWM™ Dimming (8192:1), Analog Dimming and Fault Reporting n 1000:1 External T rue Color PWM Dimming and 10:1 External Analog Dimming n PMOS Switch Driver for PWM and Output Disconnect n ±3% Constant Current Regulation n Adjustable Frequency: 200kHz to 2MHz n Frequency Synchronization with Clock Output n Programmable OPENLED Protection with Reporting n Short-Circuit Protection with Reporting n Programmable Undervoltage Lockout with Hysteresis n Internal Compensation n 9 Unique Device Addresses for I2C n Available in 5mm × 6mm 36-Lead QFN Package n General Purpose, Industrial, Medical and Automotive Lighting n Constant-Current, Constant-Voltage Source All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents, including 7199560, 7321203, 7746300. Efficiency, VIN = 34V I LED (mA) 100 200 300 400 500 600 700 800 900 1000 100 EFFICIENCY (%) IN
3964 TA01b
10µH 0.22µF 100mΩ 2.2µF 43.2k 2.2µF 100k 3.92k 499k 165k 100k 2.2µF 27.4k 2.2µF BST1 L T3964 SW1 V IN1 ISP1 ISN1 PWMTG1 CTRL1 BST2 SW2 ISP2 ISN2 PWMTG2 GND EN/UVLO CTRL2 PWM1 PWM2 PWM1 PWM2 INTVCC ALERT V IN2 GND T SET RT SCL SDA 2-WIRE I2C INTERFACE ADDR1 ADDR2 SYNC/CLKOUT 2MHz INTVCC INTV CC INTVCC FB1 FB2 10µH 0.22µF 100mΩ 2.2µF 43.2k 1A,
8 LEDs
1A, 10µF ×231V TO 36V (ENABLED AT 33V , SHUTDOWN AT 31V)
3964 TA01a
For more information www.linear .com/L T3964 3964fb PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS I P te 2 BS 4.5V V SD V Operating Junction Temperature (Notes 4, 5) LT396 0°C to 125°C LT396 40°C to 150°C 60°C to 150°C (Note 1) 11 12 13 14 TOP VIEW PGND UHE PACKAGE 36-LEAD (5mm × 6mm) PLASTIC QFN 15 16 17 18 36 35 34 33 32 31 30 29 1RT CTRL1 CTRL2 EN/UVLO INTV CC ALERT PWM1 PWM2 SDA SCL ISP1 ISN1 PWMTG1 SGND FB1 FB2 SGND PWMTG2 ISN2 ISP2 SYNC/CLKOUT T SET VIN1 VIN1 NC SW1 SW1 BST1 ADDR2 ADDR1 V IN2 VIN2 NC SW2 SW2 BST2 θJA = 43°C/W, θJC = 5°C/W EXPOSED PAD (PIN 37) IS PGND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LT3964EUHE#PBF LT3964EUHE#TRPBF 3964 36-Lead (5mm × 6mm) Plastic QFN –40°C to 125°C LT3964IUHE#PBF LT3964IUHE#TRPBF 3964 36-Lead (5mm × 6mm) Plastic QFN –40°C to 125°C LT3964HUHE#PBF LT3964HUHE#TRPBF 3964 36-Lead (5mm × 6mm) Plastic QFN –40°C to 150°C Consult ADI Marketing for parts specified with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. http://www.linear.com/product/LT3964#orderinfo
For more information www.linear .com/L T3964 3964fb ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN1 = 12V, VEN/UVLO = 5V, CTRL1 = CTRL2 = 2V, PWM1 = PWM2 = 2V unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS VIN1, VIN2 Operating Supply Range l 4 36 V VIN1 Pin Quiescent Current Not Switching 2.5 mA VIN1 Pin Shutdown Current EN/UVLO = 1.15V, PWM1,2 = 0V EN/UVLO = 0V 200 µA µA VIN2 Pin Quiescent Current Not Switching 1 10 µA VIN2 Pin Shutdown Current EN/UVLO = 1.15V, PWM1,2 = 0V EN/UVLO = 0V µA µA EN/UVLO Threshold V oltage Falling l 1.158 1.18 1.202 V EN/UVLO Rising Hysteresis 60 mV EN/UVLO Input Low Voltage 0.4 V EN/UVLO Pin Bias Current Low EN/UVLO = 1.15V 4 µA EN/UVLO Pin Bias Current High EN/UVLO = 1.3V 2 100 nA Linear Regulator INTVCC Regulation Voltage IINTVCC = –30mA, Non Switching l 3.9 4 4.1 V INTVCC Line Regulation 6V ≤ VIN1 ≤ 40V 0.03 %/V INTVCC Load Regulation –30mA ≤ IINTVCC ≤ 0mA 0.03 %/mA INTVCC Undervoltage Lockout 3.1 3.2 3.3 V INTVCC Undervoltage Lockout Hysteresis 50 mV INTVCC Current Limit VIN1 = 12V, VINTVCC = 3V 110 mA Dropout (VIN1 – VINTVCC) VIN1 = 4V, IINTVCC = –20mA, Not Switching 300 mV Error Amplifier Full Scale LED Current Sense Threshold (ISP1-ISN1), V(ISP2-ISN2)) ISP1,2 = 24V, CTRL1,2 = 1.5V, ADIM1,2[7:0] = 0xFF ISP1,2 = 0V, CTRL1,2 = 1.5V, ADIM1,2[7:0] = 0xFF l l 100 100 103 104 mV mV 1/2 Scale LED Current Sense Threshold (ISP1-ISN1), V(ISP2-ISN2)) ISP1,2 = 24V, CTRL1,2 = 0.7V, ADIM1,2[7:0] = 0xFF ISP1,2 = 0V, CTRL1,2 = 0.7V, ADIM1,2[7:0] = 0xFF l l mV mV 1/4th Scale LED Current Sense Threshold (ISP1-ISN1), V(ISP2-ISN2)) Modulated by I2C Input ADIM1,2[7:0] ISP1,2 = 24V, CTRL1,2 = 0.7V, ADIM1,2[7:0] = 0x7F ISP1,2 = 0V, CTRL1,2 = 0.7V, ADIM1,2[7:0] = 0x7F l l mV mV 1/10th Scale LED Current Sense Threshold (V (ISP1-ISN1), V(ISP2-ISN2)) ISP1,2 = 24V, CTRL1,2 = 0.3V, ADIM1,2[7:0] = 0xFF ISP1,2 = 0V, CTRL1,2 = 0.3V, ADIM1,2[7:0] = 0xFF l l mV mV ISP1,2/ISN1,2 Over current Protection Threshold (V(ISP1-ISN1), V(ISP2-ISN2)) ISP1,2 = 24V 930 mV C/10 Current Sense Threshold (ISP1-ISN1), V(ISP2-ISN2)) ISP1,2 = 24V ISP1,2 = 0V mV mV ISP1, ISP2 Input Current Bias Current PW M1,2 = 2V (ACTIVE) PWM1,2 = 0V (STANDBY) 350 µA µA ISN1, ISN2 Input Current Bias Current PW M1,2 = 2V (ACTIVE) PWM1,2 = 0V (STANDBY) µA nA CTRL1, CTRL2 Input Bias Current VCTRL1, VCTRL2 = 1V 20 200 nA CTRL1, CTRL2 PWM Shutdown Threshold l 100 150 mV CTRL1, CTRL2 PWM Threshold Hysteresis 30 mV FB1, FB2 Regulation Voltage (VFB) ISP1,2 = 24V l 1.163 1.17 1.18 1.18 1.197 1.19 V V FB1, FB2 Over voltage Threshold VFB + 43mV V FB + 53mV V FB + 63mV V
For more information www.linear .com/L T3964 3964fb PARAMETER CONDITIONS MIN TYP MAX UNITS FB1, FB2 OPENLED Threshold VFB – 43mV V FB – 53mV V FB – 63mV V FB1, FB2 SHORTLED Threshold l 250 270 mV FB1, FB2 Pin Input Bias Current Current Out of Pin, FB = 1V 20 200 nA Feedback Line Regulation 4V ≤ VIN1 ≤ 36V 0.001 %/V TSET Pin Voltage 630 mV TSET Pin Bias Current Current Out of Pin, TSET = 400mV 40 200 nA Oscillator RT Pin Voltage 0.96 V Switching Frequency RT = 357k RT = 60.4k RT = 27.4k l l l 186 0.93 1.86 200 1.0 2.0 214 1.07 2.14 kHz MHz MHz SYNC/CLKOUT Pin Resistance to GND 100 kΩ SYNC/CLKOUT Input High Threshold 1.5 V SYNC/CLKOUT Input Low Threshold 0.4 V SYNC/CLKOUT Output Duty Cycle CONFIG[6] = 1 (Clock Output Enabled) 30 50 70 % SYNC/CLKOUT Output Voltage High CONFIG[6] = 1 (Clock Output Enabled) 4 V SYNC/CLKOUT Output Voltage Low CONFIG[6] = 1 (Clock Output Enabled) 0.1 0.3 V SYNC/CLKOUT Output Rise Time C SYNC/CLKOUT = 50pF, CONFIG[6] = 1 (Clock Output Enabled) 40 ns SYNC/CLKOUT Output Fall Time C SYNC/CLKOUT = 50pF, CONFIG[6] = 1 (Clock Output Enabled) 20 ns Logic ALERT Output Low IALERT = 1mA 300 mV PWM1, PWM2 Input High Voltage l 1.18 1.3 V PWM1, PWM2 Input Low Voltage l 1.1 1.15 V PWM1, PWM2 Resistance to GND 280 kΩ Power Switch Top Switch On Resistance I SW = 1A 200 mΩ Top Switch Current Limit l 1.6 1.8 2 A Bottom Switch On Resistance ISW = 1A 180 mΩ Bottom Switch Current Limit 1.6 2 2.4 A SW Leakage Current VIN = 36V, VSW = 0V, 36V –1.5 1.5 µA Minimum Off Time 20 50 70 ns Minimum ON Time 20 40 65 ns PWMTG Gate Driver PWMTG ON Voltage (V ISP1-PWMTG1, VISP2-PWMTG2) ISP1,2 = 36V 7.5 9.5 V PWMTG OFF Voltage (VISP1-PWMTG1, VISP2-PWMTG2) ISP1,2 = 36V 0 0.3 V PWMTG Turn-On Time CLOAD = 500pF, ISP1,2 = 36V 70 ns PWMTG Turn-Off Time CLOAD = 500pF, ISP1,2 = 36V 40 ns ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN1 = 12V, VEN/UVLO = 5V, CTRL1 = CTRL2 = 2V, PWM1 = PWM2 = 2V unless otherwise noted.
For more information www.linear .com/L T3964 3964fb PARAMETER CONDITIONS MIN TYP MAX UNITS I2C Port (Note 6) I2C Address XXXX Bits Are Programmed by ADDR[1:2] l 110XXXX[R/W] VIHA High Level Input Voltage for Address Pins ADDR1, ADDR2 l INTVCC – 0.8 V VILA Low Level Input Voltage for Address Pins ADDR1, ADDR2 l 0.6 V RINH Resistance from ADDR1, ADDR2 to INTVCC to Set Chip Address Bit to 1 l 10 kΩ RINL Resistance from ADDR1, ADDR2 to GND to Set Chip Address Bit to 0 l 10 kΩ RINF Resistance from ADDR1, ADDR2 to GND or INTVCC to Set Chip Address Bit to Float l 1 MΩ SDA and SCL Input High Voltage l 1.5 V SDA and SCL Input Low Voltage l 0.4 V SDA and SCL Input High Current SDA, SCL = 3.3V 50 nA SDA and SCL Input Low Current Current Out of Pin, SDA, SCL = 0V 50 nA SDA Output Low Voltage ISDA = 3mA 0.4 V Clock Operating Frequency 400 kHz Bus Free Time Between Stop and Start Condition (t BUF) 1.3 µs Hold Time After Repeated Start Condition (t HD,SDA) 0.6 µs Repeated Start Condition Set-Up Time (t SU,STA) 0.6 µs Stop Condition Set-Up Time (tSU,STO) 0.6 µs Data Hold Time Output (tHD,DAT(O)) 0 900 ns Data Hold Time Input (tHD,DAT(I)) 0 ns Data Set-Up Time (tSU,DAT) 250 ns SCL Clock Low Period (tLOW) 1.3 µs SCL Clock High Period (tHIGH) 0.6 µs Data Fall Time CB = Capacitance of One Bus Line (pF) 20 + 0.1CB 300 ns Data Rise Time CB = Capacitance of One Bus Line (pF) 20 + 0.1CB 300 ns Input Spike Suppress Pulse Width (tSP) 50 ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Do not apply a positive or negative voltage source to the PWMTG pin or RT pin, otherwise permanent damage may occur. Note 3: Do not apply a positive or negative voltage source to INTV CC pin, otherwise permanent damage may occur. IINTVCC = 5mA is the maximum external load that can be applied. The internal load will be higher due to the power consumption of the IC. Note 4: The LT3964E is guaranteed to meet specified performance from 0°C to 125°C. Specifications over the –40°C to 125°C operating temperature range are assured by design, characterization and ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN1 = 12V, VEN/UVLO = 5V, CTRL1 = CTRL2 = 2V, PWM1 = PWM2 = 2V unless otherwise noted. correlation with statistical process controls. The LT3964I is guaranteed to meet performance specifications over the –40°C to 125°C operating temperature range. The LT3964H is guaranteed over the full –40°C to 150°C operating junction temperature range. High junction temperatures degrade operating lifetimes. Operating lifetime is derated at junction temperatures greater than 125°C. Note 5: The LT3964 includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed the maximum operating junction temperature when overtemperature is active. Continuous operating above the specified maximum operating junction temperature may impair device reliability. Note 6: All I 2C serial port timing information is shown in Figure 15.
For more information www.linear .com/L T3964 3964fb TYPICAL PERFORMANCE CHARACTERISTICS VIN Quiescent Current vs Temperature INTVCC vs Temperature (3•VIN) INTVCC vs Current (3•VIN) INTVCC UVLO vs Temperature INTVCC Current Limit vs VIN Switching Frequency vs RT EN/UVLO Thresholds vs Temperature EN/UVLO Current vs Temperature VIN Shutdown Current vs Temperature TA = 25°C, unless otherwise noted. RISING THRESHOLD FALLING THRESHOLD TEMPERATURE (°C) –55 –25 125 155 1.16 1.17 1.18 1.19 1.20 1.21 1.22 1.23 1.24 1.25 1.26 V EN/UVLO (V) 3964 G1 EN/UVLO = 1.1V TEMPERATURE (°C) –55 –25 125 155 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 I EN/UVLO (µA) 3964 G2 EN/UVLO = 1.1V V IN = 6V V IN = 24V V IN = 36V TEMPERATURE (°C) –55 –25 125 155 100 120 140 160 180 200 220 240 260 V IN SHUTDOWN CURRENT (µA) 3964 G3 V IN = 6V V IN = 24V V IN = 36V TEMPERATURE (°C) –55 –25 125 155 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 V IN QUIESCENT CURRENT (mA) 3964 G4 R T (kΩ) 100 1000 0.1 SWITCHING FREQUENCY (MHz) Switching Frequency vs R T
3964 G09
V IN = 6V V IN = 24V V IN = 36V TEMPERATURE (°C) –55 –25 125 155 3.90 3.92 3.94 3.96 3.98 4.00 4.02 4.04 4.06 4.08 4.10 INTV CC (V) CC
3964 G05
V IN = 6V V IN = 24V V IN = 36V LOAD CURRENT (mA) 3.80 3.85 3.90 3.95 4.00 4.05 4.10 4.15 4.20 INTV CC (V) INTV CC vs LOAD
3964 G06
TEMPERATURE (°C) –55 –25 125 155 3.10 3.12 3.14 3.16 3.18 3.20 3.22 3.24 3.26 3.28 3.30 INTV CC (V) INTV CC UVLO vs Temperature
3964 G07
= 0V V IN (V) I INTVCC (mA) INTV CC Current Limit vs V IN
3964 G08
For more information www.linear .com/L T3964 3964fb TYPICAL PERFORMANCE CHARACTERISTICS VFB vs Temperature OVFB Threshold vs Temperature OPENLED Threshold vs Temperature SHORTLED Threshold vs Temperature C/10 Threshold vs Temperature V ISP–ISN vs CTRL Frequency vs Temperature (1MHz) Frequency vs Temperature (2MHz) Frequency vs Temperature (200kHz) TA = 25°C, unless otherwise noted. R T = 60.4k TEMPERATURE (°C) –55 –25 125 155 800 850 900 950 1000 1050 1100 1150 1200 FREQUENCY (kHz)
3964 G10
R T = 27.4k TEMPERATURE (°C) –55 –25 125 155 1700 1750 1800 1850 1900 1950 2000 2050 2100 FREQUENCY (kHz) Frequency vs Temperature(2MHz)
3964 G11
R T = 357k TEMPERATURE (°C) –55 –25 125 155 170 175 180 185 190 195 200 205 210 FREQUENCY (kHz)
3964 G12
TEMPERATURE (°C) –55 –25 125 155 1.10 1.12 1.14 1.16 1.18 1.20 1.22 V FB (V) FB
3964 G13
TEMPERATURE (°C) –55 –25 125 155 1.15 1.16 1.17 1.18 1.19 1.20 1.21 1.22 1.23 1.24 1.25 V FB (V)
3964 G14
TEMPERATURE (°C) –55 –25 125 155 1.05 1.06 1.07 1.08 1.09 1.10 1.11 1.12 1.13 1.14 1.15 V FB (V) OPENLED Threshold vs Temperature
3964 G15
TEMPERATURE (°C) –55 –25 125 155 240 245 250 255 260 265 270 275 280 285 290 295 300 V FB (mV) Temperature
3964 G16
TEMPERATURE (°C) –55 –25 125 155 V ISP–ISN (mV) C/10 Threshold vs Temperature
3964 G17
V CTRL (V) 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 2.0 100 110 V ISP–ISN (mV) ISP–ISN CTRL
3964 G18
For more information www.linear .com/L T3964 3964fb TYPICAL PERFORMANCE CHARACTERISTICS VISP–ISN 1/2 Scale (ADIM = 0x7f) vs Temperature VISP–ISN 1/5 Scale (VCTRL = 0.4V) vs Temperature VISP–ISN 1/10 Scale (VCTRL = 0.3V) vs Temperature VISP–ISN vs VFB VISP–ISN vs VISP VISP–ISN vs VTSET at 90°C VISP–ISN vs ADIM VISP–ISN Full Scale vs Temperature VISP–ISN 1/2 Scale (VCTRL = 0.7V) vs Temperature TA = 25°C, unless otherwise noted. V CTRL = 2V ADIM CODE 128 160 192 224 256 100 V ISP–ISN (mV) ISP–ISN
3964 G19
ISP = 24V ISN = 0V TEMPERATURE (°C) –55 –25 125 155 96.0 97.0 98.0 99.0 100.0 101.0 102.0 103.0 104.0 V ISP–ISN (mV) V ISP–ISN Full Scale vs Temperature
3964 G20
ISP = 24V ISN = 0V TEMPERATURE (°C) –55 –25 125 155 46.0 47.0 48.0 49.0 50.0 51.0 52.0 53.0 54.0 V ISP–ISN (mV) vs Temperature
3964 G21
V CTRL = 2V ISP = 24V ISN = 0V TEMPERATURE (°C) –55 –25 125 155 46.0 47.0 48.0 49.0 50.0 51.0 52.0 53.0 54.0 V ISP–ISN (mV) vs Temperature
3964 G22
ISP=24V ISN=0V TEMPERATURE (°C) –55 –25 125 155 18.0 18.5 19.0 19.5 20.0 20.5 21.0 21.5 22.0 V ISP–ISN (mV) vs Temperature
3964 G23
ISP = 24V ISN = 0V TEMPERATURE (°C) –55 –25 125 155 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 V ISP–ISN (mV)
3964 G24
V FB (V) 1.10 1.12 1.14 1.16 1.18 1.20 100 125 V ISP–ISN (mmV) ISP–ISN FB
3964 G25
V CTRL = 2V V CTRL = 2V V ISP (V) 100 101 102 103 104 V ISP–ISN (mV) ISP–ISN ISP
3964 G26
V TSET (mV) 660 680 700 720 740 760 780 800 100 110 V ISP–ISN (mV) ISP–ISN TSET
3964 G27
V CTRL = 2V
For more information www.linear .com/L T3964 3964fb TYPICAL PERFORMANCE CHARACTERISTICS Power Switch On-Resistance vs Temperature PWMTG Rising Edge PWMTG Falling Edge T ransient Response at VIN = 34V Zero LED On to One LED On T ransient Response at VIN = 34V One LED On to Zero LED On Minimum On-Time vs Temperature Top Switch Current Limit vs Temperature Top Switch Current Limit vs Duty Cycle T A = 25°C, unless otherwise noted. TEMPERATURE (°C) –55 –25 125 155 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 TOP SW CURRENT LIMIT (A)
3964 G30
FREQ = 1MHz DUTY CYCLE (%) 100 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 TOP SWITCH CURRENT LIMIT (A)
3964 G31
TEMPERATURE (°C) –55 –25 125 155 100 150 200 250 300 350 400 POWER SWITCH ON RESISTANCE (mΩ) vs Temperature
3964 G32
V PWM 2V/DIV V PWMTG 5V/DIV
3964 G33
V PWM 2V/DIV V PWMTG 5V/DIV
3964 G34
SEE MATRIX LED DRIVER ON PAGE 31 5µs/DIV I 200mA/DIV I LED1 200mA/DIV
3964 G35
SEE MATRIX LED DRIVER ON PAGE 31 5µs/DIV I LED1 200mA/DIV I 200mA/DIV
3964 G36
I LED = 1A TEMPERATURE (°C) –55 –25 125 155 MIN ON-TIME (V)
3964 G28
I LED = 1A TEMPERATURE (°C) –55 –25 125 155 MIN OFF-TIME (V) Minimum OFF Time vs Temperature
3964 G29
For more information www.linear .com/L T3964 3964fb PIN FUNCTIONS RT (Pin 1): Switching Frequency Adjustment Pin. Set the master clock frequency using a resistor to GND (for resis- tor values, see Typical Performance curve or Table 3). Do not leave the RT pin open. CTRL1, CTRL2 (Pins 2, 3): Current Sense Threshold Adjustment Pins. The V(ISP-ISN) threshold is regulated by the internal 1.2V reference voltage, CTRL and ADIM[7:0] of the respective channel as follows: V(ISP-ISN) = 0V, when VCTRL < 0.2V V(ISP-ISN) = [(V CTRL –0.2V)/10]•(ADIM[7:0]+1)/256, when 0.2V ≤ VCTRL ≤ 1.1V V(ISP-ISN) = 100mV•(ADIM[7:0]+1)/256, when VCTRL > 1.3V For 1.1V < V CTRL < 1.3V, the dependence of the current sense threshold upon V CTRL transitions from a linear function to a constant value, reaching 98% of full scale value, 100mV•(ADIM[7:0]+1)/256, by VCTRL = 1.2V. See Table 1 for detailed information. Do not leave this pin open. EN/UVLO (Pin 4): Enable and Undervoltage Lockout Pin. An accurate 1.18V falling threshold with externally pro - grammable hysteresis detects when power is OK to enable switching. Rising hysteresis is generated by the external resistor divider and an accurate internal 4µA pull-down current. Tie to 0.4V or less to disable the device. INTVCC (Pin 5): Internal Low-Dropout Regulator Output. INT VCC is regulated to 4V, and must be bypassed with an external capacitor of at least 2.2μF. INTVCC is the power supply for the internal DMOS gate driver and control circuitry. Users may apply <5mA loads to INTV CC. Over- loading INTVCC can cause unintentional device shutdown from INTVCC current limiting or overheating due to power dissipation. ALERT (Pin 6): Chip Alert Status Report Pin. An open- collector pull-down on ALERT asserts when any of the following conditions happen: 1. FB Over voltage (VFB > 1.233V); 2. OPENLED (VFB > 1.127V and V(ISP-ISN) <10mV); 3. SHORTLED (VFB < 0.25V); 4. LED Over current (V(ISP-ISN) > 930mV); 5. INTVCC undervoltage; or 6. Thermal shutdown. ALER T flag stays low until all alerts have been removed and unlatched. PWM1, PWM2 (Pins 7, 8): PWM Input Signal Pin. A low signal turns off switching, reduces quiescent supply current, and drives PWMTG to the ISP level. PWM has an internal 280k pull-down resistor. If not used, connect this pin to INTV CC. SDA (Pin 9): Serial Data Line for I 2C Port. Open-drain output during read back. SCL (Pin 10): Serial Clock Line for I2C Port. ADDR2 (Pin 11): Address Select Pin. This pin is configured as a three-state (LOW, HIGH, FLOAT) address control bit for the device I2C address. See Table 14 for address selection. ADDR1 (Pin 12): Address Select Pin. This pin is configured as a three-state (LOW, HIGH, FLOAT) address control bit for the device I2C address. See Table 14 for address selection. VIN2 (Pins 13, 14): Input Supply for Channel 2. May be driven by an independent supply, or connected to V IN1. This signal must be locally bypassed. Be sure to place the positive terminal of the input capacitor as close as pos - sible to the V IN2 pin, and the negative terminal as close as possible to the PGND pin (Pin 37).
For more information www.linear .com/L T3964 3964fb SW1, SW2 (Pins 16, 17, 30, 31): SW Pins. The SW pins are the outputs of the internal power switches of each channel. Tie each channel SW pins together and connect them to the appropriate inductor and boost capacitor. These nodes should be kept small on the PCB for good performance. BST1, BST2 (Pins 18, 29): Boost Pins. These pins are used to provide a drive voltage, higher than the input voltage, to the topside power switch of each channel. Place a 0.1µF or larger boost capacitors as close as possible to the IC. ISP1, ISP2 (Pins 19, 28): Connection Points for the Posi- tive Terminals of the Current Feedback Resistors (RLED1,2). Also serves as positive rails for PWMTG drivers. ISN1, ISN2 (Pins 20, 27): Connection Points for the Nega- tive Terminals of the Current Feedback Resistors (RLED1,2). PWMTG1, PWMTG2 (Pins 21, 26): Top Gate Driver Out- puts. An inverted and level-shifted version of the PW M input signals. Used to drive the gate of an external PMOS transistor between VISP and VISP – 7.5V to provide load-side on/off control, PWM dimming and fault-mode disconnect. Leave PWMTG unconnected if not used. FB1, FB2 (Pins 23, 24): Voltage Loop Feedback Pins. The FB pin is intended for constant-voltage regulation or for LED protection/OPENLED detection. The LT3964 regulates the FB pins to 1.18V(NOMINAL). If the FB input is regulating the loop and V (ISP-ISN) is less than 10mV (Typical), the corresponding OPENLED bit in the chip status register is set and the ALERT pull-down is asserted. This action may signal an OPENLED fault for that channel. If FB is driven above 1.233V, the power switches are turned off for that channel, the corresponding OVFB bit in the chip status register is set, ALERT pull-down is asserted, and the PWMTG pin for that channel is driven high to protect the LEDs from an overcurrent event. If FB is driven below 0.25V, the power switches are turned off for that channel, the corresponding SHORTLED bit in the chip status register is set, ALERT pull-down is asserted, and the PWMTG pin for that channel is driven high to isolate the LED string from the power path. Do not tie these pins to GND. VIN1 (Pins 33, 34): Input Supply. The V IN1 pins supply current to the LT3964 internal circuitry and to the internal topside power switch of Channel 1. This pin must be lo- cally bypassed. Be sure to place the positive terminal of the input capacitor as close as possible to the VIN1 pins, and the negative terminal as close as possible to the PGND pin (Pin 37). T SET (Pin 35): Junction Temperature Adjustment Pin. Programs LT3964 junction temperature breakpoint, beyond which LED currents will begin to decrease. An internal VPTAT threshold (see Block Diagram) increases with junction temperature. When VPTAT exceeds TSET pin voltage, LED currents are decreased. If the function is not required, connect TSET pin to INTVCC pin. SYNC/CLKOUT (Pin 36): The SYNC/CLKOUT pin can be used to synchronize the internal oscillator to an external logic level signal. The R T resistor should be chosen to program an internal switching frequency 10% slower than the SYNC pulse frequency. Use a 50% duty cycle waveform to drive this pin. When CONFIG[6] bit in the chip configuration register is set, a buffered version of the clock signal is driven out of the SYNC/CLKOUT pin. Note that the SYNC/CLKOUT pin is only meant to drive capacitive loads up to 50pF. If not used, tie this pin to GND with a 20k resistor. SGND (Pins 22, 25): Chip Ground Pin. PGND ( Pin 37): Power Switch Ground. These pins are the return path of the internal bottom-side power switch. Place the negative terminal of the input capacitor as close to the PGND pins as possible. NC (Pins 15, 32): No Connect Pin. PIN FUNCTIONS
For more information www.linear .com/L T3964 3964fb BLOCK DIAGRAM 4µA 20mV 10xR1 1.18V REF SHDN 4V REG UVLO TLIM 200kHz TO 2MHz OSCILLATOR RAMP GENERATOR INTV CC VLED1 1.2V VTEMP IREF IOUT 8-BIT DAC ADIM1[7:0] VISP1 VISP1 – 7.5V INTV CC 1.18V TGOFFB1 SYNCHRONOUS CONTROLLER Q R S ADIM1[7:0] ADIM2[7:0] CH1-ON CH2-ON I2C INTERFACE OC1 OPENLED1 SHORTLED1 OVFB1 FB1 FB1 0.25V 1.233V FB1 VLED1 1.127V 10mV VLED1 0.93V INTV CC BST1 SW1 30, 31 PGND ISP1 ISN1 CTRL1 PWMTG1 FB1 EN/UVLO V IN1 33, 34 INTV CVCC RT CC RT SYNC/CLKOUT PWM1 PWM2 ALERT SGND 22, 25 SDA SCL ADDR2 ADDR1 T SET RTSET2 RTSET1 VPTAT INTV CC LOGIC INTV CC OC1, 2 SHORTLED1, 2 OPENLED1, 2 OVFB1, 2 CH1, 2-ON UVLO TLIM TGOFFB1 TGOFFB2 TGOFFB1 A10 A11 REPLICATED FOR CHANNEL 2 VC 2.5V VTEMP REN1 REN2 CBST1 RLED1 BOTTOM SWITCH TOP SWITCH RFB1 RFB2 CIN1 3964 BD
For more information www.linear .com/L T3964 3964fb OPERATION The LT3964 is a dual constant-frequency, current mode step-down DC/DC converter with internal synchronous power switches. The operation of the LT3964 is best understood by referring to the Block Diagram of the IC. In normal operation, with the PWM pin is low or CH1,2_ON signal is low, TGOFFB is disabled. The power switches are turned off, the PWMTG pin is pulled high to ISP to turn off the PMOS disconnect switch, and the ISP and ISN pin bias currents are reduced to several µA. When the PWM pin and CH1,2_ON signal transitions high, the PWMTG pin transitions low after a short delay. At the same time, the bottom switch is turned on for a short period of time to refresh the boost capacitor, followed by the top power switch turning on. A voltage input proportional to the top switch current is added to a stabilizing slope compensation ramp and the resulting top switch current sense signal is fed into the negative terminal of the PWM comparator. The current in the external inductor increases steadily during the time the top switch is on. When the switch current sense voltage exceeds the output of the error amplifier, labeled VC, the latch is reset and the switch is turned off. During the top switch off phase, the synchronous bottom switch is on until the next clock cycle begins or inductor current falls to zero. If overload conditions result in more than 2A (Typ) flowing through the bottom switch, the next clock cycle will be delayed until switch current returns to a safe level. At the completion of each oscillator cycle, internal signals such as slope compensation return to their starting points and a new cycle begins with the set pulse from the oscillator. Through this repetitive action, the PWM control algorithm establishes a switch duty cycle to regulate a current or voltage in the load. The VC signal is integrated over many switching cycles and is an amplified version of the difference between the LED current sense voltage, measured between ISP and ISN, and the target difference voltage set by the CTRL pin and I2C input ADIM[7:0]. In this manner, the error amplifier sets the correct top switch peak current level to keep the LED current in regulation. If the error amplifier output increases, more current is demanded in the switch; if it decreases, less current is demanded. The analog input at CTRL pin together with the digital input ADIM[7:0] can be used to provide a combination of temperature foldback protection via CTRL and analog dimming via I2C, or a combination of analog dimming via CTRL pin and LED binning via I2C. In voltage feedback mode, the operation is similar to that described above, except the voltage at the VC node is set by the amplified difference of the internal reference of 1.18V (typi- cal) and the FB pin. If FB is lower than the reference voltage, the top switch current increases; if FB is higher than the reference voltage, the top switch demand current decreases. The LED current sense feedback interacts with the voltage feedback so that FB does not exceed the internal reference and the voltage between ISP and ISN does not exceed the threshold set by the product of the analog input at CTRL pin and the digital input ADIM[7:0] through I2C. For accurate current or voltage regulation, it is necessary to ensure that under normal operating conditions, the appropriate loop is dominant. To deactivate the voltage loop entirely, FB can be set between 0.3V and 1.08V through a resistor network to INTVCC pin. To deactivate the LED current loop entirely, the ISP and ISN should be tied together and CTRL tied to INTVCC. Tw o LED specific functions featured on the LT3964 are controlled by the voltage feedback FB pin. First, when the FB pin exceeds a voltage 53mV lower (–4%) than the FB regula- tion voltage and V(ISP-ISN) is less than 10mV (Typical), the OPENLED bit, STATUS[1] or STATUS[5], is set in the chan- nel status register. This function provides a status indicator that the load may be disconnected and the constant-voltage feedback loop is taking control of the switching regulator. When the FB pin drops below 0.25V (typical) after start- up, the SHORTLED bit, STATUS[2] or STATUS[6], is set by comparator A8. A blanking period occurs during start-up for the SHORTLED protection feature from the EN/UVLO toggle. LT3964 features a PMOS disconnect switch driver. The PMOS disconnect switch can be used to improve the PWM dimming ratio, and operate as fault protection as well. Once a fault condition is detected, the PWMTG pin is pulled high to turnoff the PMOS switch. The action isolates the LED array from the power path, preventing excessive current from damaging the LEDs. The I 2C interface is used to communicate between LT3964 and a microprocessor. LT3964 receives digital PWM dimming and analog dimming commands from a microprocessor and sends back the chip status, i.e., FB overvoltage (FB > 1.233V), output short (FB < 0.25V) after start-up, LED overcurrent (V (ISP-ISN) > 930mV), OPENLED (FB > 1.127V and (V(ISP-ISN) < 10mV).
requirements of an application. I2C address pins are grounded, i.e. ADDR1 = ADDR2 = GND). command is received via I2C interface. PWM pin input signal rising edge after power-on reset.
- ADIM[7:0]+1 256 ,VCTRL >1.3V ILED = VCTRL – 0.2V 10 •RLED
- ADIM[7:0]+1 256 ,0.2V < VCTRL <1.1V ILED = 0,VCTRL < 200mV When the CTRL pin voltage is between 1.1V and 1.3V, the LED current varies with CTRL, but departs from the previous equation by an increasing amount as the CTRL voltage increases. Ultimately, above 1.3V, the LED current no longer varies with CTRL. The typical V(ISP-ISN) threshold vs CTRL in terms of ADIM[7:0] is listed in Table 1.
Table 1. V(ISP-ISN) Threshold vs CTRL in Terms of ADIM[7:0] the amplitude of this ripple should be less than ±5mV. Figure 1. Setting CTRL with NTC Resistors
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Table 2. Channel 1 Analog Dimming Register Table 3. RT Resistance Range frequency 10% lower than the external clock frequency. waveform will ensure proper operation of this feature. CLKOUT function is disabled initially after power on reset. pin is only meant to drive capacitive loads up to 50pF.
required on-time is greater than the minimum on-time. even at the highest switching frequency. featured in Table 4 are recommended sources of inductors. Table 4. Inductor Manufacturers good starting values, see the Typical Applications section. Consult factory applications for more detailed information. of voltage bias and temperature.
For more information www.linear .com/L T3964 3964fb APPLICATIONS INFORMATION Table 5. Capacitor Manufacturers with dynamic and time-varying output loads that have no output capacitor, the 2nd pole has to be formed between 10kHz and 40kHz with the LED sensing resistor R LED as shown in Figure 2. The time constant of the 2nd pole is C FIL T(RLED + R FIL T). ISN pin has typical 30μA loading current. To keep ISP-ISN threshold DC offset less than 0.6mV (typical), RFIL T has to be less than 20Ω. Figure 2. Forming 2nd Pole with RLED switching current into a tight local loop, minimizing EMI. placed close to the LT3964 (see the PCB Layout section). concerns the maximum input voltage rating of the LT3964. be easily avoided (see Analog Devices Application Note 88). with a minimum of 2.2μF X7R or X5R ceramic capacitor. required by the power MOSFET gate drivers. higher power dissipation across the LDO. LT3964 will draw less than 1μA. bypass the LT3964 and will easily handle the ripple current.
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relationship of TSET voltage to junction temperature. Figure 3. EN/UVLO Resistor Configuration Figure 4. Programming the TSET the LEDs current will be reduced to approximately zero. resolution this way than by varying the current level. applications or other grounded-chassis systems. Figure 5. TSET Pin Threshold vs Junction Temperature
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than the maximum LED string voltage. high, and the ALERT pin is also asserted. loads, a 100nF capacitance is recommended at output node. rating of the Schottky has to be higher than maximum VIN. is included to disable this feature. Figure 6. Catch Diode for Short Circuit Protection with Table 6. PMOS Manufacturers Figure 7. FB Resistor Configuration for Applications
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Figure 9. PWMTG Response to Short Circuit Fault 1, and the ALERT pin is also asserted. Channel 2) in the chip status register is set at the same time. Figure 6. LT3964 also monitors output overcurrent (V(ISP- is set and ALERT pin will be pulled low simultaneously. power path as shown in Figure 9. Figure 10. Hiccup Response to Short Circuit Fault in I2C Mode Figure 11. Hiccup Response to Short Circuit Fault in Non-I2C Mode Figure 8. Output Clamp for Applications with No
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is de-asserted in non-I2C mode.
pin must be toggled low to high.
- The buck output voltage is almost equal to VIN supply;
if VIN drops to a level where the LED V f is close to V IN. the top switch, as shown in Figure 13. Figure 12. Latch-off Response to a Short Circuit Fault a ground fault on the supply when the output is charged.
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Figure 13. Reverse Input Current Protection
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this fault by pulling down the ALERT pin. Table 7. Chip Status Register Table 8. Chip Status Enable Register if the corresponding STATUS bit is not cleared.
times if it were allowed to interrupt the soft-start sequence. as designated by PWM pin input or PWM input via I2C. is defined by CH1_ON[5:0]/64. aligned up with the internal clock. significance of each bit (CH1_ON[bit] or CH2_ON[bit]). Table 9. Channel 1 (CH1) PWM Register 1 (CH1PWM1) ON TIME. FREQ Denotes PWM Frequency.
Table 10. Channel 1 (CH1) PWM Register 2 (CH1PWM2) Table 11. Chip Configuration Register Table 12. I2C PWM Dimming Setting Table 13. Stretch Ratio of Each PWMON Bit Figure 14. BAM Example
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transitioning SDA from HIGH to LOW while SCL is HIGH. communication with another I2C device. most significant bit (MSB) first. LOW during the HIGH period of this clock pulse. between ADDR2 and ADDR1 pin states and addresses. Table 14. Slave Address Map (110 A3 A2 A1 A0 R/W) *Non-I2C Mode: Internal PWM Dimming Function is Disabled.
For more information www.linear .com/L T3964 3964fb APPLICATIONS INFORMATION I2C Sub-Addressed Writing The LT3964 has 9 command registers that can be accessed by the I2C port via a sub-addressed writing system. Each write cycle of the LT3964 consists of a series of three bytes beginning with the LT3964 write address. The second byte is the sub-address of the command register being written to. The sub-address is a pointer to the register where the data in the third byte will be stored. The third byte is the data to be written to the just-received sub-address. I2C Bus Write Operation The master initiates communication with the LT3964 with a START condition and the LT3964 write address. If the address matches that of the LT3964, the LT3964 returns an acknowledge pulse. The master should then deliver the sub-address. Again the LT3964 acknowledges and the cycle is repeated for the data byte. The data byte is transferred to an internal holding latch upon the return of its acknowledgement by the LT3964. If desired a REPEAT- START condition may be initiated by the master where another device on the I 2C bus is addressed. The LT3964 remembers the valid data it has received. Once all the devices on the I 2C have been addressed and sent valid data and a global STOP has been sent, the LT3964 will update its command latches with the data it has received. Figure 16 shows the LT3964 I 2C serial port write pattern. I2C Sub-Addressed Reading The LT3964 I2C interface supports random address reading of the I2C command and status registers. Before reading a register, the register’s sub-address must be written. Send a START condition followed by the LT3964 write address followed by the sub-address of the register to be read. The sub-address is now stored as a pointer to the register. Send a REPEAT-START condition followed by the LT3964 read address. Following the acknowledgment of its read address the LT3964 returns one bit of information for each of the next 8-clock cycles. A STOP condition is not required for the read operation. The read sub-address is stored until a new sub-address is written. Verify the data written to the internal data hold latches prior to commit- ting data to the command registers by reading back the data before sending a STOP condition. Continuously poll a register by repeatedly sending a START condition followed by the LT3964 read address, and then clocking the data out after the read address acknowledge. Figure 17 shows the LT3964 I 2C serial port read pattern. I2C Command and Status Registers There are nine I 2C command/status registers and three read-only I2C part number registers in the LT3964. All of the information for these registers is shown in Tables 15. I2C Broadcast (BCMODE) The BCMODE write command (0001 1000) is used to synchronize the PWM dimming cycles among the multiple LT3964 slaves on the I 2C bus. The LT3964 slaves must be operating with a common external clock in order to be synchronized. The command does not modify any register bits. It only resets each channel counter to synchronize the dimming cycles.
Figure 15. I2C Serial Port Timing Figure 16. LT3964 I2C Serial Port Multiple Write Pattern Figure 17. LT3964 I2C Serial Port Read Pattern Figure 18. LT3964 I2C Serial Port Broadcast Read Pattern
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0 A 3 A2 A1 A0 0
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Table 15. LT3964 Command Register Table
For more information www.linear .com/L T3964 3964fb APPLICATIONS INFORMATION The BCMODE read command (0001 1001) is used to inquire about which LT3964 slave on the bus is sending the alert (see Alert Response Protocol section for details). This command is two bytes long. The first byte is the broadcast read address 00011001. The second byte 110A3A2A1A00 is sent by the alerting slave, where A3A2A1A0 is an input logic value from the programmable address select pins ADDR2 and ADDR1 shown in Table 14. Figure 18 shows LT3964 BCMODE read pattern. ALERT RESPONSE PROTOCOL In a system where several slaves share a common interrupt line, the master can use the alert response address (ARA) to determine which device initiated the interrupt. The master initiates the ARA procedure with a START condition and the special 7-bit ARA bus address (0001100) followed by the read bit (R) = 1. If the LT3964 is asserting the ALERT pin, it acknowledges and responds by sending its 7-bit bus address (110A3A2A1A0) and a 0. While it is sending its address, it monitors the SDA pin to see if another device is sending an address at the same time using standard I2C bus arbitration. If the LT3964 is sending a 1 and reads a 0 on the SDA pin on the rising edge of SCL, it assumes another device with a lower address is sending and the LT3964 immediately aborts its transfer and waits for the next ARA cycle to try again. If transfer is successfully completed, the LT3964 will de-assert its ALERT pin and will not respond to further ARA requests until a new alert event occurs. DESIGNING THE PRINTED CIRCUIT BOARD For proper operation and minimum EMI, care must be taken during printed circuit board layout. Usually, large switched currents flow through the local input capacitors and the V IN and GND pins. The loops traveled by these currents should be made as small as possible by keeping the capacitors as close as possible to these pins. These capacitors, as well as the large inductor, should be placed on the same side of the board as the LT3964 and connected on the same layer. Other large, bulk input capacitors can be safely placed farther from the chip and on the other side of the board. Create a Kelvin ground network by keeping the ground connection for all of the other components separate. It should only join the ground for the input and output capacitors and the return path for the LED current at the exposed pad. To keep thermal resistance low, extend the ground plane as much as possible, and thermal vias under and near the LT3964 to additional ground planes within the circuit board and on the bottom side. There are a few other aspects of the board design that improve performance. Likewise minimizing the area of the SW and BST nodes reduces noise. The traces for FB pins should be kept short to lessen the susceptibility of these high impedance nodes to noise. Minimizing the con- nections from the external current sense resistor RLED to the ISP and ISN pins are essential for current regulation accuracy. The INTVCC bypass capacitor as well as the BST capacitor should be placed as closely as possible to their respective pins. Figure 19 shows the simplified two sided layout of power component placement with traces, ground plane and via locations. Note that the 4-layer layout is recommended for best performance. Please contact the factory for the reference layout design.
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Figure 19. Simplified Layout for Dual Buck LED Driver
For more information www.linear .com/L T3964 3964fb TYPICAL APPLICATIONS Short-LED Robust, 50W Dual Buck 1A LED Driver with Internal PWM Dimming PWM Dimming at VIN = 34V PWM DC = 4/8192 PWM DC = 6/8192 1µs/DIV I LED2 1A/DIV I 1A/DIV I LED1 1A/DIV I 1A/DIV
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10µH CBST1 0.22µF RFB1 RLED1 100mΩ COUT1 2.2µF 50V UP TO 26V LEDs RFB2 43.2k 100k 27.4k 2MHz CIN2 2.2µF 50V 10µH CBST2 0.22µF RFB3 RLED2 100mΩ COUT2 2.2µF 50V CIN1 2.2µF 50V REN1 100k RTSET1 499k 2.2µF BST1 L T3964 SW1 V IN1 ISP1 ISN1 PWMTG1 CTRL1 BST2 SW2 ISP2 ISN2 PWMTG2 UP TO 26V LEDs GND EN/UVLO CTRL2 PWM1 PWM2 INTVCC ALERT V IN2 GND T SET RT SCL SDA 2-WIRE I2C INTERFACE ADDR1 ADDR2 SYNC/CLKOUT INTV CC INTVCC INTVCC FB1 FB2 RFB4 43.2k REN2 3.92k RTSET2 165k 31V TO 36V (ENABLED AT 33V , SHUTDOWN AT 31V) CIN0 10µF 50V
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L1, L2: WURTH 74437349100 M1, M2: VISHAY Si2319CDS
For more information www.linear .com/L T3964 3964fb 10µH CBST1 0.22µF RFB3 RLED1 100mΩ COUT3 2.2µF 50V UP TO 26V LEDs RFB4 43.2k 10µH CBST2 0.22µF RFB5 RLED2 100mΩ COUT4 2.2µF 50V CIN2 2.2µF 50V REN3 100k RTSET1 499k 100k 2.2µF 27.4k 2MHz CIN3 2.2µF 50V BST1 L T3964 SW1 V IN1 ISP1 ISN1 PWMTG1 PWM1 BST2 SW2 ISP2 ISN2 PWMTG2 UP TO 26V LEDs GND EN/UVLO PWM2 CTRL1 CTRL2 CTRL CTRL INTV CC ALERT V IN2 GND T SET RT SCL SDA 2-WIRE I2C INTERFACE ADDR1 ADDR2 SYNC/CLKOUT INTV CC INTV CC INTV CC FB1 FB2 RFB6 43.2k REN4 3.92k RTSET2 165k L T3757 V IN GATE SENSE FBX INTV CC SHDN /UVLO SYNC SS RT VC GND VIN 6V TO 24V ILED DERATES AT VIN < 8V 34.5V REN1 105k REN2 28k L1 10µH CIN1 10µF CSS 0.1µF 41.2k 300kHz RCTRL1 100k RCTRL1 17.4k 10k 10nF RFB1 261k RFB2 11.8k 4.7µF RSEN 10M COUT1 47µF 50V COUT 4.7µF 50V CTRL
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L1: VISHAY SILICONIX IHLP-5050FD-01 10/uni03BCH L2, L3: WURTH 74437349100 M1: INFINEON BSC030N04NS M2, M3: VISHAY Si2319CDS D1: DIODES PDS1040 TYPICAL APPLICATIONS Multi-Channel Boost Buck LED Driver Efficiency V IN (V) EFFICIENCY (%) Efficiency
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For more information www.linear .com/L T3964 3964fb Matrix LED Driver TYPICAL APPLICATIONS 68µH C BST1 0.22µF R FB3 274k 31.6k R FB2 R LED2 200mΩ C IN2 2.2µF 100k R EN1 3.92k R EN2 499k R TSET1 165k R TSET2 2.2µF C IN3 2.2µF 178k R LED1 200mΩ 68µH C BST2 0.22µF R FB6 274k 31.6k R FB5 C IN4 1µF C IN6 1µF R EN3 49.9k R EN4 9.02k C IN5 1µF 100k C IN7 1µF C OUT2 10µF C OUT4 10µF R FB1 R FB4 C OUT1 100nF C OUT3 100nF R EN5 49.9k R EN6 9.02k R EN8 10k C IN1 10µF BST1 L T3964 SW1 V IN1 ISP1 ISN1 PWMTG1 CTRL1 BST2 SW2 ISP2 ISN2 PWMTG2 GND EN/UVLO CTRL2 PWM1 PWM2 INTVCC ALERT V IN2 GND TSET RT SCL SDA 2-WIRE I2C INTERFACE ADDR1 ADDR2 SYNC/CLKOUT 360kHz INTVCC INTVCC INTVCC FB1 FB2 L T3965 DRN8 SRC8 DRN7 SRC7 DRN6 SRC6 DRN5 SRC5 DRN4 SRC4 DRN3 SRC3 DRN2 SRC2 DRN1 SRC1 L T3965 DRN8 SRC8 DRN7 SRC7 DRN6 SRC6 DRN5 SRC5 DRN4 SRC4 DRN3 SRC3 DRN2 SRC2 DRN1 SRC1 SCL SDA 2-WIRE I2C INTERFACE SCL SDA 2-WIRE I2C INTERFACE ADDR1 ADDR2 ADDR3 ADDR4 31V TO 36V (ENABLED AT 33V , SHUTDOWN AT 31V) V IN V IN EN/UVLO EN/UVLO ADDR1 ADDR2 ADDR3 ADDR4 31V TO 36V 31V TO 36V VDD ALERT VDD ALERT RTCLK GND CLOCK (FROM L T3964) GND CLOCK LEDREF LEDREF LEDREF LEDREF RTCLK CLOCK (FROM L T3964) ALERT ALERT ALERT INTVCC LED1+ LED2+ LED1+ LED2+ UP TO 26V LED UP TO 26V LED 50V 50V 50V 50V 50V 50V 50V R EN7 10k INTVCC
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L1, L2: WURTH 7447709680 M1, M2: VISHAY Si2319CDS Single LED PWM Dimming at VIN = 34V at VIN = 34V PWM DC = 1/256 5µs/DIV V CLKOUT 5V/DIV V DRAIN8 2V/DIV I LED1 500mA/DIV I 500mA/DIV
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Efficiency, VIN = 34V I LED (mA) 100 150 200 250 300 350 400 450 500 100 EFFICIENCY (%) IN
3964 TA04c
For more information www.linear .com/L T3964 3964fb PACKAGE DESCRIPTION 5.00 ±0.10 NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS PIN 1 TOP MARK (SEE NOTE 6) 1020 1119 3629 BOTTOM VIEW—EXPOSED PAD 4.50 REF6.00 ±0.10 R = 0.125 TYP 0.25 ±0.05 4.60 ±0.10 3.60 ±0.10 (UHE36) QFN 0410 REV Ø
0.50 BSC
4.60 ±0.05 3.60 ±0.05 0.75 ±0.05 0.00 – 0.05
0.200 REF
RECOMMENDED SOLDER PAD LAYOUT APPL Y SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
3.50 REF
0.40 ±0.10 0.70 ±0.05
4.50 REF
4.10 ±0.05 5.50 ±0.05 5.10 ±0.05 6.50 ±0.05 0.25 ±0.05 PACKAGE OUTLINE 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER R = 0.10 TYP 36-Lead Plastic QFN (5mm × 6mm) (Reference LTC DWG # 05-08-1876 Rev Ø) Please refer to http://www.linear.com/product/LT3964#packaging for the most recent package drawings.
For more information www.linear .com/L T3964 3964fb
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER A 12/17 Block Diagram: corrected MOSFET symbol orientation for top switch, bottom switch and M1 MOSFETs. 12 B 3/18 Note 2: RT pin added. 5 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
For more information www.linear .com/L T3964 3964fb LT 0318 REV B • PRINTED IN USA www.linear .com/L T3964 © ANALOG DEVICES, INC. 2017 RELATED PARTS TYPICAL APPLICATION Dual 1A Single LED Driver Efficiency, ILED = 1A V IN (V) EFFICIENCY (%) LED
3964 TA05b
2.2µH CBST1 0.22µF RFB1 RLED1 100mΩ COUT1 2.2µF RFB1 357k 100k 27.4k 2MHz CIN2 2.2µF CBST2 0.22µF RFB3 RLED2 100mΩ COUT2 2.2µF CIN1 2.2µF REN1 100k RTSET1 499k 2.2µF BST1 L T3964 SW1 V IN1 ISP1 ISN1 PWMTG1 CTRL1 BST2 SW2 ISP2 ISN2 PWMTG2 GND EN/UVLO CTRL2 PWM1 PWM2 INTVCC ALERT V IN2 GND T SET RT SCL SDA ADDR1 ADDR2 SYNC/CLKOUT INTV CC INTVCC FB1 FB2 RFB4 357k REN2 28.7k RTSET2 165k 2.2µH INTV CC 2-WIRE I2C INTERFACE CIN3 10µF 6V TO 24V (ENABLED AT 6V , SHUTDOWN AT 5.2V)
3964 TA05a
L1, L2: COILCRAFT XAL4020-222MEB M1, M2: VISHAY Si2365EDS PART NUMBER DESCRIPTION COMMENTS LT3922 36V, 2A Synchronous Step-Up LED Driver VIN(MIN) = 2.8V, VIN(MAX) = 36V, VOUT = 40V, 128:1 Internal Dimming and 5,000:1 External Dimming, ISD = 1μA, 4mm × 5mm QFN-28 LT3932 36V, 2A Synchronous Step-Down LED Driver VIN(MIN) = 3.6V, VIN(MAX) = 36V, VOUT = 0V to 36V, 128:1 Internal Dimming and 5,000:1 External Dimming, ISD = 1μA, 4mm × 5mm QFN-28 LT3952 60V, 4A Synchronous Step-Up LED Driver VIN(MIN) = 3V, VIN(MAX) = 42V, VOUT = 0V to 60V, 5:1 Internal Dimming and 4,000:1 External Dimming, ISD = 1μA, TSSOP-28E LT3795 High Side 110V, 1MHz LED Driver with 3,000:1 PWM Dimming with Spread Spectrum Frequency Modulation VIN(MIN) = 4.5V, VIN(MAX) = 110V, VOUT = 110VMAX, 3000:1 PWM, 20:1 Analog, ISD = <1µA, TSSOP-28E LT3956 80VIN/80VOUT, ISW = 3.3A, 1MHz LED Driver with 3,000:1 PWM Dimming VIN(MIN) = 4.5V, VIN(MAX) = 80V, VOUT = 40VMAX, 3000:1 PWM, 20:1 Analog, ISD = <1µA, 5mm × 6mm QFN-36 LT3761 High Side 100V, 1MHz LED Controller with 3,000:1 PWM Dimming and Internal PWM Generator VIN(MIN) = 4.5V, VIN(MAX) = 60V, VOUT = 80VMAX, 3000:1 PWM, 20:1 Analog, ISD = <1µA, MSOP-16E LT3755/ LT3755-1/ LT3755-2 High Side 75V, 1MHz LED Controller with 3,000:1 PWM Dimming V IN(MIN) = 4.5V, VIN(MAX) = 40V, VOUT = 5V to 75V, 3000:1 PWM, 20:1 Analog, ISD = <1µA, 3mm × 3mm QFN-16 and MSOP-16E LT3756/ LT3756-1/ LT3756-2 High Side 100V, 1MHz LED Controller with 3,000:1 PWM Dimming V IN(MIN) = 6.0V, VIN(MAX) = 100V, VOUT = 5V to 100V, 3000:1 PWM, 20:1 Analog, ISD = <1µA, 3mm × 3mm QFN-16 and MSOP-16E