LT3960_V01 AD | Alldatasheet
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Rev. BFor more information www.analog.com Document Feedback TYPICAL APPLICATION FEATURES DESCRIPTION I2C to CAN-Physical Transceiver The LT®3960 is a robust high speed transceiver that extends a single-master I2C bus through harsh or noisy environments at up to 400kbps using the CAN-physical layer . One LT3960 sits near the I2C master , creating from SCL and SDA equivalent differential buses (I 2CAN) on two twisted pairs. At the other end of the twisted pairs, a second LT3960 recreates the I2C bus locally for any slave I2C devices. A built-in 3.3V LDO powers both the I2C and I2CAN buses from a single input supply from 4V to 60V. Alternatively, the LT3960 can be powered directly from a 3.3V or 5V supply. The LT3960 is available in a 10-lead MSOP package. I2CAN Bus Link with Large Ground Loop Voltage
APPLICATIONS
n Protected from Overvoltage Line Faults to ±40V n Up to 400kbps I2C Communications n 4V to 60V Power Supply Range with Internal 3.3V Regulator n 3.3V or 5V Bus Voltage n Extended Common Mode Range (±36V) n Current Limited Drivers with Thermal Shutdown n Power-Up/Down Glitch Free Driver Outputs n Low Current Shutdown Mode n T ransmit Data Dominant Timeout Function n E- and J-Grades Available n Available in a 10-Lead MSOP Package n AEC-Q100 Qualification in Progress n Industrial Networking n Automotive Networking n Remote Sensors All registered trademarks and trademarks are the property of their respective owners. 120/uni03A9 2.2µF 10k 10k120/uni03A9 120/uni03A9120/uni03A9 2.2µF 10k 10k L T3960 VIN
3960 TA01
3.3VCANSDAH CANSDAL CANSCLH CANSCLL GND L T3960 VIN VCC SDA SCL EN/MODE VCC VIN 4V TO 60V CANSDAH CANSDAL CANSCLH CANSCLL GND GND1 GND2 AC GROUND LOOP ≤ 36V PEAK (VCC = 5V) < 25V PEAK (VCC = 3.3V) SDA SCL FLOAT = SLAVE SDA SCL HIGH = MASTER Receiving I2C T raffic Across ±25V Common-Mode Differential 10µs/DIV SDA(MASTER) 5V/DIV SDA (SLAVE) 5V/DIV GND1–GND2 20V/DIV
3960 TA01b
POWERED BY INTERNAL LDO (VCC = 3.3V)
Rev. B For more information www.analog.com ABSOLUTE MAXIMUM RATINGS CANSDAH, CANSDAL, CANSCLH, Operating Junction Temperature Range (Notes 1, 2, 3) ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3960EMSE#PBF LT3960EMSE#TRPBF L THJP 10-Lead Plastic MSOP –40°C to 125°C LT3960JMSE#PBF LT3960JMSE#TRPBF L THJP 10-Lead Plastic MSOP –40°C to 150°C AUTOMOTIVE PRODUCTS** LT3960EMSE#WPBF LT3960EMSE#WTRPBF L THJP 10-Lead Plastic MSOP –40°C to 125°C LT3960JMSE#WPBF LT3960JMSE#WTRPBF L THJP 10-Lead Plastic MSOP –40°C to 150°C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. **Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. PIN CONFIGURATION CANSDAL CANSDAH GND CANSCLH CANSCLL SDA SCL VCC EN/MODE VIN GND TOP VIEW MSE PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 40°C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
Rev. BFor more information www.analog.com
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Low Dropout Regulator VIN Input Voltage Operating Range VCC Regulated Internally from VIN VIN Tied to VCC, 3.3V Range VIN Tied to VCC, 5V Range l l l 4.5 3.6 5.5 V V V IIN(SD) VIN Shutdown Current EN/MODE = 0V 20 26 µA VCC LDO Regulation Voltage 4V ≤ VIN ≤ 60V, ILDO = 1mA 3.1 3.3 3.5 V VLINE LDO Line Regulation 4V ≤ VIN ≤ 60V, ILDO = 1mA 0.05 %/V VLOAD LDO Load Regulation 0.1mA < ILDO < 100mA 0.05 %/mA VCC,LOW LDO Voltage at Low VIN ILDO = 85mA, VIN = 4V 3 V ILIMCC LDO Current Limit LDO Foldback Current Limit VCC = 3.0 VCC = 0.5V 100 130 160 mA mA VUVLO VCC Undervoltage Lockout Threshold VCC Undervoltage Lockout Hysteresis VCC Falling l 2.6 2.7 2.9 V mV ICC VCC Shutdown Supply Current VCC Operating Supply Current EN/MODE = 0V, VCC = VIN EN/MODE ≥ 0.7V, VCC = VIN 4.2 mA mA EN/MODE Selection VSHDN EN/MODE Shutdown Threshold Falling l 400 700 800 mV VSHDN-HYS EN/MODE Shutdown Hysteresis 50 mV VMSTR EN/MODE Master Threshold l 1.9 2 2.2 V IEN-UP EN/MODE Pin Bias Current Low EN/MODE = 350mV 2 µA CAN Drivers VO(D) Bus Output Voltage (Dominant) CANxH t < tTO:CAN VCC = 3.3V l 2.15 2.9 3.3 V VCC = 5V l 2.75 3.6 4.5 V CANxL t < tTO:CAN VCC = 3.3V l 0.5 0.9 1.65 V VCC = 5V 0.5 1.4 2.25 V VO(R) Bus Output Voltage (Recessive) VCC = 3.3V, No Load (Figure 1) VCC = 5V, No Load (Figure 1) l l 1.45 1.95 2.5 2.45 V V VOD(D) Differential Output Voltage (Dominant) RL = 50Ω to 65Ω VCC = 3.3V l 1.5 2.2 3 V VOD(D) Differential Output Voltage (Dominant) VCC = 5V 2.7 3.1 3.5 V VOD(R) Differential Output Voltage (Recessive) No Load (Figure 1) l –500 0 50 mV VOC(R) Common Mode Output Voltage (Dominant) VCC = 3.3V, (Figure 1) VCC = 5V, (Figure 1) l l 1.45 1.95 2.5 2.45 V V IOS(D) Bus Output Short-Circuit Current (Dominant) CANxH CANxH = 0V l –150 –75 –40 mA CANxH –40V < CANxH < VO(R) l –150 3 mA CANxL CANxL = 5V l 25 75 100 mA CANxL VCC < CANxL < 40V l –3 100 mA The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VCC = 3.3V, Figure 1 Applies with RPU = 4.99k, RL = 60Ω, EN/MODE = VCC, TYP values unless otherwise specified.
Rev. B For more information www.analog.com SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CAN Receivers VCM Bus Common Mode Voltage = (CANxH+CANxL)/2 for Data Reception VCC = 3.3V VCC = 5V l l ±25 ±36 V V VTH+ Bus Input Differential Threshold Voltage (Positive Going) VCC = 3.3V, –25V ≤ VCM ≤ 25V VCC = 5V, –36V ≤ VCM ≤ 36V l l 775 775 900 900 mV mV VTH– Bus Input Differential Threshold Voltage (Negative Going) VCC = 3.3V, –25V ≤ VCM ≤ 25V VCC = 5V, –36V ≤ VCM ≤ 36V l l 500 500 625 625 mV mV ∆VTH Bus Input Differential Hysteresis Voltage VCC = 3.3V, –25V ≤ VCM ≤ 25V VCC = 5V, –36V ≤ VCM ≤ 36V 150 150 mV mV RIN Input Resistance (CANxH and CANxL) SCL = SDA = VCC; RIN = ∆V/∆I; ∆I = ±20 µA l 25 35.7 50 kΩ RID Differential Input Resistance SCL = SDA = VCC; RIN = ∆V/∆I; ∆I = ±20 µA l 50 71.4 100 kΩ ∆RIN Input Resistance Matching RIN (CANxH) to RIN (CANxL) l ±3 % CIH Input Capacitance to GND (CANxH) (Note 4) 32 pF CIL Input Capacitance to GND (CANxL) (Note 4) 8 pF CID Differential Input Capacitance (Note 4) 8.4 pF IL Bus Leakage Current (Power Off) VCC = 0V, CANxH = CANxL = 5V ±10 µA VCC = 0V, CANxH = CANxL = 5V, t < 150°C l ±50 µA I2C Port VIL SDA, SCL Input Low Voltage l 0.4 V VIH SDA, SCL Input High Voltage l 1.5 V Ii SDA, SCL Input Leakage Current SDA = SCL = 0V to 5.5V –50 50 nA Vhys SDA, SCL Input Hysteresis l 0.05 • VCC V VOL1 SDA, SCL Output Low Voltage ISDA = 3mA l 0.4 V tr Clock/Data Rise Time CB = Capacitance of One Bus Line (pF) (Note 5) 20 + 0.1CB 300 ns tf Clock/Data Fall Time CB = Capacitance of One Bus Line (pF) (Note 5) 20 + 0.1CB 300 ns The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VCC = 3.3V, Figure 1 applies with RPU = 4.99k, RL = 60Ω, EN/MODE = VCC, TYP values unless otherwise specified.
Rev. BFor more information www.analog.com SWITCHING CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Transceiver Timing fSCL SCL Clock Frequency (Notes 5,6) l 0 400 kHz tPI2CBD I2C to I2CAN Dominant Propagation Delay (Figure 2, Figure 3) VCC = 3.3V l 45 80 130 ns VCC = 5V l 45 75 115 ns tPI2CBR I2C to I2CAN Recessive Propagation Delay (Figure 2, Figure 3) VCC = 3.3V l 80 120 170 ns VCC = 5V l 60 90 120 ns tPBI2CD I2CAN Dominant to I2C Propagation Delay (Figure 2, Figure 3) VCC = 3.3V l 25 40 65 ns VCC = 5V l 25 40 65 ns tPBI2CR I2CAN Recessive to I2C Propagation Delay (Figure 2, Figure 3) VCC = 3.3V l 25 45 80 ns VCC = 5V l 20 35 60 ns tTO;CAN I2CAN Dominant Timeout Time (Figure 2, Figure 4) l 0.5 1.5 2 ms tEN;I2C I2C Driver Enable from Shutdown VCC = 3.3V or 5V (Figure 2, Figure 5) l 40 µs tEN;CAN I2CAN Driver Enable from Shutdown VCC = 3.3V or 5V (Figure 2, Figure 6) l 40 µs tSHDN;I2C Time to Shutdown, I2C (Figure 2, Figure 5) l 500 ns tSHDN;CAN Time to Shutdown, I2CAN (Figure 2, Figure 6) l 500 ns The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VCC = 3.3V, Figure 2 applies with RPU = 4.99k, RL = 60Ω, EN/MODE = VCC, TYP values unless otherwise specified. Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3960E is guaranteed to meet specified performance from 0°C to 125°C. Specifications over the –40°C to 125°C operating temperature range are assured by design, characterization and correlation with statistical process controls. The LT3960J is guaranteed to meet performance specifications over the full –40°C to 150°C operating junction temperature range. High junction temperatures degrade operating lifetimes. Operating lifetime is derated at junction temperatures greater than 125°C. Note 3: The LT3960 includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed the maximum operating junction temperature when overtemperature is active. Continuous operating above the specified maximum operating junction temperature may impair device reliability. Note 4: Pin capacitance given for reference only and is not tested in production. Note 5: Rise and fall times are measured at 30% and 70% levels. Note 6: Maximum SCL clock frequency will be affected by delays through the twisted-pair interface and I/O circuitry of other devices on the bus. These delays may limit the operation frequency to below the LT3960 maximum specification. Note 7: The LT3960 does not support clock stretching. SCL should not be pulled low by slave devices.
Rev. B For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Supply Current (I2CAN Dominant) vs VCC Supply Current (I2CAN Recessive) vs VCC Supply Current (I2CAN Dominant) vs Temperature Supply Current (I2CAN Recessive) vs Temperature I2CAN Differential Output Voltage (Dominant) vs Temperature I2CAN Common Mode Voltage (Dominant) vs Temperature CANxH Short-Circuit Current (Dominant) vs CANxH Voltage CANxH Short-Circuit Current (Dominant) vs CANxH Voltage I2C to CAN Propagation Delay vs Temperature TA = 25°C, VCC = 3.3V, RPU = 60Ω unless otherwise noted. V CC (V) 3.5 4.5 5.5 I CC(D) (mA)
3960 G01
V CC (V) 3.5 4.5 5.5 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 I CC(R) (mA)
3960 G02
V CC = 5V V CC = 3.3V TEMPERATURE (˚C) –50 –25 100 125 150 I CC(D) (mA)
3960 G03
V CC = 3.3V TEMPERATURE (˚C) –50 –30 –10 110 130 150 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 I CC (mA)
3960 G04
V CC = 5V V CC = 3.3V TEMPERATURE (˚C) –50 –25 100 125 150 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 V OD(D) (V)
3960 G05
V CC = 5V V CC = 3.3V TEMPERATURE (˚C) –50 –25 100 125 150 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 V OC(D) (V)
3960 G06
V CC = 5V V CC = 3.3V CAN X H (V) –40 –35 –30 –25 –20 –15 –10 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 I CANXH(D) (mA)
3960 G07
V CC = 5V V CC = 3.3V CAN X L (V) 100 I CANXL(D) (mA)
3960 G08
TEMPERATURE (˚C) –50 –25 100 125 150 T PI2CB (ns)
3960 G09
Rev. BFor more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS CAN to I2C Recessive Propagation vs Temperature EN/MODE Shutdown Thresholds vs Temperature (VCC = 3.3V, 5V) EN/MODE Current vs Temperature (VEN/MODE = 0.35V) VIN Shutdown Current vs Temperature VIN Quiescent Current vs Temperature VCC vs Temperature (Various VIN) VCC vs Current (Various VIN) VCC UVLO vs Temperature VCC Current Limit vs VIN TA = 25°C, VCC = 3.3V, RPU = 60Ω unless otherwise noted. DOMINANT RECESSIVE TEMPERATURE (˚C) –50 –25 100 125 150 100 110 120 T PBI2C (ns)
3960 G10
TEMPERATURE (˚C) –50 –25 100 125 150 350 400 450 500 550 600 650 700 750 800 850 900 V SHDN (V)
3960 G11
TEMPERATURE (˚C) –50 –25 100 125 150 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 I EN–UP (/uni03BCA)
3960 G12
TEMPERATURE (˚C) –50 –25 100 125 150 I IN(SD) (/uni03BCA)
3960 G13
V IN = 12V V CC = EN = 5V TEMPERATURE (˚C) –50 –25 100 125 150 100 110 120 130 140 150 160 170 180 190 200 210 220 I IN(Q) (/uni03BCA)
3960 G14
I CC = 1mA V IN = 12V V IN = 24V V IN = 48V TEMPERATURE (°C) –50 –25 100 125 150 3.0 3.1 3.2 3.3 3.4 3.5 3.6 V CC (V) CC IN
3960 G15
V IN = 5V V IN = 12V V IN = 24V V IN = 48V V CC CURRENT (mA) 105 120 135 150 3.00 3.05 3.10 3.15 3.20 3.25 3.30 3.35 3.40 V CC (V) CC IN
3960 G16
TEMPERATURE (°C) –50 –25 100 125 150 2.66 2.68 2.70 2.72 2.74 2.76 2.78 2.80 V CC UVLO (V) CC
3960 G17
V IN (V) 100 120 140 160 ILIM CC (mA) V CC Current Limit vs V IN
3960 G18
Rev. B For more information www.analog.com PIN FUNCTIONS CANSDAL (Pin 1): Low Level CAN Bus Line. Carries the I2C data bus. CANSDAH (Pin 2): High Level CAN Bus Line. Carries the I2C data bus. CANSCLH (Pin 4): High Level CAN Bus Line. Carries the I2C clock bus. CANSCLL (Pin 5): Low Level CAN Bus Line. Carries the I2C clock bus. GND (Pin 3 and Exposed Pad) : Ground. Solder the exposed pad and pin directly to the ground plane. VIN (Pin 6): Input Voltage Supply. This pin is the power supply input to the LDO. It must be locally bypassed with a 1µF filter capacitor to GND as close to the pin as possi- ble. If the LDO function is unused, tie VIN to VCC. EN/MODE (Pin 7): MODE/Shutdown pin. Tie above 2.5V to select master mode, float pin to select slave mode, or pull this pin to ground for low-power shutdown mode. VCC (Pin 8): Low Dropout Regulator Output and Device Power Supply Input. Bypass this pin with a 2.2µF or greater capacitor to ground. Any bypass capacitors must be located as close to the pin as possible. SCL (Pin 9): Clock Input or Output Pin for the I 2C Serial Port. When EN/MODE is 2.5V or above, the SCL pin is an input for the master clock. When EN/MODE is float - ing, the SCL pin is an output for data received on the CANSCLH/L pins. SDA (Pin 10): Data Input and Output Pin for the I 2C Serial Port.
Rev. BFor more information www.analog.com BLOCK DIAGRAM 1.95V FOR VCC = 3.3V 2.5V FOR VCC = 5V SHUTDOWN SHUTDOWN 3960 BD CANSDAH CANSDAL35.7k 35.7k VCCVCC VCC VCC PREDRIVETX TIMEOUT READ/WRITE ARBITRATION SDA GND 1.1k1.1k 1.1k RPU VCC VCC RPU 1.1k CANSCLH CANSCLL VCC VIN VIN 4V TO 60V 35.7k 35.7k PREDRIVETX TIMEOUT MODE SELECT SCL EN/MODE I2C MASTER 3.3V0.5V 2.2/uni03BCF
3960 F01
3960 F02
Figure 1. All Electrical Characteristic Measurements Figure 2. All Switching Characteristic Measurements
3960 F03
Figure 3. T ransceiver Data Propagation Timing Diagram Figure 4. I2CAN Dominant Timeout Figure 5. I2CAN Enable and Disable Times Figure 6. I2CAN Enable and Disable Times
3960 F04
3960 F05
3960 F06
±36V, depending on VCC voltage. data signal is always permitted.
3960 F07
Figure 7. Simple Single-Slave Application
Rev. BFor more information www.analog.com Data T ransmission Detail The timing diagram in Figure 8 shows how a byte of data is sent by the I 2C master and acknowledged by the I 2C slave in the single-master single-slave system described in Figure 7. The I 2C master issues a start command to initiate a communication frame. The LT3960 connected to the master drives the CANSCL and CANSDA buses dom- inant in response to the change in state on the SCL and SDA pins without interpretation or delay. The LT3960 con- nected to the I2C slave receives the dominant signals on the CANSCL and CANSDA buses and drives the slave SCL and SDA pins dominant without interpretation or delay. The result on the slave I2C bus is an I2C Start command nearly identical to that generated by the master , delayed by propagation delays of the master LT3960, twisted pairs, and slave LT3960. As additional clock and data edges are written by the I2C master , they too are recreated, first on the CANSCL and CANSDA buses and then on the slave I 2C bus. Once the entire byte of data is written on the slave I2C bus, the I2C slave device issues an ACK, pulling down SDA to acknowl- edge receipt of a valid byte. The slave LT3960 recognizes that a slave I 2C device is driving the SDA line dominant and switches from receiving to transmitting to drive the CANSDA bus dominant. The master LT3960 then receives the ACK on the CANSDA bus and pulls the master SDA low, communicating the ACK to the master . Note that clock data is always transmitted from master to slave, but the LT3960 dynamically switches the direction of SDA communication based primarily on the time of arrival of dominant signals on its inputs. Bidirectional Arbitration of SDA The LT3960 facilitates bidirectional SDA communication between master and slave I 2C devices by dynamically controlling the direction of traffic between SDA and the CANSDA bus. The primary factor determining the direction of communication is the time of arrival of dominant sig - nals on SDA and CANSDA. The first of SDA and CANSDA to be asserted dominant by an external device will cause the LT3960 to drive the other dominant, establishing the direction of communication until it is released and returns to a recessive state. The transmitter which opposes the established direction of communication will be blocked until it can be safely re-enabled without locking up a bus or misinterpreting the direction of communication. To fully describe the method of arbitration, communication in each direction is described in detail below. In the default state, SDA and CANSDA are in a recessive state and no direction of communication is set. If SDA is asserted dominant (low) by an external I 2C device from a default state, the LT3960 will drive CANSDA dominant and the LT3960’s receiver on CANSDA is blocked from driving SDA. When the SDA line is eventually released by the external I2C device and returns to a recessive state, the LT3960 stops driving the CANSDA bus dominant. After allowing the CANSDA bus sufficient time to return to a passive state as required by the CAN physical layer specifications, the LT3960 reopens the possibility of bidi- rectional traffic and waits for a dominant signal on SDA or CANSDA to once again set a direction for communication. If, from the default state, CANSDA is asserted dominant by another LT3960 on the bus while SDA remains reces- sive (high), the LT3960 will drive SDA dominant (low) and the CAN transmitter is blocked from driving CANSDA based on its input while CANSDA is held dominant. When the CANSDA bus returns to a recessive state, the LT3960 stops driving the other dominant. When it is safe to do so without causing glitches or latch up, the LT3960 reopens the possibility of bidirectional traffic and waits for a dom- inant signal on SDA or CANSDA to once again set a direc- tion for communication. OPERATION
Figure 8. Simple Single-Slave Application
3960 F08
Rev. BFor more information www.analog.com Supply Voltage Ranges The LT3960 can be operated with or without using its internal LDO. Tying VIN to VCC and powering directly from a 3.3V or 5V supply will bypass the LDO. With a 5V supply on VCC, transmitter common-mode voltage and receiver common-mode input range are increased from their 3.3V values. In this configuration, an internal comparator mon- itors the supply voltage and switches internal reference voltages and output drive strengths at approximately 4.1V. Operation with a supply between 3.6V and 4.5V is not recommended, because of the discontinuity in the internal voltages at this switch point. When using the internal LDO to generate the 3.3V bus supply on V CC, any V IN supply voltage between 4V and 60V is allowed. In this configuration, the switch point mentioned above is avoided since V CC is regulated to a fixed 3.3V. An LT3960 operating with a VCC at 5V may share an I2CAN bus with an LT3960 operating with VCC at 3.3V. However , the fluctuation in common mode voltage between 1.95V (when an LT3960 with V CC = 3.3V is dominant) and 2.5V (when an LT3960 with V CC = 5V is dominant) may increase electromagnetic emissions. Master and Slave Mode Configurations The LT3960 connected to the I 2C master must be oper- ated in Master Mode, with the EN/MODE pin driven greater than 2.5V. When operating in Master Mode, it is recom - mended that V CC be tied to V IN and driven from a bus voltage of 3.3V or 5V. Additionally, EN/MODE should be driven from a digital output pin from the I 2C Master as shown below. In this configuration, EN/MODE can be held low until the VCC cap is fully charged. Do not tie the EN/MODE pin directly to V CC when oper- ating in Master Mode. With EN/MODE and V CC shorted, every power-up sequence will set the LT3960 into slave mode for many microseconds while the V CC capacitor charges between the enable threshold and the Master Mode threshold. APPLICATIONS INFORMATION Figure 9. L T3960 VIN VCC VCC 3.3V OR 5V BUS VOL TAGE EN/MODE I/O µCONTROLLER 30k 2.2µF
3960 F09
Recommended Master Mode Power Setup An LT3960 connected to slave I2C devices must be oper- ated in Slave Mode, with the EN/MODE pin between 0.7V and 2V. When left floating, the EN/MODE pin will pull up to approximately 1.2V, enabling the LT3960 and set - ting it in Slave Mode, whenever the V IN pin is powered above approximately 2V. It is recommended that the EN/ MODE pin be left floating for Slave Mode LT3960 devices, regardless of whether the internal LDO is employed. LT3960 and Standard CAN T ransceivers It should be noted that while the LT3960 uses the CAN physical layer to conduct bidirectional I 2C data, the CANSCL and CANSDA buses created by the LT3960 are not traditional CAN buses carrying traditional CAN data. As such, the CANSCL and CANSDA buses between LT3960 devices cannot be shared with standard CAN transceivers in a multidrop configuration. ±40V Fault Protection The LT3960 provides ± 40V fault protection on the I2CAN interface pins (CANSCLH, CANSCLL, CANSDAH, CANSDAL), allowing I2C communication in applications where it was previously impractical. Addressing the need the overvoltage tolerance in many industrial and auto - motive applications, the driver outputs use a progressive foldback current limit to protect against overvoltage faults while still allowing high current output drive. The LT3960 is protected from ± 40V faults powered or unpowered, even in the case of VCC open or shorted to ground. When VCC is open or shorted to GND, the transceivers are off and the I2CAN bus pins remain in the high impedance state.
Rev. B For more information www.analog.com ±36V Extended Common-Mode Range The LT3960 receiver features an extended common mode range of -36V to 36V when operating from a 5V VCC and -25V to 25V when operating from a 3.3V VCC. The wide common mode increases the reliability of oper- ation in environments with electrical noise or local ground potential differences due to ground loops. This extended common mode range allows the LT3960 to conduct I 2C communication in environments inhospitable to standard I2C, such as between two distant PCBs in an automobile. I2CAN Driver When the SCL or SDA pin is asserted low by external I2C device and the conditions are met (whether by mode selection or bidirectional arbitration) to propagate this data from I2C to CAN, the I2CAN driver asserts the dom- inant state on the corresponding bus lines ; the CANxH driver pulls high and the CANxL driver pulls low. When the SCL or SDA pin is high under these same conditions, the I2CAN driver is in the recessive state; both the CANxH and CANxL drivers are in the high impedance state and the bus termination resistor equalizes the voltage on CANxH and CANxL. In the recessive state, the impedance on CANxH and CANxL is determined by the receiver input resistance, RIN. When EN/MODE is low or the V CC is in UVLO, the LT3960 is in shutdown; all I2CAN drivers are in the high impedance state, and the receiver input resistance RIN is disconnected from the bus by a FET switch. T ransmit Dominant Timeout Function Both transceivers in the LT3960 include a 1.5ms (typical) timer to limit the time that driver can hold the I2CAN bus in the dominant state. For example, if the SCL line is held low in Master Mode, a dominant state is asserted on the CANSCL bus until the timer expires, after which the driver releases the bus to a recessive state. The timer is reset when SCL is brought high. I2CAN Driver Overvoltage, Overcurrent, and Overtemperature Protection The I2CAN driver outputs are protected from short cir - cuits to any voltage within the absolute maximum range of -40V to 40V. The maximum current on I2CAN interface pins in a fault condition is ±150mA. The drivers include a progressive foldback current limiting circuit that contin - uously reduces the driver current with increasing output fault voltage. The fault current is typically ±2mA for faults at the absolute maximum voltages of ±40V. The LT3960 also features thermal shutdown protection that disables the chip in the case of excessive power dissipation from the drivers. When the die temperature exceeds 168 ˚ C (typical), the LT3960 is forced into shut- down mode and the I2CAN drivers enter a high impedance state. Power-Up/Down Glitch-Free Outputs The LT3960 employs an undervoltage monitoring circuit on the VCC supply to control the activation of the trans - ceiver circuitry. During start-up SDA, SCL, and all I2CAN outputs are in a high impedance state until VCC reaches a voltage sufficient to reliably operate the chip. At this point, if EN/MODE is out of its shutdown region, the chip acti - vates. The CANSCL and CANSDA receivers activate after a short delay t EN;I2C allowing SCL or SDA to follow the state of CANSCL or CANSDA. The CANSCL and CANSDA drivers power up in the transmit dominant timeout state regardless of the state of SCL or SDA and remain in the recessive state until the first high to low transition of SCL or SDA, respectively. This assures that the LT3960 does not disturb the I 2CAN bus by glitching to the dominant state during start-up. During power-down, similar protection exists. When the undervoltage detection circuit senses low supply voltage on VCC, it immediately puts the chip into shutdown. All I2C and I2CAN pin outputs go the high impedance state. APPLICATIONS INFORMATION
Rev. BFor more information www.analog.com Passive Leakage on I2CAN Bus Pins When the power supply is removed or the chip is in shut- down, the I2CAN pins are in a high impedance state. The I2CAN receiver inputs are isolated from the CANxH and CANxL pins by FET switches which open in the absence of power , preventing the resistor dividers on the receiver inputs from loading the bus. The high impedance state of I2CAN pins is maintained over a range determined by the ESD protection of the pins, typically -0.3V to 7V. For bus voltages outside this range, the current flowing into the receiver is governed by the conduction voltages of the ESD device and the 35.7k nominal I 2CAN receiver input resistance. I2CAN Bus Termination I2CAN buses must be terminated at the ends of each twisted pair with a 120Ω resistor . Split termination is an optional termination technique to reduce common mode voltage perturbations that can produce EME. A split ter - minator divides the single line-end termination resistor (nominally 120Ω) into two series resistors of half the value of the single termination resistor (Figure 10). The center point of the two resistors is connected to a 4.7nF capacitor . Split termination suppresses common mode voltage perturbations by providing a low impedance load to common mode noise sources such as transmitter noise or coupling to external noise sources. In the case of single resistor termination, the only load on a com - mon mode noise source is the parallel impedance of the input resistors of the I2CAN transceivers on the bus. This results in a common mode impedance of several kΩ for a small network. The split termination, on the other hand, provides a common mode load equal to the parallel resis- tance of the two split termination resistors (30Ω). This low common mode impedance results in a reduction of the common mode noise voltage compared to the much higher common mode impedance of the single resistor termination. Figure 11 and Figure 12 compare the com - mon mode noise of an application with and without split cap termination. Figure 10. 4.7nF L T3960 CANxH CANxL CANxH BUS CANxL BUS 60/uni03A9 60/uni03A9 L T3960 CANxH CANxL CANxH BUS CANxL BUS 120/uni03A9
3960 F10
Split Termination for Improved Common Mode Behavior Figure 11. V CC = 3.3V 200ns/DIV SDA 5V/DIV CANSDAH 1V/DIV CANSDAL 1V/DIV CANSDA CM 50mV/DIV 3960 F11I2CAN Common Mode Noise (4.7nF Split Cap) Figure 12. V CC = 3.3V 200ns/DIV
3960 F12
500mV/DIVI2CAN Common Mode Noise (No Split Cap) APPLICATIONS INFORMATION
Rev. B For more information www.analog.com APPLICATIONS INFORMATION Multidrop Applications The LT3960 can be used in a multidrop setup, employ - ing multiple slave-mode LT3960’ s to generate multiple local I2C buses on multiple PCBs along the length of the I2CAN bus lines. No additional termination is required in a multidrop system, but some care must be taken in the design of such systems. The stub length, or the distance from twisted pairs to any additional LT3960, should be less than 0.3m. Stub lengths to the CANSDA and CANSCL buses should be as close as possible in length to avoid adding unequal transmission delays to the clock and data signals. Figure 13. L T3960I2C SLAVE L T3960I2C SLAVE L T3960 I2C SLAVE I2C SLAVE 120/uni03A9 120/uni03A9 120/uni03A9 120/uni03A9
3960 F14
Maximum Data T ransmission Rate Successful communication in any I 2C application is dependent on slave I2C devices’ timely acknowledgment (or ACK) upon receiving a byte of data. Specifically, I 2C slaves must assert the SDA line after the eighth clock pulse leaving enough setup time before the ninth rising edge of SCL to guarantee that the ACK will be received by the I2C master . This requirement is straightforward when all I2C devices share the same I 2C bus, but in LT3960 applications where master and slave I2C buses are sepa- rated by various propagation delays, extra care must be taken to ensure that ACKs from slave I2C devices will be received by the I 2C master at the desired transmission rate. In LT3960 applications, the SCL low period between successive clock pulses (tLOW)must be less than the sum of the propagation delays (tPI2CBD and tPBI2CD), slave ACK time (tVD;ACK), and master data setup time (tSU;ACK). This requirement is shown explicitly in Equation 1. tLOW > 2 tPI2CBD,max + tCABLE + tPBI2CD,max( ) +tVD;ACK,max + tSU;ACK (1) A conservative estimate of propagation delay through a twisted pair based on cable length is shown in Equation 2. Equation 2 is useful for rough estimates, but when designing applications always calculate propaga - tion delay based on the actual physical properties of the cabling used for the I2CAN bus lines. tCABLE = ICABLE 0.15m / ns (2) Fast-mode (400kHz capable) I2C devices are allowed 0.9µs to acknowledge a valid data byte, even while ACK times (tVD;ACK) are often much shorter in practice. A tVD;ACK of 0.9µs would limit the data transmission rate of a LT3960 application to under 400kHz for even one meter of twisted pair . For this reason, it is recommended that all I2C slaves be Fast-mode Plus (1MHz) devices instead of Fast-mode (400kHz) devices when attempting to maximize trans - mission rate. The shorter maximum t VD;ACK (450ns) of Fast-mode plus devices allows for communication across a greater distance at any given clock speed. Figure 14 consolidates the information above, plotting maximum clock speeds for a given bus length for applications with fast-mode and fast-mode plus devices. Figure 14. FAST–MODE SLAVE DEVICES FAST–MODE PLUS SLAVE DEVICES BUS LENGTH (m) 200 225 250 275 300 325 350 375 400 425 450 MAX CLOCK SPEED (kHz)
3960 F14Maximum I2CAN Clock Speed
Rev. BFor more information www.analog.com TYPICAL APPLICATIONS 1A Matrix LED Dimmer with Remote I2C Control 68µH 0.22µF 274k 31.6k 2.2µF 100k 3.92k 2.2µF 100mΩ 178k 360kHz 1µF 10k 1µF 100k 10µF 1M/uni03A9 100nF 10µF BST1 L T3964 SW1 V IN1 ISP1 ISN1 PWMTG1 TSET CTRL1 RT GND EN/UVLO ADDR1 ADDR2 PWM1 INTVCC ALERT SCL SDA 2-WIRE I2C INTERFACE SYNC/CLKOUT INTVCC FB1 L T3967 DRN8 SRC8 DRN7 SRC7 DRN6 SRC6 DRN5 SRC5 DRN4 SRC4 DRN3 SRC3 DRN2 SRC2 DRN1 SRC1 SCL SDA ADDR4 ADDR3 ADDR2 ADDR1 31V TO 36V (ENABLED AT 33V , SHUTDOWN AT 31V) V IN ENH 31V TO 36V VDD ALERT WDI GND CLOCK (FROM L T3964) CLOCK RTCLK ALERT ALERT INTVCC LED1+ UP TO 26V LED 50V 50V 50V 50V 499k 165k INTVCC ADDR-1100011 GND 49.9k LED1+ LED1+ INTVCC INTVCC ADDR-0101100 POR-LED OFF 10nF 28k 22k 120/uni03A9 2.2µF 10k 10k120/uni03A9 120/uni03A9 120/uni03A9120/uni03A9 2.2µF 5k 5k L T3960 VIN
3960 TA03
3.3V OR 5V CANSDAH CANSDAL CANSCLH CANSCLL GND1 GND2 SDA SCL DIG I/O GND 1µFGND /uni03BCCONTROLLER I2C MASTER GND REMOTE I2C MASTER
Rev. B For more information www.analog.com PACKAGE DESCRIPTION MSOP (MSE) 0213 REV I 0.53 ±0.152 (.021 ±.006) SEATING PLANE 0.18 (.007) 1.10 (.043) MAX 0.17 –/uni00A00.27 (.007 – .011) TYP 0.86 (.034) REF 0.50 (.0197) BSC 1 2 3 4 5 4.90 ±0.152 (.193 ±.006) 0.497 ±0.076 (.0196 ±.003) REF8910 7 6 3.00 ±0.102 (.118 ±.004) (NOTE 3) 3.00 ±0.102 (.118 ±.004) (NOTE 4) NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED 0.254mm (.010") PER SIDE. 0.254 (.010) 0° – 6° TYP DETAIL “A” DETAIL “A” GAUGE PLANE 5.10 (.201) MIN 3.20 – 3.45 (.126 – .136) 0.889 ±0.127 (.035 ±.005) RECOMMENDED SOLDER PAD LAYOUT 1.68 ±0.102 (.066 ±.004) 1.88 ±0.102 (.074 ±.004) 0.50 (.0197) BSC 0.305 ± 0.038 (.0120 ±.0015) TYP BOTTOM VIEW OF EXPOSED PAD OPTION 1.68 (.066) 1.88 (.074) 0.1016 ±0.0508 (.004 ±.002) DETAIL “B” DETAIL “B” CORNER TAIL IS PART OF THE LEADFRAME FEATURE. FOR REFERENCE ONL Y NO MEASUREMENT PURPOSE
0.05 REF
0.29 REF 10-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1664 Rev I)
Rev. BFor more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER A 02/21 Changed topmark from LHJP to L THJP . 2 B 10/21 Removed ESD rating. Updated TVS circuit. 1, 16, 22
Rev. B For more information www.analog.com ANALOG DEVICES, INC. 2021 www.analog.com RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS LT3965 8-Switch Matrix LED Dimmer I2C Multidrop Serial Interface, 16 Unique I2C Addresses, VDD Range: 2.7V to 5.5V, VIN Range: 8V to 60V, Digital Programmable 256:1 PWM Dimming, 28-Lead TSSOP LT3967 1.3A Eight-Switch Matrix LED Dimmer with CRC-8 Controls LED Dimming of Strings Up to 54V, I2C Serial Interface with Programmable Address, 28-Lead TSSOP LT3964 Dual 36V Synchronous 1.6A Buck LED Driver with I2C Wide Input Voltage Range: 4V to 36V, T wo Independent 1.6A/40V Synchronous Bucks, I2C Interface for Internal T rue Color PWM™ Dimming (8192:1), 36-Lead QFN LTC4331 I2C Slave Device Extender Over Rugged Differential Link Up to 1MHz Serial Clock, Fast-Mode Plus (FM+), Selectable Link Baud Rates Extend I2C Up to 1200m, 20-Lead QFN Network for IEC 6100-4-2 Level 4 ESD Protection 60.4/uni03A9 60.4/uni03A9 4.7nF 60.4/uni03A9 60.4/uni03A9 4.7nF L T3960 CANSDAL CANSDAH CANSCLH CANSCLL GND TVS TVS CANSDAL TVS: ON SEMI NUP2105L, 350W DUAL BIDIRECTIONAL TVS DIODE, SOT-23 CANSDAH GND CANSCLH CANSCLL