LT3958

LT3958 High Input Voltage, Boost, Flyback, SEPIC and Inverting Converter

Document overview

• Manufacturer or author: Linear Technology Corporation
• PDF pages: 30

Technical content

3958faFor more information www.linear.com/LT3958 n Wide Input Voltage Range: 5V to 80V n Single Feedback Pin for Positive or Negative Output Voltage n Internal 3.3A/84V Power Switch n Current Mode Control Provides Excellent T ransient Response n Programmable Operating Frequency (100kHz to 1MHz) with One External Resistor n Synchronizeable to an External Clock n Low Shutdown Current < 1µA n Internal 7.2V Low Dropout Voltage Regulator n Programmable Input Undervoltage Lockout with Hysteresis n Programmable Soft-Start n Thermally Enhanced QFN (5mm × 6mm) Package Typical applicaTion

DescripTion

High Input Voltage, Boost, Flyback, SEPIC and Inverting Converter The LT®3958 is a wide input range, current mode, DC/DC converter which is capable of generating either positive or negative output voltages. It can be configured as either a boost, flyback, SEPIC or inverting converter . It features an internal low side N-channel power MOSFET rated for 84V at 3.3A and driven from an internal regulated 7.2V supply. The fixed frequency, current-mode architecture results in stable operation over a wide range of supply and output voltages. The operating frequency of L T3958 can be set with an external resistor over a 100kHz to 1MHz range, and can be synchronized to an external clock using the SYNC pin. A minimum operating supply voltage of 5V , and a low shutdown quiescent current of less than 1µA, make the L T3958 ideally suited for battery-powered systems. The L T3958 features soft-start and frequency foldback functions to limit inductor current during start-up. L, L T , L TC, L TM, Linear Technology and the Linear logo are registered trademarks and No RSENSE and ThinSOT are trademarks of Analog Devices, Inc. All other trademarks are the property of their respective owners. Patents pending. High Efficiency Boost Converter

FeaTures

applicaTions

Efficiency vs Output Current SENSE2 SENSE1 LT3958 33µH VIN SW GND FBX RT SS INTVCC EN/UVLO SYNC SGND 53.6k VC

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41.2k 300kHz 4.7µF0.33µF 10k 10nF 464k 15.8k 4.7µF VOUT 48V 0.5A V IN 12V TO 40V 4.7µF OUTPUT CURRENT (mA) EFFICIENCY (%) 100 100 200 300 400

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VIN = 24V

3958fa For more information www.linear.com/LT3958 pin conFiguraTionabsoluTe MaxiMuM raTings INT Operating T emperature Range Maximum Junction Temperature (Note 1) 12 13 14 TOP VIEW SGND SW UHE PACKAGE 36-LEAD (5mm × 6mm) PLASTIC QFN 15 16 17 36 35 34 33 32 31 30 1 NC NC SENSE2 SGND SENSE1 SW SW NC INTV CC VIN EN/UVLO SGND SGND SW SW NC NC SYNC RT SS FBX VC GND GND GND GND GND GND 209 TJMAX = 125°C, θJA = 43°C/W , θJC = 5°C/W EXPOSED PAD (PIN 37) IS SGND, MUST BE SOLDERED TO SGND PLANE EXPOSED PAD (PIN 38) IS SW , MUST BE SOLDERED TO SW PLANE LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L T3958EUHE#PBF L T3958EUHE#TRPBF 3958 36-Lead (5mm × 6mm) Plastic QFN –40°C to 125°C L T3958IUHE#PBF L T3958IUHE#TRPBF 3958 36-Lead (5mm × 6mm) Plastic QFN –40°C to 125°C Consult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear .com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. orDer inForMaTion http://www.linear .com/product/L T3958#orderinfo

3958faFor more information www.linear.com/LT3958 elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 24V , EN/UVLO = 24V , SENSE2 = 0V , unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Operating Range 5 80 V VIN Shutdown IQ EN/UVLO = 0V EN/UVLO = 1.15V 0.1 1 µA µA V IN Operating IQ VC = 0.3V , RT = 41.2k 1.6 2.2 mA VIN Operating IQ with Internal LDO Disabled VC = 0.3V , R T = 41.2k, INTVCC = 7.5V 350 400 µA SW Pin Current Limit SENSE2 = SENSE1 l 3.3 4.0 4.6 A SW Pin On Voltage ISW = 2A 180 mV SENSE2 Input Bias Current Current Out of Pin –65 µA Error Amplifier FBX Regulation Voltage (VFBX(REG)) FBX > 0V (Note 3) FBX < 0V (Note 3) l l 1.569 –0.816 1.6 –0.800 1.631 –0.784 V V FBX Overvoltage Lockout FBX > 0V (Note 4) FBX < 0V (Note 4) FBX Pin Input Current FBX = 1.6V (Note 3) FBX = – 0.8V (Note 3) –10 70 100 nA nA T ransconductance g m (∆IVC /∆FBX) (Note 3) 230 µS VC Output Impedance (Note 3) 5 MΩ VFBX Line Regulation (∆VFBX/[∆VIN • VFBX(REG)]) FBX > 0V , 5V < VIN < 80V (Notes 3, 6) FBX < 0V , 5V < VIN < 80V (Notes 3, 6) 0.006 0.005 0.03 0.038 %/V V VC Current Mode Gain (∆ VVC /∆VSENSE) 10 V/V VC Source Current VC = 1.5V , FBX = 0V , Current Out of Pin –15 µA VC Sink Current FBX = 1.7V FBX = –0.85V µA µA Oscillator Switching Frequency R T = 140k to SGND, FBX = 1.6V, VC = 1.5V RT = 41.2k to SGND, FBX = 1.6V, VC = 1.5V RT = 10.5k to SGND, FBX = 1.6V, VC = 1.5V 270 850 100 300 1000 120 330 1200 kHz kHz kHz RT V oltage FBX = 1.6V 1.2 V SW Minimum Off-Time 200 275 ns SW Minimum On-Time 250 300 ns SYNC Input Low 0.4 SYNC Input High 1.5 SS Pull-Up Current SS = 0V , Current Out of Pin –10 µA Low Dropout Regulator INTVCC Regulation Voltage l 7 7.2 7.4 V INTVCC Undervoltage Lockout Threshold Falling INTVCC UVLO Hysteresis 3.55 3.75 0.15 4.00 V V INTVCC Overvoltage Lockout Threshold 11.5 12.8 V

3958fa For more information www.linear.com/LT3958 elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 24V , EN/UVLO = 24V , SENSE2 = 0V , unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS INTVCC Current Limit VIN = 80V VIN = 20V 19 24 29 mA mA INTVCC Load Regulation (∆VINTVCC /V INTVCC) 0 < IINTVCC < 10mA, VIN = 8V –1 –0.4 % INTVCC Line Regulation (∆VINTVCC /[ ∆VIN • VINTVCC]) 8V < VIN < 80V 0.005 0.025 %/V Dropout Voltage (VIN – VINTVCC) VIN = 6V , IINTVCC = 10mA, VC = 0V 500 mV INTVCC Current in Shutdown EN/UVLO = 0V , INTVCC = 8V 16 µA INTVCC Voltage to Bypass Internal LDO 7.5 V Logic Inputs EN/UVLO Threshold Voltage Falling VIN = INTVCC = 8V l 1.17 1.22 1.27 V EN/UVLO Voltage Hysteresis 20 mV EN/UVLO Input Low Voltage IVIN Drops Below 1µA 0.4 V EN/UVLO Pin Bias Current Low EN/UVLO = 1.15V 1.7 2 2.5 µA EN/UVLO Pin Bias Current High EN/UVLO = 1.33V 10 100 nA Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The L T3958E is guaranteed to meet performance specifications from the 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The L T3958I is guaranteed over the full –40°C to 125°C operating junction temperature range. Note 3: The L T3958 is tested in a feedback loop which servos V FBX to the reference voltages (1.6V and –0.8V) with the VC pin forced to 1.3V . Note 4: FBX overvoltage lockout is measured at VFBX(OVERVOL TAGE) relative to regulated VFBX(REG). Note 5: For 5V < VIN < 6V , the EN/UVLO pin must not exceed VIN. Note 6: EN/UVLO = 1.33V when VIN = 5V .

3958faFor more information www.linear.com/LT3958 Dynamic Quiescent Current vs Switching Frequency RT vs Switching Frequency Normalized Switching Frequency vs FBX SWITCHING FREQUENCY (kHz) 100 IQ(mA) 300 500 600 700 200 400 900 8001000

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SWITCHING FREQUENCY (kHz)

10 RT (k/uni03A9)100

300 500 600 700100 200 400 900 8001000

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FBX VOL TAGE (V) –0.8 NORMALIZED FREQUENCY (%)20 120 –0.4 0 0.4 0.8

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1.2 1.6 100 Switching Frequency vs Temperature SW Pin Current Limit vs Temperature TEMPERATURE (°C) –50 275 SWITCHING FREQUENCY (kHz) 280 285 290 295 300 305 310 325 –25 0 25 75 50

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RT = 41.2k TEMPERATURE (°C) –50 3.6 SW PIN CURRENT LIMIT (A) 4.1 4.0 3.9 3.8 4.2 4.3 4.4 0 50 75 3.7 –25 25 100 125

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DUTY CYCLE (%) 3.6 3.7 3.8 3.9 SW PIN CURRENT LIMIT (A) 4.2 20 40 80 60 4.4 4.1 4.0 4.3 100

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Typical perForMance characTerisTics Positive Feedback Voltage vs Temperature, VIN Negative Feedback Voltage vs Temperature, V IN Quiescent Current vs Temperature, V IN TA = 25°C, unless otherwise noted. TEMPERATURE (°C) –50 1.590REGULATED FEEDBACK VOLTAGE (V)1.592 1.596 1.598 1.600 1.604 0 50 75 1.594 1.602 –25 25 100 125

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VIN = 80V VIN = 24V VIN = 8V VIN = INTVCC = 5V TEMPERATURE (°C) –50 –804REGULATED FEEDBACK VOLTAGE (mV) –802 –800 –798 –792 –794 0 50 75 –796 –25 25 100 125

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VIN = 80VVIN = 24V VIN = 8V VIN = INTVCC = 5V TEMPERATURE (°C) –50

1.4 QUIESCENT CURRENT (mA)

1.6 1.8 0 50 75 1.5 1.7 –25 25 100 125

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VIN = 80V VIN = 24V VIN = INTVCC = 5V

3958fa For more information www.linear.com/LT3958 INTVCC Line Regulation INTVCC Dropout Voltage vs Current, Temperature INTVCC vs Temperature INTVCC Load Regulation TEMPERATURE (°C) –50 7.0 INTVCC (V) 7.1 7.2 7.3 7.4 0 50 75–25 25 100 125

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INTVCC LOAD (mA) 6.8 7.1 7.2 7.3 10 20 25 6.9 5 15

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INTVCC VOLTAGE (V) VIN = 8V VIN (V) INTVCC VOL TAGE (V) 7.25 7.20 20 30 5010 40 60 70 80 7.15 7.10 7.30

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INTVCC LOAD (mA) DROPOUT VOL TAGE (mV) 700 600 800 400 500 200 300 42 6 8 10 100 900

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125°C 25°C 0°C –40°C 75°C Internal Switch On-Resistance vs Temperature TEMPERATURE (°C) –50 ON-RESISTANCE (mΩ) 120 140 160 100 –25 25 0 50 75 100 125 180

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Internal Switch On-Resistance vs INTVCC INTVCC (V) ON-RESISTANCE (mΩ) 100 6 7 8 95 11 10 12 102

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Typical perForMance characTerisTics TA = 25°C, unless otherwise noted. EN/UVLO Threshold vs Temperature EN/UVLO Current vs Voltage EN/UVLO Hysteresis Current vs Temperature TEMPERATURE (°C) –50 1.18 1.22 1.24 1.28 0 50 75 1.20 –25 25 100 125 1.26

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EN/UVLO VOLTAGE (V) EN/UVLO RISING EN/UVLO FALLING EN/UVLO VOL TAGE (V) EN/UVLO CURRENT (µA) 20 6040

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TEMPERATURE (°C) –50 1.6 IEN/UVLO (µA) 1.8 2.0 2.2 2.4 0 50 75–25 25 100 125

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3958faFor more information www.linear.com/LT3958 Typical perForMance characTerisTics TA = 25°C, unless otherwise noted. SEPIC Typical Start-Up Waveforms SEPIC FBX Frequency Foldback Waveforms During Overcurrent 5ms/DIV SEE TYPICAL APPLICATION: 10V TO 60V INPUT , 12V OUTPUT SEPIC CONVERTER VOUT 5V/DIV IL1A + IL1B 2A/DIV

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VIN = 24V 50µs/DIV VOUT 10V/DIV VSW 20V/DIV IL1A + IL1B 2A/DIV

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VIN = 24V SEE TYPICAL APPLICATION: 10V TO 60V INPUT , 12V OUTPUT SEPIC CONVERTER

3958fa For more information www.linear.com/LT3958 pin FuncTions NC (Pins 1, 2, 10, 35, 36): No Internal Connection. Leave these pins open or connect them to the adjacent pins. SENSE2 (Pin 3): The Current Sense Input for the Control Loop. Connect this pin to SENSE1 pin directly or through a low pass filter (connect this pin to SENSE1 pin through a resistor , and to SGND through a capacitor). SGND (Pins 4, 23, 24, Exposed Pad Pin 37): Signal Ground. All small-signal components should connect to this ground. SGND is connected to GND inside the IC to ensure Kelvin connection for the internal switch current sensing. Do not connect SGND and GND externally. SENSE1 (Pin 6): The Current Sense Output of the Inter - nal N-channel MOSFET . Connect this pin to SENSE2 pin directly or through a low pass filter (connect this pin to SENSE1 pin through a resistor , then connect SENSE2 to SGND through a capacitor). SW (Pins 8,9,20,21, Exposed Pad Pin 38): Drain of Internal Power N-channel MOSFET . GND (Pins 12,13,14,15,16,17): Ground. These pins con- nect to the source terminal of internal power N-channel MOSFET through an internal sense resistor. GND is con- nected to SGND inside the IC to ensure Kelvin connection for the internal switch current sensing. Do not connect GND and SGND externally. EN/UVLO (Pin 25): Shutdown and Undervoltage Detect Pin. An accurate 1.22V (nominal) falling threshold with externally programmable hysteresis detects when power is okay to enable switching. Rising hysteresis is generated by the external resistor divider and an accurate internal 2µA pull-down current. An undervoltage condition resets sort-start. Tie to 0.4V , or less, to disable the device and reduce V IN quiescent current below 1µA. VIN (Pin 27): Input Supply Pin. V IN pin can be locally bypassed with a capacitor to GND (not SGND). INTVCC (Pin 28): Regulated Supply for Internal Loads and Gate Driver . Supplied from V IN and regulated to 7.2V (typical). INTVCC must be bypassed to SGND with a minimum of 4.7µF capacitor placed close to pin. INTVCC can be connected directly to VIN, if VIN is less than 11.5V. INTVCC can also be connected to a power supply whose voltage is higher than 7.5V , and lower than VIN, provided that supply does not exceed 11.5V. VC (Pin 30): Error Amplifier Compensation Pin. Used to stabilize the voltage loop with an external RC network. Place compensation components between the VC pin and SGND. FBX (Pin 31): Positive and Negative Feedback Pin. Re - ceives the feedback voltage from the external resistor divider between the output and SGND. Also modulates the switching frequency during start-up and fault conditions when FBX is close to SGND. SS (Pin 32): Soft-Start Pin. This pin modulates compen- sation pin voltage (VC) clamp. The soft-start interval is set with an external capacitor between SS pin and SGND. The pin has a 10µA (typical) pull-up current sour ce to an internal 2.5V rail. The soft-start pin is reset to SGND by an under voltage condition at EN/UVLO, an INTV CC undervoltage or overvoltage condition or an internal thermal lockout. RT (Pin 33): Switching Frequency Adjustment Pin. Set the frequency using a resistor to SGND. Do not leave this pin open. SYNC (Pin 34): Frequency Synchronization Pin. Used to synchronize the switching frequency to an outside clock. If this feature is used, an R T resistor should be chosen to program a switching frequency 20% slower than the SYNC pulse frequency. Tie the SYNC pin to SGND if this feature is not used. SYNC is ignored when FBX is close to SGND.

Figure 1. L T3958 Block Diagram Working as a SEPIC Converter

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3958fa For more information www.linear.com/LT3958 applicaTions inForMaTion Main Control Loop The L T3958 uses a fixed frequency, current mode control scheme to provide excellent line and load regulation. Op- eration can be best understood by referring to the Block Diagram in Figure 1. The start of each oscillator cycle sets the SR latch (SR1) and turns on the internal power MOSFET switch M1 through driver G2. The switch current flows through the internal current sensing resistor R SENSE and generates a voltage proportional to the switch current. This current sense voltage V ISENSE (amplified by A5) is added to a stabilizing slope compensation ramp and the resulting sum (SLOPE) is fed into the positive terminal of the PWM comparator A7. When SLOPE exceeds the level at the negative input of A7 (VC pin), SR1 is reset, turning off the power switch. The level at the negative input of A7 is set by the error amplifier A1 (or A2) and is an amplified version of the difference between the feedback voltage (FBX pin) and the reference voltage (1.6V or –0.8V , depending on the configuration). In this manner , the error amplifier sets the correct peak switch current level to keep the output in regulation. The L T3958 has a switch current limit function. The current sense voltage is input to the current limit comparator A6. If the SENSE2 pin voltage is higher than the sense current limit threshold V SENSE(MAX) (48mV , typical), A6 will reset SR1 and turn off M1 immediately. The L T3958 is capable of generating either positive or negative output voltage with a single FBX pin. It can be configured as a boost, flyback or SEPIC converter to gen- erate positive output voltage, or as an inverting converter to generate negative output voltage. When configured as a SEPIC converter, as shown in Figure 1, the FBX pin is pulled up to the internal bias voltage of 1.6V by a volt - age divider (R1 and R2) connected from V OUT to SGND. Comparator A2 becomes inactive and comparator A1 performs the inverting amplification from FBX to VC. When the L T3958 is in an inverting configuration, the FBX pin is pulled down to –0.8V by a voltage divider connected from V OUT to SGND. Comparator A1 becomes inactive and comparator A2 performs the noninverting amplification from FBX to VC. The L T3958 has overvoltage protection functions to protect the converter from excessive output voltage overshoot during start-up or recovery from a short-circuit condition. An overvoltage comparator A11 (with 20mV hysteresis) senses when the FBX pin voltage exceeds the positive regulated voltage (1.6V) by 8% and provides a reset pulse. Similarly, an overvoltage comparator A12 (with 10mV hysteresis) senses when the FBX pin voltage exceeds the negative regulated voltage (–0.8V) by 11% and provides a reset pulse. Both reset pulses are sent to the main RS latch (SR1) through G6 and G5. The power MOSFET switch M1 is actively held off for the duration of an output overvoltage condition. Programming Turn-On and Turn-Off Thresholds with the EN/UVLO Pin The EN/UVLO pin controls whether the L T3958 is enabled or is in shutdown state. A micropower 1.22V reference, a comparator A10 and a controllable current source I allow the user to accurately program the supply voltage at which the IC turns on and off. The falling value can be accurately set by the resistor dividers R3 and R4. When EN/UVLO is above 0.4V , and below the 1.22V threshold, the small pull-down current source I S1 (typical 2µA) is active. The purpose of this current is to allow the user to program the rising hysteresis. The Block Diagram of the comparator and the external resistors is shown in Figure 1. The typical falling threshold voltage and rising threshold voltage can be calculated by the following equations: VVIN,FALLING = 1.22 •(R3+ R4) VVIN,RISING = 2µA •R3+ VIN,FALLING For applications where the EN/UVLO pin is only used as a logic input, the EN/UVLO pin can be connected directly to the input voltage V IN through a 1k resistor for always- on operation.

the soft-start operation will be triggered. enough to turn off the internal LDO regulator . Figure 2. Connecting INTVCC to VOUT

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frequency also has implications for loop compensation. resistor to SGND for proper operation of the L T3958. frequency is shown in Table 1. Table 1. Timing Resistor (RT) Value to a maximum value of R1 at about 158k).

3958faFor more information www.linear.com/LT3958 applicaTions inForMaTion Soft-Start The L T3958 contains several features to limit peak switch currents and output voltage (V OUT) overshoot during start-up or recovery from a fault condition. The primary purpose of these features is to prevent damage to external components or the load. High peak switch currents during start-up may occur in switching regulators. Since V OUT is far from its final value, the feedback loop is saturated and the regulator tries to charge the output capacitor as quickly as possible, resulting in large peak currents. A large surge current may cause inductor saturation or power switch failure. The L T3958 addresses this mechanism with the SS pin. As shown in Figure 1, the SS pin reduces the power MOSFET current by pulling down the VC pin through Q2. In this way the SS allows the output capacitor to charge gradually toward its final value while limiting the start-up peak currents. The typical start-up waveforms are shown in the Typical Per formance Characteristics section. The inductor current IL slewing rate is limited by the soft-start function. Besides start-up (with EN/UVLO), soft-start can also be triggered by the following faults: 1. INTVCC > 12.8V (typical) 2. INTVCC < 3.55V 3. Thermal lockout Any of these three faults will cause the L T3958 to stop switching immediately. The SS pin will be discharged by Q3. When all faults are cleared and the SS pin has been discharged below 0.2V , a 10µA current source I S2 starts charging the SS pin, initiating a soft-start operation. The soft-start interval is set by the soft-start capacitor selection according to the equation: TSS = CSS •1.25V 10µA FBX Frequency Foldback When VOUT is very low during start-up, or an output short- circuit on a SEPIC, an inverting, or a flyback converter , the switching regulator must operate at low duty cycles to maintain the power switch current within the current limit range, since the inductor current decay rate is very low during switch off time. The minimum on-time limitation may prevent the switcher from attaining a sufficiently low duty cycle at the programmed switching frequency. So, the switch current may keep increasing through each switch cycle, exceeding the programmed current limit. To prevent the switch peak currents from exceeding the programmed value, the L T3958 contains a frequency foldback function to reduce the switching frequency when the FBX voltage is low (see the Normalized Switching Frequency vs FBX graph in the Typical Performance Characteristics section). During frequency foldback, external clock synchroniza- tion is disabled to prevent interference with frequency reducing operation. Loop Compensation Loop compensation determines the stability and transient per formance. The L T3958 uses current mode control to regulate the output which simplifies loop compensation. The optimum values depend on the converter topology, the component values and the operating conditions (including the input voltage, load current, etc.). To compensate the feedback loop of the L T3958, a series resistor-capacitor network is usually connected from the VC pin to SGND. Figure 1 shows the typical VC compensation network. For most applications, the capacitor should be in the range of 470pF to 22nF , and the resistor should be in the range of 5k to 50k. A small capacitor is often connected in parallel with the RC compensation network to attenuate the VC voltage ripple induced from the output voltage ripple through the internal error amplifier . The parallel capacitor usually ranges in value from 10pF to 100pF . A practical approach to design the compensation network is to start with one of the circuits in this data sheet that is similar to your application, and tune the compensation network to optimize the performance. Stability should then be checked across all operating condi- tions, including load current, input voltage and temperature. Application Note 76 is a good reference.

tics section. VSW(PEAK) is the peak switch off-state voltage. J(MAX) does not exceed 125°C. protective actions. The power switch will be turned off. Figure 3. The Switch Current During a Switching Cycle

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Figure 4. The RC Filter on SENSE1 Pin and SENSE2 Pin

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margin (10% or higher is recommended). SENSE immediately after M1 is turned on.

3958faFor more information www.linear.com/LT3958 applicaTions inForMaTion APPLICATION CIRCUITS The L T3958 can be configured as different topologies. The first topology to be analyzed will be the boost converter , followed by the flyback, SEPIC and inverting converters. Boost Converter: Switch Duty Cycle and Frequency The L T3958 can be configured as a boost converter for the applications where the converter output voltage is higher than the input voltage. Remember that boost con- verters are not short-circuit protected. Under a shorted output condition, the inductor current is limited only by the input supply capability . For applications requiring a step-up converter that is short-cir cuit protected, please refer to the Applications Information section covering SEPIC converters. The conversion ratio as a function of duty cycle is VOUT VIN = 1 1− D in continuous conduction mode (CCM). For a boost converter operating in CCM, the duty cycle of the main switch can be calculated based on the output voltage (V OUT) and the input voltage (VIN). The maximum duty cycle (D MAX) occurs when the converter has the minimum input voltage: DMAX = VOUT − VIN(MIN) VOUT Discontinuous conduction mode (DCM) provides higher conversion ratios at a given frequency at the cost of reduced efficiencies and higher switching currents. Boost Converter: Maximum Output Current Capability and Inductor Selection For the boost topology, the maximum average inductor current is: IL(MAX) = IO(MAX) • 1 1− DMAX Due to the current limit of its internal power switch, the L T3958 should be used in a boost converter whose maxi- mum output current (I O(MAX)) is less than the maximum output current capability by a sufficient margin (10% or higher is recommended): IO(MAX) ≤ VIN(MIN) VOUT The inductor ripple current ∆ISW has a direct effect on the choice of the inductor value and the converter’s maximum output current capability. Choosing smaller values of SW increases output current capability, but requires large inductances and reduces the current loop gain (the converter will approach voltage mode). Accepting larger values of ∆I SW provides fast transient response and allows the use of low inductances, but results in higher input current ripple, greater core losses, lower output current capability and in some cases, subharmonic oscillation. A good start point for ∆I SW is 0.6A though careful evaluation of system stabililty should be made to ensure adequate design margin. Given an operating input voltage range, and having chosen the operating frequency and ripple current in the inductor , the inductor value of the boost converter can be determined using the following equation: L = VIN(MIN) ∆ISW •ƒ •DMAX The peak inductor current is the switch current limit (typical 4A), and the RMS inductor current is approximately equal to I L(MAX). The user should choose the inductors having sufficient saturation and RMS current ratings. Boost Converter: Output Diode Selection To maximize efficiency, a fast switching diode with low forward drop and low reverse leakage is desirable. The peak reverse voltage that the diode must withstand is equal to the regulator output voltage plus any additional ringing across its anode-to-cathode during the on-time. The average forward current in normal operation is equal to the output current. It is recommended that the peak repetitive reverse voltage rating V RRM is higher than VOUT by a safety margin (a 10V safety margin is usually sufficient).

not exceed the diode maximum junction temperature rating. frequency switching noise on the converter output. Figure 5. The Output Ripple Waveform of a Boost Converter

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period T S, three subintervals occur: DT S, D2T S, D3T S. LS currents are zero during D3TS.

• D According to Figure 6, the peak SW voltage is: VSW(PEAK) = VIN(MAX) + VSN where VSN is the snubber capacitor voltage. A smaller VSN results in a larger snubber loss. A reasonable V SN is 1.5 to 2 times of the reflected output voltage: VSN = k • VOUT •NP NS k = 1.5 ~ 2 According to the Absolute Maximum Ratings table, the SW voltage Absolute Maximum value is 84V . Therefore, the maximum primary to secondary turns ratio (for both the continuous and the discontinuous operation) should be. NP NS ≤ 84V − VIN(MAX) k •VOUT FL YBACK CONVERTER APPLICATIONS The L T3958 can be configured as a flyback converter for the applications where the converters have multiple outputs, high output voltages or isolated outputs. Figure 6 shows a simplified flyback converter . The flyback converter has a very low parts count for mul- tiple outputs, and with prudent selection of turns ratio, can have high output/input voltage conversion ratios with a desirable duty cycle. However , it has low efficiency due to the high peak currents, high peak voltages and consequent power loss. The flyback converter is commonly used for an output power of less than 50W . The flyback converter can be designed to operate either in continuous or discontinuous mode. Compared to con- tinuous mode, discontinuous mode has the advantage of smaller transformer inductances and easy loop compen- sation, and the disadvantage of higher peak-to-average current and lower efficiency.

Figure 7. Waveforms of the Flyback Converter

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Figure 6. A Simplified Flyback Converter

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• D 1− D where NS/NP is the second to primary turns ratio. D is duty cycle. Figure 7 shows the waveforms of the flyback converter in discontinuous mode operation. During each switching

3958fa For more information www.linear.com/LT3958 applicaTions inForMaTion According to the preceding equations, the user has relative freedom in selecting the switch duty cycle or turns ratio to suit a given application. The selections of the duty cycle and the turns ratio are somewhat iterative processes, due to the number of variables involved. The user can choose either a duty cycle or a turns ratio as the start point. The following trade-offs should be considered when select - ing the switch duty cycle or turns ratio, to optimize the converter per formance. A higher duty cycle affects the flyback converter in the following aspects: Lower MOSFET RMS current ISW(RMS), but higher MOSFET VSW peak voltage

• Lower diode peak reverse voltage, but higher diode RMS current ID(RMS)
• Higher transformer turns ratio (NP/NS) It is recommended to choose a duty cycle between 20% and 80%. Flyback Converter: Maximum Output Current Capability and T ransformer Design The maximum output current capability and transformer design for continuous conduction mode (CCM) is chosen as presented here. The maximum duty cycle (D MAX) occurs when the converter has the minimum VIN: DMAX = VOUT • NP NS VOUT • NP NS  + VIN(MIN) Due to the current limit of its internal power switch, the L T3958 should be used in a flyback converter whose maxi- mum output current (IO(MAX)) is less than the maximum output current capability by a sufficient margin (10% or higher is recommended): IO(MAX) ≤ VIN(MIN) VOUT
• DMAX • 3.3A − 0.5 •∆ISW( ) The transformer ripple current ∆ISW has a direct effect on the design/choice of the transformer and the converter’s output current capability. Choosing smaller values of SW increases the output current capability, but requires large primary and secondary inductances and reduce the current loop gain (the converter will approach voltage mode). Accepting larger values of ∆I SW allows the use of low primary and secondary inductances, but results in higher input current ripple, greater core losses, lower output current capability and in some cases, subharmonic oscillation. A good start point for ∆I SW is 0.6A though careful evaluation of system stabililty should be made to ensure adequate design margin. Given an operating input voltage range, and having chosen the operating frequency and ripple current in the primary winding, the primary winding inductance can be calculated using the following equation: L = VIN(MIN) ∆ISW •ƒ •DMAX The primary winding peak current is the switch current limit (typical 4A). The primary and secondary maximum RMS currents are: ILP(RMS) ≈ POUT(MAX) DMAX •VIN(MIN) •η ILS(RMS) ≈ IOUT(MAX) 1− DMAX where η is the converter efficiency. Based on the preceding equations, the user should design/ choose the transformer having sufficient saturation and RMS current ratings. Flyback Converter: Snubber Design T ransformer leakage inductance (on either the primary or secondary) causes a voltage spike to occur after the MOSFET turn-off. This is increasingly prominent at higher load currents, where more stored energy must be dissi - pated. In some cases a snubber circuit will be required to avoid overvoltage breakdown at the MOSFET ’s drain node. There are different snubber circuits (such as RC snubber , RCD snubber , etc.) and Application Note 19 is a good reference on snubber design. An RCD snubber is shown in Figure 6.

3958faFor more information www.linear.com/LT3958 applicaTions inForMaTion The snubber resistor value (RSN) can be calculated by the following equation: RSN = 2 • SN − VSN •VOUT •NP NS SW(PEAK) •LLK •ƒ LLK is the leakage inductance of the primary winding, which is usually specified in the transformer character - istics. L LK can be obtained by measuring the primary inductance with the secondary windings shorted. The snubber capacitor value (C SN) can be determined using the following equation: CSN = VSN ∆VSN •RSN •ƒ where ∆VSN is the voltage ripple across CSN. A reasonable ∆VSN is 5% to 10% of VSN. The reverse voltage rating of DSN should be higher than the sum of VSN and VIN(MAX). Flyback Converter: Output Diode Selection The output diode in a flyback converter is subject to large RMS current and peak reverse voltage stresses. A fast switching diode with a low forward drop and a low reverse leakage is desired. Schottky diodes are recommended if the output voltage is below 100V . Approximate the required peak repetitive reverse voltage rating V RRM using: VRRM > NS NP

• VIN(MAX) + VOUT The power dissipated by the diode is: PD = IO(MAX) • VD and the diode junction temperature is: TJ = TA + PD • RθJA The RθJA to be used in this equation normally includes the RθJC for the device, plus the thermal resistance from the board to the ambient temperature in the enclosure. TJ must not exceed the diode maximum junction temperature rating. Flyback Converter: Output Capacitor Selection The output capacitor of the flyback converter has a similar operation condition as that of the boost converter . Refer to the Boost Converter: Output Capacitor Selection section for the calculation of C OUT and ESRCOUT. The RMS ripple current rating of the output capacitors in continuous operation can be determined using the following equation: IRMS(COUT),CONTINUOUS ≈ IO(MAX) • DMAX 1− DMAX Flyback Converter: Input Capacitor Selection The input capacitor in a flyback converter is subject to a large RMS current due to the discontinuous primary current. To prevent large voltage transients, use a low ESR input capacitor sized for the maximum RMS current. The RMS ripple current rating of the input capacitors in continuous operation can be determined using the fol - lowing equation: IRMS(CIN),CONTINUOUS ≈ POUT(MAX) VIN(MIN) •η • 1− DMAX DMAX SEPIC CONVERTER APPLICATIONS The L T3958 can be configured as a SEPIC (single-ended primar y inductance converter), as shown in Figure 1. This topology allows for the input to be higher , equal, or lower than the desired output voltage. The conversion ratio as a function of duty cycle is: VOUT + VD VIN = D 1− D in continuous conduction mode (CCM). In a SEPIC converter , no DC path exists between the input and output. This is an advantage over the boost converter for applications requiring the output to be disconnected from the input source when the cir cuit is in shutdown.

3958fa For more information www.linear.com/LT3958 applicaTions inForMaTion Compared to the flyback converter , the SEPIC converter has the advantage that both the power MOSFET and the output diode voltages are clamped by the capacitors (C IN, CDC and C OUT), therefore, there is less voltage ringing across the power MOSFET and the output diodes. The SEPIC converter requires much smaller input capacitors than those of the flyback converter . This is due to the fact that, in the SEPIC converter , the current through inductor L1 (which is series with the input) is continuous. SEPIC Converter: Switch Duty Cycle and Frequency For a SEPIC converter operating in CCM, the duty cycle of the main switch can be calculated based on the output voltage (V OUT), the input voltage (V IN) and the diode forward voltage (VD). The maximum duty cycle (DMAX) occurs when the converter has the minimum input voltage: DMAX = VOUT + VD VIN(MIN) + VOUT + VD SEPIC Converter: The Maximum Output Current Capability and Inductor Selection As shown in Figure 1, the SEPIC converter contains two inductors: L1 and L2. L1 and L2 can be independent, but can also be wound on the same core, since identical volt- ages are applied to L1 and L2 throughout the switching cycle. For the SEPIC topology , the current through L1 is the converter input current. Based on the fact that, ideally , the output power is equal to the input power , the maximum average inductor currents of L1 and L2 are: IL1 (MAX)= IIN(MAX) = IO(MAX) • DMAX 1− DMAX IL2(MAX) = IO(MAX) In a SEPIC converter , the switch current is equal to IL1 + IL2 when the power switch is on, therefore, the maximum average switch current is defined as: ISW(MAX) = IL1(MAX) + IL2(MAX) = IO(MAX) • 1 1− DMAX Due to the current limit of its internal power switch, the L T3958 should be used in a SEPIC converter whose maximum output current (I O(MAX)) is less than the output current capability by a sufficient margin (10% or higher is recommended): IO(MAX) < (1 – DMAX) • (3.3A – 0.5 • ∆ISW) The inductor ripple currents ∆IL1 and ∆IL2 are identical: ∆IL1 = ∆IL2 = 0.5 • ∆ISW The inductor ripple current ∆ISW has a direct effect on the choice of the inductor value and the converter’s maximum output current capability. Choosing smaller values of ∆I SW requires large inductances and reduces the current loop gain (the converter will approach voltage mode). Accepting larger values of ∆I SW allows the use of low inductances, but results in higher input current ripple, greater core losses, lower output current capability and in some cases, subharmonic oscillation. A good start point for ∆I SW is 0.6A though careful evaluation of system stabililty should be made to ensure adequate design margin. Given an operating input voltage range, and having chosen the operating frequency and ripple current in the induc - tor , the inductor value (L1 and L2 are independent) of the SEPIC converter can be determined using the following equation: L1= L2 = VIN(MIN) 1.5A •∆ISW •ƒ •DMAX For most SEPIC applications, the equal inductor values will fall in the range of 1µH to 100µH.

equal to the maximum average inductor currents. margin (a 10V safety margin is usually sufficient). exceed the diode maximum junction temperature rating. SEPIC converter are similar to those of the boost converter . in continuous conduction mode (CCM). Figure 8. A Simplified Inverting Converter

3758 F10

3958fa For more information www.linear.com/LT3958 applicaTions inForMaTion Inverting Converter: Switch Duty Cycle and Frequency For an inverting converter operating in CCM, the duty cycle of the main switch can be calculated based on the negative output voltage (V OUT) and the input voltage (VIN). The maximum duty cycle (DMAX) occurs when the converter has the minimum input voltage: DMAX = VOUT − VD VOUT − VD − VIN(MIN) Inverting Converter: Output Diode and Input Capacitor Selections The selections of the inductor , output diode and input capacitor of an inverting converter are similar to those of the SEPIC converter . Please refer to the corresponding SEPIC converter sections. Inverting Converter: Output Capacitor Selection The inverting converter requires much smaller output capacitors than those of the boost, flyback and SEPIC converters for similar output ripples. This is due to the fact that, in the inverting converter , the inductor L2 is in series with the output, and the ripple current flowing through the output capacitors are continuous. The output ripple voltage is produced by the ripple current of L2 flowing through the ESR and bulk capacitance of the output capacitor: ∆VOUT(P–P) = ∆IL2 • ESRCOUT + 1 8 •ƒ •COUT After specifying the maximum output ripple, the user can select the output capacitors according to the preceding equation. The ESR can be minimized by using high quality X5R or X7R dielectric ceramic capacitors. In many applications, ceramic capacitors are sufficient to limit the output volt- age ripple. The RMS ripple current rating of the output capacitor needs to be greater than: IRMS(COUT) > 0.3 • ∆IL2 Inverting Converter: Selecting the DC Coupling Capacitor The DC voltage rating of the DC coupling capacitor (CDC, as shown in Figure 10) should be larger than the maximum input voltage minus the output voltage (nega- tive voltage): VCDC > VIN(MAX) – VOUT CDC has nearly a rectangular current waveform. During the switch off-time, the current through CDC is IIN, while approximately –I O flows during the on-time. The RMS rating of the coupling capacitor is determined by the fol- lowing equation: IRMS(CDC) > IO(MAX) • DMAX 1− DMAX A low ESR and ESL, X5R or X7R ceramic capacitor works well for C DC. Board Layout The high power and high speed operation of the L T3958 demands careful attention to board layout and component placement. Careful attention must be paid to the internal power dissipation of the L T3958 at high input voltages, high switching frequencies, and high internal power switch currents to ensure that a junction temperature of 125°C is not exceeded. This is especially important when operating at high ambient temperatures. Exposed pads on the bot- tom of the package are SGND and SW terminals of the IC, and must be soldered to a SGND ground plane and a SW plane respectively. It is recommended that multiple vias in the printed cir cuit board be used to conduct heat away from the IC and into the copper planes with as much as area as possible. To prevent radiation and high frequency resonance problems, proper layout of the components connected to the IC is essential, especially the power paths with higher di/dt. The following high di/dt loops of different topologies should be kept as tight as possible to reduce inductive ringing: In boost configuration, the high di/dt loop contains the output capacitor , the internal power MOSFET and the Schottky diode.

• In flyback configuration, the high di/dt primary loop contains the input capacitor , the primary winding, the internal power MOSFET . The high di/dt second- ary loop contains the output capacitor , the secondary winding and the output diode. In SEPIC configuration, the high di/dt loop con- tains the internal power MOSFET , output capacitor , Schottky diode and the coupling capacitor . In inverting configuration, the high di/dt loop con- tains internal power MOSFET , Schottky diode and the coupling capacitor . Check the stress on the internal power MOSFET by measur- ing the SW -to-GND voltage directly across the IC terminals. Make sure the inductive ringing does not exceed the maximum rating of the internal power MOSFET (84V). The small-signal components should be placed away from high frequency switching nodes. For optimum load regula- tion and true remote sensing, the top of the output voltage sensing resistor divider should connect independently to the top of the output capacitor (Kelvin connection), staying away from any high dV/dt traces. Place the divider resis- tors near the L T3958 in order to keep the high impedance FBX node short. Figure 9 shows the suggested layout of the 48V V OUT boost converter (see the Typical Applications section).

3958 F09

Figure 9. Suggested Layout of the 10V to 40V Input, 48V Output Boost Converter

Table 2. Recommended Component Manufacturers General Semiconductor Diodes generalsemiconductor .

3958faFor more information www.linear.com/LT3958 Typical applicaTions 10V to 40V Input, 48V Output Boost Converter Efficiency vs Output Current High Voltage Flyback Power Supply SENSE2 SENSE1 LT3958 33µH VIN SW GND FBX RT SS INTVCC EN/UVLO SYNC SGND 53.6k VC

3958 TA02a

41.2k 300kHz CVCC 4.7µF 10V X5R CSS 0.33µF RC 10k CC 10nF 464k 15.8k COUT 4.7µF 50V X5R V OUT 48V 0.5A V IN 12V TO 40V CIN 4.7µF 50V X5R CIN, COUT : MURATA GRM32ER71H475KA88L D1: VISHAY SILICONIX 10BQ060 L2: VISHAY SILICONIX IHLP-4040DZ-11 OUTPUT CURRENT (mA) EFFICIENCY (%) 100 100 200 300 400

3958 TA02b

VIN = 24V SENSE2 FBX SENSE1 LT3958 1:10 VIN SW GND RT SS INTVCC EN/UVLO SYNC SGND 10k VC

3958 TA03

DANGER! HIGH VOLTAGE OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY 31.6k 140k 100kHz 4.7µF 10V X5R 0.1µF 10k 10nF 10nF 100pF 1.5M 1.5M 16.2k 22Ω COUT 68nF VOUT 300V 10mA V IN 5.5V TO 12V 47µF 16V CIN : MURATA GRM32ER61C476M COUT : TDK C3225X7R2J683K D1: VISHAY SILICONIX GSD2004S DUAL DIODE CONNECTED IN SERIES T1: TDK DCT15EFD-U44S003 22Ω 220pF

3958fa For more information www.linear.com/LT3958 Typical applicaTions 10V to 60V Input, 12V Output SEPIC Converter Efficiency vs Output Current Load Step Waveforms OUTPUT CURRENT (mA) EFFICIENCY (%)65 200 400 600 800

3958 TA04b

VIN = 24V 500µs/DIV VOUT 0.5V/DIV (AC) IOUT 0.5A/DIV 0.8A 0.2A

3958 TA04c

VIN = 24V Start-Up Waveforms Frequency Foldback Waveforms When Output Short-Circuit 5ms/DIV VOUT 5V/DIV IL1A + IL1B 2A/DIV

3958 TA04d

VIN = 24V 50µs/DIV VOUT 10V/DIV VSW 20V/DIV IL1A + IL1B 2A/DIV

3958 TA04e

VIN = 24V SENSE2 SENSE1 LT3958 L1A L1BVIN SW GND FBX RT SS INTVCC EN/UVLO SYNC SGND 66.5k VC

3958 TA04a

41.2k 300kHz CVCC 4.7µF 10V X5R 0.47µF 10k 10nF 105k 15.8k CDC 2.2µF, 100V X7R, ×2 V OUT 12V V IN 10V TO 60V CIN 2.2µF 100V X5R C OUT 22µF 16V X5R CIN, CDC: MURATA GRM32ER72A225KA35L COUT: MURATA GRM32ER61C226KE20 D1: VISHAY SILICONIX 10MQ100N L1A, L1B: COILTRONICS DRQ125-220

3958faFor more information www.linear.com/LT3958 Typical applicaTions 10V to 60V Input, –12V Output Inverting Converter Efficiency vs Output Current Load Step Waveforms Start-Up Waveforms Frequency Foldback Waveforms When Output Short-Circuit SENSE2 SENSE1 LT3958 L1A L1B VIN SW GND FBX RT SS INTVCC EN/UVLO SYNC SGND 66.5k VC

3958 TA05a

41.2k 300kHz CVCC 4.7µF 10V X5R 0.47µF 10k 10nF 105k 7.5k CDC 2.2µF, 100V X7R, ×2 V OUT –12V V IN 10V TO 60V CIN 2.2µF 100V X5R C OUT 22µF 16V X5R CIN, CDC: MURATA GRM32ER72A225KA35L COUT: MURATA GRM32ER61C226KE20 D1: VISHAY SILICONIX 10MQ100N L1A, L1B: COILTRONICS DRQ125-220 500µs/DIV VOUT 1V/DIV (AC) IOUT 0.5A/DIV 0.8A 0.2A

3958 TA05c

VIN = 24V 5ms/DIV VOUT 5V/DIV IL1A + IL1B 2A/DIV

3958 TA05d

VIN = 24V 50µs/DIV VOUT 10V/DIV VSW 20V/DIV IL1A + IL1B 2A/DIV

3958 TA05e

VIN = 24V OUTPUT CURRENT (mA) EFFICIENCY (%)65 200 400 600 800

3958 TA05b

VIN = 24V

3958fa For more information www.linear.com/LT3958 package DescripTion Please refer to http://www.linear .com/product/L T3958#packaging for the most recent package drawings. 5.00 ± 0.10 6.00 ± 0.10 NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (NOTE 6) 0.40 ± 0.10 36 3530 31 32 33 34 27 2 12 13 14 15 16 17 BOTTOM VIEW—EXPOSED PAD

2.00 REF

1.50 REF

0.75 ± 0.05 R = 0.125 TYP R = 0.10 TYP PIN 1 NOTCH R = 0.30 OR 0.35 × 45° CHAMFER 0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05 (UHE36(28)MA) QFN 0112 REV D RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 4.10 ± 0.05 5.50 ± 0.05 PACKAGE OUTLINE 1.88 ± 0.10 1.53 ± 0.10 5.10 ± 0.05 6.50 ± 0.05 Variation: UHE36(28)MA 36(28)-Lead Plastic QFN (5mm × 6mm) (Reference LTC DWG # 05-08-1836 Rev D) 3.00 ± 0.10 3.00 ± 0.10 0.12 ± 0.10 1.88 ± 0.05 1.53 ± 0.05 0.48 ± 0.05 0.12 ± 0.05 0.48 ± 0.10 0.25 ±0.05

3958faFor more information www.linear.com/LT3958 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER A 09/17 Clarification for Boost, Flyback and SEPIC Maximum Output Current Capability sections 15, 18, 20

3958fa For more information www.linear.com/LT3958  LINEAR TECHNOLOGY CORPORATION 2010 LT 0917 REV A • PRINTED IN USA www.linear.com/LT3958 Typical applicaTions PART NUMBER DESCRIPTION COMMENTS L T3580 Boost/Inverting DC/DC Converter with 2A Switch, Soft-Start and Synchronization 2.5V ≤ VIN ≤ 32V , Current Mode Control, 200kHz to 2.5MHz, 3mm × 3mm DFN-8, MSOP-8E L T3573 Isolated Flyback Switching Regulator with 60V Integrated Switch 3V ≤ V IN ≤ 40V , Up to 7W , No Opto-Isolator or Third Winding Required, MSOP-16E L T3574 Isolated Flyback Switching Regulator with 60V Integrated Switch 3V ≤ V IN ≤ 40V , Up to 3W , No Opto-Isolator or Third Winding Required, MSOP-16E L T3757 Boost, Flyback, SEPIC and Inverting Controller 2.9V ≤ V IN ≤ 40V , Current Mode Control, 100kHz to 1MHz Programmable Operation Frequency, 3mm × 3mm DFN-10 and MSOP-10E Package L T3758 Boost, Flyback, SEPIC and Inverting Controller 5.5V ≤ V IN ≤ 100V , Current Mode Control, 100kHz to 1MHz Programmable Operation Frequency, 3mm × 3mm DFN-10 and MSOP-10E Package LT C®1871/L TC1871-1/ L TC1871-7 Wide Input Range, No RSENSE™ Low Quiescent Current Flyback, Boost and SEPIC Controller Adjustable Switching Frequency, 2.5V ≤ VIN ≤ 36V , Burst Mode Operation at Light Load L T3825 Isolated No-Opto Synchronous Flyback Controller V IN 16V to 75V Limited by External Components, Up to 60W , Current Mode Control LT3837 Isolated No-Opto Synchronous Flyback Controller VIN 4.5V to 36V Limited by External Components, Up to 60W , Current Mode Control LT1725 Isolated No-Opto Flyback Controller VIN 16V to 75V Limited by External Components, Current Mode Control L T1737 Isolated No-Opto Flyback Controller VIN 4.5V to 36V Limited by External Components, Current Mode Control L TC3803/L TC3803-5 200kHz Flyback DC/DC Controller VIN and VOUT Limited Only by External Components, ThinSOT™ Package L TC3805/L TC3805-5 Adjustable Fixed 70kHz to 700kHz Operating Frequency Flyback Controller VIN and VOUT Limited Only by External Components, 3mm × 3mm DFN-10, MSOP-10E L T1619 Boost, SEPIC and Flyback Current Mode PWM Controller 1.9V ≤ V IN ≤ 18V , 300kHz Fixed Operating Frequency relaTeD parTs 5V Output Nonisolated Flyback Power Supply Efficiency vs Output Current SENSE2 FBX SENSE1 LT3958 3:1 VIN SW GND RT SS INTVCC EN/UVLO SYNC SGND 32.4k VC

3958 TA06a

63.4k 200kHz 4.7µF 10V X5R 0.47µF 10k 10nF 100pF 34k 15.8k COUT 100µF 6.3V V OUT V IN 10V TO 40V CIN 4.7µF 50V X5R T1: COILTRONICS VP2-0066

• 0.1µF 50V 1.8k DSN OUTPUT CURRENT (A) EFFICIENCY (%)

0 0.5 1 1.5 2 VIN = 24V