LT3845

LT3845 - High Voltage Synchronous Current Mode Step-Down Controller with Adjustable Operating Frequency

Document overview

• Manufacturer or author: Linear Technology Corporation
• PDF pages: 26

Technical content

FEATURES

APPLICATIONS

DESCRIPTION

Controller with Adjustable Operating Frequency The L T®3845 is a high voltage, synchronous, current mode controller used for medium to high power , high effi ciency supplies. It offers a wide 4V to 60V input range (7.5V minimum start-up voltage). An onboard regulator simplifi es the biasing requirements by providing IC power directly from V IN. Burst Mode® operation maintains high effi ciency at light loads by reducing IC quiescent current to 120μA. Light load effi ciency is also improved with the reverse inductor current inhibit function which supports discontinuous operation. Additional features include adjustable fi xed operating frequency that can be synchronized to an external clock for noise sensitive applications, gate drivers capable of driving large N-channel MOSFETs, a precision undervoltage lockout, 10μA shutdown current, short-circuit protection and a programmable soft-start. The L T3845 is available in a 16-lead thermally enhanced TSSOP package and 16-pin through hole N package. ■ High Voltage Operation: Up to 60V ■ Synchronizable Up to 600kHz ■ Adjustable Constant Frequency: 100kHz to 500kHz ■ Output Voltages Up to 36V ■ Adaptive Nonoverlap Circuitry Prevents Switch Shoot-Through ■ Reverse Inductor Current Inhibit for Discontinuous Operation Improves Effi ciency with Light Loads ■ Programmable Soft-Start ■ 120μA No Load Quiescent Current ■ 10μA Shutdown Supply Current ■ 1% Regulation Accuracy ■ Standard Gate N-Channel Power MOSFETs ■ Current Limit Unaffected by Duty Cycle ■ Reverse Overcurrent Protection ■ 16-Lead Thermally Enhanced TSSOP Package, 16-Pin PDIP ■ 12V and 42V Automotive and Heavy Equipment ■ 48V Telecom Power Supplies ■ Avionics and Industrial Control Systems ■ Distributed Power Converters High Voltage Step-Down Regulator 48V to 12V at 75W Effi ciency and Power Loss vs Load Current L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective VIN SHDN CSS BURST_EN VFB VC SYNC fSET BOOST TG SW VCC BG PGND SENSE+ SENSE– SGND BAS521 1N4148

3845 TA01a

0.1μF 1500pF Si7370DP Si7370DP B160 15μH 0.01ΩL T3845 1μF 33μF VOUT 12V 75W 82.5k 16.2k VIN 20V TO 55V 2.2μF 100V 49.9k 20k 100pF 2200pF 143k 47μF 63V LOAD CURENT (A) 100

3845 TA01b

EFFICIENCY(%) POWER LOSS (W) 0.1 101 VIN = 48V LOSS

ABSOLUTE MAXIMUM RATINGS(Note 1) Differential Boost Voltage Bias Supply Voltage (V Differential Sense Voltage (SENSE LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L T3845EFE#PBF L T3845EFE#TRPBF 3845FE 16-Lead Plastic TSSOP –40°C to 125°C L T3845IFE#PBF L T3845IFE#TRPBF 3845FE 16-Lead Plastic TSSOP –40°C to 125°C L T3845MPFE#PBF L T3845MPFE#TRPBF 3845FE 16-Lead Plastic TSSOP –55°C to 125°C L T3845EN#PBF L T3845EN#TRPBF 3845N 16-Lead PDIP –40°C to 125°C Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container. Consult L TC Marketing for information on non-standard lead based fi nish parts. For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear .com/tapeandreel/ FE PACKAGE 16-LEAD PLASTIC TSSOP TOP VIEW V IN SHDN CSS BURST_EN VFB VC SYNC fSET BOOST TG SW V CC BG PGND SENSE SENSE– TJMAX = 125°C, θJA = 40°C/W , θJC = 10°C/W EXPOSED PAD (PIN 17) IS SGND, MUST BE SOLDERED TO PCB N PACKAGE 16-LEAD PDIP TOP VIEW V FB VC fSET SGND SENSE– SENSE+ PGND BG BURST_EN C SS SHDN V IN BOOST TG SW V CC TJMAX = 125°C, θJA = 70°C/W , θJC = 34°C/W PIN CONFIGURATION Operating Junction Temperature Range (Note 2)

PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Operating Voltage Range (Note 4) VIN Minimum Start Voltage VIN UVLO Threshold (Falling) VIN UVLO Threshold Hysteresis 3.6 3.8 670 7.5 V V V mV V IN Supply Current VIN Burst Mode Current VIN Shutdown Current VCC > 9V VBURST_EN = 0V , VFB = 1.35V VSHDN = 0V ● 91 5 μA μA μA BOOST Operating Voltage Range BOOST Operating Voltage Range (Note 5) BOOST UVLO Threshold (Rising) BOOST UVLO Threshold Hysteresis V BOOST – VSW VBOOST – VSW VBOOST – VSW 400 V V V mV BOOST Supply Current (Note 6) BOOST Burst Mode Current BOOST Shutdown Current V BURST_EN = 0V VSHDN = 0V 1.4 0.1 0.1 mA μA μA V CC Operating Voltage Range (Note 5) VCC Output Voltage VCC UVLO Threshold (Rising) VCC UVLO Threshold Hysteresis Over Full Line and Load Range

• 8 6.25 500 8.3 V V V mV V CC Supply Current (Note 6) VCC Burst Mode Current VCC Shutdown Current VCC Current Limit VBURST_EN = 0V VSHDN = 0V
• –40 100 –150 3.7 mA μA μA mA Error Amp Reference Voltage Measured at V FB Pin 1.224 1.215 1.231 1.238 1.245 V V VFB Pin Input Current V FB = 1.231V 25 nA SHDN Enable Threshold (Rising) SHDN Threshold Hysteresis
• 1.3 1.35 120 1.4 V mV Sense Pins Common Mode Range Current Limit Sense Voltage Reverse Protect Sense Voltage Reverse Current Inhibit Offset V SENSE+ – VSENSE– VSENSE+ – VSENSE–, VBURST_EN = VCC VBURST_EN = 0V or VBURST_EN = VFB 90 100 –100 115 V mV mV mV Input Current (I SENSE+ + ISENSE–)V SENSE(CM) = 0V VSENSE(CM) = 2V VSENSE(CM) > 4V 800 –20 –300 μA μA μA Operating Frequency
• 270 300 330 kHz Minimum Programmable Frequency Maximum Programmable Frequency
• 500 100 kHz kHz External Sync Frequency Range ● 100 600 kHz SYNC Input Resistance 40 kΩ SYNC Voltage Threshold ● 1.4 2 V Soft-Start Capacitor Control Current 2μ A Error Amp T ransconductance ● 270 340 410 μS Error Amp DC Voltage Gain 62 dB Error Amp Sink/Source Current ±30 μA ELECTRICAL CHARACTERISTICSThe l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VIN = 20V , VCC = BOOST = BURST_EN = 10V , SHDN = 2V , RSET = 49.9kΩ, SENSE– = SENSE+ = 10V , SGND = PGND = SW = SYNC = 0V , unless otherwise noted.

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The L T3845 includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specifi ed maximum operating junction temperature may impair device reliability. Note 3: The L T3845E is guaranteed to meet performance specifi cations from 0°C to 125°C junction temperature. Specifi cations over the – 40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The L T3845I is guaranteed over the full –40°C to 125°C operating junction temperature range. The L T3845MP is 100% tested and guaranteed over the –55°C to 125°C temperature range. Note 4: V IN voltages below the start-up threshold (7.5V) are only supported when the VCC is externally driven above 6.5V . Note 5: Operating range is dictated by MOSFET absolute maximum VGS. Note 6: Supply current specifi cation does not include switch drive currents. Actual supply currents will be higher . Note 7: DC measurement of gate drive output “ON” voltage is typically 8.6V . Internal dynamic bootstrap operation yields typical gate “ON” voltages of 9.8V during standard switching operation. Standard operation gate “ON” voltage is not tested but guaranteed by design. Note 8: The –2V absolute maximum on the SW pin is a transient condition. It is guaranteed by design and not subject to test. ELECTRICAL CHARACTERISTICSThe l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VIN = 20V , VCC = BOOST = BURST_EN = 10V , SHDN = 2V , RSET = 49.9kΩ, SENSE– = SENSE+ = 10V , SGND = PGND = SW = SYNC = 0V , unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS TG, BG Drive On Voltage (Note 7) TG, BG Drive Off Voltage CLOAD = 3300pF CLOAD = 3300pF 9.8 0.1 V V TG, BG Drive Rise/Fall Time 10% to 90% or 90% to 10%, C LOAD = 3300pF 50 ns Minimum TG Off Time ● 350 650 ns Minimum TG On Time ● 250 400 ns Gate Drive Nonoverlap Time TG Fall to BG Rise BG Fall to TG Rise 200 150 ns ns

Shutdown Threshold (Rising) vs Temperature VCC vs Temperature VCC vs ICC(LOAD) ICC Current Limit vs Temperature VCC UVLO Threshold (Rising) vs Temperature I CC vs VCC (SHDN = 0V) Error Amp T ransconductance vs Temperature TYPICAL PERFORMANCE CHARACTERISTICS

3845 G01

SHUTDOWN THRESHOLD, RISING (V) 1.38 1.37 1.36 1.35 1.34 1.33 1.32 TEMPERATURE (°C) –50 25 75–25 0 50 100 125 Shutdown Threshold (Falling) vs Temperature

3845 G02

TEMPERATURE (°C) –50 SHUTDOWN THRESHOLD, FALLING (V) 1.26 1.25 1.24 1.23 1.22 1.21 1.20 25 75–25 0 50 100 125 TEMPERATURE (°C) –50 25 75–25 0 50 100 125

3845 G03

8.2 8.1 8.0 7.9 7.8 7.7 7.6 7.5 VCC (V) ICC = 20mA ICC(LOAD) (mA) VCC (V)

3845 G04

8.05 8.00 7.95 7.90 7.85 51 5 2 5 35 TA = 25°C VCC vs VIN

3845 G05

VIN (V) VCC (V) 4 6 8 957 10 11 12 ICC = 20mA TA = 25°C –50 –25 100 0 50 12525 75 TEMPERATURE (°C) 225 200 175 150 125 100

3845 G06

ICC CURRENT LIMIT (mA)

3845 G07

TEMPERATURE (°C) –50 25 75–25 0 50 100 12 5 VCC UVLO THRESHOLD, RISING (V) 6.5 6.4 6.3 6.2 6.1 6.0

3845 G08

VCC (V) ICC (μA) 246 81 0 12 14 18 20 TA = 25°C TEMPERATURE (°C) –50 ERROR AMP TRANSCONDUCTANCE (μS) 350 345 340 335 330 325 320 25 75

3845 G09

–25 0 50 100 125

TEMPERATURE (°C) –50 CURRENT SENSE THRESHOLD (mV) 102 104 106 25 75

3845 G13

–25 0 50 100 125 VIN UVLO Threshold (Rising) vs Temperature TEMPERATURE (°C) –50 25 75–25 0 50 100 125

3845 G14

4.54 4.52 4.50 4.48 4.46 4.44 4.42

4.40 VIN UVLO THRESHOLD, RISING (V)

VIN UVLO Threshold (Falling) vs Temperature TEMPERATURE (°C) –50 25 75–25 0 50 100 125

3845 G15

VIN UVLO THRESHOLD, FALLING (V) 3.86 3.84 3.82 3.80 3.78 3.76 TYPICAL PERFORMANCE CHARACTERISTICS I(SENSE+ + SENSE–) vs VSENSE(CM) Operating Frequency vs Temperature VSENSE(CM) (V) I(SENSE+ + SENSE–) (μA) 800 600 400 200 –200 –400 1.0 2.0 3.0 4.0

3845 G10

5.0 TA = 25°C TEMPERATURE (°C) –50

290 OPERATING FREQUENCY (kHz)

3845 G11

0–25 75 10025 12 5 302 304 306 TEMPERATURE (°C) –50 25 75

3845 G12

–25 0 50 100 125 1.234 1.233 1.232 1.231 1.230 1.229 1.228

1.227 ERROR AMP REFERENCE (V)

BG: The BG pin is the gate drive for the bottom N-channel MOSFET . Since very fast high currents are driven from this pin, connect it to the gate of the power MOSFET with a short and wide, typically 0.02" width, PCB trace to minimize inductance. BOOST : The BOOST pin is the supply for the bootstrapped gate drive and is externally connected to a low ESR ceramic boost capacitor referenced to SW pin. The recommended value of the BOOST capacitor , C BOOST, is at least 50 times greater than the total gate capacitance of the topside MOSFET . In most applications 0.1μF is adequate. The maximum volt- age that this pin sees is V IN + VCC, ground referred. BURST_EN: Burst Mode Operation Enable Pin. This pin also controls reverse-current inhibit mode of operation. When the pin voltage is below 0.5V , Burst Mode operation and reverse-current inhibit functions are enabled. When the pin voltage is above 0.5V , Burst Mode operation is dis- abled, but reverse-current inhibit operation is maintained. In this mode of operation (BURST_EN = V FB) there is a 1mA minimum load requirement. Reverse-current inhibit is disabled when the pin voltage is above 2.5V . This pin is typically shorted to ground to enable Burst Mode operation and reverse-current inhibit, shorted to V FB to disable Burst Mode operation while enabling reverse-current inhibit, and connected to V CC pin to disable both functions. See Applications Information section. CSS: The soft-start pin is used to program the supply soft- start function. Use the following formula to calculate CSS for a given output voltage slew rate: C SS = 2μA(tSS/1.231V) The pin should be left unconnected when not using the soft-start function. fSET: The fSET pin programs the oscillator frequency with an external resistor , RSET. The resistor is required even when supplying external sync clock signal. See the Applications Information section for resistor value selection details. PGND: The PGND pin is the high-current ground reference for internal low side switch driver and the V CC regulator circuit. Connect the pin directly to the negative terminal of the VCC decoupling capacitor . See the Application Informa- tion section for helpful hints on PCB layout of grounds. SENSE–: The SENSE – pin is the negative input for the current sense amplifi er and is connected to the V OUT side of the sense resistor for step-down applications. The sensed inductor current limit is set to ±100mV across the SENSE inputs. SENSE +: The SENSE + pin is the positive input for the current sense amplifi er and is connected to the inductor side of the sense resistor for step-down applications. The sensed inductor current limit is set to ±100mV across the SENSE inputs. SGND: The SGND pin is the low noise ground reference. It should be connected to the –V OUT side of the output capacitors. Careful layout of the PCB is necessary to keep high currents away from this SGND connection. See the Application Information section for helpful hints on PCB layout of grounds. SHDN: The SHDN pin has a precision IC enable threshold of 1.35V (rising) with 120mV of hysteresis. It is used to implement an undervoltage lockout (UVLO) circuit. See Application Information section for implementing a UVLO function. When the SHDN pin is pulled below a transistor V BE (0.7V), a low current shutdown mode is entered, all internal circuitry is disabled and the V IN supply current is reduced to approximately 9μA. Typical pin input bias current is <10nA and the pin is internally clamped to 6V . If the function is not used, this pin may be tied to V IN through a high value resistor . SW: Reference for VBOOST Supply and High Current Return for Bootstrapped Switch. SYNC: The Sync pin provides an external clock input for synchronization of the internal oscillator . RSET is set such that the internal oscillator frequency is 10% to 25% below the external clock frequency. If unused the Sync pin is connected to SGND. For more information see “Oscillator Sync” in the Application Information section of this data sheet. Sync pin not available in PDIP package. PIN FUNCTIONS

TG: The TG pin is the bootstrapped gate drive for the top N-Channel MOSFET . Since very fast high currents are driven from this pin, connect it to the gate of the power MOSFET with a short and wide, typically 0.02” width, PCB trace to minimize inductance. V C: The VC pin is the output of the error amplifi er whose voltage corresponds to the maximum (peak) switch current per oscillator cycle. The error amplifi er is typically confi g- ured as an integrator by connecting an RC network from the V C pin to SGND. This circuit creates the dominant pole for the converter regulation control loop. Specifi c integra- tor characteristics can be confi gured to optimize transient response. When Burst Mode operation is enabled (see Pin 4 description), an internal low impedance clamp on the V C pin is set at 100mV below the burst threshold, which limits the negative excursion of the pin voltage. Therefore, this pin cannot be pulled low with a low impedance source. If the V C pin must be externally manipulated, do so through a 1kΩ series resistance. VCC: The V CC pin is the internal bias supply decoupling node. Use a low ESR, 1μF or greater ceramic capacitor to decouple this node to PGND. Most internal IC functions PIN FUNCTIONS are powered from this bias supply. An external diode con- nected from V CC to the BOOST pin charges the bootstrapped capacitor during the off-time of the main power switch. Back driving the V CC pin from an external DC voltage source, such as the VOUT output of the regulator supply, increases overall effi ciency and reduces power dissipation in the IC. In shutdown mode this pin sinks 20μA until the pin voltage is discharged to 0V . V FB: The output voltage feedback pin, V FB, is externally connected to the supply output voltage via a resistive divider . The V FB pin is internally connected to the inverting input of the error amplifi er . In regulation, VFB is 1.231V . VIN: The V IN pin is the main supply pin and should be decoupled to SGND with a low ESR capacitor (at least 0.1μF) located close to the pin. Exposed Pad (SGND) (TSSOP Only): The exposed lead- frame is internally connected to the SGND pin. Solder the exposed pad to the PCB ground for electrical contact and optimal thermal performance.

– + – + VIN UVLO (<4V) BST UVLO REG FEEDBACK REFERENCE 1.231V 3.8V REG INTERNAL SUPPL Y RAIL VIN VCC UVLO (<6V) SHDN VREF DRIVE CONTROL NOL SWITCH LOGIC DRIVE CONTROL BURST_EN RB VC CSS SENSE– VFB VREF + 100mV FAUL T CONDITIONS: VIN UVLO VCC UVLO VSHDN UVLO 2μA 0.5V100mV ERROR AMP Burst Mode OPERATION SOFT-START BURST DISABLECSS CLAMPED TO VREF + VBE R SQ OSCILLATOR SLOPE COMP GENERATOR BOOST CBOOST M1TG DRIVER DRIVER SW VCC BG PGND SYNC fSET RSET SENSE+ 3845 FD BOOSTED SWITCH DRIVER CURRENT SENSE COMPARATOR gm R S Q – + 110mV REVERSE CURRENT INHIBIT 10mV SGND COUT VOUT RSENSE (OPTIONAL) CVCC CIN VIN RC CC1 RA CSS CC2

The L T3845 is a high input voltage range step-down synchronous DC/DC converter controller IC that uses a programmable constant frequency, current mode archi- tecture with external N-channel MOSFET switches. The L T3845 has provisions for high effi ciency, low load operation for battery-powered applications. Burst Mode operation reduces total average input quiescent currents to 120μA during no load conditions. A low current shutdown mode can also be activated, reducing quiescent current to 10μA. Burst Mode operation can be disabled if desired. A reverse-current inhibit feature allows increased effi cien- cies during light loads through nonsynchronous operation. This feature disables the synchronous switch if inductor current approaches zero. If full time synchronous opera- tion is desired, this feature can be disabled. Much of the IC’s internal circuitry is biased from an internal linear regulator . The output of this regulator is the V CC pin, allowing bypassing of the internal regulator . The associated internal circuitry can be powered from the output of the converter , increasing overall converter effi ciency. Using externally derived power also eliminates the IC’s power dissipation associated with the internal V IN to VCC regulator . Theory of Operation (See Block Diagram) The L T3845 senses converter output voltage via the VFB pin. The difference between the voltage on this pin and an internal 1.231V reference is amplifi ed to generate an error voltage on the V C pin which is used as a threshold for the current sense comparator . During normal operation, the L T3845 internal oscillator runs at the programmed frequency. At the beginning of each oscillator cycle, the switch drive is enabled. The switch drive stays enabled until the sensed switch current exceeds the V C derived threshold for the current sense comparator and, in turn, disables the switch driver . If the current comparator threshold is not obtained for the entire oscillator cycle, the switch driver is disabled at the end of the cycle for 350ns, typical. This minimum off-time mode of operation assures regeneration of the BOOST bootstrapped supply. Power Requirements The L T3845 is biased using an internal linear regulator to generate operational voltages from the V IN pin. Virtually all of the circuitry in the L T3845 is biased via this internal linear regulator output (V CC). This pin is decoupled with a low ESR, 1μF capacitor to PGND. The VCC regulator generates an 8V output provided there is ample voltage on the V IN pin. The V CC regulator has approximately 1V of dropout, and will follow the V IN pin with voltages below the dropout threshold. The L T3845 has a start-up requirement of VIN > 7.5V . This assures that the onboard regulator has ample headroom to bring the V CC pin above its UVLO threshold. The V CC regulator can only source current, so forcing the VCC pin above its 8V regulated voltage allows use of externally derived power for the IC, minimizing power dissipation in the IC. Using the onboard regulator for start-up, then deriving power for V CC from the converter output maximizes conversion effi ciencies and is common practice. If VCC is maintained above 6.5V using an external source, the L T3845 can continue to operate with V IN as low as 4V . The L T3845 operates with 3mA quiescent current from the VCC supply. This current is a fraction of the actual VCC quiescent currents during normal operation. Additional current is produced from the MOSFET switching currents for both the boosted and synchronous switches and are typically derived from the V CC supply. Because the L T3845 uses a linear regulator to generate VCC, power dissipation can become a concern with high VIN voltages. Gate drive currents are typically in the range of 5mA to 15mA per MOSFET , so gate drive currents can create substantial power dissipation. It is advisable to derive V CC and V BOOST power from an external source whenever possible. The onboard VCC regulator will provide gate drive power for start-up under all conditions with total MOSFET gate charge loads up to 180nC. The regulator can operate the L T3845 continuously, provided the power dissipation of the regulator does not exceed 250mW . The power dissipation of the regulator is calculated as follows: P D(REG) = (VIN – 8V) • (fSW • QG(TOTAL) + 3mA)

where QG(TOTAL) is the total MOSFET gate charge of the TG and BG. In applications where these conditions are exceeded, VCC must be derived from an external source after start-up. Maximum continuous regulator power dissipation may be exceeded for short duration V IN transients. In L T3845 converter applications with output voltages in the 9V to 20V range, back-feeding VCC and VBOOST from the converter output is trivial, accomplished by connect- ing diodes from the output to these supply pins. Deriving these supplies from output voltages greater than 20V will require additional regulation to reduce the feedback voltage. Outputs lower than 9V will require step-up techniques to increase the feedback voltage to something greater than the 8V V CC regulated output. Low power boost switchers are sometimes used to provide the step-up function, but a simple charge-pump can perform this function in many instances. Burst Mode The L T3845 employs low current Burst Mode functional- ity to maximize effi ciency during no load and low load conditions. Burst Mode operation is enabled by shorting the BURST_EN pin to SGND. Burst Mode operation can be disabled by shorting BURST_EN to either V FB or VCC. When the required switch current, sensed via the V C pin voltage, is below 15% of maximum, the Burst Mode operation is employed and that level of sense current is latched onto the IC control path. If the output load requires less than this latched current level, the converter will overdrive the output slightly during each switch cycle. This overdrive condition is sensed internally and forces the voltage on the V C pin to continue to drop. When the voltage on V C drops 150mV below the 15% load level, switching is disabled and the L T3845 shuts down most of its internal circuitry, reducing total quiescent current to 120μA. When the converter output begins to fall, the V C pin voltage begins to climb. When the voltage on the VC pin climbs back to the 15% load level, the IC returns to normal operation and switching resumes. An internal clamp on the V C pin is set at 100mV below the switch disable threshold, which limits the negative excursion of the pin voltage, minimizing the converter output ripple during Burst Mode operation. During Burst Mode operation, V IN pin current is 20μA and VCC current is reduced to 100μA. If no external drive is provided for VCC, all VCC bias currents originate from the APPLICATIONS INFORMATION VOUT 1μF B0520 B0520 1μF Si1555DL L T3845 Charge Pump Doubler Charge Pump T ripler VCC BG VOUT 1μF B0520 B0520 1μF 1μF Si1555DLSi1555DL L T3845 VCC BG B0520

3845 AI01

3845 AI04

N L T3845 Inductor Auxiliary Winding

then reduced by the converter buck ratio. pulse-skipping mode at light loads. Refer to Figure 1. positive offset at the sense inputs. converter output voltage programming resistors (R1). conduction mode (BURST_EN > 2.5V). Figure 1. Inductor Current vs Mode

3845 F01

at start-up the soft-start circuit will discharge the VC pin voltage below the DC control voltage equivalent to zero inductor current. This will reduce the input supply inrush current. The soft-start circuit is disabled once the C SS pin voltage has been charged to 200mV above the internal reference of 1.231V . During a V IN UVLO, VCC UVLO or SHDN UVLO event, the CSS pin voltage is discharged with a 50μA current source. In normal operation the C SS pin voltage is clamped to a diode above the VFB pin voltage. Therefore, the value of the CSS capacitor is relevant to how long of a fault event will retrigger a soft-start. If any of the above UVLO conditions occur , the C SS pin voltage will be discharged with a 50μA current source. There is a diode worth of voltage headroom to ride through the fault before the C SS pin voltage enters its active region and the soft-start function is enabled. Also, since the CSS pin voltage is clamped to a diode above the VFB pin voltage, during a short circuit the CSS pin volt- age is pulled low because the VFB pin voltage is low. Once the short has been removed the VFB pin voltage starts to recover . The soft-start circuit takes control of the output voltage slew rate once the V FB pin voltage has exceeded the slowly ramping CSS pin voltage, reducing the output voltage overshoot during a short circuit recovery. Adaptive Nonoverlap (NOL) Output Stage The FET driver output stages implement adaptive nonover- lap control. This feature maintains a constant dead time, preventing shoot-through switch currents, independent of the type, size or operating conditions of the external switch elements. Each of the two switch drivers contains a NOL control circuit, which monitors the output gate drive signal of the other switch driver . The NOL control circuits interrupt the “turn on” command to their associated switch driver until the other switch gate is fully discharged. Antislope Compensation Most current mode switching controllers use slope com- pensation to prevent current mode instability. The L T3845 is no exception. A slope-compensation circuit imposes an artifi cial ramp on the sensed current to increase the rising slope as duty cycle increases. Unfortunately, this additional APPLICATIONS INFORMATION ramp corrupts the sensed current value, reducing the achievable current limit value by the same amount as the added ramp represents. As such, current limit is typically reduced as duty cycles increase. The L T3845 contains circuitry to eliminate the current limit reduction typically associated with slope compensation. As the slope-com- pensation ramp is added to the sensed current, a similar ramp is added to the current limit threshold reference. The end result is that current limit is not compromised, so an L T3845 converter can provide full power regardless of required duty cycle. Shutdown The L T3845 SHDN pin uses a bandgap generated reference threshold of 1.35V . This precision threshold allows use of the SHDN pin for both logic-level controlled applications and analog monitoring applications such as power supply sequencing. The L T3845 operational status is primarily controlled by a UVLO circuit on the V CC regulator pin. When the IC is enabled via the SHDN pin, only the VCC regulator is enabled. Switching remains disabled until the UVLO threshold is achieved at the V CC pin, when the remainder of the IC is enabled and switching commences. Because an L T3845 controlled converter is a power transfer device, a voltage that is lower than expected on the input supply could require currents that exceed the sourcing capabilities of that supply, causing the system to lock up in an undervoltage state. Input supply start-up protection can be achieved by enabling the SHDN pin using a resistive divider from the V IN supply to ground. Setting the divider output to 1.35V when that supply is at an adequate voltage prevents an L T3845 converter from drawing large currents until the input supply is able to provide the required power . 120mV of input hysteresis on the SHDN pin allows for almost 10% of input supply droop before disabling the converter . R SENSE Selection The current sense resistor , RSENSE, monitors the inductor current of the supply (See Typical Application on front page). Its value is chosen based on the maximum required output load current. The L T3845 current sense amplifi er

has a maximum voltage threshold of, typically, 100mV . Therefore, the peak inductor current is 100mV/R SENSE. current, resulting in a larger inductor size and higher cost. Table 1. Recommended 1% Standard Values tion current and/or RMS current. fSW is the switch frequency. Figure 2. Timing Resistor (RSET) Value

will increase the peak currents, requiring more fi ltering on the input and output of the supply. If ΔI L is too high, the slope compensation circuit is ineffective and current mode instability may occur at duty cycles greater than 50%. To satisfy slope compensation requirements the minimum inductance is calculated as follows: LMIN > VOUT  2DCMAX –1 DCMAX  RSENSE  8.33 fSW The magnetics vendors specify either the saturation cur- rent, the RMS current or both. When selecting an inductor based on inductor saturation current, use the peak cur- rent through the inductor , I OUT(MAX) + ΔIL/2. The inductor saturation current specifi cation is the current at which the inductance, measured at zero current, decreases by a specifi ed amount, typically 30%. When selecting an inductor based on RMS current rating, use the average current through the inductor , I OUT(MAX). The RMS current specifi cation is the RMS current at which the part has a specifi c temperature rise, typically 40°C, above 25°C ambient. After calculating the minimum inductance value, the volt-second product, the saturation current and the RMS current for your design, select an off-the-shelf inductor . Contact the Application group at Linear Technology for further support. For more detailed information on selecting an inductor , please see the “Inductor Selection” section of Linear Technology Application Note 44. MOSFET Selection The selection criteria of the external N-channel standard level power MOSFETs include on resistance (R DS(ON)), reverse transfer capacitance (C RSS), maximum drain source voltage (VDSS), total gate charge (QG) and maximum continuous drain current. For maximum effi ciency, minimize R DS(ON) and C RSS. Low RDS(ON) minimizes conduction losses while low CRSS minimizes transition losses. The problem is that RDS(ON) is inversely related to CRSS. In selecting the top MOSFET balancing the transition losses with the conduction losses is a good idea while the bottom MOSFET is dominated by the conduction loss, which is worse during a short-circit condition or at a very low duty cycle. Calculate the maximum conduction losses of the MOSFETs: PCOND(TOP) =IOUT(MAX) 2  VOUT VIN RDS(ON) PCOND(BOT) =IOUT(MAX) 2  VIN –V OUT VIN RDS(ON) Note that RDS(ON) has a large positive temperature depen- dence. The MOSFET manufacturer’s data sheet contains a curve, R DS(ON) vs Temperature. In the main MOSFET , transition losses are proportional to VIN2 and can be considerably large in high voltage ap- plications (VIN > 20V). Calculate the maximum transition losses: P TRAN(TOP) = k • VIN2 • IOUT(MAX) • CRSS • fSW where k is a constant inversely related to the gate driver current, approximated by k = 2 for L T3845 applications. The total maximum power dissipations of the MOSFET are: P TOP(TOTAL) = PCOND(MAIN) + PTRAN(MAIN) P BOT(TOTAL) = PCOND(SYNC) To achieve high supply effi ciency, keep the total power dis- sipation in each switch to less than 3% of the total output power . Also, complete a thermal analysis to ensure that the MOSFET junction temperature is not exceeded. T J = TA + P(TOTAL) • θJA where θJA is the package thermal resistance and TA is the ambient temperature. Keep the calculated TJ below the max- imum specifi ed junction temperature, typically 150°C. Note that when VIN is high and fSW is high, the transition losses may dominate. A MOSFET with higher R DS(ON) and lower CRSS may provide higher effi ciency. MOSFETs with higher voltage VDSS specifi cation usually have higher RDS(ON) and lower CRSS.

Choose the MOSFET V DSS specifi cation to exceed the maximum voltage across the drain to the source of the MOSFET , which is V IN(MAX) plus any additional ringing on the switch node. Ringing on the switch node can be greatly reduced with good PCB layout and, if necessary, an RC snubber . In some applications, parasitic FET capacitances couple the negative going switch node transient onto the bottom gate drive pin of the L T3845, causing a negative voltage in excess of the Absolute Maximum Rating to be imposed on that pin. Connection of a catch Schottky diode from this pin to ground will eliminate this effect. A 1A current rating is typically suffi cient of the diode. The internal V CC regulator is capable of sourcing up to 40mA limiting the maximum total MOSFET gate charge, Q G, to 35mA/fSW. The QG vs VGS specifi cation is typically provided in the MOSFET data sheet. Use QG at VGS of 8V . If VCC is back driven from an external supply, the MOSFET drive current is not sourced from the internal regulator of the L T3845 and the Q G of the MOSFET is not limited by the IC. However , note that the MOSFET drive current is supplied by the internal regulator when the external supply back driving V CC is not available such as during start-up or short circuit. The manufacturer’s maximum continuous drain current specifi cation should exceed the peak switch current, I OUT(MAX) + ΔIL/2. During the supply start-up, the gate drive levels are set by the VCC voltage regulator , which is approximately 8V . Once the supply is up and running, the VCC can be back driven by an auxiliary supply such as VOUT. It is important not to exceed the manufacturer’s maximum V GS specifi cation. A standard level threshold MOSFET typically has a V GS maximum of 20V . Input Capacitor Selection A local input bypass capacitor is required for buck convert- ers because the input current is pulsed with fast rise and fall times. The input capacitor selection criteria are based on the bulk capacitance and RMS current capability. The bulk capacitance will determine the supply input ripple voltage. The RMS current capability is used to prevent overheating the capacitor . The bulk capacitance is calculated based on maximum input ripple, ΔV IN: CIN(BULK) = IOUT(MAX) V OUT ΔVIN f SW V IN(MIN) ΔVIN is typically chosen at a level acceptable to the user . 100mV to 200mV is a good starting point. Aluminum elec- trolytic capacitors are a good choice for high voltage, bulk capacitance due to their high capacitance per unit area. The capacitor’s RMS current is: ICIN(RMS) =IOUT VOUT (VIN –V OUT) (VIN)2 If applicable, calculate it at the worst case condition, VIN = 2V OUT. The RMS current rating of the capacitor is specifi ed by the manufacturer and should exceed the calculated I CIN(RMS). Due to their low ESR (Equivalent Series Resistance), ceramic capacitors are a good choice for high voltage, high RMS current handling. Note that the ripple current ratings from aluminum electrolytic capacitor manufacturers are based on 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. The combination of aluminum electrolytic capacitors and ceramic capacitors is an economical approach to meet- ing the input capacitor requirements. The capacitor volt- age rating must be rated greater than V IN(MAX). Multiple capacitors may also be paralleled to meet size or height requirements in the design. Locate the capacitor very close to the MOSFET switch and use short, wide PCB traces to minimize parasitic inductance. Output Capacitor Selection The output capacitance, C OUT, selection is based on the design’s output voltage ripple, ΔVOUT and transient load requirements. ΔVOUT is a function of ΔI L and the C OUT ESR. It is calculated by: VOUT = IL •E S R + 1 (8 • fSW •COUT)

LC fi lter stage can be added to the output of the supply. lockout is disabled and the supply turns on.

3845 F03

3845 F04

Figure 3. Output Voltage Feedback Divider Figure 4. Undervoltage Feedback Divider

If low supply current in standby mode is required, select a higher value of RB. The supply turn off voltage is 9% below turn on. In the example the VSUPPL Y(OFF) would be 13.2V . If additional hysteresis is desired for the enable function, an external positive feedback resistor can be used from the L T3845 regulator output. The shutdown function can be disabled by connecting the SHDN pin to the V IN through a large value pull-up resistor . This pin contains a low impedance clamp at 6V , so the SHDN pin will sink current from the pull-up resistor(RPU): ISHDN = VIN –6V RPU Because this arrangement will clamp the SHDN pin to the 6V , it will violate the 5V absolute maximum voltage rating of the pin. This is permitted, however , as long as the absolute maximum input current rating of 1mA is not exceeded. Input SHDN pin currents of <100μA are recommended: a 1MΩ or greater pull-up resistor is typically used for this confi guration. Soft-Start The desired soft-start time (t SS) is programmed via the CSS capacitor as follows: CSS = 2µA  tSS 1.231V The amount of time in which the power supply can withstand a VIN, VCC or VSHDN UVLO fault condition (tFAULT) before the CSS pin voltage enters its active region is approximated by the following formula: tFAULT = CSS  0.65V 50µA Oscillator SYNC The oscillator can be synchronized to an external clock. Set the RSET resistor at least 10% below the desired sync frequency. It is recommended that the SYNC pin be driven with a square wave that has amplitude greater than 2V , pulse width greater than 1μs and rise time less than 500ns. The rising edge of the sync wave form triggers the discharge of the internal oscillator capacitor . The SYNC pin is not available in the N-Package. Minimum On-Time Considerations (Buck Mode) Minimum on-time t ON(MIN) is the smallest amount of time that the L T3845 is capable of turning the top MOSFET on and off again. It is determined by internal timing delays and the amount of gate charge required turning on the top MOSFET . Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: tON = VOUT VIN f SW > tON(MIN) where tON(MIN) is 400ns worst case. If the duty cycle falls below what can be accommodated by the minimum on-time, the L T3845 will begin to skip cycles. The output will be regulated, but the ripple current and ripple voltage will increase. If lower frequency operation is acceptable, the on-time can be increased above t ON(MIN) for the same step-down ratio. Layout Considerations The L T3845 is typically used in DC/DC converter designs that involve substantial switching transients. The switch drivers on the IC are designed to drive large capacitances and, as such, generate signifi cant transient currents themselves. Careful consideration must be made regard- ing supply bypass capacitor locations to avoid corrupting the ground reference used by IC. Typically, high current paths and transients from the input supply and any local drive supplies must be kept isolated from SGND, to which sensitive circuits such as the error amp reference and the current sense circuits are referred. Effective grounding can be achieved by considering switch current in the ground plane, and the return current paths of each respective bypass capacitor . The V IN bypass return, VCC bypass return, and the source of the synchronous APPLICATIONS INFORMATION

FET carry PGND currents. SGND originates at the negative terminal of the V OUT bypass capacitor , and is the small signal reference for the L T3845. Don’t be tempted to run small traces to separate ground paths. A good ground plane is important as always, but PGND referred bypass elements must be oriented such that transient currents in these return paths do not corrupt the SGND reference. During the dead-time between switch conduction, the body diode of the synchronous FET conducts inductor current. Commutating this diode requires a signifi cant charge contribution from the main switch. At the instant the body diode commutates, a current discontinuity is created and parasitic inductance causes the switch node to fl y up in response to this discontinuity. High currents and excessive parasitic inductance can generate ex- tremely fast dV/dt rise times. This phenomenon can cause avalanche breakdown in the synchronous FET body di- ode, signifi cant inductive overshoot on the switch node, and shoot-through currents via parasitic turn-on of the synchronous FET . Layout practices and component ori- entations that minimize parasitic inductance on this node is critical for reducing these effects. Ringing waveforms in a converter circuit can lead to device failure, excessive EMI, or instability. In many cases, you can damp a ringing waveform with a series RC network across the offending device. In L T3845 applications, any ringing will typically occur on the switch node, which can usually be reduced by placing a snubber across the synchronous FET . Use of a snubber network, however , should be considered a last resort. Effective layout practices typically reduce ringing and overshoot, and will eliminate the need for such solutions. Effective grounding techniques are critical for successful DC/DC converter layouts. Orient power path components such that current paths in the ground plane do not cross through signal ground areas. Signal ground refers to the Exposed Pad on the backside of the L T3845 IC in the TSSOP package. SGND is referenced to the (–) terminal of the V OUT decoupling capacitor and is used as the con- verter voltage feedback reference. Power ground currents are controlled on the L T3845 via the PGND pin, and this ground references the high current synchronous switch drive components, as well as the local V CC supply. It is important to keep PGND and SGND voltages consistent with each other , so separating these grounds with thin traces is not recommended. When the synchronous FET is turned on, gate drive surge currents return to the L T3845 PGND pin from the FET source. The BOOST supply refresh surge currents also return through this same path. The synchronous FET must be oriented such that these PGND return currents do not corrupt the SGND reference. Problems caused by the PGND return path are generally recognized during heavy load conditions, and are typically evidenced as multiple switch pulses occurring during a single switch cycle. This behavior indicates that SGND is being corrupted and grounding should be improved. SGND corruption can often be eliminated, however , by adding a small capacitor (100pF to 200pF) across the synchronous switch FET from drain to source. The high di/dt loop formed by the switch MOSFETs and the input capacitor (C IN) should have short wide traces to minimize high frequency noise and voltage stress from inductive ringing. Surface mount components are preferred to reduce parasitic inductances from component leads. Connect the drain of the main switch MOSFET directly to the (+) plate of C IN, and connect the source of the syn- chronous switch MOSFET directly to the (–) terminal of C IN. This capacitor provides the AC current to the switch MOSFETs. Switch path currents can be controlled by orienting switch FETs, the switched inductor , and input and output decoupling capacitors in close proximity to each other . Locate the V CC and BOOST decoupling capacitors in close proximity to the IC. These capacitors carry the MOSFET drivers’ high peak currents. Locate the small-signal components away from high frequency switching nodes (BOOST , SW , TG, V CC and BG). Small-signal nodes are oriented on the left side of the L T3845, while high current switching nodes are oriented on the right side of the IC to simplify layout. This also helps prevent corruption of the SGND reference. Connect the V FB pin directly to the feedback resistors independent of any other nodes, such as the SENSE– pin. The feedback resistors should be connected between the (+) and (–) terminals of the output capacitor (C OUT). APPLICATIONS INFORMATION

Locate the feedback resistors in close proximity to the L T3845 to minimize the length of the high impedance V FB node. The SENSE– and SENSE+ traces should be routed together and kept as short as possible. APPLICATIONS INFORMATION The L T3845 TSSOP package has been designed to ef- fi ciently remove heat from the IC via the Exposed Pad on the backside of the package. The Exposed Pad is soldered to a copper footprint on the PCB. This footprint should be made as large as possible to reduce the thermal resistance of the IC case to ambient air . Orientation of Components Isolates Power Path and PGND Currents, Preventing Corruption of SGND Reference BOOST VCC SW PGNDSGND L T3845SGND REFERRED COMPONENTS + BG TG VOUT

3845 AI03

9V-16V to 3.3V at 10A DC/DC Converter Capable of Withstanding 60V T ransients, All Ceramic Capacitors and Soft-Start Enabled VIN SHDN CSS BURST_EN V FB VC SYNC f SET BOOST TG SW VCC BG PGND SENSE+ SENSE– SGND D2A BAV99 1μF 16V 8200pF Si7370DP Si7370DP 3.3μH RSENSE 0.006ΩL T3845 2.2μF 16V

3845 TA02

100μF 6.3V V OUT 3.3V 10A 1.1M V IN 9V TO 16V 60V TRANSIENTS CIN2 0.1μF 100V 49.9k VIN 100k SYNC 4.99k 12V 25k 10k 16.9k CIN 2.2μF 100V C IN: TDK C4532X7R2A225K COUT: MURATA GRM32ER60J107ME20 D1: DIODES INC. B3100 L1: WURTH 7443551370 D2B BAV99 60V LOAD CURRENT (A) 0.1 BATTERY VOL TAGE (V) POWER LOSS (W) 11 0

3845 TA02b

VIN = 9V VIN = 14V VIN = 16V POWER LOSS VIN = 14V Effi ciency and Power Loss

9V-16V to 5V at 10A DC/DC Converter , 500kHz Frequency Operation, Capable of Withstanding 36V T ransients, All Ceramic Capacitors, Soft-Start and Burst Mode Enabled VIN SHDN CSS BURST_EN V FB VC SYNC f SET BOOST TG SW VCC BG PGND SENSE+ SENSE– SGND D2 BAS19 1μF 16V 8200pF M1 Si7884DP Si7884DP Si1555DL 2.7μH RSENSE 0.005ΩL T3845 2.2μF 16V 1μF D3B BAV99 D3A BAV99

3845 TA03

100μF 6.3V V OUT 10A 1.1M V IN 9V TO 16V 36V TRANSIENTS CIN2 0.1μF 50V 23.2k 10k 49.9k 154k CIN 6.8μF 50V C IN: TDK C4532X7R1H685K COUT: MURATA GRM32ER60J107ME20 D1: DIODES INC. B170 L1: WURTH 744318270LF Effi ciency and Power Loss LOAD CURRENT (A) 0.1 EFFICIENCY (%) POWER LOSS (W) 100 11 0

3845 TA03b

VIN = 9V VIN = 14V VIN = 16V POWER LOSS VIN = 14V

9V-24V to 3.3V , 2-Phase at 10A per Phase, DC/DC Converter with Spread Spectrum Operation VIN SHDN CSS BURST_EN V FB VC SYNC f SET BOOST TG SW VCC BG PGND SENSE+ SENSE– SGND 1μF 16V D2 BAS19 C3 8200pF C11 47pF Si7850DP Si7850DP B160 4.7μH RSENSE 0.005ΩL T3845 2.2μF 16V 1.21M 1.21M VIN 24V 130k SYNC CIN 6.8μF 50V C IN: TDK C4532X7R1H685K COUT: MURATA GRM32ER60J107ME20 D1, D3: DIODES, INC. B160 L1, L2: VISHAY IHLP-5050FD-01 VIN SHDN CSS BURST_EN V FB VC SYNC f SET BOOST TG SW VCC BG PGND SENSE+ SENSE– SGND C10 1μF 16V C8 8200pF Si7850DP Si7850DP B160 4.7μH RSENSE2 0.005ΩL T3845 2.2μF 16V

3845 TA05

4.99k 5600pF 47pF CIN3 0.1μF 100V SYNC1 SYNC2 SYNC 10k R11 500k R12 25k 5.7V C11 0.1μF 16.8k L TC6908-1 GND SET3 OUT1 OUT2 MOD COUT 100μF 6.3V V OUT 3.3V 20A D4 BAS19

16-Lead Plastic TSSOP (4.4mm) (Reference L TC DWG # 05-08-1663) Exposed Pad Variation BC FE16 (BC) TSSOP 0204 0.09 – 0.20 (.0035 – .0079) 0o – 8o 0.25 REF 0.50 – 0.75 (.020 – .030) 4.30 – 4.50* (.169 – .177) 13 4 5 6 7 8 10 9 4.90 – 5.10* (.193 – .201) 16 1514 13 12 11 1.10 (.0433) MAX 0.05 – 0.15 (.002 – .006) 0.65 (.0256) BSC 2.94 (.116) 0.195 – 0.30 (.0077 – .0118) TYP 2RECOMMENDED SOLDER PAD LAYOUT 0.45 p0.05

0.65 BSC

4.50 p0.10 6.60 p0.10 1.05 p0.10 2.94 (.116) 3.58 (.141) 3.58 (.141) MILLIMETERS (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE SEE NOTE 4 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT 6.40 (.252) BSC N Package 16-Lead PDIP (Reference L TC DWG # 05-08-1510) N16 1002 .255 p .015* (6.477 p 0.381) .770* (19.558) MAX 1 2 3 4 5 6 7 8 9101112131415 .020 (0.508) MIN .120 (3.048) MIN .130 p .005 (3.302 p 0.127) .065 (1.651) TYP .045 – .065 (1.143 – 1.651) .018 p .003 (0.457 p 0.076) .008 – .015 (0.203 – 0.381) .300 – .325 (7.620 – 8.255) .325 +.035 –.015 +0.889 –0.3818.255 NOTE: 1. DIMENSIONS ARE INCHES MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm) .100 (2.54) BSC

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER D 1/10 Updated Features and Description Revised Absolute Maximum Ratings, Pin Confi guration and Order Information to Add New Package and Grade Options Revised Electrical Characteristics Revised Pin Functions Updated Block Diagram Revised Oscillator SYNC Section Revised Typical Applications Updated Related Parts List 3, 4 7, 8 21, 22, 23, 26 (Revision history begins at Rev D) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com © LINEAR TECHNOLOGY CORPORATION 2006 LT 0110 REV D • PRINTED IN USA RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS L T3800 High Voltage Low I Q Synchronous Step-Down DC/DC Controller Fixed 200kHz Operating Frequency 4V≤ VIN ≤ 60V , 1.23V ≤ VOUT ≤ 36V , IQ = 100μA, TSSOP-16 L T3844 High Voltage Low I Q Switching Regulator DC/DC Controller Synchronizable Fixed Operating Frequency 100kHz to 600kHz, 4V ≤ VIN ≤ 60V , 1.23V ≤ VOUT ≤ 36V , IQ = 120μA, TSSOP-16 L T3724 High Voltage Low I Q Switching Regulator DC/DC Controller Fixed 200kHz Operating Frequency 4V ≤ V IN ≤ 60V , 1.23V ≤ VOUT ≤ 36V , IQ = 100μA, TSSOP-16 L TC3812-5 High Voltage Synchronous Step-Down DC/DC Controller 4.2V ≤ V IN ≤ 60V , 0.8V ≤ VOUT ≤ 0.9VIN, TSSOP-16 L TC3810 100V Synchronous Step-Down DC/DC Controller 6.2V ≤ V IN ≤ 100V , 0.8V ≤ VOUT ≤ 0.9VIN, SSOP-28 L T3758 100V Boost, Flyback, SEPIC and Inverting Controller 5.5V ≤ V IN ≤ 100V , Selectable Operating Frequency 100kHz to 1MHz 3mm × 3mm DFN-10 and MSOP-10E Package L T3757 Boost, Flyback, SEPIC and Inverting Controller 2.9V ≤ V IN ≤ 40V , Selectable Operating Frequency 100kHz to 1MHz 3mm × 3mm DFN-10 and MSOP-10E Package L TC3824 High Voltage Low I Q DC/DC Controller , 100% Duty Cycle Selectable Fixed Operating Frequency 200kHz to 600kHz 4V ≤ V IN ≤ 60V , 0.8V ≤ VOUT ≤ VIN, IQ = 40μA, MSOP-10E L TC3834/ L TC3834-1 Low IQ, Synchronous Step-Down Controllers 30μA I Q, 4V ≤ VIN ≤ 36V , 0.8V ≤ VOUT ≤ 10V L TC3835/ L TC3835-1 Low IQ, Synchronous Step-Down Controllers 80μA I Q, 4V ≤ VIN ≤ 36V , 0.8V ≤ VOUT ≤ 10V L TC3857/ L TC3857-1 Low IQ, Dual Output 2-Phase Synchronous Step-Down DC/DC Controller with 99% Duty Cycle Phase-Lockable Fixed Operating Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 38V , 0.8V ≤ VOUT ≤ 24V , IQ = 50μA L TC3858/ L TC3858-1 Low IQ, Dual Output 2-Phase Synchronous Step-Down DC/DC Controller with 99% Duty Cycle Phase-Lockable Fixed Operating Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 38V , 0.8V ≤ VOUT ≤ 24V , IQ = 170μA, 9V-16V to 3.3V at 5A DC/DC Converter , Frequency Synchronization Range 150kHz to 300kHz, Capable of Withstanding 60V T ransients, All Ceramic Capacitors, Soft-Start and Burst Mode Enabled VIN SHDN CSS BURST_EN V FB VC SYNC f SET BOOST TG SW VCC BG PGND SENSE+ SENSE– SGND D2 BAS521 1μF 16V 8200pF M1 Si7850DP Si7850DP B160 10μH RSENSE 0.01ΩL T3845 2.2μF 16V

3845 TA04

100μF 6.3V V OUT 3.3V 1.1M V IN 9V TO 16V 60V TRANSIENTS CIN2 0.1μF 100V 130k SYNC 10k 100k 10k 16.8k CIN 2.2μF 100V C IN: TDK C4532X7R2A225K COUT: MURATA GRM32ER60J107ME20 L1: VISHAY IHLP-5050FD-01 M1, M2: VISHAY Si7850DP