LT3755-2

LT8355-1_V01 AD | Alldatasheet

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Technical content

Rev. AFor more information www.analog.com TYPICAL APPLICATION FEATURES DESCRIPTION 60VIN/120VOUT Dual LED Controller with Exponential PWM and Scalable Dimming The LT®8355-1 a dual-channel DC/DC controller designed to drive two strings of high current LEDs. The fixed fre - quency, current mode architecture results in stable oper- ation over a wide range of supply and output voltages. Voltage feedback pins serve as the inputs for several LED protection features and makes it possible for the convert- ers to operate as a constant-voltage sources. The LT8355-1 senses output current at the high or low side of the load. The product of CTRL2 and IADJ2 inputs provides analog programming of the output current for channel 2. Channel 1 output current is programmed through CTRL1 input. The PWM input and PWMTG high side PMOS driver provides precision time-based LED dimming capability. When driven by an external digital signal, the PWM input provides LED dimming ratios of up to 20,000:1 at 100Hz. When driven by a constant voltage, the PWM input selects from one of 128 internally gen - erated, precision, exponentially spaced dimming ratios ranging from 0.78% up to 100%. Dual 32W Boost LED Driver

APPLICATIONS

n T wo independent High Voltage LED Driver Controllers Channels n 128:1 Internal Exponential PWM Dimming n T wo-Pin Multiplying Analog Dimming (CH2) n Spread Spectrum Frequency Modulation n 20,000:1 External PWM Dimming at 100Hz n Rail-to-Rail LED Current Sensing: 0V to 120V n ±2% LED Current Regulation n ±2% Output Voltage Regulation n LED Short/Open Protection and Indication n Wide Input Voltage Range (5V to 60V) n PMOS Switch Driver for PWM and Output Disconnect n Independent Channel Dimming n Constant-Voltage and Constant-Current Regulation n Adjustable Switching Frequency 100kHz to 2MHz n Independent OPEN/SHORT LED FAUL T per channel n Programmable VIN UVLO with Hysteresis n Side Solderable 28-Lead 4mm × 5mm QFN Package n AEC-Q100 Qualified for Automotive Applications n High Voltage LED Applications n Automotive Head Lamps/Running Lamps n Accurate Current Limited Voltage Regulator All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. patents, including 7199560, 7321203, 7746300, 8116045. 500m/uni03A9 51.1k 499k 15µH 4.7µF 147k 0.47nF 40.2k 2.2µF 12.5m/uni03A9 500m/uni03A9 15µH 10µF 10k 12.5m/uni03A9 10µF 576k 100k V IN (6V TO 36V) GATE1 SENSEN1 I LIM = 8A PWM1 CHANNEL 1 DIMMING V REF RT 0.5A INTV CC FAUL T1-2 f = 400kHz L T8355-1 SENSEP1 ISP1 ISN1 PWMTG1 V IN EN/UVLO VC1-2 FB1-2 ISN1-2 ISP1-2 CTRL1-2 IADJ2 PWM2 CHANNEL 2 DIMMING GATE2 SENSEN2 I LIM = 8A 0.5A SENSEP2 ISP2 ISN2 PWMTG2 32W LED ARRAY GND 32W LED ARRAY 8355-1 TA01a BOTH CHANNELS CH1 ONL Y CH2 ONL Y V IN (V) EFFICIENCY (%)

83551 TA01b

Rev. A For more information www.analog.com PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS Operating Junction Temperature Range (Notes 3, 4) (Note 1) 9 10 TOP VIEW UFDM PACKAGE 28-LEAD (4mm × 5mm) SIDE-SOLDERABLE PLASTIC QFN θJA = 43°C/W, θJC = 3.4°C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB GND 11 12 13 28 27 26 25 24 1PWMTG1 ISN1 ISP1 FB1 VC1 CTRL1 FAULT1 CTRL2 INTVCC PWMTG2 ISN2 ISP2 FB2 VC2 VIN EN/UVLO GATE1 SENSEP1 SENSEN1 SENSEN2 SENSEP2 GATE2 IADJ2 PWM1 PWM2 RT FAULT2 VREF 8 15 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE AUTOMOTIVE PRODUCTS* LT8355IUFDM-1#WPBF LT8355IUFDM-1#WTRPBF 83551 28-Lead (4mm × 5mm) Side-Solderable Plastic QFN –40°C to 125°C Contact the factory for parts specified with wider operating temperature ranges. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. *Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.

ELECTRICAL CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITS Operating Supply Range l 5 60 V Input (VIN) Quiescent Current PWM1,2 = 0V 3 mA Input (VIN) Shutdown Current EN/UVLO = 0.3V EN/UVLO = 1.1V, EN/UVLO Rising 0.1 µA µA EN/UVLO Shutdown Threshold EN/UVLO Falling l 1.15 1.25 1.35 V EN/UVLO Rising Hysteresis EN/UVLO Rising 60 mV EN/UVLO Pin Current (Device Off) EN/UVLO = 1.1V, EN/UVLO Rising 2.4 µA EN/UVLO Pin Current (Device On) EN/UVLO = 1.35V 0 µA The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2). Unless otherwise noted, VIN = EN/UVLO = 12V, ISP1,2 = ISN1,2 = 60V, CTRL1,2 = IADJ2 = 2V, PWM1,2 = INTVCC, FB1,2 = 1V, SENSEN1,2 = 0V.

Rev. AFor more information www.analog.com PARAMETER CONDITIONS MIN TYP MAX UNITS Internal Voltage Regulators INTVCC Regulation Voltage PWM1,2 = 0V, IINTVCC = 1mA, 12V < VIN < 60V 7.35 7.5 7.65 V INTVCC Line Regulation PWM1,2 = 0V, 10 < VIN < 60V 0.75 3 mV/V INTVCC Load Regulation PWM1,2 = 0V, 1mA < IINTVCC < 30mA 2.25 4.5 mV/mA INTVCC Current Limit PWM1,2 = 0V, VIN = 12V, INTVCC = 7V PWM1,2 = 0V, VIN = 60V, INTVCC = 7V 110 140 170 mA mA INTVCC Dropout Voltage PWM1,2 = 0V, VIN = 5V, ILOAD = 10mA 250 mV INTVCC Undervoltage Lockout Threshold PWM1,2 = 0V, INTVCC Falling 4.3 V VREF Voltage IVREF = 0.5mA l 1.97 2 2.02 V VREF Load Regulation IVREF = 0.1mA to 1mA 5 8 mV/mA VREF Current Limit VREF = 1.8V 2.5 3.2 4.0 mA Channel 1, Channel 2 Current Regulation (Note 5) ISP , ISN Common Mode Voltage Range l 0 110 V LED Current Sense Threshold (VISP – VISN) CTRL1,2 = 2V, IADJ2 = 2V (100%), ISP1,2 = 100V CTRL1,2 = 1V, IADJ2 = 2V (50%), ISP1,2 = 100V CTRL1,2 = 0.6V, IADJ2 = 2V (10%), ISP1,2 = 100V CTRL1,2 = 2V, IADJ2 = 2V (100%), ISN1,2 = 0V l l l 245 120 240 250 125 250 255 130 260 mV mV mV mV LED2 Current Sense Threshold (VISP2 – VISN2) CTRL2 = 2V, IADJ2 = 1V (50%), ISP = 100V l 118 125 134 mV SENSE Current Limit Threshold (SENSEP − SENSEN) 50% Duty Cycle at GATE (Note 6) l 95 108 120 mV CTRL Off Threshold (Falling) l 285 310 335 mV IADJ2 Off Threshold (Falling) 500 mV CTRL Off Hysteresis 30 mV IADJ2 Off Hysteresis 20 mV CTRL Pin Current Current Out of Pin, CTRL1,2 = 0 20 nA IADJ2 Pin Current IADJ2 = 1.5V 0 nA ISP , ISN Pin Current (Combined) PWM1,2 = INTVCC, ISP1,2 = 100V (Active) PWM1,2 = 0V, ISP1,2 = 100V (Standby) 600 µA µA Error Amp T ransconductance CTRL1,2 = 2V, IADJ2 = 2V (Full-Scale) 65 µS Error Amp Output Resistance 15 MΩ Channel 1, Channel 2 Output Voltage Regulation FB Regulation Voltage (VFB) CTRL1,2 = 2V, IADJ2 = 2V CTRL1,2 = 2V, IADJ2 = 2V l 1.182 1.176 1.2 1.2 1.218 1.224 V V FB Pin Current Current Out of Pin, VFB1,2 = 1.18V 20 nA FB Amplifier T ransconductance 380 µS Oscillator Programmed Switching Frequency (fSW1, Channel 1) RT = 9.09kΩ RT = 51.1kΩ RT = 215kΩ l 1800 380 1950 400 102 2100 420 108 kHz kHz kHz Channel Frequency Difference (fSW2 – fSW1) RT = 51.1kΩ 4.5 %fSW1 Spread Spectrum Frequency Range 100 126 %fSW Minimum Off-Time RT = 9.09kΩ RT = 51.1kΩ RT = 215kΩ l l l 100 120 170 165 240 ns ns ns The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2). Unless otherwise noted, VIN = EN/UVLO = 12V, ISP1,2 = ISN1,2 = 60V, CTRL1,2 = IADJ2 = 2V, PWM1,2 = INTVCC, FB1,2 = 1V, SENSEN1,2 = 0V.

Rev. A For more information www.analog.com Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Do not apply a positive or negative voltage to the PWMTG1, PWMTG2, RT , VREF, VC1, VC2, GATE1 or GATE2 pin, otherwise permanent damage may occur . Use these pins only as directed in the Pin Functions and Applications Information sections. Note 3: LT8355I-1 is guaranteed to meet performance specifications from –40°C to 125°C junction temperature. Operation lifetime is derated at junction temperatures greater than 125°C. Note 4: This IC include overtemperature protection that is intended to protect the device during momentary overload conditions. The maximum rated junction temperature will be exceeded when this protection is active. Continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. Note 5: LED voltage and current sense amplifier parameters are measured in a servo loop with VC. Note 6: Tested in a non-switching setup and correlated by design. Note 7: Tested at RT = 51.1kΩ, guaranteed for all RT by design. Note 8: GATE1,2 rise and fall times as well as the step size for the PWM ADC are guaranteed by design and not tested. Note 9: ISP1 – ISN1 and ISP2 – ISN2 may exceed 10V transiently. Do not exceed ISP1 – ISN1 = 10V or ISP2 – ISN2 = 10V for more than 1 ms. PARAMETER CONDITIONS MIN TYP MAX UNITS Minimum On-Time CGATE1,2 = 3.3nF CGATE1,2 = 10nF, RT = 51.1kΩ (Note 7) 100 180 ns ns Channel 1, Channel 2 External NMOS Power Switch Driver Pull-Up Device On-Resistance 5 Ω Pull-Down Device On-Resistance 3 Ω GATE Rise Time (Note 8) CGATE1,2 = 3.3nF, 10% to 90% 45 ns GATE Fall Time (Note 8) CGATE1,2 = 3.3nF, 90% to 10% 40 ns Channel 1, Channel 2 External PMOS Driver PWMTG ON Voltage (VISP – VPWMTG) VISP1,2 = 100V 7.5 8.5 9.5 V PWMTG OFF Voltage (VISP – VPWMTG) VISP1,2 = 100V 0 0.3 V PWMTG Turn-On Time CL = 470pF, VISP1,2 = 100V 150 ns PWMTG Turn-Off Time CL = 470pF, VISP1,2 = 100V 180 ns Channel 1, Channel 2 Fault Detection FB LED Open Threshold VISP1,2 = VISN 1,2, FB Rising 1.116 1.14 1.164 V FB Overvoltage Threshold FB1,2 Rising 1.235 1.26 1.285 V FB Shorted LED Threshold FB1,2 Falling 300 330 mV LED Overcurrent Protection Threshold (VISP – VISN) 580 670 760 mV FAUL T Pin Pull Down Current VFAUL T1-2 = 0.3V, VFB1,2 = 1.3V 0.5 mA FAUL T Pin Leakage Current VFAUL T1-2 = 15V, VFB1,2 = 0.7V 100 nA Channel 1, Channel 2 Internal PWM Generator PWM Pin Voltage for Max Duty Ratio 1.5 V PWM Pin Voltage for Min Duty Ratio 0.5 V PWM Off Threshold (Falling) 0.4 V PWM On Threshold (Rising) 1.6 V Minimum Duty Ratio VPWM1,2 = 0.5V, RT = 51.1kΩ 0.78 % Maximum Duty Ratio VPWM1,2 = 1.5V, RT = 51.1kΩ 100 % PWM Voltage Step per Duty Ratio Setting (Note 8) 7.8 mV PWM Pin Current VPWM1,2 = 1V 0 nA PWM Clock Frequency fSW/1000 Hz Fraction of VREF for 10% Duty RT = 51.1kΩ 0.511VREF V The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2). Unless otherwise noted, VIN = EN/UVLO = 12V, ISP1,2 = ISN1,2 = 60V, CTRL1,2 = IADJ2 = 2V, PWM1,2 = INTVCC, FB1,2 = 1V, SENSEN1,2 = 0V.

Rev. AFor more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS EN/UVLO Thresholds vs Temperature EN/UVLO Hysteresis Current vs Temperature EN/UVLO Current vs Voltage Above Turn-On Threshold TA = 25°C, unless otherwise noted. VIN Shutdown Current vs Temperature VIN Quiescent Current vs Temperature INTVCC Voltage vs Temperature INTVCC Dropout vs Temperature INTVCC Current Limit vs Temperature INTVCC Current Limit vs VIN INPUT VOL TAGE (V) 110 130 150 CURRENT (mA) 8355-1 G09 TEMPERATURE (°C) –50 –25 100 125 150 7.2 7.3 7.4 7.5 7.6 7.7 INTV CC VOL TAGE (V) 8355-1 G06 V EN/UVLO > 1.35V EN PIN VOL TAGE (V) 0.2 0.4 0.6 0.8 1.0 EN PIN CURRENT (µA) 8355-1 G03 V IN = 12V V IN = 60V TEMPERATURE (°C) –50 –25 100 125 150 100 120 140 160 180 INTV CC PIN CURRENT (mA) 8355-1 G08 V IN = 5V V IN = 12V V IN = 60V TEMPERATURE (°C) –50 –25 100 125 150 2.2 2.6 3.0 3.4 3.8 4.2 V IN QUIESCENT CURRENT (µA) 8355-1 G05 TEMPERATURE (°C) –50 –25 100 125 150 1.6 1.8 2.0 2.2 2.4 2.6 EN/UVLO PIN CURRENT (µA) 8355-1 G02 V IN = 7 V T A = –45°C T A = 130°C T A = 25°C INTV CC PIN CURRENT (mA) –1.6 –1.4 –1.2 –1.0 –0.8 –0.6 –0.4 –0.2 0.0 LDO DROPOUT VOL TAGE (V) 8355-1 G07 V EN/UVLO = 1.1V TEMPERATURE (°C) –50 –25 100 125 150 V IN SHUTDOWN CURRENT (µA) 8355-1 G04 V IN = 5V V IN = 12V V IN = 60V RISING THRESHOLD FALLING THRESHOLD TEMPERATURE (°C) –50 –25 100 125 150 1.22 1.24 1.26 1.28 1.30 EN PIN VOL TAGE (V) 8355-1 G01

Rev. A For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICSTA = 25°C, unless otherwise noted. VREF Voltage vs Temperature VREF Line Regulation VREF Load Regulation Switching Frequency vs RT Resistor Switching Frequency (400kHz) vs Temperature Switching Frequency (100kHz) vs Temperature Switching Frequency (2MHz) vs Temperature ISP − ISN Voltage vs ISP Voltage ISP − ISN Accuracy Full-Scale Threshold vs Temperature V CTRL1,2 = 2V , V IADJ2 = 2V ISN = 0V ISP = 48V ISP = 100V TEMPERATURE (°C) –50 –25 100 125 150 240.0 242.5 245.0 247.5 250.0 252.5 255.0 257.5 260.0 ISP – ISN VOL TAGE (mV) 8355-1 G18 GATE2 GATE1 R T = 215k TEMPERATURE (°C) –50 –25 100 125 150 100 104 108 112 116 SWITCHING FREQUENCY (kHz) 8355-1 G15 I REF PIN CURRENT (mA) 0.1 0.2 0.4 0.5 0.6 0.7 0.8 1.0 1.1 1.2 1.94 1.96 1.98 2.00 2.02 2.04 2.06 V REF PIN VOL TAGE (V) 8355-1 G12 ISP PIN VOL TAGE (V) 100 110 240.0 242.5 245.0 247.5 250.0 252.5 255.0 257.5 260.0 ISP – ISN VOL TAGE (mV) 8355-1 G17 GATE2 GATE1 R T = 51.1k TEMPERATURE (°C) –50 –25 100 125 150 380 390 400 410 420 430 440 450 SWITCHING FREQUENCY (kHz) 8355-1 G14 I VREF = 0.5 mA V IN PIN VOL TAGE (V) 1.94 1.96 1.98 2.00 2.02 2.04 2.06 V REF PIN VOL TAGE (V) 8355-1 G11 GATE2 GATE1 R T = 9.09k TEMPERATURE (°C) –50 –25 100 125 150 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20 SWITCHING FREQUENCY (MHz) 8355-1 G16 GATE1 GATE2 RT RESISTOR (kΩ) 100 300 100k FREQUENCY (Hz) 8355-1 G13 I VREF = 0.5 mA TEMPERATURE (°C) –50 –25 100 125 150 1.94 1.96 1.98 2.00 2.02 2.04 2.06 V REF PIN VOL TAGE (V) 8355-1 G10

Rev. AFor more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS ISP − ISN Accuracy at CTRL = 1V vs Temperature ISP − ISN Accuracy at CTRL = 0.6V vs Temperature ISP1-ISN1 Regulation Voltage vs CTRL1 Pin Voltage TA = 25°C, unless otherwise noted. ISP2-ISN2 Regulation Voltage vs CTRL2, IADJ2 Pin Voltage ISP-ISN Voltage vs FB Pin Voltage Output Voltage Regulation vs Temperature C/10 Threshold vs Temperature FB Short LED Threshold vs Temperature FB Overvoltage Threshold vs Temperature FALLING THRESHOLD RISING THRESHOLD TEMPERATURE (°C) –50 –25 100 125 150 1.20 1.22 1.24 1.26 1.28 1.30 1.32 FB PIN VOL TAGE (V) 8355-1 G27 TEMPERATURE (°C) –50 –25 100 125 150 1.14 1.16 1.18 1.20 1.22 1.24 1.26 FB PIN VOL TAGE (V) 8355-1 G24 CTRL1 PIN VOL TAGE (V) 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 100 125 150 175 200 225 250 275 ISP1-ISN1 VOL TAGE (mV) 8355-1 G21 TEMPERATURE (°C) –50 –25 100 125 150 240 260 280 300 320 340 360 FB PIN VOL TAGE (mV) 8355-1 G26 FALLING THRESHOLD RISING THRESHOLD FB PIN VOL TAGE (V) 1.180 1.185 1.190 1.195 1.200 1.205 1.210 100 125 150 175 200 225 250 275 ISP-ISN VOL TAGE (mV) 8355-1 G23 V CTRL1,2 = 0.6V , V IADJ2 = 2V ISN = 0V ISP = 48V ISP = 100V TEMPERATURE (°C) –50 –25 100 125 150 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 35.0 ISP – ISN VOL TAGE (mV) 8355-1 G20 TEMPERATURE (°C) –50 –25 100 125 150 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 35.0 ISP – ISN VOL TAGE (mV) 8355-1 G25 FALLING THRESHOLD RISING THRESHOLD IADJ2 = 1.5V IADJ2 = 1.25V IADJ2 = 1.0V IADJ2 = 0.75V IADJ2 = 0.6V CTRL2 PIN VOL TAGE (V) 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 100 125 150 175 200 225 250 275 ISP2-ISN2 VOL TAGE (mV) 8355-1 G22 TEMPERATURE (°C) –50 –25 100 125 150 115.0 117.5 120.0 122.5 125.0 127.5 130.0 132.5 135.0 ISP – ISN VOL TAGE (mV) 8355-1 G19 V CTRL1,2 = 1V , V IADJ2 = 2V ISN = 0V ISP = 48V ISP = 100V

Rev. A For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICSTA = 25°C, unless otherwise noted. FB Open LED Threshold vs Temperature SENSEP − SENSEN Current Limit vs Temperature SENSEP − SENSEN Current Limit vs Duty Ratio PWMTG Duty vs PWM Pin Voltage PWMTG Duty vs Temperature PWMTG Frequency vs Temperature PWMTG Frequency vs Temperature Minimum Off-Time vs CH1 Switching Frequency Minimum Off-Time vs Temperature f SW1 = 400kHz f SW1 = 100kHz f SW1 = 2MHz TEMPERATURE (°C) –50 –25 100 125 150 100 120 140 160 180 200 MINIMUM OFF-TIME (ns) 8355-1 G36 f SW1 = 400kHz TEMPERATURE (°C) –50 –25 100 125 150 360 370 380 390 400 410 420 430 440 PWMTG FREQUENCY (Hz) 8355-1 G33 GATE PIN DUTY CYCLE (%) 100 100 105 110 115 120 SENSEP – SENSEN THRESHOLD (mV) 8355-1 G30 f SW1 = 400kHz CH1 SWITCHING FREQUENCY (Hz) 100k 100 125 150 175 200 MINIMUM OFF-TIME (ns) 8355-1 G35 V PWM = 0.511V REF f SW1 = 400kHz f SW1 = 2MHz TEMPERATURE (°C) –50 –25 100 125 150 9.4 9.6 9.8 10.0 10.2 10.4 10.6 PWMTG PIN DUTY (%) 8355-1 G32 f SW1 = 400kHz 20% DUTY 50% DUTY 80% DUTY TEMPERATURE (°C) –50 –25 100 125 150 100 105 110 115 120 SENSEP – SENSEN THRESHOLD (mV) 8355-1 G29 f SW1 = 2MHz TEMPERATURE (°C) –50 –25 100 125 150 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20 PWMTG FREQUENCY (kHz) 8355-1 G34 PWM PIN VOL TAGE (V) 0.5 0.7 0.9 1.1 1.3 1.5 0.5 100 PWM DUTY (%) 8355-1 G31 V ISP – V ISN = 0V TEMPERATURE (°C) –50 –25 100 125 150 1.08 1.10 1.12 1.14 1.16 1.18 1.20 FB PIN VOL TAGE (V) 8355-1 G28 FALLING THRESHOLD RISING THRESHOLD

Rev. AFor more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICSTA = 25°C, unless otherwise noted. Minimum On-Time vs Gate Capacitance GATE Rise/Fall Time vs GATE Capacitance PWMTG Driver Rise/Fall Time vs PWMTG Capacitance PWMTG ON Voltage vs Temperature ISP/ISN Pin Current vs CTRL Voltage at ISP = 100V ISP/ISN Pin Current vs CTRL Voltage at ISN = 0V ISN = 0V CTRL PIN VOL TAGE (V) 0.25 0.50 0.75 1.25 1.50 1.75 –120 –100 –80 –60 –40 –20 PIN CURRENT (µA) 8355-1 G42 ISP ISN PWMTG CAPACITANCE (nF) 1.1 2.2 3.3 400 800 1200 1600 2000 TIME (ns) 8355-1 G39 RISE FALL ISP = 100V ISP ISN CTRL PIN VOL TAGE (V) 0.25 0.50 0.75 1.25 1.50 1.75 100 150 200 250 300 350 400 450 500 550 600 PIN CURRENT (µA) 8355-1 G41 RISE FALL GATE CAPACITANCE (nF) 100 125 150 175 TIME (ns) 8355-1 G38 V ISP = 12V V ISP = 48V V ISP = 100V TEMPERATURE (°C) –50 –25 100 125 150 7.0 7.5 8.0 8.5 9.0 9.5 10.0 PWMTG ON VOL TAGE (V) 8355-1 G40 GATE CAPACITANCE (nF) 100 125 150 175 200 225 MINIMUM ON-TIME (ns) 8355-1 G37

Rev. A For more information www.analog.com PIN FUNCTIONS PWMTG1, PWMTG2 (Pins 1, 21): High Side Gate Driver for the External Series PMOS Switch of Each Channel. Use these pins to disconnect the load for PWM dimming as well as fault events. PWMTG drives the PMOS gate between ISP – 8.5V and ISP (typical) to cut off the flow of residual charge from the output capacitor when the LED load should be disconnected, as well as to prevent the long transient that would result from needing to recharge the output capacitor at the end of a long PWM off period. Leave open if unused. The voltage at PWMTG is limited to 8.5V (typical) below the voltage at ISP to protect the gate of the PMOS switch. ISN1, ISN2 (Pins 2, 20): Kelvin connect this pin to the low side of the LED current feedback sense resistors RILED1,2 of each channel. Current through sense resistor , RILED2 is 250mV/RILED2 while CTRL2 > 1.5V and IADJ2 > 1.5V. It varies as [(CTRL2 – 0.48V) • (IADJ2 – 0.5V) –0.02V]/ (4RILED2) if the voltage at the CTRL2 and IAJD2 pins vary between 0.5V to 1.5V. The current through sense resistor RILED1 is 250mV/RILED1 while CTRL1 > 1.5V. It varies as (CTRL1 − 500mV)/(4RILED1) if the voltage at the CTR L1 pin is between 500mV and 1.5V. ISP1, ISP2 (Pins 3, 19) : Kelvin connect this pin to the high side of the LED current feedback sense resistor RILED of each channel, see IS N1, ISN2 for more details. If the voltage difference VISP – VISN ever exceeds around 670mV (typical), switching stops, PWMTG goes high to disconnect the load, and soft-start resets. After a cooldown period, the part will re-enter soft-start. See the Applications Information section for more details. FB1, FB2 (Pins 4, 18): Output Voltage Feedback Pin for Each Channel. This pin is used for output voltage regula- tion and limiting. Tie this pin to a resistive voltage divider from the output voltage. When the voltage at FB reaches 1.2V (typical), the control loop will reduce the switch cur- rent to regulate the output voltage such that FB remains around 1.2V. If the voltage at FB exceeds 1.26V (typical), PWMTG is driven high and switching briefly stops. If the voltage at FB falls below 300mV (typical) after soft-start has finished, PWMTG is driven high, soft-start resets, and switching stops. After a cooldown period, the part will re-enter soft-start. See the Applications Information section for more info on the use of the FB pin for general applications. VC1, VC2 (Pins 5, 17) : An Internal Error Amplifier Node Used for Compensation. Stabilize the loop by connecting a capacitor or RC network between this pin and ground for each channel. Read more in the Applications Information section for details about compensation. CTRL1, CTRL2, IADJ2 (Pins 6, 8, 9) : T wo-Pin Analog Alternative to PWM Dimming. Tie CTRL1,2 and IADJ2 to VREF or INTVCC to set RILED current to full-scale for each channel. The product of the offset CTRL2 and IADJ2 pin voltages sets the current in RILED2 as [(CTRL2 – 0.48V) • (IADJ2 – 0.5V) – 0.02V]/(4RILED2) when the voltages at CTRL2 and IAD J2 pins vary between 0.5V to 1.5V. The pin voltage of CTR L1 linearly sets the current in R ILED1 as (CTRL1 – 0.5V)/(4RILED1) when the voltage at CTRL1 pin varies between 0.5V and 1.5V. FAUL T1, FAUL T2 (Pins 7, 13): Open-Drain Fault Indication Pin Indicating Short LED, Open LED, Overvoltage and Overcurrent Faults for Each Channel. Tie these pins through 100k resistors to INTVCC, or any supply less than 15V or use them as open-drain signals. LT8355-1 pulls these pins low to signal all reported fault events from each channel independently. PWM1, PWM2 (Pins 10, 11) : Pulse Width Modulation (PWM) Dimming Generation Control Pin for Each Channel. Connect an analog signal to this pin to use the internal exponential PWM dimming generator . When the voltages at these pins remain between 0.5V and 1.5V, the duty ratio of the internal dimming PWM generator will vary with the pin voltage. A linear ramp of voltage on the PWM pins between 0.5V and 1.5V lasting many PWMTG cycles at fSW/1000 will result in an exponentially increasing PWM duty ratio. An external PWM signal can also drive this pin directly if the ON and OFF voltages are above 1.6V and below 0.4V, respectively. If PWM dimming is not used, tie these pins to INTVCC or VREF. RT (Pin 12) : Connect a resistor between this pin and ground to set the switching frequency and PWM dimming frequency. Do not connect anything but a resistor to this pin or the device may not function correctly.

Rev. AFor more information www.analog.com PIN FUNCTIONS VREF (Pin 14) : A 2V (Typical) Reference Voltage. It can supply a maximum of 2.5mA at room temperature, useful for resistor networks that set voltages across CTR L1,2; IADJ2; and PW M1,2 pins. The output is stable without a local bypass but, if needed, bypass this pin to ground with a 1µF capacitor . If no load is connected or unused, leave pin floating. EN/UVLO (Pin 15): When the voltage at this pin falls below 1.25V (typical), switching stops and the part shuts down. A hysteresis of approximately 60mV is included when returning over 1.25V. Drive this pin high with a logic level greater than 1.4V or low with a logic level below 0.3V for simple ON/OFF functionality or tie it through a resistive voltage divider to V IN for a precise input undervoltage shutdown threshold. For all uses of this pin, ensure that the minimum Thevenin equivalent resistance is 20k. VIN (Pin 16): Input Supply Pin. Must be locally bypassed. INTVCC (Pin 22): Voltage Supply Used by Internal Circuits. Tie a capacitor from this pin to ground. It requires a min- imum capacitance of 2.2µF; but considering temperature and voltage coefficients, 4.7µF is recommended. The typ- ical INTVCC voltage is 7.5V, and a 16V rated capacitor will usually be appropriate. This pin is not intended for use as a power source for external loads and connecting it to certain external loads may interfere with operation of the device. Using the INTVCC pin for any purpose other than those described in the Applications Information section is not recommended. SENSEN1, SENSEN2 (Pins 26, 25) : Kelvin connect this pin to the negative side of the switch current sense resis- tor for each channel. For more information about this, see the PCB layout guidelines in the Applications Information section. SENSEP1, SENSEP2 (Pins 27, 24): Kelvin connect this pin to the positive side of the grounded switch current sense resistor for each channel. For more information about this, see the PCB layout guidelines in the Applications Information section. GATE1, GATE2 (Pins 28, 23) : External NMOS Power Switch Gate Driver for Each Channel. Connect this pin to the gate of an NMOS whose source is connected to the switch current sense resistor . GND (Pin 29 Exposed Pad): Ground. Solder the exposed pad directly to the ground plane.

Rev. A For more information www.analog.com BLOCK DIAGRAM R R 100kHz TO 2MHz OSCILLATOR PWMTG1 LOG SCALE ADC 0.4V R S Q COUNT OVRFW 1.6V PWM1 PWM1 ISP1 ISP1 – 8.5V VC1 CTRL1 ISN1 ISP1 670mV 25mV OC1 C/10-1 1.2V FBOK1 FB1 0.3V 1.26V FBOC1 FBOV1 GATE1 SENSEP1 R S Q SLOPE COMP PWMTG2 [4R, 512R] SET BY DAC LOG SCALE ADC 0.4V R S Q COUNT OVRFW 1.6V PWM2 PWM2 VC2 CTRL2 ISN2 ISP2 IADJ2 ADC OC2 C/10-2 1.2V FBOK2 FB2 0.3V 1.26V FBOC2 FBOV2 GATE2 SENSEP2 R S Q SLOPE COMP GND VREF RT SOFT START FAUL T LOGIC VIN EN/UVLO INTVCC VIN 1.25V SHDN SENSEN1 SENSEN2 FSW1/1000 2V REF 2.4µA FAUL T2 FVOV2 OC2 FVOC2 C/10-2 FB2>1.14V FAUL T1 FVOV1 OC1 FVOC1 C/10-1 FB1>1.14V ISP2 ISP2 – 8.5V 670mV 25mV RSENSE1 RILED1 RSENSE2 RILED2 ISP1 ISP2 0.5V 0.48V 1.5V 1.5V 8355-1 BD 5mV

Rev. AFor more information www.analog.com OPERATION The LT8355-1 is a dual-channel constant-frequency, constant-current/constant-voltage (CC/CV) boost power stage controller . The operation of the part can be best understood by looking at the Block Diagram. The con - troller can implement boost, SEPIC, buck mode or buck- boost mode LED drivers. At the beginning of every clock cycle, the clock signal sets an SR-latch controlling the gate driver . The external NMOS switch turns on and con- nects the inductor to ground. The positive voltage drops across the inductor results in linearly increasing current in the inductor . The switch will remain on until the current comparator resets it. This reset will occur when the switch current, as measured by the switch current sense resistor , exceeds the internal demand current. This demand cur - rent comes from the error amplifier of each respective channel. The external LED current sense resistor used to program load current drives the error amplifier . The voltage drop across the sense resistor multiplied by the amplifier’s transconductance establishes the demand cur- rent. Without a forced offset, the error amplifier regulates the load to zero current based on the voltage across the LED current sense resistor . To establish the positive offset in the error amplifier needed to program the LED current, a small current is intentionally pulled from only one input of the amplifier through an internal series resistor . The CTR L1,2 and IADJ2 pins establish this offset current by varying the voltage dropped across a second internal resistor to GND. Changing the CTR L1,2 pin voltage will vary the voltage dropped across the second internal resistor , while chang- ing the IAD J2 pin voltage will change the value of that resistor for channel 2. This varies the LED current sense resistor regulation voltage between true zero and 250mV. During constant-current operation, the FB pin provides overvoltage protection. When the FB pin voltage is below its regulation threshold, the FB amplifier has little effect on demand current. However , as the FB pin voltage approaches 1.2V, the FB amplifier has an increasingly pronounced effect, until it eventually dominates the demand current. If the FB pin voltage exceeds the reg - ulation threshold by 60mV (typical), the part detects an overvoltage event. Similarly, if the voltage at the FB pin ever falls below 300mV (typical, excluding startup) then the part detects a short LED event. Fast overcurrent protection relies on a separate signal path than the main LED current sense amplifier . If the LED current sense resistor voltage (VISP − VISN) exceeds 670mV (typical), switching stops. This event causes a brief interruption of switching while soft-start is reset, followed by a soft-start of the switching. Four different methods for dimming the LED load are pro- vided with LT8355-1. First, the voltages at the CTR L1,2 and IADJ2 pins, which set the LED current sense resistor regulation threshold for each channel, provide continu - ous, analog dimming of the LED load. In addition, two methods of PWM dimming exist. The first, external PWM, relies on a user-provided PWM signal. This signal drives the PWM pin, directly turning on and off the LED load. This method can achieve dimming ratios of 20,000 :1 at 100Hz PWM frequency. Alternatively, the part can gen - erate the PWM signal internally from an analog control signal at the PWM pin. The internal dimming PWM generator selects one of 128 predetermined duty ratio values based on the analog volt- age at the PWM pin. An exponential relationship exists between the PWM pin voltage and these duty ratio values. For example, consider a voltage at the PWM pin starting at 0V. When the voltage increases until the duty ratio is 9.6%, further increasing by 7.8mV(typical) will change the duty ratio to 10%. By the time the voltage is high enough to set 96% duty, the same 7.8mV (typical) increase will move the duty ratio up to 100%. A straight ramp at the PWM pin lasting many PWMTG dimming periods as set by RT will create an exponentially increasing PWM duty ratio for the LED load.

oping a good understanding of the part. the Low Voltage (SEPIC) Start-Up section. Figure 1. VISP – VISN vs CTRL1,2 and VIADJ2 Pin Voltage LED current for varying values of IADJ2 for channel 2.

Rev. A For more information www.analog.com APPLICATIONS INFORMATION at start-up or after faults, when the output is still low. During start-up, or when restarting after faults, switching frequency will drop to around 20% of its nominal value, and step-up over the duration of around 256 times the nominal switching period. For more information about this, see the Soft-Start section. The internal dimming PWM generator clock runs at approximately f SW1/1000. Spread spectrum frequency modulation for the switch clock does not affect the PWM generator clock, which continues to run at fSW1(MIN)/1000. Pulse Width Modulation (PWM) Dimming Pulse width modulation (PWM) allows high dynamic range dimming of the LED load. When using PWM dim - ming, a pulse train with duty ratio proportional to desired LED current controls the load. During ON periods, the part operates normally. During OFF periods the part stops switching. While the part is not switching, the compen - sation node is high impedance to minimize changes to the compensation capacitor voltage. This reduces tran - sient settling time when the next ON period arrives. In addition to this, the LT8355-1 provides an optional load disconnect. Disconnecting the load makes turn-off much faster , as the output capacitor does not continue to con- duct current into the load. T ransient settling time is also shorter when turning back ON, as the output capacitor’s state is less affected by the load. To use the external load disconnect, tie a PMOS in series with the load such that the source of the PMOS connects to the ISN node, and the drain to the LED load. Connect the gate of the PMOS to the PWMTG pin. The voltage at the PWMTG pin will vary between V ISP and V ISP – 8.5V (typical) to turn the PMOS off and on. Note that this configuration works for any of the supported power stage topologies. For more information on power stage topologies, see the Typical Applications section. The PWM1,2 pins allow two modes of PWM dimming. The first mode is external PWM. In this mode, a digital signal created by some other device, such as a micro - processor , drives the PWM1,2 pins. This PWM signal directly controls the part : when this signal is high, the corresponding channel runs, when this signal is low, the corresponding channel does not run, and disconnects Figure 4. PWM Duty vs PWM1,2 Pin Voltages the load if an external PMOS is used. Tying the PWM1,2 pins to INTV CC or V REF results in continuous, uninter - rupted operation. Conversely, tying the PW M1,2 pins to ground results in the system remaining idle indefinitely. External PWM dimming can support ON periods shorter than 500ns, allowing a PWM dimming dynamic range of 20,000:1 at 100Hz. Careful design of the wiring, includ - ing short cabling to reduce parasitic inductance, to the LED load improves turn on speed and regulation accu - racy for brief (<1µs), high current (>0.5A) pulses. While sub-microsecond PWM dimming ON times are supported by LT8355-1, very brief OFF times (<0.3µs) are not sup- ported. This means that negative going glitches on the CTRL1,2; IADJ2; and PW M1,2 pins should be avoided. High dynamic range PWM dimming can produce a single pulse of LED current lasting longer than a single nominal PWM on time which may be perceived as a flash. The second mode of PWM dimming is internal. When using internal PWM dimming, the analog voltages at the PWM1,2 pins control the duty ratio of the PWMTG signal. The voltage range for internal PWM dimming is from 0.5V to 1.5V at the PWM1,2 pins. The internal PWM generator converts the voltages at the PW M1,2 pins to a 7-bit digital representation. The analog-to-digital con - verter responsible for this uses a linear scale, each code is around 7.8mV wide. Each 7-bit code corresponds to a unique duty ratio value. The values of duty ratio are separated exponentially. Refer to Figure 4 for a graphical representation of this relationship and Table 2 for recom- mended PWM voltage for selected PWM Duties. PWM1,2 PIN VOL TAGE (V) 0.50 0.75 1.25 1.50 1.75 0.5 100 PWM DUTY (%) 8355-1 F04

Figure 5. Maximum Duty as a Function of Switching Frequency Table 2. Recommended PWM Voltage for Selected PWM Duties reference design and layout. LT8355-1 switching frequencies variations. transients does not result in subharmonic oscillations. switch current based on the value of the sense resistor . mation, see the Inductor Selection section.

• VIN VISP (6)

Equation 7 for buck mode current limit. instantaneous current flows in the switch and inductor . rent, cannot exceed the programmed switch current limit. less than maximum peak switch current. many cases, a 1nF capacitor and 47k resistor will suffice. These are good values to start with for all applications. Figure 6. LT8355-1 Compensation Network the loop remains unstable the following steps can help. lower value input capacitor than buck mode converters. Use Equation 8 to estimate the value of the input capacitor .

current for the buck converter case. forward current of this rectifier . to select an inductor with around 20% ripple. Table 3 provides some recommended inductor vendors. Table 3. Recommended Inductor Vendors

Rev. A For more information www.analog.com APPLICATIONS INFORMATION NMOS switch and Schottky rectifier . The gate-source volt- age rating should be higher than 12V. The drain current rating should be sufficient to conduct the full programmed LED current with some margin. Ensure that the PWMTG drive voltage of 8.5V will fully enhance the PMOS device. Be careful when selecting a PMOS to consider the effect that higher current ratings have on gate charge (Q g). A very high Qg PMOS will slow turn-on and turn-off times and can lead to offsets for very brief on-time PWM dim- ming (shorter than 500ns). A clamping diode might be necessary near PMOS’s drain to prevent the drain ringing well below ground when being shorted to ground through a long cable. Power NMOS Selection Choose an external NMOS switch with breakdown volt - age higher than the programmed output voltage by at least 20%. Select the forward current rating based on the load requirements and maximum current through the switch. Be sure to set the programmable switch current limit lower than the maximum rated forward current of the switch. Like the power PMOS, the gate charge of the external NMOS can impact performance. Very low Q g MOSFETs (<1nC) can turn on quickly, potentially nega - tively impacting EMI performance. Conversely, very high Qg MOSFETs (>100nC) can draw excessive current from the part ’s internal LDO regulator at higher switching frequencies. Sense Resistors Selection Select the LED and switch current sense resistors for power dissipation limits and PCB footprint convenience. The control loop will limit the steady state voltage dropped across the LED current sense resistor to 250mV (typical) and the switch current sense resistor to 100mV (typical). Large footprint resistors such as 2010 may be needed for high power applications. Be sure to Kelvin all sense resistors connections to the LT8355-1. LED Fault Events LT8355-1 provides a variety of fault detection to mitigate damage to external components. While LT8355-1 has many self-protection features, three LED types of faults (LED Short, Overvoltage and LED Overcurrent) will cause the part to immediately stop switching and, if an exter - nal PMOS is used according to instructions in the PWM Dimming section, disconnect the load from the output capacitor . The LED overcurrent fault detection uses the LED current sense resistor RILED. If the voltage drop across the sense resistor is greater than 670mV (typical), an internal fault signal gets asserted. The LED Short fault senses load volt- age. This can allow the detection of limited failures, such as one or two of the LEDs in a string becoming shorted. LT8355-1 senses the voltage at the FB pin and detects a LED Short fault if that voltage falls below 300mV (typical, excluding during start-up). It is important to note that the FB resistor divider must be in place to use the LED Short fault detection. After a successful start up, LT8355-1 can regulate VISP-ISN to any setting provided that FB pin volt- age stays above LED Short threshold. The Overvoltage fault occurs when the voltage at the FB pin exceeds 1.26V (typical). The FB resistor divider must be in place to take advantage of the over voltage fault protection. LT8355-1 clears faults and resumes switching depending on the type of fault. Switching resumes as soon as an overvolt- age fault has cleared. Recovery from Short LED and LED Overcurrent faults will enter soft-start as if it had just been turned on via the EN/ UVLO pin. Upon successful completion of the soft-start process with no faults, the internal fault clears and normal operation resumes. The PWM dimming logic falling edge is ignored for both internal and external PWM until soft- start is complete or the control loop approaches steady state. Table 4 summarizes operating conditions that can trigger a fault, and/or turn off switching at the PWMTG1,2 and GATE1,2 pins.

Table 4. Conditions and Effects on FAUL T, PWMTG and GATE state is ignored and the part runs continuously. (see Equation 12 and Figure 7). Figure 7. LT8355-1 Resistor Network for Accurate UVLO. around 2.4µA(RUV1) provides the desired hysteresis. add a 20k resistor in series.

Rev. A For more information www.analog.com APPLICATIONS INFORMATION and ISN are both near (or at) 0V. The LED current sense amplifier will continue to command the LED current pro- grammed by CTRL1,2 and IADJ2 all the way down to 0V on ISP . However , recall that ISP provides the positive rail for the driver of the external disconnect PMOS. Therefore, the use of low side sensing of LED current is not rec - ommended for applications that use PWM dimming or for any boost configuration applications requiring output short circuit protection. Planning for Thermal Shutdown The LT8355-1 will automatically shuts down when the internal temperature is above 170°C (typical). This shut- down is guaranteed to always be outside of the operating region of the device. The effects of thermal shutdown are like that of the load faults: switching stops, soft-start is reset, and if an external PMOS is used according to instructions in the PWM Dimming section, the load is disconnected from the output capacitor . The exposed pad is ground, and must be soldered to a good, large ground plane with many vias to aid thermal management. Since LT8355-1 controls power components and does not itself conduct any meaningful portion of the load current, power dissipation in the LT8355-1 may be lower than a monolithic converter . Power dissipation will increase with VIN and switching frequency. Die temperature will increase with power dissipation. Higher ambient tempera- ture applications will not be able to dissipate as much power , and high power dissipation in any condition may overstress die temperature. PCB Layout Guidelines and Information Printed Circuit Board (PCB) layout profoundly affects performance of all power applications. Proper electrical and thermal connection of the IC and power components with the outside world will mean the difference between success or failure of any system. Do not neglect spending adequate design time on the layout of any application PCB. The exposed ground pad on the bottom of the pack- age must be soldered to a ground plane. The switch current sense resistor RSENSE should connect to a large, unbroken ground plane. The ground termi - nal of the switch current sense resistor should be Kelvin connected to the SENSE1,2 pins of the respective channel of LT8355-1. Connect the INTVCC bypass capacitor from the INTVCC pin directly to the exposed pad by the short - est route possible. Analog and control functions such as VC1,2; PWM1,2; CTRL1,2; IADJ2; and VREF should have a separate ground plane, which includes the exposed pad of the IC. The power and analog ground planes should meet only in a Kelvin connection to the exposed pad and at the power input to the PCB. Be sure to design proper ground planes for power and ana- log functions within the application PCB. Ground planes should not be interrupted by other traces, and should be continuous, very wide sheets of copper . Connect the exposed pad of the IC to such a ground plane. Use as many vias as will fit in the exposed pad area to make the connection. Filled or capped vias may ease soldering for the exposed pad area. Do not copy any particular layout for the exposed pad connection, but instead use as many vias as will fit given the capabilities of the PCB fab house. In addition to soldering down the exposed pad, it is critical to provide a good, robust layout for the power path. Use wide traces for VIN and to connect to the load. Keep the LED and switch current sense resistors close to the IC and ensure that the ISP and ISN traces run as close to one another as possible. It is strongly recommended to not allow ISP and ISN to take different paths to the LED current sense resistor , but instead to keep them beside one another as much as possible. Minimize the total area of any switching node (SW) traces, keep the output capacitor and external catch diode as close as possible to the external NMOS switch and switch current sense resistor to help this. Finally, use wide traces to connect to the external PMOS switch, if used. Note, however , that the gates of both external switches should be connected by a narrow trace. Except for the external switch gates, avoid vias where possible in the power path. If vias are truly unavoidable, use many in parallel. Proper PCB lay - out is critical for suppressing radiated and conducted Electromagnetic interference (EMI). Minimizing the area of the SW node will decrease the amount of capacitance that the switch sees, and thus reduce the current spike seen during switching events. Failing to minimize the area of the so-called hot loop will dramatically degrade EMI

Figure 8. Dual Boost Reference Layout for LT8355-1 sure to keep the above guidance in mind for all changes. uation circuit for a 4-layer PCB reference layout design.

Rev. A For more information www.analog.com TYPICAL APPLICATIONS Dual 32W Boost LED Driver Efficiency vs VIN Voltage LED Short Fault Detection and Response 0.47nF f = 400kHz 151k 499k 10µF 39k 2.2µF 500m/uni03A9 12.5m/uni03A9 ILIM = 8A 10k 576k 500m/uni03A9 15µH 12.5m/uni03A9 ILIM = 8A 10k 576k 15µH 10µF 10µF 0.47nF 39k V IN 6V TO 36V EN/UVLO V V V REF CTRL1 CTRL2 IADJ2 INTV CC 51.1k L T8355-1 CH1 DIMMING RT GND V IN 0.5A 0.5A FB2 ISP2 ISN2 PWMTG2 32W LED ARRAY FAUL T1 FAUL T2 GATE2 SENSEP2 SENSEN2 PWM1 PWM2 CH2 DIMMING FB1 ISP1 ISN1 PWMTG1 GATE1 SENSEP1 SENSEN1 V IN 32W LED ARRAY 8355-1 TA02a 100V 100V 100V L1, L2: WURTH 74435571500 M1, M2: VISHAY Si7852DP M3, M4: VISHAY Si7113DN D1, D2: VISHAY 12CWQ10FN 100k BOTH CHANNELS CH1 ONL Y CH2 ONL Y V IN (V) EFFICIENCY (%)

83551 TA02b

Rev. AFor more information www.analog.com TYPICAL APPLICATIONS Efficiency vs VIN Voltage 10% Internal PWM Dimming Dual 35W Buck-Boost Mode LED Driver 0.62nF f = 300kHz 102k 499k 47k 47k 10µF 500m/uni03A9 22µH 634k 10k 12.5m/uni03A9 ILIM = 8A 500m/uni03A9 634k 2.2µF 10k 100k 100k 10µF 10µF 22µH 12.5m/uni03A9 ILIM = 8A 0.62nF 2.2µF 2.2µF 50k 52.3k 10nF V IN 8V TO 36V EN/UVLO V V V REF CTRL1 IADJ2 INTV CC 69.8k L T8355-1 V IN GATE1 0.5A FB1 ISP1 ISN1 PWMTG1 SENSEP1 SENSEN1 PWM2 RT GND 35W LED ARRAY V IN V IN GATE2 0.5A FB2 ISP2 ISN2 PWMTG2 SENSEP2 SENSEN2 35W LED ARRAY FAUL T1 FAUL T2 V IN 100V 100V 50V 100V 100V L1, L2: WURTH 74435572200 M1, M2: VISHAY Si7430DP M3, M4: VISHAY Si4409DY D1,D2: DIODES INC SBR12U120P5 8355-1 TA03a CTRL2 PWM1 100k NO DIMMING BOTH CHANNELS CH1 ONL Y CH2 ONL Y V IN (V) EFFICIENCY (%)

83551 TA03b

V PWM = 0.511V REF (10% TYPICAL) 400µs/DIV INDUCTOR CURRENT 2A/DIV LED CURRNET 250mA/DIV 8355-1 TA03c

Rev. A For more information www.analog.com TYPICAL APPLICATIONS Complete Automotive Headlamp Solution Efficiency vs VIN Voltage 500:1 External PWM Dimming at 100Hz Cold Crank LED Regulation Boost Channel LED Current vs VIADJ2 0.68nF 0.68nF 51.1k 147k 499k 10µF 15k 33k 10µF 190m/uni03A9 15µH 255k 10k 12.5m/uni03A9 ILIM = 8A 2.2µF 500m/uni03A9 2.2µF 22µH 20m/uni03A9 ILIM = 5A 10k 549k 10µF 100k V IN 8V TO 36V (DOWN TO 6V TEMPORARIL Y) EN/UVLO V V V REF CTRL1 CTRL2 IADJ2 INTV CC f = 400kHz L T8355-1 DRL/POSITION LIGHTS GATE1 1.3A FB1 ISP1 ISN1 PWMTG1 SENSEP1 SENSEN1 RT GND 32W LED ARRAY V IN V IN 0.5A FB2 ISP2 ISN2 PWMTG2 30W LED ARRAY FAUL T1 GATE2 SENSEP2 SENSEN2 PWM1 PWM2 HIGH/LOW BEAMS V IN 100V 100V 100V L1: WURTH 74435571500 L2: WURTH 74435572200 M1: VISHAY Si7852DP M2: VISHAY Si7812DN M3: VISHAY Si7113DN M4: VISHAY Si7117DN D1: DIODES INC SBR12U120P5 D2: DIODES INC PDS5100H 8355-1 TA04a 50V LED CURRENT GAIN DIMMING FAUL T2 100k BUCK-BOOST BOOST BOTH CHANNELS V IN (V) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 EFFICIENCY (%) LED CURRENT (A)

83551 TA04b

V IN = 6V V IN = 8V 1s/DIV V IN VOL TAGE 2V/DIV BUCK-BOOST LED CURRENT 500mA/DIV BOOST LED CURRENT 250mA/DIV 8355-1 TA04c V IN = 14V , INFINITE PERSISTANCE 10µs/DIV PWM1 PIN VOL TAGE 3V/DIV PWM2 PIN VOL TAGE 3V/DIV BUCK-BOOST LED CURRENT 1A/DIV BOOST LED CURRENT 500mA/DIV 8355-1 TA04d V CTRL2 = 2V V CTRL2 = 1V V IADJ2 (V) 0.25 0.50 0.75 1.25 1.50 1.75 125 250 375 500 625 BOOST (CH2) LED CURRENT (mA) 8355-1 TA04e

Rev. AFor more information www.analog.com TYPICAL APPLICATIONS Dual 10W Buck Mode High Switching Frequency (2MHz) LED Driver Efficiency vs VIN Voltage 200m/uni03A9 ILIM = 0.5A 0.47µF 750m/uni03A9 9.09k 20k 499k 1µF 100k 243k 10k 0.47µF 750m/uni03A9 33µH 100k 243k 10k 200m/uni03A9 ILIM = 0.5A 33µH 0.15nF 5.1k 0.15nF 5.1k 10nF 10nF V VIN VIN IN 36V TO 54V EN/UVLO GATE2 SENSEP2 330mA FB2 ISP2 ISN2 PWMTG2 V V V IN V REF CTRL1 CTRL2 IADJ2 f = 2MHz L T8355-1 10W LED ARRAY V IN GATE1 330mA FB1 ISP1 ISN1 PWMTG1 10W LED ARRAY SENSEP1 SENSEN1 SENSEN2 RT GND L1, L2: WURTH 7447789133 M1, M2: VISHAY Si2308BDS M3, M4: VISHAY Si2309CDS D1, D2: DIODES INC DFLS160Q 8355-1 TA05a 100V 50V 50V 2.2µF INTV CC PWM1 INTV CC FAUL T1 FAUL T2 100k PWM2 CH1 ONL Y CH2 ONL Y BOTH CHANNELS V IN (V) EFFICIENCY (%) 8355-1 TA05b

Rev. A For more information www.analog.com TYPICAL APPLICATIONS Boost LED Driver as Pre-boost for Buck-Mode LED Driver Efficiency vs VIN Voltage 25:1 External PWM Dimming at 100Hz V IN (V) EFFICIENCY (%)

83551 TA06b

V IN = 12V 100µs/DIV PWM2 PIN 5V/DIV INDUCTOR L1 5A/DIV VBOOST 10V/DIV BOOST LED CURRENT 500mA/DIV BUCK LED CURRENT 1A/DIV 8355-1 TA06c LED-2 LED-2 500m/uni03A9 84.5k 499k 22µH 10µF 147k 0.33nF 56k 250m/uni03A9 10k 715k 10k 100k 324k 6.8nF 4.7 10nF 10µF 10µF VBOOST 47µH 3.3µF 20k V IN 8V TO 36V GATE1 SENSEN1 PWM2 V REF RT 0.5A f = 250kHz L T8355-1 SENSEP1 ISP1 ISN1 PWMTG1 V IN EN/UVLO FB2 ISN2 ISN1 ISN2 ISN1 ISP2 ISP2 CHANNEL 2 DIMMING GATE2 SENSEN2 ISP2 ISN2 PWMTG2 35W LED ARRAY GND 35W LED ARRAY SENSEP2 FB1 VC1 VC2 L1: COILCRAFT XAL1510-223MEB L2: WURTH 74435574700 M1: INFINEON BSC160N10NS3-G M2: VISHAY Si7810DN M3: VISHAY Si7113DN M4: VISHAY Si3437DV D1: DIODES INC SBR12U120P5 D2: DIODES INC PDS5100H 100V 100V 100V 100V 8355-1 TA06a ISP1 ISP1 10nF 50m/uni03A9 ILIM = 2A 9m/uni03A9 ILIM = 11A 2.2µF INTV CC FAUL T1 CTRL1 IADJ2 PWM1 CTRL2 FAUL T2 100k 100k

Rev. AFor more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. PACKAGE DESCRIPTION 4.00 ±0.10 (2 SIDES)

2.50 REF

5.00 ±0.10 (2 SIDES) NOTE: 1. DRAWING NOT TO SCALE 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT , SHALL NOT EXCEED 0.15mm ON ANY SIDE 4. SHADED AREA IS ONL Y A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (NOTE 6) 0.40 ±0.10 27 28 BOTTOM VIEW—EXPOSED PAD

3.50 REF

0.75 ±0.05 R = 0.115 TYP R = 0.05 TYP PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER 0.25 ±0.05

0.50 BSC

0.200 REF

0.00 – 0.05 (UFDM28) QFN 1218 REV Ø RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPL Y SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 0.25 ±0.05 4.10 ±0.05 5.50 ±0.05 2.65 ±0.05 3.10 ±0.05 4.50 ±0.05 PACKAGE OUTLINE 2.65 ±0.10 3.65 ±0.10 3.65 ±0.05 28-Lead Plastic Side Wettable QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1682 Rev Ø)

0.203 REF

0.40 ± 0.10

0.05 REF

0.10 REF

Rev. A For more information www.analog.com

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 12/22 Updated Pulse Width Modulation (PWM) Dimming section Updated LED Fault Events section

Rev. AFor more information www.analog.com  ANALOG DEVICES, INC. 2022 www.analog.com RELATED PARTS TYPICAL APPLICATION High External PWM Dimming Boost Dual LED Driver Efficiency vs VIN Voltage 10000:1 External PWM Dimming at 100Hz BOTH CHANNELS CH1 ONL Y CH2 ONL Y V IN (V) EFFICIENCY (%)

83551 TA07b

V IN = 12V 2µs/DIV PWM PIN VOL TAGE 2V/DIV LED CURRENT 200mA/DIV INDUCTOR CURRENT 1A/DIV 8355-1 TA07c 1.5/uni03A9 51.1k 499k 47µH 102k 1nF 10k 1.5/uni03A9 10k 50m/uni03A9 ILIM = 2A 50m/uni03A9 ILIM = 2A 536k 4.7µF 47µH 2.2µF 2.2µF V IN 8V TO 18V GATE1 SENSEN1 PWM1 CHANNEL 1 DIMMING V REF RT 0.167A f = 400kHz L T8355-1 SENSEP1 ISP1 ISN1 PWMTG1 V IN EN/UVLO VC2 FB1 PWM2 CHANNEL 2 DIMMING GATE2 SENSEN2 0.167A SENSEP2 ISP2 ISP2 ISP1 ISN2 PWMTG2 10W LED ARRAY GND 10W LED ARRAY 50V 100V 100V L1, L2: WURTH 7447709470 M1, M2: VISHAY Si7810DN M3, M4: VISHAY Si4409DY D1, D2: DIODES INC PDS3100 8355-1 TA07a 1nF 10k VC1 10k 536k FB2 2.2µF INTV CC CTRL1 IADJ2 FAUL T1 FAUL T2 100k 100k CTRL2 PART NUMBER DESCRIPTION COMMENTS LT8356-1 100VIN/120VOUT LED Controller with Exponential PWM and Scalable Dimming VIN: 5V to 100V, VOUT(MAX): 120V, 20,000:1 External Dimming, 128:1 Exponential Internal PWM Dimming, ISD <1µA, 3mm × 4mm QFN-20, MSOP-16E Packages LT3952A 60V, 4A Synchronous Step-Up LED Driver VIN(MIN) = 3V, VIN(MAX) = 42V, VOUT = 0V to 60V, 5:1 Internal Dimming and 4,000:1 External Dimming, ISD = 1μA, TSSOP-28E LT3755/LT3755-1/ LT3755-2 High Side 75V, 1MHz LED Controller with 3,000:1 PWM Dimming VIN: 4.5V to 40V, VOUT: 5V to 60V, T rue Color PWM, Analog = 3000:1, ISD <1µA, 3mm × 3mm QFN-16, MSOP-16E Packages LT3756/LT3756-1/ LT3756-2 High Side 100V, 1MHz LED Controller with 3,000:1 PWM Dimming VIN: 6V to 100V, VOUT: 5V to 100V, T rue Color PWM, Analog = 3000:1, ISD <1µA, 3mm × 3mm QFN-16, MSOP-16E Packages LT3761/LT3761A High Side 100V, 1MHz LED Controller with 3,000:1 PWM Dimming and Internal PWM Generator V IN: 4.5V to 60V, VOUT(MAX) = 80V, PWM and Analog Dimming, ISD <1µA,