LT3752

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Technical content

Rev. CFor more information www.analog.com TYPICAL APPLICATION FEATURES DESCRIPTION Active Clamp Synchronous Forward Controllers with Internal Housekeeping Controller The LT®3752/L T3752-1 are current mode PWM controllers optimized for an active clamp forward converter topology. A DC/DC housekeeping controller is included for improved efficiency and performance. The L T3752 allows operation up to 100V input and the L T3752-1 is optimized for ap - plications with input voltages greater than 100V . A programmable volt-second clamp allows primar y switch duty cycles above 50% for high switch, transformer and rectifier utilization. Active clamp control reduces switch voltage stress and increases efficiency. A synchronous output is available for controlling secondary side syn - chronous rectification. The L T3752/L T3752-1 are available in a 38-lead plastic TSSOP package with missing pins for high voltage spacings. 18V to 72V , 12V/12.5A, 150W Active Clamp Isolated Forward Converter

APPLICATIONS

n Input V oltage Range: L T3752: 6.5V to 100V , L T3752-1:Limited Only by External Components n Internal Housekeeping DC/DC Controller n Programmable V olt-Second Clamp n High Efficiency Control: Active Clamp, Synchronous Rectification, Programmable Delays n Short-Cir cuit (Hiccup Mode) Overcurrent Protection n Programmable Soft-Start/Stop n Programmable OVLO and UVLO with Hysteresis n Programmable Frequency (100kHz to 500kHz) n Synchronizable to an External Clock n AEC-Q100 Qualified for Automotive Applications n Offline and HV Car Batter y Isolated Power Supplies n 48V T elecommunication Isolated Power Supplies n Industrial, Automotive and Militar y Systems All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. patents, including XXXXX, XXXXX. 49.9k 22.6k 1.82k 7.32k 34k 71.5k 31.6k 100k 100k 2.8k 10k 560/uni03A9 3.16k 100k VAUX VAUX SYNC VIN GND FBL T8311PGOOD 0.006/uni03A9 10k0.15/uni03A9499/uni03A9 2.2µF2.2µF INTVCC VAUX ZVN4525E6 100/uni03A9 1.1k 1.2k 2.2nF EFFICIENCY: 94% AT 48VIN/10AOUT 0.33µF 22nF 22nF 4.7µF 2.2µF 22µF 16V V OUT 12V 12.5A 470µF 16V 4.7µF 220nF

3752 TA01

4.7nF 220pF 1µF TAO TAS TOS TBLNK IVSEC RT SS1 SS2 HCOMP FB COMP OPTO INTVCC TIMER SS COMP CSP PMODE INTVCC INTVCC SOUT ISENSEN ISENSEP OUTVIN AOUTHISENSEHOUT OC 5.9k 100k UVLO_VSEC L T3752 SYNC 100nF 15nF Si2325DS 4:4 BSC077N12NS3FDMS86101 BSC077N12NS3 499k 13.7k 6.8µH 100k 11.3k CSN FG FSW CG CSW 100/uni03A9100/uni03A9

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• •• 4.7µF 100V VIN 18V TO 72V GND OVLO HFB 68pF Document Feedback

Rev. C For more information www.analog.com TABLE OF CONTENTS

Electrical Characteristics

Programming System Input Undervoltage Lockout (UVLO) Threshold and Hysteresis Soft-Stop Shutdown Micropower Shutdown Programming System Input Overvoltage Lockout (OVLO) Threshold LT3752-1 Micropower Start-Up from High System Input Voltages Programming Switching Frequency Synchronizing to an External Clock H OUSEKEEPING CONTROLLER Housekeeping: Operation Housekeeping: Soft-Start/Shutdown Housekeeping: Programming Output Voltage Housekeeping: Programming Cycle-by-Cycle Peak Inductor Current and Slope Compensation H ousekeeping: Adaptive Leading Edge Blanking .26 Housekeeping: Overcurrent Hiccup Mode Housekeeping: Output Overvoltage and Power Good Housekeeping: Transformer Turns Ratio and Leakage Inductance Housekeeping: Operating Without This Supply ...27 FORWARD CONTROLLER Adaptive Leading Edge Blanking Plus Current Sensing and Programmable Slope Compensation Overcurrent: Hiccup Mode Programming Maximum Duty Cycle Clamp: DVSEC DVSEC Open Loop Control: No Opto-Coupler, Error T ransformer Reset: Active Clamp Technique LO Side Active Clamp Topology (LT3752) HI Side Active Clamp Topology (LT3752-1) Active Clamp Capacitor Value and Active Clamp MOSFET Selection Programming Active Clamp Switch Timing: AOUT to OUT (t Programming Synchronous Rectifier Timing: SOUT to OUT (t SO) and OUT to SOUT (tOS) Soft-Start (SS1, SS2) Soft-Stop (SS1) Hard-Stop (SS1, SS2) OUT, AOUT, SOUT Pulse-Skipping Mode AOUT Timeout Main Transformer Selection P rimary-Side Power MOSFET Selection Synchronous Control (SOUT) Output Inductor Value Output Capacitor Selection Input Capacitor Selection PCB Layout / Thermal Guidelines Typical Applications Package Description

Revision History

Rev. CFor more information www.analog.com PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS FB, SYNC SS1, COMP , HCOMP , HFB, RT IVSEC Operating Junction Temperature Range (Notes 2, 3) L T3752EFE, LT3752EFE-1 LT 3752IFE, LT3752IFE-1 LT 3752HFE, LT3752HFE-1 L T3752MPFE, LT3752MPFE-1 Storage Temperature Range Lead Temperature (Soldering, 10 Sec) (Note 1) TOP VIEW FE PACKAGE VARIATION: FE38(31) 38-LEAD PLASTIC TSSOP HFB HCOMP RT FB COMP SYNC SS1 IVSEC UNLO_V SEC OVLO TAO TAS TOS TBLNK NC NC SS2 GND PGND PGND NC HI SENSE HOUT AOUT SOUT V IN INTVCC OUT OC I SENSEP ISENSEN PGND GND θJA = 25°C/W EXPOSED PAD (PIN 39) IS PGND AND GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L T3752EFE#PBF L T3752EFE#TRPBF L T3752FE 38-Lead Plastic TSSOP –40°C to 125°C L T3752IFE#PBF L T3752IFE#TRPBF L T3752FE 38-Lead Plastic TSSOP –40°C to 125°C L T3752HFE#PBF L T3752HFE#TRPBF L T3752FE 38-Lead Plastic TSSOP –40°C to 150°C L T3752MPFE#PBF L T3752MPFE#TRPBF L T3752FE 38-Lead Plastic TSSOP –55°C to 150°C L T3752EFE-1#PBF L T3752EFE-1#TRPBF L T3752FE-1 38-Lead Plastic TSSOP –40°C to 125°C L T3752IFE-1#PBF L T3752IFE-1#TRPBF L T3752FE-1 38-Lead Plastic TSSOP –40°C to 125°C L T3752HFE-1#PBF L T3752HFE-1#TRPBF L T3752FE-1 38-Lead Plastic TSSOP –40°C to 150°C L T3752MPFE-1#PBF L T3752MPFE-1#TRPBF L T3752FE-1 38-Lead Plastic TSSOP –55°C to 150°C

Rev. C For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V , UVLO_VSEC = 2.5V . PARAMETER CONDITIONS MIN TYP MAX UNITS Operational Input Voltage (L T3752) l 6.5 100 V Operational Input Voltage (L T3752-1) l 10.5 16 V VIN(ON) (L T3752) l 5.8 6.4 V VIN(OFF) (L T3752) 5.5 5.9 V VIN(ON/OFF) Hysteresis (L T3752) l 0.1 0.3 0.5 V VIN(ON) (L T3752-1) l 9.5 10.4 V VIN(OFF) (L T3752-1) 7.6 V VIN(ON/OFF) Hysteresis (L T3752-1) l 1.61 1.9 2.19 V VIN Start-Up Current (L T3752-1) (Notes 6, 7) l 170 265 µA VIN Quiescent Current (Housekeeping Controller Only) (L T3752) HCOMP = 1V (Housekeeping Not Switching), HFB = 0.85V l 4 6.2 mA VIN Quiescent Current (Housekeeping Controller Only) (L T3752-1) HCOMP = 1V (Housekeeping Not Switching), HFB = 0.85V l 3 4.6 mA VIN Quiescent Current (Housekeeping Controller + Forward Controller) HCOMP = 1V (Housekeeping Not Switching), HFB = 1.35V , FB = 1.5V (Main Loop Not Switching) 7.5 9.5 mA UVLO_VSEC Micropower Threshold (VSD) IVIN < 20µA l 0.2 0.4 0.6 V VIN Shutdown Current (Micropower) UVLO_VSEC = 0.2V 20 40 µA UVLO_VSEC Threshold (VSYS_UV) l 1.180 1.250 1.320 V VIN Shutdown Current (After Soft-Stop) UVLO_VSEC = 1V 165 220 µA UVLO_VSEC (ON) Current UVLO_VSEC = VSYS_UV + 50mV 0 µA UVLO_VSEC (OFF) Current Hysteresis Current With One-Shot Communication Current UVLO_VSEC = VSYS_UV – 50mV (Note 15) l 4.0 6.0 µA µA OVLO (Rising) (No Switching, Reset SS1) l 1.220 1.250 1.280 V OVLO (Falling) (Restart SS1) 1.215 V ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE AUTOMOTIVE PRODUCTS** L T3752EFE#WPBF L T3752EFE#WTRPBF L T3752FE 38-Lead Plastic TSSOP –40°C to 125°C L T3752IFE#WPBF L T3752IFE#WTRPBF L T3752FE 38-Lead Plastic TSSOP –40°C to 125°C L T3752HFE#WPBF L T3752HFE#WTRPBF L T3752FE 38-Lead Plastic TSSOP –40°C to 150°C L T3752EFE-1#WPBF L T3752EFE-1#WTRPBF L T3752FE-1 38-Lead Plastic TSSOP –40°C to 125°C L T3752IFE-1#WPBF L T3752IFE-1#WTRPBF L T3752FE-1 38-Lead Plastic TSSOP –40°C to 125°C L T3752HFE-1#WPBF L T3752HFE-1#WTRPBF L T3752FE-1 38-Lead Plastic TSSOP –40°C to 150°C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. **Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.

Rev. CFor more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V , UVLO_VSEC = 2.5V . PARAMETER CONDITIONS MIN TYP MAX UNITS OVLO Hysteresis l 23 35 47 mV OVLO Pin Current (Note 10) OVLO = 0V OVLO = 1.5V (SS1 = 2.7V) OVLO = 1.5V (SS1 = 1.0V) 0.9 100 100 nA mA nA Oscillator (For ward Controller: OUT , SOUT , AOUT) Frequency: fOSC = 100kHz RT = 82.5k 94 100 106 kHz Frequency: fOSC = 300kHz RT = 24.9k l 279 300 321 kHz Frequency: fOSC = 500kHz RT = 14k 470 500 530 kHz fOSC Line Regulation RT = 24.9k 6.5V < VIN < 100V (L T3752) 10.5V < VIN < 16V (L T3752-1) 0.05 0.05 0.1 0.1 %/V %/V Frequency and D VSEC Foldback Ratio (L T3752) (Fold) SS1 = V SSACT + 25mV , SS2 = 2.7V 4 Frequency and DVSEC Foldback Ratio (L T3752-1) (Fold)SS1 = VSS1ACT + 25mV , SS2 = 2.7V 2 SYNC Input High Threshold (Note 4) l 1.2 1.8 V SYNC Input Low Threshold (Note 4) l 0.6 1.025 V SYNC Pin Current SYNC = 6V 75 µA SYNC Frequency/Programmed fOSC 1.0 1.25 kHz/kHz Linear Regulator (INTVCC) (L T3752) INTVCC Regulation Voltage 6.6 7 7.2 V Dropout (VIN-INTVCC) VIN = 6.5V , IINTVCC = 10mA 0.8 V INTVCC UVLO(+) (Start Switching) 4.75 5 V INTVCC UVLO(–) (Stop Switching) 4.6 4.85 V INTVCC UVLO Hysteresis 0.075 0.15 0.24 V Linear Regulator (INTVCC) (L T3752-1) INTVCC Regulation Voltage 9.4 10 10.4 V Dropout (VIN-INTVCC) VIN = 8.75V , IINTVCC = 10mA 0.6 V INTVCC UVLO(+) (Start Switching) 7 7.4 V INTVCC UVLO(–) (Stop Switching) 6.8 7.2 V INTVCC UVLO Hysteresis 0.1 0.2 0.3 V Linear Regulator (INTVCC) (L T3752/L T3752-1) INTVCC OVLO(+) (Stop Switching) 15.9 16.5 17.2 V INTVCC OVLO(–) (Start Switching) 15.4 16 16.7 V INTVCC OVLO Hysteresis 0.38 0.5 0.67 V INTVCC Current Limit INTVCC = 0V INTVCC = 5.75V (L T3752) INTVCC = 8.75V (L T3752-1) l l mA mA mA Error Amplifier FB Reference V oltage l 1.220 1.250 1.275 V FB Line Reg 6.5V < VIN < 100V (L T3752) 10.5V < VIN < 16V (L T3752-1) 0.1 0.1 0.3 0.3 mV mV/V FB Load Reg COMP_SW – 0.1V < COMP < COMP_VOH – 0.1V 0.1 0.3 mV/V FB Input Bias Current (Note 10) 50 200 nA Open-Loop Voltage Gain 85 dB Unity-Gain Bandwidth (Note 8) 2.5 MHz COMP Source Current FB = 1V , COMP = 1.75V (Note 10) 6 11 mA

Rev. C For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V , UVLO_VSEC = 2.5V . PARAMETER CONDITIONS MIN TYP MAX UNITS COMP Sink Current FB = 1.5V , COMP = 1.75V 6.5 11.5 mA COMP Output High Clamp FB = 1V 2.6 V COMP Switching Threshold 1.25 V Current Sense (Main Loop) ISENSEP Maximum Threshold FB = 1V , OC = 0V 180 220 260 mV COMP Current Mode Gain ∆VCOMP/∆VISENSEP 6.1 V/V ISENSEP Input Current (D = 0%) (Note 10) 2 µA ISENSEP Input Current (D = 80%) (Note 10) 33 µA ISENSEN Input Current FB = 1.5V (COMP Open) (Note 10) FB = 1V (COMP Open) (Note 10) 135 µA µA OC Over current Threshold l 82.5 96 107.5 mV OC Input Current 200 500 nA AOUT Driver (Active Clamp Switch Control) (L T3752 External PMOS; L T3752-1 External NMOS) AOUT Rise Time C L = 1nF (Note 5), INTVCC = 12V 23 ns AOUT Fall Time CL = 1nF (Note 5), INTVCC = 12V 19 ns AOUT Low Level 0.1 V AOUT High Level INTVCC = 12V 11.9 V AOUT High Level in Shutdown (L T3752) UVLO_VSEC = 0V , INTVCC = 8V , IAOUT = 1mA Out of the Pin 7.8 V AOUT Low Level in Shutdown (L T3752-1) UVLO_VSEC = 0V , INTVCC = 12V , IAOUT = 1mA Into the Pin 0.25 V AOUT Edge to OUT (Rise): (tAO) CSOUT = 1nF , COUT = 3.3nF , INTVCC = 12V RTAO = 44.2k RTAO = 73.2k (Note 11) 168 253 218 328 268 403 ns ns OUT (Fall) to AOUT Edge: (t OA) CSOUT = 1nF , COUT = 3.3nF , INTVCC = 12V RTAO = 44.2k RTAO = 73.2k (Note 12) 150 214 196 295 250 376 ns ns SOUT Driver (Synchronous Rectification Control) SOUT Rise T ime COUT = 1nF , INTVCC = 12V (Note 5) 21 ns SOUT Fall Time COUT = 1nF , INTVCC = 12V (Note 5) 19 ns SOUT Low Level 0.1 V SOUT High Level INTVCC = 12V 11.9 V SOUT High Level in Shutdown UVLO_VSEC = 0V , INTVCC = 8V , ISOUT = 1mA Out of the Pin 7.8 V AOUT Edge to SOUT (Fall): (tAS) CAOUT = CSOUT = 1nF , INTVCC = 12V RTAS = 44.2k (Note 13) RTAS = 73.2k 168 253 218 328 268 403 ns ns SOUT (Fall) to OUT (Rise): (t SO = tAO – tAS) C SOUT = 1nF , COUT = 3.3nF , INTVCC = 12V RTAO = 73.2k, RTAS = 44.2k (Notes 11, 13) RTAO = 44.2k, RTAS = 73.2k –70 110 –110 132 –132 ns ns OUT (Fall) to SOUT (Rise): (t OS) CSOUT = 1nF , COUT = 3.3nF , INTVCC = 12V RTOS = 14.7k RTOS = 44.2k (Note 14) 102 133 164 ns ns OUT Driver (Main Power Switch Control) OUT Rise T ime COUT = 3.3nF , INTVCC = 12V (Note 5) 19 ns OUT Fall Time COUT = 3.3nF , INTVCC = 12V (Note 5) 20 ns OUT Low Level 0.1 V

Rev. CFor more information www.analog.com PARAMETER CONDITIONS MIN TYP MAX UNITS OUT High Level INTVCC = 12V 11.9 V OUT Low Level in Shutdown UVLO_VSEC = 0V , INTVCC = 8V , IOUT = 1mA Into the Pin 0.25 V OUT (Volt-Sec) Max Duty Cycle Clamp DVSEC (1 • System Input (Min)) × 100 DVSEC (2 • System Input (Min)) × 100 DVSEC (4 • System Input (Min)) × 100 RT = 24.9k, RIVSEC = 51.1k, FB = 1V , SS1 = 2.7V UVLO_VSEC = 1.25V UVLO_VSEC = 2.50V UVLO_VSEC = 5.00V 68.5 34.3 17.5 72.5 36.5 18.6 76.2 38.7 19.7 OUT Minimum ON T ime COUT = 3.3nF , INTVCC = 12V (Note 9) RTBLNK = 14.7k RTBLNK = 73.2k (Note 16) 325 454 ns ns SS1 Pin (Soft-Start: Frequency and D VSEC) (Soft-Stop: COMP Pin, Frequency and DVSEC) SS1 Reset Threshold (VSS1(RTH)) 150 mV SS1 Active Threshold (VSS1(ACT)) (Allow Switching) 1.25 V SS1 Charge Current (Soft-Start) SS1 = 1.5V (Note 10) 7 11.5 16 µA SS1 Discharge Current (Soft-Stop) SS1 = 1V , UVLO_VSEC = VSYS_UV – 50mV 6.4 10.5 14.6 µA SS1 Discharge Current (Hard Stop) OC > OC Threshold INTVCC < INTVCC UVLO(–) OVLO > OVLO(+) SS1 = 1V 0.9 0.9 0.9 mA mA mA SS2 Pin (Soft-Start: Comp Pin) SS2 Discharge Current SS1 < V SS(ACT), SS2 = 2.5V 2.8 mA SS2 Charge Current SS1 > VSS(ACT), SS2 = 1.5V 11 21 28 µA Error Amplifier (Housekeeping Controller) HFB Reference Voltage 0.90 1.000 1.10 V HFB Line Reg 6.5V < V IN < 100V (L T3752) 10.5V < VIN < 16V (L T3752-1) 0.1 0.1 mV mV/V HFB Load Reg HCOMP VSW – 0.1V < HCOMP < HCOMP VOH – 0.1V –6 mV/V HFB Input Bias Current HFB = 1.1V (Note 10) 85 170 nA T ransconductance ∆IHCOMP ±5µA 250 µS Voltage Gain 175 V/V Power Good(+) (HFB Level) 0.96 V Power Good(–) (HFB Level) 0.92 V HFB OVLO(+) (Disable HOUT Switching) 1.206 V HFB OVLO(–) (Enable Housekeeping Operation) 1.150 V HCOMP Source Current HCOMP = 1.75V (Note 10) 11 15 19 µA HCOMP Sink Current HCOMP = 1.75V 13 18 23 µA HCOMP Output High Clamp 2.9 V HCOMP Switching Threshold 1.28 V Current Sense (Housekeeping Controller) HI SENSE Peak Current Threshold HFB = 0.8V 69 79 86.5 mV HCOMP Current Mode Gain ∆VHCOMP/∆VHISENSE 9.1 V/V HISENSE Input Current (D = 0%) HISENSE Input Current (D = 80%) (Note 10) 2 µA µA HISENSE Overcurrent Threshold 84.6 98 105.4 mV ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V , UVLO_VSEC = 2.5V .

Rev. C For more information www.analog.com Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The L T3752EFE/L T3752EFE-1 are guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The L T3752IFE/L T3752IFE-1 are guaranteed to meet performance specifications from –40°C to 125°C junction temperature. The L T3752HFE/ L T3752HFE-1 are guaranteed to meet performance specifications from –40°C to 150°C junction temperature. The L T3752MPFE/L T3752MPFE-1 are tested and guaranteed to meet performance specifications from –55°C to 150°C junction temperature. Note 3: For maximum operating ambient temperature, see the Thermal Calculations section in the Applications Information section. Note 4: SYNC minimum and maximum thresholds are guaranteed by SYNC frequency range test using a clock input with guard banded SYNC levels of 0.7V low level and 1.7V high level. Note 5: Rise and fall times are measured between 10% and 90% of gate driver supply voltage. Note 6: Guaranteed by correlation to static test. Note 7: V IN start-up current is measured at VIN = VIN(ON) – 0.25V and then scaled by 1.18× to correlate to worst-case VIN current required for part start-up at VIN = VIN(ON). Note 8: Guaranteed by design. Note 9: ON times are measured between rising and falling edges at 50% of gate driver supply voltage. Note 10: Current flows out of pin. Note 11: Guaranteed by correlation to R TAS = 73.2k test. Note 12: tOA timing guaranteed by design based on correlation to measured tAO timing. Note 13: Guaranteed by correlation to RTAO = 44.2k test. Note 14: Guaranteed by correlation to RTOS = 14.7k test. Note 15: A 2µs one-shot of 20µA from the UVLO_VSEC pin allows communication between ICs to begin shutdown (useful when stacking supplies for more power ( = inputs in parallel/outputs in series)). The current is tested in a static test mode. The 2µs one-shot is guaranteed by design. Note 16: Guaranteed by correlation to R TBLNK = 14.7k test. PARAMETER CONDITIONS MIN TYP MAX UNITS HOUT Driver (Housekeeping Controller) HOUT Rise Time CL = 1nF (Note 5), INTVCC = 12V 13 ns HOUT Fall Time CL = 1nF (Note 5), INTVCC = 12V 12 ns HOUT Low Level 0.1 V HOUT High Level L T3752 L T3752-1 INTV CC = 12V 11.9 11.9 V V HOUT Low Level in Shutdown UVLO_V SEC = 0V , INTVCC = 12V , IHOUT = 1mA Into the Pin 0.25 V HOUT Maximum Duty Cycle HCOMP = 2.7V , RT = 24.9k 90 95 % HOUT Minimum ON Time CL = 1nF (Note 9), INTVCC = 12V 350 ns Soft-Start (HSS) (Housekeeping Controller) HSS (Internal) Ramp Time (tHSS) HCOMP SW ≥ HCOMP VOH – 0.1V 2.2 4 ms Oscillator (Housekeeping Controller) Frequency (f HOUT) (fOSC Folded Back) (L T3752) HFB = 0.8V , R T = 24.9k, SS1 = 0V 55 65 75 kHz Frequency (fHOUT) (fOSC Folded Back) (L T3752-1) HFB = 0.8V , R T = 24.9k, SS1 = 0V 119 141 163 kHz Frequency (fHOUT) (Full-Scale fOSC) HFB = 1.15V , HCOMP = 2.7V l 279 300 321 kHz The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V , UVLO_VSEC = 2.5V .

Rev. CFor more information www.analog.com VIN Start-Up and Shutdown Current vs Junction Temperature VIN(ON), VIN(OFF) Thresholds vs Junction Temperature VIN Quiescent Current vs Junction Temperature UVLO_VSEC Turn-On Threshold vs Junction Temperature UVLO_VSEC Hysteresis Current vs Junction Temperature HFB PGOOD Thresholds vs Junction Temperature TYPICAL PERFORMANCE CHARACTERISTICSTA = 25°C, unless otherwise noted. JUNCTION TEMPERATURE (°C) –75 VIN CURRENT (µA) 220 180 200 160 140 120 100 25 150–25 100

3752 G01

1750 125–50 50 75 L T3752-1 VIN START-UP CURRENT (VIN = VIN_ON) L T3752/L T3752-1 VIN SHUTDOWN CURRENT (VIN = 12V) UVLO_VSEC = 0.2V JUNCTION TEMPERATURE (°C) –75 UVLO_VSEC THRESHOLD (V) 1.275 1.270 1.265 1.260 1.255 1.250 1.245 1.240 1.235 1.230 1.225 25 150–25 100

3752 G04

1750 125–50 50 75 JUNCTION TEMPERATURE (°C) –75 HFB PGOOD THRESHOLDS (V) 1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 25 150–25 100

3752 G06

1750 125–50 50 75 HFB PGOOD (+) = ENABLE FORWARD CONTROLLER CIRCUITRY HFB PGOOD (–) = DISABLE FORWARD CONTROLLER CIRCUITRY JUNCTION TEMPERATURE (°C) –75 UVLO_VSEC HYSTERESIS CURRENT (µA) 6.0 5.5 5.0 4.5 4.0 25 150–25 100

3752 G05

1750 125–50 50 75 JUNCTION TEMPERATURE (°C) –75 VIN IQ (mA) 25 150–25 100

3752 G03

1750 125–50 50 75 L T3752: HOUSEKEEPING ONL Y (NO SWITCHING) L T3752/-1: HOUSEKEEPING + FORWARD (NO SWITCHING) L T3752-1: HOUSEKEEPING ONL Y (NO SWITCHING) JUNCTION TEMPERATURE (°C) –75 VIN ON/OFF THRESHOLDS (V) 10.0 9.0 9.5 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 25 150–25 100

3752 G02

1750 125–50 50 75 L T3752-1 VIN_ON L T3752-1 VIN_OFF L T3752 VIN_ON L T3752 VIN_OFF HFB Reference Voltage vs Junction Temperature HFB OVLO Thresholds vs Junction Temperature JUNCTION TEMPERATURE (°C) –75 HFB OVLO THRESHOLDS (V) 1.30 1.25 1.20 1.15 1.10 1.05 1.00 25 150–25 100

3752 G08

1750 125–50 50 75 HFB > OVLO (+) = DISABLE HOUT SWITCHING HFB < OVLO (–) = ENABLE HOUSEKEEPING OPERATION JUNCTION TEMPERATURE (°C) –75 HFB REFERENCE VOL TAGE (V) 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 0.900 25 150–25 100

3752 G07

1750 125–50 50 75

Rev. C For more information www.analog.com L T3752-1: INTVCC in Dropout at VIN = 8.75V vs Current, Junction Temperature L T3752: INTVCC in Dropout at VIN = 6.5V vs Current, Junction Temperature L T3752: INTVCC UVLO Thresholds vs Junction Temperature L T3752: INTVCC Regulation Voltage vs Current, Junction Temperature TYPICAL PERFORMANCE CHARACTERISTICSTA = 25°C, unless otherwise noted. JUNCTION TEMPERATURE (°C) –75 INTVCC (V) 7.0 6.5 6.0 5.5 5.0 3.5 4.5 4.0 3.0 25 150–25 100

3752 G13

1750 125–50 50 75 ILOAD = 0mA ILOAD = 10mA ILOAD = 15mA ILOAD = 20mA JUNCTION TEMPERATURE (°C) –75 INTVCC (V) 7.00 6.95 6.90 6.85 6.80 6.65 6.75 6.70 6.60 25 150–25 100

3752 G15

1750 125–50 50 75 ILOAD = 0mA ILOAD = 10mA ILOAD = 20mA ILOAD = 30mA VIN = 12V JUNCTION TEMPERATURE (°C) –75 INTVCC (V) 10.0 9.5 9.0 8.5 7.5 8.0 5.5 7.0 6.5 6.0 5.0 25 150–25 100

3752 G16

1750 125–50 50 75 ILOAD = 0mA ILOAD = 10mA ILOAD = 15mA ILOAD = 20mA VIN = 12V HISENSE Peak Current Threshold vs Junction Temperature HISENSE Pin Current vs Duty Cycle HISENSE Overcurrent (Hiccup Mode) Threshold vs Junction Temperature Housekeeping Internal Soft-Start Time (HSS) vs Junction Temperature JUNCTION TEMPERATURE (°C) –75 HISENSE PEAK CURRENT THRESHOLD (mV) 25 150–25 100

3752 G09

1750 125–50 50 75 DUTY CYCLE (%) HISENSE PIN CURRENT (µA) 40 9020 70

3752 G10

TJ = 150°C TJ = 25°C TJ = –55°C JUNCTION TEMPERATURE (°C) –75 HISENSE OVERCURRENT THRESHOLD (mV) 110 105 100 25 150–25 100

3752 G11

1750 125–50 50 75 JUNCTION TEMPERATURE (°C) –75 HOUSEKEEPING INTERNAL SOFT-START TIME (ms) 3.00 2.75 2.50 2.25 1.75 2.00 1.50 25 150–25 100

3752 G12

1750 125–50 50 75 JUNCTION TEMPERATURE (°C) –75 INTVCC UVLO THRESHOLD (V) 4.85 4.80 4.75 4.70 4.55 4.65 4.60 4.50 25 150–25 100

3752 G14

1750 125–50 50 75 INTVCC < UVLO (–): DISABLE SWITCHING INTVCC > UVLO (+): ENABLE SWITCHING

Rev. CFor more information www.analog.com L T3752-1: INTVCC UVLO Thresholds vs Junction Temperature SS1 Soft-Start/Soft-Stop Pin Currents vs Junction Temperature SS1 High, Active and Reset Levels vs Junction Temperature SS2 Soft-Start Charge Current vs Junction Temperature L T3752-1: INTV CC Regulation Voltage vs Current, Junction Temperature TYPICAL PERFORMANCE CHARACTERISTICSTA = 25°C, unless otherwise noted. JUNCTION TEMPERATURE (°C) –75 INTVCC (V) 10.00 9.95 9.90 9.85 9.80 9.65 9.75 9.70 9.40 9.60 9.55 9.50 9.45 25 150–25 100

3752 G18

1750 125–50 50 75 ILOAD = 0mA ILOAD = 10mA ILOAD = 20mA ILOAD = 30mA VIN = 12V JUNCTION TEMPERATURE (°C) –75 SS2 SOFT-START CHARGE CURRENT (µA) 25 150–25 100

3752 G21

1750 125–50 50 75 SS2 PIN CURRENT* (–1) JUNCTION TEMPERATURE (°C) –75 SS1 CURRENTS (µA) 14.0 13.5 13.0 12.5 8.5 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.0 25 150–25 100

3752 G19

1750 125–50 50 75 SS1 SOFT-START : CHARGE CURRENT* (–1) SS1 SOFT-STOP: DISCHARGE CURRENT JUNCTION TEMPERATURE (°C) –75 SS1 HIGH, ACTIVE AND RESET LEVELS (V) 3.00 2.75 2.50 2.25 0.25 2.00 1.75 1.50 1.25 1.00 0.75 0.50 25 150–25 100

3752 G20

1750 125–50 50 75 SS1 ACTIVE LEVEL (ALLOW FORWARD CONVERTER SWITCHING) SS1 HIGH LEVEL SS1 RESET LEVEL (RESET SS1 LATCH) Switching Frequency vs SS1 Pin Voltage Switching Frequency vs Junction Temperature JUNCTION TEMPERATURE (°C) –75 SWITCHING FREQUENCY (kHz) 325 320 315 280 310 305 300 295 290 285 275 25 150–25 100

3752 G23

1750 125–50 50 75 RT = 24.9k FB Reference Voltage vs Junction Temperature JUNCTION TEMPERATURE (°C) –75 FB REFERENCE VOL TAGE (V) 1.30 1.29 1.28 1.21 1.27 1.26 1.25 1.24 1.23 1.22 1.20 25 150–25 100

3752 G24

1750 125–50 50 75 JUNCTION TEMPERATURE (°C) –75 INTVCC UVLO THRESHOLDS (V) 7.20 7.15 7.10 7.05 6.65 7.00 6.95 6.90 6.85 6.80 6.75 6.70 6.60 25 150–25 100

3752 G17

1750 125–50 50 75 INTVCC < UVLO (–): DISABLE FORWARD CONVERTER SWITCHING INTVCC > UVLO (+): ENABLE FORWARD CONVERTER SWITCHING SS1 (V) SWITCHING FREQUENCY (kHz) 350 325 300 275 250 225 200 175 150 100 125 1 2.25 2.50.5 1.75

3752 G22

RT = 24.9k L T3752-1 f(HOUT) f(OUT) f(HOUT)L T3752-1 f(HOUT)L T3752 f(OUT) L T3752 f (HOUT) f(OUT)

Rev. C For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICSTA = 25°C, unless otherwise noted. SOUT (Fall) to OUT (Rise) Delay (tSO = tAO – tAS) vs Junction Temperature OUT (Fall) to SOUT (Rise) Delay OS) vs Junction Temperature JUNCTION TEMPERATURE (°C) –75 tSO (ns) 160 140 120 100 25 150–25 100

3752 G32

1750 125–50 50 75 RTOS = 44.2k RTOS = 14.7k RTOS = 7.32k JUNCTION TEMPERATURE (°C) –75 tSO (ns) 120 100 –20 –40 –60 –80 –100 –120 25 150–25 100

3752 G31

1750 125–50 50 75 RTAO = 73.2k, RTAS = 44.2k RTAO = 44.2k, RTAS = 73.2k ISENSEP Maximum Threshold vs COMP Extended Blanking Duration vs Junction Temperature AOUT to SOUT Delay (tAS) vs Junction Temperature AOUT to OUT Delay (tAO) and OUT to AOUT Delay (tOA) vs Junction Temperature ISENSEP Maximum Threshold – VSLP vs Duty Cycle (Programming Slope Compensation) OC Overcurrent (Hiccup Mode) Threshold vs Junction Temperature JUNCTION TEMPERATURE (°C) –75 OC OVERCURRENT THRESHOLD (mV) 110 105 100 25 150–25 100

3752 G27

1750 125–50 50 75 JUNCTION TEMPERATURE (°C) –75 tAO AND tCA (ns) 340 300 320 280 200 180 160 260 240 220 140 25 150–25 100

3752 G29

1750 125–50 50 75 RTAO = 73.2k tAO RTAO = 44.2k tOA tAO tOA COMP (V) 1.2 ISENSEP THRESHOLD (mV) 240 220 200 180 160 140 120 100 2.4 2.2

3752 G25

2.61.6 1.4 1.8 2 OC THRESHOLD DUTY CYCLE (%) ISENSEP MAXIMUM THRESHOLD - VSLOPE (V) 240 220 200 180 160 140 90 80

3752 G26

RISLP = 0/uni03A9 VSLP = I(ISENSEP) • RISLP RISLP = 1.5k/uni03A9 RISLP = 2k/uni03A9 JUNCTION TEMPERATURE (°C) –75 tAS (ns) 340 300 320 280 200 180 160 260 240 220 140 25 150–25 100

3752 G30

1750 125–50 50 75 RTAS = 73.2k RTAS = 44.2k JUNCTION TEMPERATURE (°C) –75 EXTENDED BLANKING DURATION (ns) 220 200 180 100 160 140 120 25 150–25 100

3752 G28

1750 125–50 50 75 RTBLNK = 73.2k RTBLNK = 14.7k

Rev. CFor more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICSTA = 25°C, unless otherwise noted. Required RIVSEC vs Switching Frequency (for DVSEC × 100 = 72.5%, UVLO_VSEC = 1.25V) OUT Pin Rise/Fall Times vs OUT Pin Load Capacitance OUT Maximum Duty Cycle Clamp VSEC) vs UVLO_VSEC SWITCHING FREQUENCY (kHz) 100 PROGRAMMED RIVSEC (k) 160 140 120 100 250 450 400

3752 G34

OUT PIN LOAD CAPACITANCE (nF) OUT PIN RISE/FALL TIMES (ns) 3 8 9 7

3752 G35

INTVCC = 12V (OVERDRIVEN FROM HOUSEKEEPING SUPPL Y) UVLO_VSEC (V) IDVSEC × 100 (%) 3.75 8.75 7.5

3752 G33

102.5 1.25 5 6.25 VIN = 12V RT = 24.9k (300kHz) RIVSEC = 51.1k PIN FUNCTIONS HFB (Pin 1): Housekeeping Supply Error Amplifier Inverting Input. HCOMP (Pin 2): Housekeeping Supply Error Amplifier Output and Compensation Pin. RT (Pin 3): A resistor to ground programs switching frequency. FB (Pin 4): Error Amplifier Inverting Input. COMP (Pin 5): Error Amplifier Output. Allows various compensation networks for nonisolated applications. SYNC (Pin 6): Allows synchronization of internal oscillator to an external clock. f SYNC equal to fOSC allowed. SS1 (Pin 7): Capacitor controls soft-start/stop of switch- ing frequency and volt-second clamp. During soft-stop it also controls the COMP pin. IVSEC (Pin 8): Resistor Programs OUT Pin Maximum Duty Cycle Clamp (D VSEC). This clamp moves inversely proportional to system input voltage to provide a volt- second clamp. UVLO_VSEC (Pin 9): A resistor divider from system in- put allows switch maximum duty cycle to vary inversely proportional with system input. This volt-second clamp prevents transformer saturation for duty cycles above 0%. Resistor divider ratio programs undervoltage lockout (UVLO) threshold. A 5µA pin current hysteresis allows programming of UVLO hysteresis. Pin below 0.4V reduces V IN currents to microamps. OVLO (Pin 10): A resistor divider from system input programs overvoltage lockout (OVLO) threshold. Fixed hysteresis included. T AO (Pin 11): A resistor programs nonoverlap timing between AOUT rise and OUT rise control signals. T AS (Pin 12): Resistors at TAO and TAS define delay between SOUT fall and OUT rise (= tAO – tAS). TOS (Pin 13): Resistor programs delay between OUT fall and SOUT rise. T BLNK (Pin 14): Resistor programs extended blanking of ISENSEP and OC signals during MOSFET turn-on. NC (Pins 15, 16, 37): No Connect Pins. These pins are not connected inside the IC. These pins should be left open. SS2 (Pin 17): Capacitor controls soft-start of COMP pin. Alternatively can connect to OPTO to communicate start of switching to secondary side. If unused, leave the pin open. GND (Pin 18): Analog Signal Ground. Electrical connection exists inside the IC to the exposed pad (Pin 39).

Rev. C For more information www.analog.com PGND (Pins 19, 38, 39): The Power Grounds for the IC. The package has an exposed pad (Pin 39) underneath the IC which is the best path for heat out of the package. Pin 39 should be soldered to a continuous copper ground plane under the device to reduce die temperature and increase the power capability of the L T3752/L T3752-1. I SENSEN (Pin 20): Negative input for the current sense comparator . Kelvin connect to the sense resistor in the source of the power MOSFET . ISENSEP (Pin 21): Positive input for the current sense comparator . Kelvin connect to the sense resistor in the source of the power MOSFET . A resistor in series with I SENSEP programs slope compensation. OC (Pin 22): An accurate 96mV threshold, independent of duty cycle, for detection of primary side MOSFET over- current and trigger of hiccup mode. Connect directly to sense resistor in the sour ce of the primary side MOSFET . Missing Pins 23, 25, 27, 29, 31, 33, 35: Pins removed for high voltage spacings and improved reliability. OUT (Pin 24): Drives the gate of an N-channel MOSFET between 0V and INTV CC. Active pull-off exists in shutdown. INTVCC (Pin 26): A linear regulator supply generated from VIN. L T3752 supplies 7V for AOUT , SOUT , OUT and HOUT gate drivers. L T3752-1 supplies 10V for AOUT ,SOUT , and OUT gate drivers (HOUT supplied from V IN). INTVCC must be bypassed with a 4.7µF capacitor to power ground. Can be externally driven by the housekeeping supply to remove power from within the IC. V IN (Pin 28): Input Supply Pin. Bypass with 1µF to ground. SOUT (Pin 30): Sync signal for secondary side synchro- nous rectifier controller . AOUT (Pin 32): Control signal for external active clamp switch. (P-channel L T3752, N-channel L T3752-1). HOUT (Pin 34): Drives the gate of an N-channel MOSFET used for the housekeeping supply. Active pull-off exists in shutdown. HI SENSE (Pin 36): Current sense input for the house keep- ing supply. Connect to sense resistor in the source of the power MOSFET . A resistor in series with HISENSE programs slope compensation. PIN FUNCTIONS

Rev. CFor more information www.analog.com BLOCK DIAGRAM PART SYSTEM INPUT MAX V IN PIN MAX VIN ON/OFF INTVCC UVLO(+)/(REG) AOUT PHASING L T3752 100V 100V 5.8V/5.5V 4.75V/7V for External PMOS L T3752-1 Limited Only by External Components 16V , 8mA (Internal VIN Clamp) 9.5V/7.6V 7V/10V for External NMOS + – 1.25V +– +– 1.25V (+) 1.215V (–) EN_SS1 UVLO_VSEC EN PGOOD HISLP OUT 0.4V 5µA 0.9mA SS1 > 1.25V HARD STOP VIN_ON VIN_OFF VIN SOFT STOP SS1 < 150mV 20µA (1 SHOT) UVLO_VSEC HFB 1.0V 1.25V HCOMP HOUSEKEEPING CONTROLLER HISENSE 79mV CLAMP HOUT 34 VIN OVLO10 IVSEC8 SYNC 100k RT3 SS2 SS1 FB COMP TAO TAS TOS TBLNK GND (+ EXPOSED PAD PIN 39) (+ EXPOSED PAD PIN 39) 14 18 PGND (19, 38) – + 1.25V REF HSS HISLP HICCUP 98mV ±0.7A ±0.4A ±0.4A ±2A 1.25V R OSC FOLD BACK ISLP 1.25V 150mV HARD STOP SOFT START SS2 1.25V SS1 EN_SS1 (0→220)mV SOFT STOP SS1 > 2.2V VSEC CLAMP TIMING LOGIC S Q S RQ S Q SS1 < 1.25V TJ > 170°C INTVCC_OV INTVCC_UV R INTVCC AOUTOFF ON 96mV OFF FG CG ON ACTIVE CLAMP CONTROL SYNCHRONOUS CONTROL MAIN SWITCH SOUT 30 OUT 24 OC 22 ISENSEP ISENSEN 3752 BD EA BLANK ISLP HICCUP (INVERT LEVEL FOR L T3752-1) CONTROL R S Q

• •
• • –VIN VIN –VOUT

3752 F02

Figure 1. L T3752 Timing Diagram Figure 2. Timing Reference Circuit

3752 F01

Figure 3. L T3752 Start-Up and Shutdown Timing Diagram

3752 F03

Figure 4. L T3752-1 Start-Up and Shutdown Timing Diagram

3752 F04

Rev. CFor more information www.analog.com OPERATION Introduction The L T3752/L T3752-1 are primary side, current mode, PWM controllers optimized for use in a synchronous forward converter with active clamp reset. Combined with an integrated housekeeping controller , each IC provides a compact, versatile, and highly efficient solution. The L T3752 allows V IN pin operation between 6.5V and 100V . For applications with system input voltages greater than 100V , the L T3752-1 allows RC start-up from input voltage levels limited only by external components. The L T3752 and L T3752-1 based forward converters are targeted for power levels up to 400W and are not intended for battery charger applications. For higher power levels the converter outputs can be stacked in series. Connecting UVLO_V SEC pins, OVLO pins, SS1 pins and SS2 pins together allows blocks to react simultaneously to all fault modes and conditions. Each IC contains an accurate programmable volt-second clamp. When set above the natural duty cycle of the con- verter , it provides a duty cycle guardrail to limit primary switch reset voltage and prevent transformer saturation during load transients. The accuracy and excellent line regulation of the volt-second clamp provides V OUT regu- lation for open-loop conditions such as no opto-coupler , reference or error amplifier on the secondar y side. For applications not requiring isolation but requiring high step-down ratios, each IC contains a voltage error ampli- fier to allow a very simple nonisolated, fully regulated synchronous for ward converter . The integrated housekeeping controller reduces the com- plexity and size of the main power transformer by avoid- ing the need for extra windings to create bias supplies. Secondar y side ICs no longer require start-up circuitry and can operate even when output voltage is 0V . A range of protection features include programmable overcurrent (OC) hiccup mode, programmable system input undervoltage lockout (UVLO), programmable system input overvoltage lockout (OVLO) and built-in thermal shutdown. Programmable slope compensation and switching frequency allow the use of a wide range of output inductor values and transformer sizes. L T3752 Part Start-Up L T3752 start-up is best described by referring to the Block Diagram and to the start-up waveforms in Figure 3. For part start-up, system input voltage must be high enough to drive the UVLO_V SEC pin above 1.25V and the VIN pin must be greater than 6.5V . An internal linear regulator is activated and provides a 7V INTV CC supply for all gate drivers. The housekeeping controller starts up before the forward controller . An internal soft-start (HSS) ramps the housekeeping HCOMP pin to allow switching at the gate driver output HOUT to drive an external N-channel MOSFET . The housekeeping controller output voltage V HK is regulated when the HFB pin reaches 1.0V . VHK can be used to override INTVCC to reduce power in the part, increase efficiency and to optimize the INTVCC level. Dur- ing start-up the housekeeping controller switches at the programmed switching frequency (f OSC) folded back by 1/4.6. The SS1 pin of the forward controller is allowed to start charging when V HK reaches 96% of its target value (PGOOD). When SS1 reaches 1.25V , the SS2 pin begins to charge, controlling COMP pin rise and the soft-start of output inductor peak current. The SS1 pin independently soft starts switching frequency and a volt-second clamp. As SS1 charges towards 2.6V the switching frequencies of both controllers remain equal, synchronized and soft started towards full-scale f OSC. If secondary side control already exists for soft starting the converter output voltage then the SS2 pin can still be used to control initial inductor peak current rise. Simply programming the primary side SS2 soft-start faster than the secondary side allows the secondary side to take over . If SS2 is not needed for soft-start control, its pull-down strength and voltage rating also allow it to drive the input of an opto-coupler connected to INTV CC. This allows the option of communicating to the secondary side that switching has begun. L T3752-1 Part Start-Up The L T3752-1 start-up of housekeeping supply and forward converter are similar to the L T3752 except for a small change in architecture and V IN pin level. L T3752-1 start-up is best described by referring to the Block Diagram and to

Rev. C For more information www.analog.com OPERATION the start-up waveforms in Figure 4. The L T3752-1 starts up by using a high valued resistor from system input to charge up the input capacitor at the V IN pin. If system input is already high enough to generate UVLO_V SEC above 1.25V , then the part turns on once VIN pin charges past VIN(ON) (9.5V). If system input is not high enough to generate UVLO_VSEC above 1.25V , the VIN pin charges towards system input until it reaches an internal 16V , 8mA clamp. The part turns on when system input becomes high enough to generate UVLO_V SEC above 1.25V . As the supply current of the part discharges the VIN capacitor a bootstrap supply must be generated to prevent V IN pin from falling below VIN(OFF) (7.6V). The L T3752-1 uses the housekeeping controller to provide the bootstrap bias to the V IN pin during RC start-up instead of waiting for the forward converter to also start. This meth- od is more efficient, requires a smaller VIN input capacitor and avoids the need for an auxiliary winding in the main transformer . The part’s low start-up current at the V IN pin allows the use of a large start-up resistor to minimize power loss from system input. The V IN capacitor value required for proper start-up is minimized by providing a large VIN(ON)- VIN(OFF) hysteresis, a low VIN IQ and a fast start-up time for the housekeeping controller . In contrast to the L T3752, the L T3752-1 housekeeping gate driver (HOUT) runs from the V IN pin instead of INTVCC. This avoids having to use cur- rent from the VIN pin to charge the INTVCC capacitor during initial start-up. This means the regulated 10V INTVCC on the L T3752-1 does not wake up until the housekeeping supply is valid. Start-up from this point is similar to the L T3752. The housekeeping supply and forward converter switch together with a soft-started frequency and volt-second clamp. The forward converter peak inductor current is also soft started similar to the L T3752.

3752 F05

Figure 5. Programming Undervoltage Lockout (UVLO) forward converter are shut down. below the micropower shutdown threshold of 0.6V(max). IN quiescent current after soft-stop is 165µA. 1.215V and allows the part to restart in soft-start mode.

Figure 6. Programming Overvoltage Lockout (OVLO)

3752 F07

Figure 7. Micropower Start-Up from High System Input

3752 F06

values until the charge-up time for CSTART is acceptable. CSTART value and hence a faster start-up time. RT pin. Table 1 shows typical fOSC vs RT resistor values. Table 1. RT vs Switching Frequency (fOSC) pin low level should fall below 0.6V for at least 100ns. Sensing and Programmable Slope Compensation).

1/x for an fSYNC/fOSC ratio of x. charge for the gate drivers. VCC level but not exceed 16V . threshold of 4.6V (6.8V for L T3752-1). as long as INTVCC remains above INTVCC UVLO(–) levels. INTVCC performance vs VIN and load current. and cost of the transformer . Figure 8. Housekeeping Supply

3752 F08

Rev. CFor more information www.analog.com APPLICATIONS INFORMATION Integrating the housekeeping controller saves cost and space and allows switching frequency to be inherently synchronized to the main forward converter . The housekeeping supply can be used to overdrive the INTV CC pin to take power outside of the part, improve efficiency, provide more drive current and optimize the INTV CC level. It can also be used as a bootstrap bias to the V IN pin as described in the section L T3752-1 Part Start-Up. The housekeeping supply also allows bias to any secondary side IC before the main forward converter starts switching. This removes the need for external start- up circuitry on the secondary side. Alternative methods involve powering secondary side ICs directly from the output voltage of the forward converter . This can cause issues depending on the minimum and maximum allowed input voltages for each IC. Housekeeping: Operation The L T3752/L T3752-1 housekeeping controller opera - tion is best described by referring to the Block Diagram and Figure 8. The housekeeping controller uses a ±0.7A gate driver at HOUT to control an external N-channel MOSFET . When current in the primary winding of the flyback transformer exceeds a level commanded by HCOMP and sensed at the HI SENSE pin, the duty cycle of the HOUT is terminated. Stored energy in the transformer is delivered to the output during the off time of HOUT . The housekeep- ing output voltage is programmed using a resistor divider to the HFB pin. A transconductance amplifier monitors the error signal between HFB pin and a 1.0V reference to control HCOMP level and hence peak switch current. A simple RC network from HCOMP pin to ground provides compensation. Over current protection exists for the exter- nal switch when 98mV is sensed at the HISENSE pin. This causes a low power hiccup mode (repeated retry cycles’ of shutdown followed by soft-start) until the overcurrent condition is removed. Housekeeping: Soft-Start/Shutdown During start-up of the L T3752/L T3752-1, the housekeeping controller has a built-in soft-start of approximately 2.2ms. The time will vary depending on the HCOMP level needed to achieve regulation. The housekeeping controller is shut down and the internal soft-start capacitor is discharged for any of the following conditions (typical values): (1) UVLO_VSEC < 1.25V (and SS1 < 0.15V) :Soft-Stop Shutdown (2) UVLO_VSEC < 0.4V :Micropower Shutdown (3) OVLO > 1.250V :System Input OVLO (4) HISENSE > 98mV :Housekeeping Over current (5) INTVCC < X, > 16.5V :INT VCC UVLO, OVLO (6) TJ > 170°C :Thermal Shutdown (7) VIN < Y :VIN Pin UVLO (X = 4.6V , Y = 5.5V for L T3752) (X = 6.8V , Y = 7.6V for L T3752-1) Housekeeping: Programming Output Voltage The output voltage, V HK, of the housekeeping controller is programmed using a resistor divider between VHK and the HFB pin (Figure 8) using the equation: VHK = 1V• 1+ R1 The HFB pin bias current is typically 85nA. Housekeeping: Programming Cycle-by-Cycle Peak Inductor Current and Slope Compensation The housekeeping controller limits cycle-by-cycle peak current in the external switch and primary winding of the flyback transformer by sensing voltage at a resistor HISENSE) connected in the source of the external N-chan- nel MOSFET (Figure 8). This sense voltage is compared to a sense threshold at the HI SENSE pin, controlled by HCOMP with an upper limit of 79mV . Since there is only one sense line from the positive terminal of the sense resistor , any parasitic resistance in ground side will increase its effec- tive value and reduce available peak switch current. For operation in continuous mode and above 50% duty cycle, required slope compensation can be programmed by adding a resistor R HISLP in series with the HISENSE pin. A ramped current always flows out of the HISENSE pin. The current starts from 2µA at 0% duty cycle and ramps to 52µA at 100% duty cycle. Minimize capacitance on this pin.

Rev. C For more information www.analog.com APPLICATIONS INFORMATION For a desired peak switch current, the value for RHISENSE should be calculated using a 30% derated 79mV sense threshold with the effects of slope compensation included: RHSENSE = 52.5mV – ∆VHSLP ILP(PEAK) where: ∆VHSLP = (2µA + D • (62.5µA) • RHISLP) ILP(PEAK) = cycle-by-cycle peak current in primary winding D = switch duty cycle R HISLP = slope compensation programming resistor If operating in continuous mode above 50% duty cycle, a good starting value for R HISLP is 499Ω which gives a 26mV total drop in current comparator threshold at 80% duty cycle. An f SYNC/fOSC ratio of x (1.0V < x < 1.25) will reduce the externally programmed slope compensation by a factor of 1.2x. If required, the external resistor R HISLP can be reprogrammed higher by a factor of 1.2x. Housekeeping: Adaptive Leading Edge Blanking Blanking of the HI SENSE signal on the leading edge of HOUT is adaptive to allow a wide range of MOSFETs. The blanking occurs from the start of HOUT rise and waits until HOUT has reached within 1V of its maximum level (INTV CC for L T3752, VIN for L T3752-1) before adding an additional fixed 100ns of blanking. Housekeeping: Overcurrent Hiccup Mode To protect the housekeeping controller during a short- to-ground fault on the housekeeping output voltage, a 98mV fixed overcurrent threshold exists at the HI SENSE pin to discharge the internal soft-start capacitor and enter a hiccup (retry) mode. This hiccup mode significantly reduces the average power in the external components compared to continued cycle-by-cycle switching at the 79mV threshold. Having already calculated the R HSENSE resistor for peak cycle-by-cycle current, the typical hiccup mode over current level in the switch and primary winding is given by: ILP(OVERCURRENT) = 98mV – ∆V HSLP RHSENSE where: ∆VHSLP = (2µA + D • (62.5µA) • RHISLP) D = switch duty cycle RHISLP = slope compensation programming resistor RHSENSE = current sense resistor Housekeeping: Output Overvoltage and Power Good The housekeeping controller monitors its supplies’ ris - ing output voltage V HK via the HFB pin and determines power good (PGOOD(+)) when V HK reaches 96% of its programmed value. 10µs after confirmation of PGOOD, the circuitry for the L T3752/L T3752-1 forward controller is activated. The SS1 pin is allowed to begin charging and eventually allows the forward converter to start switching. If V HK falls below 92% of its programmed level (PGOOD(–)), the SS1 pin is discharged and forward controller circuitry is disabled. To limit housekeeping output overvoltage, V HK, the house- keeping controller overrides it’s own regulation loop and immediately stops switching if its output voltage exceeds 20% of its programmed value. This is especially impor - tant when using the housekeeping supply to bias other ICs. The for ward controller is still allowed to switch. The housekeeping controller returns to normal regulation loop control when it’s output voltage, V HK, falls to less than 15% above it’s programmed value. Housekeeping: T ransformer Turns Ratio and Leakage Inductance The external resistor divider used to set the output voltage of the housekeeping supply provides a relative freedom in selecting the transformer turns ratio to suit a given

be considered for the breakdown rating of the MOSFET . circuit will be required to limit this spike. VCC = 7V (Regulated), HFB = 1.7V . VCC = 8V (Overdriven), HFB = 2V . Care should be taken not to exceed HFB = 3V . be used in a fully regulated forward converter application. to transformer input voltage. main power delivery in the forward converter (Figure 10). Figure 9. Adaptive Leading Edge Blanking Plus

3752 F09

3752 F10

• • L TC3752/L T3752-1 INTVCC COMP OUT OC ISENSEP FROM REGULATION LOOP ISENSEN GND

Figure 10. Current Sensing and Programmable increases M1 minimum on time (Figure 10). threshold at the ISENSEP pin, controlled by COMP pin level. RISLP can be reprogrammed higher by a factor of 1.2x.

ISLP used for slope compensation.

• 96mV RISENSE  – 1/2 IRIPPLE(P-P)( ) where: NP = forward transformer primary turns NS = forward transformer secondary turns IRIPPLE(P-P) = Output inductor peak-to-peak ripple current RISENSE should be programmed to allow maximum DC load current for the application plus enough margin during load transients to avoid overcurrent hiccup mode. Programming Maximum Duty Cycle Clamp: DVSEC (Volt-Second Clamp) Unlike other converters which only provide a fixed maxi- mum duty cycle clamp, the L T3752/L T3752-1 provide an accurate programmable maximum duty cycle clamp (DVSEC) on the OUT pin which moves inversely with system input. D VSEC provides a duty cycle guardrail to limit the volt-seconds-on product over the entire natural duty cycle range (Figures 11 and 12). This limits the drain voltage required for complete transformer reset. A resistor R IVSEC from the IVSEC pin to analog ground (Pin 18) programs DVSEC. DVSEC (OUT pin duty cycle clamp) = 0.725 • RIVSEC 51.1k
• fOSC 300
• 1.25 UVLO_V SEC where: RIVSEC = programming resistor at IVSEC pin fOSC = switching frequency (kHz) UVLO_VSEC = resistor divided system input voltage RIVSEC can program any D VSEC required at minimum system input. D VSEC will then follow natural duty cycle as V IN varies. Maximum programmable D VSEC is typi -

Figure 11. Volt-Second (DVSEC) Clamp

3752 F12

Figure 12. Programming DVSEC

3752 F11

Rev. C For more information www.analog.com APPLICATIONS INFORMATION cally 0.75 but may be further limited by the transformer design and voltage ratings of components connected to the drain of the primary side power MOSFET (SWP). See voltage calculations in the LO side and HI side active clamp topologies sections. If system input voltage falls below it's UVLO threshold the part will enter soft-stop with continued switching. The L T3752/L T3752-1 include an intelligent circuit which prevents D VSEC from continuing to rise as system input voltage falls (see Soft-Stop). Without this, too large a DVSEC would require extremely high reset voltages on the SWP node to properly reset the transformer . The UVLO_V SEC pin maximum operational level is the lesser of V IN – 2V or 12.5V . The L T3752/L T3752-1 volt-second clamp architecture is superior to an external RC network connected from system input to trip an internal comparator threshold. The RC method suffers from external capacitor error , part- to-part mismatch between the RC time constant and the IC’s switching period, the error of the internal comparator threshold and the nonlinearity of charging at low input voltages. The L T3752/L T3752-1 use the R IVSEC resistor to define the charge current for an internal timer capacitor to set an OUT pin maximum on-time, t ON(VSEC). The voltage across R IVSEC follows UVLO_V SEC pin voltage (divided down from system input voltage). Hence, RIVSEC current varies linearly with input supply. The L T3752/L T3752-1 also trim out internal timing capacitor and comparator threshold errors to optimize part-to-part matching between t ON(VSEC) and T . DVSEC Open Loop Control: No Opto-Coupler , Error Amplifier or Reference The accuracy of the programmable volt-second clamp (DVSEC) safely controls VOUT if open loop conditions exist such as no opto-coupler , error amplifier or reference on the secondary side. DVSEC controls the output of the converter by controlling duty cycle inversely proportional to system input. If D VSEC duty cycle guardrail is programmed X% above natural duty cycle, V OUT will only increase by X% if a closed loop system breaks open. This volt-second clamp is operational over a 10:1 system input voltage range. See D VSEC versus UVLO_V SEC pin voltage in the Typical Performance Characteristics section. RIVSEC: Open Pin Detection Provides Safety The L T3752/L T3752-1 provide an open-detection safety feature for the R IVSEC pin. If the R IVSEC resistor goes open circuit the part immediately stops switching. This prevents the part from running without the volt-second clamp in place. T ransformer Reset: Active Clamp Technique The L T3752/L T3752-1 include a ±0.4A gate driver at the AOUT pin to allow the use of an active clamp transformer reset technique (Figures 13, 17). The active clamp method improves efficiency and reduces voltage stress on the main power switch, M1. By switching in the active clamp capacitor only when needed, the capacitor does not lose its charge during M1 on-time. By allowing the active clamp capacitor , C CL, to store the average voltage required to reset the transformer , the main power switch sees lower drain voltage. An imbalance of volt-seconds will cause magnetizing cur- rent to walk upwards or downwards until the active clamp capacitor is charged to the optimal voltage for proper transformer reset. The voltage rating of the capacitor will depend on whether the active clamp capacitor is actively switched to ground (Figure 13) or actively switched to

3752 F14

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Figure 15. LO Side VCCL vs Duty Cycle Figure 14. Active Clamp Reset: Magnetizing Current and M1 Drain Voltage Figure 13. LO Side Active Clamp Topology

• • VD D1 R1 M2 M4M3 SWP OUT VIN –VIN VOUT –VOUT AOUT L T3752 FG L TXXXX CG

3752 F13

Figure 16. HI Side VCCL vs Duty Cycle

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Figure 17. HI Side Active Clamp Topology may require a larger margin to improve transient response. side to HI side active clamp topology.

• •
• • VD –VIN OUT VIN –VIN VOUT –VOUT AOUT L T3752-1 FG L TXXXX CG

3752 F17

Rev. CFor more information www.analog.com APPLICATIONS INFORMATION moment the active clamp capacitor is passively switched in to ground (due to the forward conduction of M2 body diode) and the drain voltage increases at a slower rate due to the loading of C CL. SWP above V IN causes I MAG to reduce from a positive value towards zero (dV SWP/dT = 0). As I MAG becomes negative it begins to discharge the SWP node. Switching in M2 before I MAG reverses, actively connects the bottom plate of CCL to ground and allows SWP to be discharged slowly. The resulting SWP waveform during M1 off-time appears as a square wave with a superimposed sinusoidal peak representing ripple voltage on C CL. The switch M2 experiences near zero voltage switching (ZVS) since only the body diode voltage drop appears across it at switch turn on. HI Side Active Clamp Topology (L T3752-1) For high input voltage applications the V DS rating of avail- able P-channel MOSFETs might not be high enough to be used as the active clamp switch in the LO side active clamp topology (Figure 13). An N-channel approach using the HI side active clamp topology (Figure 17) should be used. This topology requires a gate drive transformer or a simple gate drive opto-coupler to drive the N-channel MOSFET (M2) for switching in the active clamp capacitor from SWP to VIN. The M1 drain voltage calculation is the same as in the LO side active clamp case and M1 should be rated in a similar manner . The voltage across the clamp capacitor in the HI side architecture, however , is lower by V IN since it is referenced to VIN. The steady-state active clamp capacitor voltage V CCL to reset the transformer in a HI side active clamp topology can be approximated by: VCCL (HI side): (a) Steady state: VCCL = VRESET = VDS – VIN = D 1– D  •V IN = VIN •VOUT • N VIN – V OUT •N( ) (b) T ransient: During load transients, duty cycle and hence V CCL may increase. Replace D with DVSEC in the equation above to calculate transient V CCL values. D VSEC guardrail can be programmed as close as 6% higher than D but may require a larger margin to improve transient response. See the previous section Programming Duty Cycle Clamp–D VSEC. CCL should be rated for a voltage higher than the above steady-state calculation due to tolerances in duty cycle, load transients, voltage ripple on C CL and the effect of voltage coefficient on capacitance value. A typical choice for C CL is a good quality (X7R) capacitor . When using a gate drive transformer to provide control of the active clamp switch (M2), the external components C1, C2, R1, D1 and T4 are required. T4 size will increase for lower programmed switching frequencies due to a minimum volt-second requirement. Alternatively, a simple gate driver opto-coupler can be used as a switch to control M2, for a smaller solution size. The input supply capacitor for the gate drive opto-coupler is easily charged using the housekeep- ing supply of the L T3752-1. Common component values are shown in the T ypical Applications section. Active Clamp Capacitor Value and Voltage Ripple The active clamp capacitor value should be chosen based on the amount of voltage ripple which can be tolerated by components attached to SWP . Lower C CL values will create larger voltage ripple (increased drain voltage for the primary side power MOSFET) but will require less swing in magnetizing current to move the active clamp capacitor during duty cycle changes. Choosing too high a value for the active clamp capacitor (beyond what is needed to keep ripple voltage to an acceptable level) will require unneces- sary additional flux swing during transient conditions. For systems with flux swing detection, too high a value for the active clamp capacitor will trigger the detection system early and degrade transient response.

Rev. C For more information www.analog.com APPLICATIONS INFORMATION Another factor to consider is the resonance between CCL and the magnetizing inductance (LMAG) of the main transformer . An RC snubber (RS, CS) in parallel with CCL will dampen the sinusoidal ringing and limit the peak voltages at the primary side MOSFET drain during input/load transients. Check circuit performance to determine if the snubber is required. Component values can be approximated as: CCL (active clamp capacitance) = 10 LMAG

• (1– DMIN ) 2 • π • fOSC where, DMIN = (VOUT/VIN(MAX)) • NP/NS and (if needed), CS (snubber capacitance) = 6 • CCL RS (snubber resistance) = (1/(1-DMAX)) • √(LMAG/CCL) where, DMAX = ( VOUT/VIN(MIN)) • NP/NS Check the voltage ripple on SWP during steady-state operation. CCL voltage ripple can be estimated as: VCCL(RIPPLE) = VCCL • (1-D)2/(8 • CCL • LMAG • fOSC2) where, D = (VOUT/VIN) • (NP/NS) VCCL = VIN/(1-D) (Lo side active clamp topology) VCCL = D • VIN/(1-D) (Hi side active clamp topology) Example : For V IN = 36V , VOUT = 12V , NP/NS = 2, V CCL = 108V (Lo side active clamp topology), C CL = 22nF , LMAG = 100µH, fOSC = 250kHz, VCCL(RIPPLE) = 108(0.33)2/(8(22 The transformer is typically chosen to operate at a maximum flux density that is low enough to avoid excessive core losses. This also allows enough headroom during input and load transients to move the active clamp capacitor at a fast enough rate to keep up with duty cycle changes. Active Clamp MOSFET Selection The selection of active clamp MOSFET is determined by the maximum levels expected for the drain voltage and drain current. The active clamp switch (M2) in a either a lo side or hi side active clamp topology has the same BVdss requirements as the main N-channel power MOSFET . The current requirements are divided into two categories : (A) Drain Current This is typically less than the main N-channel power MOSFET because the active clamp MOSFET sees only magnetizing current, estimated as : Peak I MAG (steady state) = (1/2) • (N P/NS) • (V OUT/ LMAG) • (1/fOSC) where, LMAG = main transformer’s magnetizing inductance Example (L T3752) : For V OUT =12V , NP/NS = 2, f OSC = 250kHz and LMAG = 100µH, Peak IMAG = 0.48A. This value should be doubled for safety margin due to variations in L MAG, fOSC and transient conditions. (B) Body Diode Current The body diode will see reflected output current as a pulse every time the main N-channel power MOSFET turns off. This is due to residual energy stored in the transformer's leakage inductance. The body diode of the active clamp MOSFET should be rated to withstand a forward pulsed current of: ID(MAX) = (NS/NP) (IOUT(MAX) + (IL(RIPPLE)(P-P)/2)) where, IL(RIPPLE)(P-P) = output inductor ripple current = (VOUT/ (LOUT • fOSC)) • (1–(VOUT/VIN)(NP/NS)) IOUT(MAX) = maximum output load current

Rev. CFor more information www.analog.com APPLICATIONS INFORMATION Programming Active Clamp Switch Timing: AOUT to OUT (tAO) and OUT to AOUT (tOA) Delays The timings tAO and tOA represent the delays between AOUT and OUT edges (Figures 1 and 2) and are programmed by a single resistor , R TAO, connected from analog ground (Pin 18) to the TAO pin. Once tAO is programmed for the reasons given below, tOA will be automatically generated. Front-end timing tAO (M2 off, M1 on) = AOUT(edge)-to-OUT(rising) = 50ns + 3.8ns• RTAO  , 14.7k < R TAO < 125k In order to minimize turn-on transition loss in M1 the drain of M1 should be as low as possible before M1 turns on. To achieve this, AOUT should turn M2 off a delay of t AO before OUT turns M1 on. This allows the main transformer’s magnetizing current to discharge M1 drain voltage quickly towards V IN before M1 turns on. As SWP falls below VIN, however , the rectifying diodes on the secondary side are typically active and clamp the SWP node close to V IN. If enough leakage inductance exists, however , the clamping action on SWP by the secondary side will be delayed—potentially allowing the drain of M1 to be fully discharged to ground just before M1 turns on. Even with this delay due to the leakage inductance, L MAG needs to be low enough to allow IMAG to be negative enough to slew SWP down to ground before M1 turns on. If achievable, M1 will experience zero voltage switching (ZVS) for highest efficiency. As will be seen in a later sec- tion entitled Primary-Side Power MOSFET Selection, M1 transition loss is a significant contributor to M1 losses. Back-end timing tOA (M1 off, M2 on) is automatically generated = OUT(falling)-to-AOUT(edge) = 0.9 • tAO tOA should be checked to ensure M2 is not turned on until M1 and M3 are turned off. Programming Synchronous Rectifier Timing: SOUT to OUT (t SO) and OUT to SOUT (tOS) Delays The L T3752/L T3752-1 include a ±0.4A gate driver at the SOUT pin to send a control signal via a pulse transformer to the secondary side of the forward converter for syn - chronous rectification (see Figures 1 and 2). For the highest efficiency , M4 should be turned on whenever M1 is turned off. This suggests that SOUT should be a non- overlapping signal with OUT with very small non-overlap times. Inherent timing delays, however , which can vary from application to application, can exist between OUT to CSW and between SOUT to CG. Possible shoot-through can occur if both M1 and M4 are on at the same time, resulting in transformer and/or switch damage. Front-end timing: tSO (M4 off, M1 on) = SOUT(falling)-to-OUT(rising) delay = tSO = tAO – tAS = 3.8ns • (RTAS – RTAO) where: tAS = 50ns + (3.8ns • RTAS/1k) , 14.7k < RTAS < 125k, tAO = 50ns + (3.8ns • RTAO/1k), 14.7k < RTAO < 125k, tSO is defined by resistors RTAS and RTAO connected from analog ground (Pin 18) to their respective pins T AS and TAO. Each of these resistor defines a delay referenced to the AOUT edge at the start of each cycle. R TAO was already programmed based on requirements defined in the previous section Programming AOUT to OUT Delay. R TAS is then programmed as a delay from AOUT to SOUT to fulfill the equation above for tSO. By choosing RTAS less than or greater than RTAO, the delay between SOUT falling and OUT rising can be programmed as positive or nega- tive. While a positive delay can always be programmed for t SO, the ability to program a negative delay allows for improved efficiency if OUT(rising)-to-CSW(rising) delay is larger than SOUT(falling)-to-CG(rising) delay.

Rev. C For more information www.analog.com APPLICATIONS INFORMATION Back-end timing: tOS (M1 off, M4 on) = OUT (falling)-to-SOUT (rising) delay = tOS = 35ns + (2.2ns • RTOS/1k), 7.32k < RTOS < 249k The timing resistor , RTOS, defines the OUT (falling)-to-SOUT (rising) delay. This pin allows programming of a positive delay, for applications which might have a large inherent delay from OUT fall to SW2 fall. Soft-Start (SS1, SS2) The L T3752/L T3752-1 use SS1 and SS2 pins for soft starting various parameters (Figures 3, 4 and 18). SS1 soft starts internal oscillator frequency and D VSEC (maximum duty cycle clamp). SS2 soft starts COMP pin voltage to control output inductor peak current. Using separate SS1 and SS2 pins allows the soft-start ramp of oscillator frequency and D VSEC to be independent of COMP pin soft-start. Typically SS1 capacitor (CSS1) is chosen as 0.47µF and SS2 capaci- tor (CSS2) is chosen as 0.1µF . Soft-start charge currents are 11.5µA for SS1 and 21µA for SS2. SS1 is allowed to start charging (soft-start) if all of the following conditions exist (typical values) : (1) UVLO_VSEC > 1.25V: System input not in UVLO (2) OVLO < 1.215V: System input not in OVLO (3) HFB > 0.96V: Housekeeping supply valid (4) OC < 96mV: No over current condition (5) X < INTV CC < 16V: INTVCC valid (6) TJ < 165°C: Junction temperature valid (7) VIN > Y: VIN pin valid (X = 4.75V , Y = 5.8V for L T3752) (X = 7.0V , Y = 9.5V for L T3752-1) SS1 = 0V to 1.25V (no switching). This is the SS1 range for no switching for the forward converter . SS2 = 0V . SS1 > 1.25V allows SS2 to begin charging from 0V . SS1 = 1.25V to 2.45V (soft-start f OSC, DVSEC). This is the SS1 range for soft-starting fOSC and DVSEC folded back from 22% (50% for L T3752-1) to 100% of their programmed levels. Fold back of f OSC and D VSEC reduces effective minimum duty cycle for the primary side MOSFET . This allows inductor current to be controlled at low output voltages during start-up. SS1 ramp rate is chosen slow enough to ensure f OSC and DVSEC foldback lasts long enough for the converter to take control of inductor current at low output voltages. In ad- dition, slower SS1 ramp rate increases the non-switching period during an output short to ground fault (over current hiccup mode) to reduce average power dissipation (see Hard-Stop). SS2 = 0V to 1.6V (soft-start COMP pin). This is the SS2 range for soft-starting COMP pin from approximately 1V to 2.6V SS2 ramp rate is chosen fast enough to allow a (slower) soft-start control of COMP pin from a secondary side opto-coupler controller . SS1 soft-start non-switching period (0V to 1.25V) = 1.25V • C SS1/11.5µA SS1 soft-start f OSC, D VSEC period (1.25V to 2.45V) = 1.2V • CSS1/11.5µA SS2 soft-start COMP period (0V to 1.6V) = 1.6V • CSS2/21µA Soft-Stop (SS1) The L T3752/L T3752-1 gradually discharge the SS1 pin (soft-stop) when a system input UVLO occurs or when an external soft-stop shutdown command occurs (0.4V < UVLO_V SEC < 1.25V). During SS1 soft-stop the converter continues to switch, folding back fOSC, DVSEC and COMP pin voltage (Figures 3, 4 and 18). Soft-stop discharge current is 10.5µA for SS1. Soft-stop provides: 1) A ctive control of the secondary winding during output discharge for clean shutdown in self-driven applica- tions. (2) Controlled discharge of the active clamp capacitor t o minimize magnetizing current swing during restart.

Rev. CFor more information www.analog.com APPLICATIONS INFORMATION SS1: 2.45V to 1.25V (soft-stop fOSC, DVSEC, COMP). This is the SS1 range for soft-stop folding back of: (1) fOSC and DVSEC from 100% to 22% (50% for L T3752-1) of their programmed levels. 2) COMP pin (100% to 0% of commanded peak current). SS1 soft-stop fOSC , DVSEC, COMP period (2.45V to 1.25V) = 1.2V • CSS1/10.5µA SS1 < 1.25V . Forward converter stops switching and SS2 pin is discharged to 0V using 2.8mA. SS1 = 1.25V to 0V: When SS1 falls below 0.15V the internal SS1 latch is reset. If all faults are removed, SS1 begins charging again. If faults still remain, SS1 discharges to 0V . SS1 soft-stop non-switching period (1.25V to 0V) = 1.25V • C SS1/10.5µA DVSEC rises as system input voltage falls in order to provide a maximum duty cycle guardrail (volt-second clamp). When system input falls below it's UVLO thresh- old, however , this triggers a soft-stop with the converter continuing to switch. It is important that DVSEC no longer increases even though system input voltage may still be falling. The L T3752/L T3752-1 achieve an upper clamp on D VSEC by clamping the minimum level for the I VSEC pin to 1.25V . As SS1 pin discharges during soft-stop it folds back D VSEC. As DVSEC falls below the natural duty cycle of the converter , the converter loop follows DVSEC. If the system input voltage rises (I VSEC pin rises) during soft- stop the volt-second clamp circuit further reduces DVSEC. The I.C. chooses the lowest DVSEC commanded by either the IVSEC pin or the SS1 soft-stop function. Hard-Stop (SS1, SS2) Switching immediately stops and both SS1 and SS2 pins are rapidly discharged (Figure 18. Hard-Stop) if any of the following faults occur (typical values): (1) UVLO_V SEC < 0.4V: Micropower shutdown (2) OVLO > 1.250V: System input OVLO (3) HFB < 0.92V: Housekeeping supply UVLO (4) OC > 96mV: Over current condition (5) INTV CC < X(UVLO), > 16.5V (OVLO) (6) TJ > 170°C: Thermal shutdown (7) VIN < Y: VIN pin UVLO (X = 4.6V , Y = 5.5V for L T3752) (X = 6.8V , Y = 7.6V for L T3752-1) Switching stops immediately for any of the faults listed above. When SS1 discharges below 0.15V it begins charg- ing again if all faults have been removed. For an over cur- rent fault triggered by OC > 96mV , the disable of switching will cause the OC pin voltage to fall back below 96mV . This will allow SS1 and SS2 to recharge and eventually attempt switching again. If the over current condition still exists, OC pin will exceed 96mV again and the discharge/ charge cycle of SS1 and SS2 will repeat in a hiccup mode. The non-switching dead time period during hiccup mode reduces the average power seen by the converter in an over current fault condition. The dead time is dominated by SS1 recharging from 0.15V to 1.25V . Non-switching period in over current (hiccup mode): = 1.1V • C SS1/11.5µA OUT , AOUT , SOUT Pulse-Skipping Mode During load steps, initial soft-start, end of soft-stop or light load operation (if the forward converter is designed to operate in DCM), the loop may require pulse skipping on the OUT pin. This occurs when the COMP pin falls below its switching threshold. If the COMP pin falls below it's switching threshold while OUT is turned on, the L T3752/ L T3752-1 will immediately turn OUT off ; both AOUT and SOUT will complete their normal signal timings referenced from the OUT falling edge. If the COMP pin remains below it's switching threshold at the start of the next switching cycle, the L T3752/L T3752-1 will skip the next OUT pulse and therefore also skip AOUT and SOUT pulses. For AOUT control, this prevents the active clamp capacitor from be-

and/or causing reverse saturation of the transformer . ward FET and synchronous FET conduction. means the AOUT pin on time duration can be large. Figure 18. SS1, SS2 and COMP Pin Voltages During Faults, Soft-Start and Soft-Stop

3752 F18

Rev. CFor more information www.analog.com The selection of the main transformer will depend on the applications requirements : isolation voltage, power level, maximum volt-seconds, turns ratio, component size, power losses and switching frequency. T ransformer construction using the planar winding technol- ogy is typically chosen for minimizing leakage inductance and reducing component height. T ransformer core type is usually a ferrite material for high frequency applications. Find a family of transformers that meet both the isolation and power level requirements of the application. The next step is to find a transformer within that family which is suitable for the application. The subsequent thought pro- cess for the transformer design will include : (1) Secondar y turns (N S), core losses, temperature rise, flux density , switching frequency (2) Primar y turns (NP), maximum duty cycle and reset voltages (3) Copper losses The expression for secondary turns (NS) is given by, NS = 108 VOUT/(fOSC • AC • BM) where, AC = cross-sectional area of the core in cm2 BM = maximum AC flux density desired For flux density, choose a level which achieves an accept- able level of core loss/temperature rise at a given switching frequency . The transformer data sheet will provide curves of core loss versus flux density at various switching fre- quencies. The data sheet will also provide temperature rise versus core loss. While choosing a value for BM to avoid excessive core losses will usually allow enough headroom for flux swing during input / load transients, still make sure to stay well below the saturation flux density of the transformer core. If needed, increasing N S will reduce flux density. After calculating NS, the number of primary turns (NP) can be calculated from, NP = NS • DMAX VIN(MIN)/VOUT where, VIN(MIN) = minimum system input voltage DMAX = maximum switch duty cycle at VIN(MIN) (typically chosen between 0.6 and 0.7) At minimum input voltage the converter will run at a maxi- mum duty cycle D MAX. A higher transformer turns ratio (NP/NS) will create a higher D MAX but it will also require higher voltages at the drain of the primary side switch to reset the transformer (see previous sections Lo side Active Clamp Topology and Hi side Active Clamp Topology). D MAX values are typically chosen between 0.6 and 0.7. Even for a given D MAX value, the loop must also provide protection against duty cycles that may excessively exceed D MAX during transients or faults. While most converters only provide a fixed duty cycle clamp, the L T3752/L T3752-1 provide a programmable maximum duty cycle clamp D VSEC that also moves inversely with input voltage. The resulting function is that of a programmable volt- second clamp. This allows the user to choose a transformer turns ratio for D MAX and then customize a maximum duty cycle clamp D VSEC above D MAX for safety. D VSEC then follows the natural duty cycle of the converter as a safety guardrail (see previous section Programming Duty Cycle Clamp). After deciding on the particular transformer and turns ratio, the copper losses can then be approximated by, PCU = D • I(Load)(MAX)2 (RSEC + (NS/NP)2 RPRI) where, D = switch duty cycle (choose nominal 0.5) I(Load)(MAX) = maximum load current APPLICATIONS INFORMATION

Rev. C For more information www.analog.com RPRI = primary winding resistance RSEC = secondary winding resistance If there is a large difference between the core losses and the copper losses then the number of secondary turns can be adjusted to achieve a more suitable balance. The number of primary turns should then be recalculated to maintain the desired turns ratio. Primary-Side Power MOSFET Selection The selection of the primary-side N-channel power MOSFET M1 is determined by the maximum levels expected for the drain voltage and drain current. In addition, the power losses due to conduction losses, gate driver losses and transition losses will lead to a fine tuning of the MOSFET selection. If power losses are high enough to cause an unacceptable temperature rise in the MOSFET then several MOSFETs may be required to be connected in parallel. The maximum drain voltage expected for the MOSFET M1 follows from the equations previously stated in the active clamp topology sections: VDS (M1) = VIN2/(VIN – (VOUT • N)) The MOSFET should be selected with a BVDSS rating ap- proximately 20% greater than the above steady state VDS calculation due to tolerances in duty cycle, load transients, voltage ripple on C CL and leakage inductance spikes. A MOSFET with the lowest possible voltage rating for the application should be selected to minimize switch on re- sistance for improved efficiency. In addition, the MOSFET should be selected with the lowest gate charge to further minimize losses. MOSFET M1 losses at maximum output current can be approximated as : PM1 = PCONDUCTION + PGATEDRIVER + PTRANSITION (i) PCONDUCTION = (NP/NS) • (VOUT/VIN) • (NS/NP • IOUT(MAX))2 • RDS(ON) Note: The on resistance of the MOSFET , R DS(ON), in- creases with the MOSFET’s junction temperature. RDS(ON) should therefore be recalculated once junction tem - perature is known. A final value for RDS(ON) and therefore PCONDUCTION can be achieved from a few iterations. (ii) PGATEDRIVER = (QG • INTVCC • fOSC) where, QG = gate charge (VGS = INTVCC) (iii) PTRANSITION = PTURN_OFF + PTURN_ON (≈ 0 if ZVS) (a) P TURN_OFF = (1/2)I OUT(MAX) (NS/NP)(VIN/1-D) (QGD/IGATE) • fOSC where, QGD = gate to drain charge IGATE = 2A source/sink for OUT pin gate driver (b) PTURN_ON = (1/2)IOUT(MAX)(NS/NP)(VDS)(QGD/IGATE)

• fOSC where, VDS = M1 drain voltage at the beginning of M1 turn on VDS typically sits between VIN and 0V (ZVS) During programmable timing tAO, negative IMAG discharges M1 drain SWP towards VIN (Figure 1). ZVS is achieved if enough leakage inductance exists—to delay the second- ary side from clamping M1 drain to V IN—and if enough energy is stored in LMAG to discharge SWP to 0V during that delay. (see Programming Active Clamp Switch Timing: AOUT to OUT (t AO)). Synchronous Control (SOUT) The L T3752 / L T3752-1 use the SOUT pin to communicate synchronous control information to the secondary side synchronous rectifier controller (Figure 19). The isolating transformer (T SYNC), coupling capacitor (CSYNC) and resis- tive load (RSYNC) allow the ground referenced SOUT signal to generate positive and negative signals required at the SYNC input of the secondary side synchronous rectifier controller . For the typical L T3752/L T3752-1 applications operating with an L T8311, C SYNC is 220pF , RSYNC is 560Ω and TSYNC is typically a PULSE PE-68386NL. APPLICATIONS INFORMATION

LT3752-1 timing resistors RTAS, RTOS (leave open). Current Sensing and Programmable Slope Compensation). chosen to be 40% of IOUT(MAX). voltage excursions during load steps. Figure 19. SOUT Pulse T ransformer

3752 F19

Rev. C For more information www.analog.com A small 1µF bypass capacitor should also be placed close to the IC between VIN and GND. As input voltage levels increase, any use of bulk capacitance to minimize input ripple can impact on solution size and cost. In addition, inputs with higher source impedance will cause an increase in voltage ripple. In these applications it is recommended to include an LC input filter . The output impedance of the input filter should remain below the negative input impedance of the DC/DC forward converter . PCB Layout / Thermal Guidelines For proper operation, PCB layout must be given special attention. Critical programming signals must be able to co-exist with high dv/dt signals. Compact layout can be achieved but not at the cost of poor thermal management. The following guidelines should be followed to approach optimal performance. 1. Ensure that a local bypass capacitor is used (and placed as close as possible) between V IN and GND for the controller IC(s). 2. The critical programming resistors for timing (pins TAO,TAS,TOS,TBLNK, IVSEC and RT) must use short traces to each pin. Each resistor should also use a short trace to connect to a single ground bus specifically connected to pin 18 of the IC (GND). 3. The current sense resistor for the forward converter must use short Kelvin connections to the I SENSEP and ISENSEN pins. The current sense resistor for the housekeeping supply should have it’s ground connection as close as possible to the power ground (PGND) pin 38. 4. High dv/dt lines should be kept away from all timing resistors, current sense inputs, HCOMP/COMP pins, UVLO_VSEC/OVLO pins and both HFB and FB feedback traces. 5. Gate driver traces (HOUT , AOUT , SOUT , OUT) should be kept as short as possible. 6. When working with high power components, multiple parallel components are the best method for spread - ing out power dissipation and minimizing temperature rise. In particular , multiple copper layers connected by vias should be used to sink heat away from each power MOSFET . 7. Keep high switching current PGND paths away from signal ground. Also minimize trace lengths for those high current switching paths to minimize parasitic inductance. APPLICATIONS INFORMATION

Figure 20. 18V to 72V , 12V/12.5A, 150W Active Clamp Isolated Forward Converter

3752 F20a

• •
• •• 4.7µF 100V VIN 18V TO 72V GND OVLO HFB C28 68pF LOAD CURRENT (A) EFFICIENCY (%) 6 3

3752 F20b

Rev. C For more information www.analog.com TYPICAL APPLICATIONS 18V to 72V , 12V/12.5A, 150W No-Opto, Active Clamp Isolated Forward Converter VOUT vs Load Current (No-Opto) Efficiency vs Load Current 49.9k 22.6k 1.82k 7.32k 34k 60.4k 31.6k R10 2.8k R11 10k T1: CHAMPS G45AH2-0404-04 T2: BH ELECTRONICS L00-3250 T3: PULSE PE-68386NL L1: CHAMPS PQI2050-6R8 D1, D2, D3: BAS516 D4: CENTRAL SEMI CMMR1U-02 R13 560/uni03A9 V AUX VAUX SYNC VIN GND FBL T8311PGOOD R14 2k R15 0.006/uni03A9 R16 10k R18 0.15/uni03A9 R17 499/uni03A9 C10 2.2µF 2.2µF INTV CC VAUX M5 ZVN4525E6 BSC077N12NS3 FDMS86101 R12 1.1k 2.2nF 0.33µF 22nF 22nF 4.7µF C11 2.2µF C13 22µF 16V V OUT 12V 12.5A C14 470µF 16V C12 4.7µF

3752 TA02

5.9k 100k UVLO_VSEC L T3752 SYNC 100nF 15nF 4:4 R20 499k 6.8µHCSN FG FSW CG CSW R21 100/uni03A9 R22 100/uni03A9

• •
• •• 4.7µF 100V VIN 18V TO 72V GND OVLO HFB Si2325DS BSC077N12NS3 C24 2.2nF 250V R38 20k LOAD CURRENT (A) VOUT (V) 14.0 13.5 13.0 12.5 12.0 11.0 10.5 11.5 10.0 4 2

3752 TA02a

VIN = 70V VIN = 60V VIN = 48V VIN = 36V VIN = 20V LOAD CURRENT (A) EFFICIENCY (%) 6 3

3752 TA02b

Rev. CFor more information www.analog.com TYPICAL APPLICATIONS 150V to 400V , 12V/16.7A, 200W Active Clamp Isolated Forward Converter Efficiency vs Load Current 95.3k 40.2k 2.94k 13k 100k 124k 78.7k R23 22k R24 22k R10 22k R11 10k T1: CHAMPS L T80R2-12AC-3124005 T2: WÜRTH 750817020 T3: PULSE PE-68386NL L1: COILCRAFT AGP2923-153 D1: CENTRAL SEMI CMR1U-10 D2, D3, D5: BAS516 D4: CENTRAL SEMI CMMR1U-02 R13 560/uni03A9 R28 3.16k R27 100k VAUX SYNC VIN GND FBL T8311PGOOD R14 2k R15 0.022/uni03A9 R18 0.15/uni03A9 R17 499/uni03A9 R35 374k R36 374k C10 4.7µFC9 10µF INTV CC VAUX INTVCC BSP300 IPD65R25OC6 IPD60R1K4C6 R25 100/uni03A9 R12 806/uni03A9 R26 1.2k 2.2nF 0.47µF 0.22µF PS2801-1 3.3nF 4.7µF C11 2.2µF C13 33µF 16V C24 10nF 250V V OUT 12V 16.7A C14 330µF 16V C12 4.7µF C17 1µF

3752 TA03

1µF TAO TAS TOS TBLNK IVSEC RT SS1 SS2 HCOMP FB COMP OPTO INTVCC VAUX TIMER SS COMP CSP PMODE INTVCC INTVCC SOUT ISENSEN ISENSEP OUTVIN AOUTHISENSEHOUT OC 5.76k 499k R34 499k UVLO_VSEC L T3752-1 SYNC RJK0653DPB 31:5 C20 10µF FDMS86200 R20 432k R29 5.11k 15µH R30 100k R31 11.3k CSN FG FSW CG CSW R21 100/uni03A9 R22 100/uni03A9 R38 10k R38 0.002 C27 120pF

• •
• • R16 4.2/uni03A9C1 2.2µF 630V VIN 150V TO 400V GND OVLO HFB CATHODE ANODE ACPL-W346 VEE VOUT VCC C21 0.22µF 47nF 630V C15 10nF 630V R19 402/uni03A9 C28 68pF LOAD CURRENT (A) EFFICIENCY (%) 5 2.5

3752 TA03a

17.510 12.5 157.5 VIN = 150V VIN = 250V VIN = 350V VIN = 400V

Rev. C For more information www.analog.com TYPICAL APPLICATIONS 150V to 400V , 12V/16.7A, 200W No-Opto, Active Clamp Isolated Forward Converter VOUT vs Load Current (No-Opto) Efficiency vs Load Current 95.3k 40.2k 2.94k 13k 100k 107k 78.7k R10 22k R11 10k T1: CHAMPS L T80R2-12AC-3124005 T2: WÜRTH 750817020 T3: PULSE PE-68386NL L1: COILCRAFT AGP2923-153 D1: CENTRAL SEMI CMR1U-10 D2, D3, D5: BAS516 D4: CENTRAL SEMI CMMR1U-02 R13 560/uni03A9 V AUX SYNC VIN GND FBL T8311PGOOD R14 2k R15 0.022/uni03A9 R18 0.15/uni03A9 R17 499/uni03A9 R35 374k R36 374k C10 4.7µFC9 10µF INTV CC VAUX INTVCC BSP300 IPD65R25OC6 IPD60R1K4C6 R12 806/uni03A9 2.2nF 0.47µF 0.22µF 3.3nF 4.7µF C11 2.2µF C13 33µF 16V V OUT 12V 16.7A C14 330µF 16V C12 4.7µF V AUX

3752 TA04

5.76k 499k R34 499k UVLO_VSEC L T3752-1 SYNC RJK0653DPB 31:5 C20 10µF FDMS86200 R20 432k 15µHCSN FG FSW CG CSW

• •
• • ACPL-W346 R16 4.2/uni03A9C1 2.2µF 630V VIN 150V TO 400V GND OVLO HFB CATHODE ANODE VEE VOUT VCC C21 0.22µF 47nF 630V C15 10nF 630V R19 402/uni03A9 R38 0.002 R21 100/uni03A9 R22 100/uni03A9 C27 120pF C24 10nF 250V D4 R38 10k LOAD CURRENT (A) VOUT (V) 14.0 13.5 13.0 12.5 12.0 11.5 10.0 11.0 10.5 4 2

3752 TA04a

VIN = 150V VIN = 250V VIN = 350V VIN = 400V LOAD CURRENT (A) EFFICIENCY (%) 5 2.5

3752 TA04b

17.510 12.5 157.5 VIN = 150V VIN = 250V VIN = 350V VIN = 400V

Rev. CFor more information www.analog.com TYPICAL APPLICATIONS 150V to 400V , 12V/16.7A, 200W , Active Clamp Isolated Forward Converter (Using Gate Drive T ransformer for High Side Active Clamp) Efficiency vs Load Current 95.3k 40.2k 2.94k 13k 100k 124k 78.7k R23 22k R24 22k R10 22k R11 10k T1: CHAMPS L T80R2-12AC-3124005 T2: WÜRTH 750817020 T3: PULSE PE-68386NL T4: ICE GT05-111-100 L1: COILCRAFT AGP2923-153 D1: CENTRAL SEMI CMR1U-10 D2, D3, D5: BAS516 D4: CENTRAL SEMI CMMR1U-02 R13 560/uni03A9 R28 3.16k R27 100k VAUX SYNC VIN GND FBL T8311PGOOD R14 2k R15 0.022/uni03A9 R18 0.15/uni03A9 R16 10k C23 3.3nFR17 499/uni03A9 R35 374k C22 220nF R37 100/uni03A9 R36 374k C10 4.7µFC9 10µF INTV CC VAUX C21 470pF BSP300 D3T2 IPD65R25OC6 IPD60R1K4C6 R25 100/uni03A9 R12 806k R26 1.2k 2.2nF 0.47µF 0.22µF PS2801-1 3.3nF 4.7µF C11 2.2µF C13 33µF 16V V OUT 12V 16.7A C14 330µF 16V C12 4.7µF V AUX C17 1µF

3752 TA05

1µF TAO TAS TOS TBLNK IVSEC RT SS1 SS2 HCOMP FB COMP OPTO INTVCC TIMER SS COMP CSP PMODE INTVCC INTVCC SOUT ISENSEN ISENSEP OUTVIN AOUTHISENSEHOUT OC 5.76k 499k R34 499k UVLO_VSEC L T3752-1 SYNC RJK0653DPB 31:5 C20 10µF FDMS86200 R20 432k R29 5.11k 15µH R30 100k R31 11.3k CSN FG FSW CG CSW

• •
• • 2.2µF 630V VIN 150V TO 400V GND OVLO HFB 47nF 630V C15 10nF 630V R19 402/uni03A9
• • R21 100/uni03A9 R22 100/uni03A9 R38 0.002 C27 120pF C24 10nF 250V D4 R38 10k C28 68pF LOAD CURRENT (A) EFFICIENCY (%) 5 2.5

3752 TA05a

17.510 12.5 157.5 VIN = 150V VIN = 250V VIN = 350V VIN = 400V

Rev. C For more information www.analog.com TYPICAL APPLICATIONS 150V to 400V , 12V/16.7A 200W , No-Opto, Active Clamp Isolated Forward Converter (Using Gate Drive T ransformer for High Side Active Clamp) VOUT vs Load Current (No-Opto) Efficiency vs Load Current 95.3k 40.2k 2.94k 13k 100k 107k 78.7k R10 22k R11 10k T1: CHAMPS L T80R2-12AC-3124005 T2: WÜRTH 750817020 T3: PULSE PE-68386NL T4: ICE GT05-111-100 L1: COILCRAFT AGP2923-153 D1: CENTRAL SEMI CMR1U-10 D2, D3, D5: BAS516 D4: CENTRAL SEMI CMMR1U-02 R13 560/uni03A9 V AUX SYNC VIN GND FBL T8311PGOOD R14 2k R15 0.022/uni03A9 R18 0.15/uni03A9 R16 10k C23 3.3nFR17 499/uni03A9 R35 374k C22 220nF R37 100/uni03A9 R36 374k C10 4.7µFC9 10µF INTV CC VAUX C21 470pF BSP300 D3T2 IPD65R25OC6 IPD60R1K4C6 R12 806/uni03A9 2.2nF 0.47µF 0.22µF 3.3nF 4.7µF C11 2.2µF C13 33µF 16V V OUT 12V 16.7A C14 330µF 16V C12 4.7µF

3752 TA06

5.76k 499k R34 499k UVLO_VSEC L T3752-1 SYNC RJK0653DPB 31:5 C20 10µF FDMS86200 R20 432k 15µHCSN FG FSW CG CSW

• •
• • 2.2µF 630V VIN 150V TO 400V GND OVLO HFB 47nF 630V C15 10nF 630V R19 402/uni03A9
• • R21 100/uni03A9 R38 0.002/uni03A9 R22 100/uni03A9 C27 120pF C24 10nF 250V D4 R38 10k LOAD CURRENT (A) VOUT (V) 14.0 13.5 13.0 12.5 12.0 11.5 10.0 11.0 10.5 4 2

3752 TA06a

VIN = 150V VIN = 250V VIN = 350V VIN = 400V LOAD CURRENT (A) EFFICIENCY (%) 5 2.5

3752 TA06b

17.510 12.5 157.5 VIN = 150V VIN = 250V VIN = 350V VIN = 400V

Rev. CFor more information www.analog.com TYPICAL APPLICATIONS 75V to 150V , 24V/14A 340W Active Clamp Isolated Forward Converter (Using Gate Drive T ransformer for High Side Active Clamp) Efficiency vs Load Current 93.1k 53k 5.76k 10k 80.1k 82.5k 52.3k R23 22k R24 22k R10 22k R11 10k T1: CHAMPS L T80R2-12AC-1006 T2: WÜRTH 750817020 T3: PULSE PE-68386NL T4: ICE GT05-111-100 L1: COILCRAFT AGP2923-153 D1: CENTRAL SEMI CMR1U-10 D2, D3, D5: BAS516 D4: CENTRAL SEMI CMMR1U-02 R13 560/uni03A9 R28 3.16k R27 100k VAUX SYNC VIN GND FBL T8311PGOOD R14 2k R15 0.0075/uni03A9 R18 0.15/uni03A9 R16 10k C23 3.3nFR17 499/uni03A9 R35 102k C22 220nF R37 100/uni03A9 R36 102k C10 4.7µFC9 10µF INTV CC VAUX C21 470pF BSP300 D3T2 IPB200N25N3 IRFL214 R25 100/uni03A9 R12 806/uni03A9 R26 1.2k 2.2nF 0.47µF 0.22µF PS2801-1 3.3nF 4.7µF C11 2.2µF C13 22µF 25V V OUT 24V 14A C14 470µF 25V C12 4.7µF C17 0.33µF VAUX

3752 TA07

1µF TAO TAS TOS TBLNK IVSEC RT SS1 SS2 HCOMP FB COMP OPTO INTVCC TIMER SS COMP CSP PMODE INTVCC INTVCC SOUT ISENSEN ISENSEP OUTVIN AOUTHISENSEHOUT OC 6.04k 6.98k R34 698k UVLO_VSEC L T3752-1 SYNC BSC047N08NS3 10:6 C20 10µF IPB072N15N3G R20 365k R29 5.11k 15µH R30 100k R31 5.36k CSN FG FSW CG CSW

• •
• • 2.2µF 250V VIN 75V TO 150V GND OVLO HFB 15nF 250V C15 4.7nF 250V R19
• • R21 100/uni03A9 R22 100/uni03A9 R38 0.003/uni03A9 C27 120pF C24 10nF 250V D4 R38 10k C28 68pF LOAD CURRENT (A) EFFICIENCY (%) 2.5

3752 TA07a

157.5 10 12.55 VIN = 75V VIN = 100V VIN = 125V VIN = 150V

Rev. C For more information www.analog.com PACKAGE DESCRIPTION 4.75 (.187) REF FE38 (AB) TSSOP REV B 0910 0.09 – 0.20 (.0035 – .0079) 0° – 8° 0.25 REF 0.50 – 0.75 (.020 – .030) 4.30 – 4.50* (.169 – .177) 1 19 PIN NUMBERS 23, 25, 27, 29, 31, 33 AND 35 ARE REMOVED REF 9.60 – 9.80* (.378 – .386) 1.20 (.047) MAX 0.05 – 0.15 (.002 – .006) 0.50 (.0196) BSC 0.17 – 0.27 (.0067 – .0106) TYP RECOMMENDED SOLDER PAD LAYOUT 0.315 ±0.05

0.50 BSC

4.50 REF

6.60 ±0.10 1.05 ±0.10

4.75 REF

2.74 REF

2.74 (.108) MILLIMETERS (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE SEE NOTE 4 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT 6.40 (.252) BSC 38-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1665 Rev B) Exposed Pad Variation AB

Rev. CFor more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. REV DATE DESCRIPTION PAGE NUMBER A 06/14 Minor typographical changes throughout data sheet. All B 07/15 Changed Absolute Maximum SS2 rating to 16V . Changed Absolute Maximum SS1 rating to 3V . Changed Output Low Level in Shutdown conditions to INTVCC = 3V . Changed AOUT Rise and Fall Times. Changed SOUT Rise and Fall Times. Changed SS2 Discharge Current conditions to SS2 = 2.5V . Changed SS2 Charge Current conditions to SS2 = 1.5V . Changed HOUT Rise and Fall Times. C 06/19 Added AEC-Q100 Qualification and W Flow Part Numbers 1, 3, 4

Rev. C For more information www.analog.com www.analog.com  ANALOG DEVICES, INC. 2014–2019 RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS L T8311 Preactive Secondary Synchronous and Opto Control for Forward Converters Optimized for Use with Primary-Side L T3752/-1, L T3753 and L T8310 Controllers L TC3765/L TC3766 Synchronous No-Opto Forward Controller Chip Set with Active Clamp Reset Direct Flux Limit, Supports Self Starting Secondary Forward Control L TC3722/L TC3722-2 Synchronous Full Bridge Controllers Adaptive or Manual Delay Control for Zero Voltage Switching, Adjustable Synchronous Rectification Timing L T3748 100V Isolated Flyback Controller 5V ≤ V IN ≤ 100V , No Opto Flyback , MSOP-16 with High Voltage Spacing L T3798 Off-Line Isolated No-Opto Flyback Controller with Active PFC V IN and VOUT Limited Only by External Components 75V to 150V , 24V/14A 340W No-Opto, Active Clamp Isolated Forward Converter Efficiency vs Load CurrentVOUT vs Load Current (No-Opto) 93.1k 53k 5.76k 10k 80.1k 75k 52.3k R10 22k R11 10k T1: CHAMPS L T80R2-12AC-1006 T2: WÜRTH 750817020 T3: PULSE PE-68386NL T4: ICE GT05-111-100 L1: COILCRAFT AGP2923-153 D1: CENTRAL SEMI CMR1U-10 D2, D3, D5: BAS516 D4: CENTRAL SEMI CMMR1U-02 R13 560/uni03A9 V AUX SYNC VIN GND FBL T8311PGOOD R14 2k R15 0.0075/uni03A9 R18 0.15/uni03A9 R16 10k C23 3.3nFR17 499/uni03A9 R35 C22 220nF R37 100/uni03A9 R36 C10 4.7µFC9 10µF INTV CC VAUX C21 470pF BSP300 D3T2 IPB200N25N3 IRFL214 R12 806/uni03A9 2.2nF 0.47µF 0.1µF 3.3nF 4.7µF C11 2.2µF C13 22µF 25V V OUT 24V 14A C14 470µF 25V C12 4.7µF

3752 TA08

6.04k 6.98k R34 698k UVLO_VSEC L T3752-1 SYNC BSC047N08NS3 10:6 C20 10µF IPB072N15N3G R20 432k L1, 15µH CSN FG FSW CG CSW

• •
• • 2.2µF 250V VIN 75V TO 150V GND OVLO HFB 15nF 250V C15 4.7nF 250V R19
• • R21 100/uni03A9 R38 0.003/uni03A9 R22 100/uni03A9 C27 120pF C24 10nF 250V D4 R38 10k LOAD CURRENT (A) VOUT (V)

3752 TA08a

VIN = 75V VIN = 100V VIN = 125V VIN = 150V LOAD CURRENT (A) EFFICIENCY (%) 2.5

3752 TA08b

157.5 10 12.55 VIN = 75V VIN = 100V VIN = 125V VIN = 150V