LT3751 - High Voltage Capacitor Charger Controller with Regulation
Document overview
- Manufacturer or author: Analog Devices
- PDF pages: 34
Technical content
3751fdFor more information www.linear.com/LT3751 TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
Charger Controller with Regulation The LT®3751 is a high input voltage capable flyback con- troller designed to rapidly charge a large capacitor to a user-adjustable high target voltage set by the transformer turns ratio and three external resistors. Optionally, a feed- back pin can be used to provide a low noise high voltage regulated output. The LT3751 has an integrated rail-to-rail MOSFET gate driver that allows for efficient operation down to 4.75V. A low 106mV differential current sense threshold volt - age accurately limits the peak switch current. Added pro- tection is provided via user-selectable overvoltage and undervoltage lockouts for both VCC and VTRANS. A typical application can charge a 1000µF capacitor to 500V in less than one second. The CHARGE pin is used to initiate a new charge cycle and provides ON/OFF control. The DONE pin indicates when the capacitor has reached its programmed value and the part has stopped charging. The FAUL T pin indicates when the LT3751 has shut down due to either V CC or VTRANS voltage exceeding the user-programmed supply tolerances. n Charges Any Size Capacitor n Low Noise Output in Voltage Regulation Mode n Stable Operation Under a No-Load Condition n Integrated 2A MOSFET Gate Driver with Rail-to-Rail Operation for V CC ≤ 8V n Selectable 5.6V or 10.5V Internal Gate Drive Voltage Clamp n User-Selectable Over/Undervoltage Detect n Easily Adjustable Output Voltage n Primary or Secondary Side Output Voltage Sense n Wide Input VCC Voltage Range (5V to 24V) n Available in 20-Pin QFN 4mm × 5mm and 20-Lead TSSOP Packages n High Voltage Regulated Supply n High Voltage Capacitor Charger n Professional Photoflash Systems n Emergency Strobe n Security/Inventory Control Systems n Detonators CHARGE CLAMP VCC DONE FAUL T UVLO1 OVLO1 UVLO2 OVLO2 RDCM RV OUT HVGATE LVGATE CSP CSN FB RVTRANS 1:10 D1 500V
0 TO 150mA
10µF
3751 TA01a
DANGER HIGH VOL TAGE! OPERATION BY HIGH VOL TAGE TRAINED PERSONNEL ONL Y GND RBG 40.2k OFF ON 330µF ×2VCC 24V 10µF 18.2k 40.2k 6m/uni03A9 100µF 715k 1.74k10nF 732/uni03A9 VTRANS VCC TO MICRO 0.47µF 374k 475k 475k 374k LOAD CURRENT (mA) OUTPUT VOL TAGE (V) EFFICIENCY (%) 500 498 494 496 492 490 10050
3751 TA01b
Load Regulation and Efficiency All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents including 6518733 and 6636021.
3751fd For more information www.linear.com/LT3751 ABSOLUTE MAXIMUM RATINGS V V HV te 9 F C A C (Note 1) ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3751EFE#PBF LT3751EFE#TRPBF LT3751FE 20-Lead Plastic TSSOP –40°C to 125°C LT3751IFE#PBF LT3751IFE#TRPBF LT3751FE 20-Lead Plastic TSSOP –40°C to 125°C LT3751EUFD#PBF LT3751EUFD#TRPBF 3751 20-Pin (4mm × 5mm) Plastic QFN –40°C to 125°C LT3751IUFD#PBF LT3751IUFD#TRPBF 3751 20-Pin (4mm × 5mm) Plastic QFN –40°C to 125°C LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3751EFE LT3751EFE#TR LT3751FE 20-Lead Plastic TSSOP –40°C to 125°C LT3751IFE LT3751IFE#TR LT3751FE 20-Lead Plastic TSSOP –40°C to 125°C LT3751EUFD LT3751EUFD#TR 3751 20-Pin (4mm × 5mm) Plastic QFN –40°C to 125°C LT3751IUFD LT3751IUFD#TR 3751 20-Pin (4mm × 5mm) Plastic QFN –40°C to 125°C Consult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. A A A 5°C Operating Temperature Range (Note 2).. –40°C to 125°C C to 150°C FE PACKAGE 20-LEAD PLASTIC TSSOP TOP VIEW RV TRANS UVLO1 OVLO1 UVLO2 OVLO2 FAULT DONE CHARGE CLAMP FB RDCM NC RV OUT NC RBG HVGATE LVGATE V CC CSP CSN TJMAX = 125°C, θJA = 38°C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB 20 19 18 17 7 8 TOP VIEW UFD PACKAGE 20-PIN (4mm × 5mm) PLASTIC QFN 9 10 16OVLO1 UVLO2 OVLO2 FAULT DONE CHARGE RV OUT NC RBG HVGATE LVGATE V CC UVLO1 RV TRANS NC RDCM CLAMP FB CSN CSP TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 21) IS GND, MUST BE TIED TO PCB PIN CONFIGURATION http://www.linear.com/product/LT3751#orderinfo
3751fdFor more information www.linear.com/LT3751 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = CHARGE = 5V, CLAMP = 0V, unless otherwise noted. Individual 25kΩ resistors tied from 5V VTRANS supply to RVTRANS, RVOUT, RDCM, unless otherwise noted. (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS VCC Voltage l 4.75 24 V RVTRANS Voltage (Note 3) l 4.75 65 V VCC Quiescent Current Not Switching, CHARGE = 5V Not Switching, CHARGE = 0.3V 5.5 mA µA RV TRANS, RDCM Quiescent Current (Note 4) Not Switching, CHARGE = 5V Not Switching, CHARGE = 0.3V l µA µA RV OUT Quiescent Current (Note 4) Not Switching, CHARGE = 5V Not Switching, CHARGE = 0.3V l µA µA UVLO1, UVLO2, OVLO1, OVLO2 Clamp Voltage Measured at 1mA into Pin, CHARGE = 0V 55 V RVTRANS, RVOUT, RDCM Clamp Voltage Measured at 1mA into Pin, CHARGE = 0V 60 V CHARGE Pin Current CHARGE = 24V CHARGE = 5V CHARGE = 0V 425 µA µA µA CHARGE Minimum Enable Voltage l 1.5 V CHARGE Maximum Disable Voltage IVCC ≤ 1µA l 0.3 V Minimum CHARGE Pin Low Time 20 μs One-Shot Clock Period l 32 38 44 μs VOUT Comparator T rip Voltage Measured at RBG Pin l 0.955 0.98 1.005 V VOUT Comparator Overdrive 2µs Pulse Width, RVTRANS, RVOUT = 25kΩ RBG = 0.83kΩ mV DCM Comparator Trip V oltage Measured as VDRAIN – VTRANS, RDCM = 25kΩ, VCC = 4.75V (Note 5) 350 600 900 mV Current Limit Comparator T rip Voltage FB Pin = 0V FB Pin = 1.3V l l 100 106 112 mV mV FB Pin Bias Current Current Sourced from FB Pin, Measured at FB Pin V oltage 64 300 nA FB Pin Voltage (Note 6) l 1.19 1.22 1.25 V FB Pin Charge Mode Threshold 1.12 1.16 1.2 V FB Pin Charge Mode Hysteresis (Note 7) 55 mV FB Pin Overvoltage Mode Threshold 1.29 1.34 1.38 V FB Pin Overvoltage Hysteresis 60 mV DONE Output Signal High 100kΩ to 5V 5 V DONE Output Signal Low 100kΩ to 5V 40 200 mV DONE Leakage Current DONE = 5V 5 200 nA FAUL T Output Signal High 100kΩ to 5V 5 V FAUL T Output Signal Low 100kΩ to 5V 40 200 mV FAUL T Leakage Current FAUL T = 5V 5 200 nA UVLO1 Pin Current UVLO1 Pin Voltage = 1.24V l 48.5 50 51.5 μA UVLO2 Pin Current UVLO2 Pin Voltage = 1.24V l 48.5 50 51.5 μA OVLO1 Pin Current OVLO1 Pin Voltage = 1.24V l 48.5 50 51.5 μA OVLO2 Pin Current OVLO2 Pin Voltage = 1.24V l 48.5 50 51.5 μA
3751fd For more information www.linear.com/LT3751 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = CHARGE = 5V, CLAMP = 0V, unless otherwise noted. Individual 25kΩ resistors tied from 5V VTRANS supply to RVTRANS, RVOUT, RDCM, unless otherwise noted. (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS UVLO1 Threshold Measured from Pin to GND l 1.195 1.225 1.255 V UVLO2 Threshold Measured from Pin to GND l 1.195 1.225 1.255 V OVLO1 Threshold Measured from Pin to GND l 1.195 1.225 1.255 V OVLO2 Threshold Measured from Pin to GND l 1.195 1.225 1.255 V Gate Minimum High Time 0.7 μs Gate Peak Pull-Up Current VCC = 5V, LVGATE Active VCC = 12V, LVGATE Inactive 2.0 1.5 A A Gate Peak Pull-Down Current V CC = 5V, LVGATE Active VCC = 12V, LVGATE Inactive 1.2 1.5 A A Gate Rise Time 10% → 90%, CGATE = 3.3nF (Note 8) VCC = 5V, LVGATE Active VCC = 12V, LVGATE Inactive ns ns Gate Fall Time 90% → 10%, CGATE = 3.3nF (Note 8) VCC = 5V, LVGATE Active VCC = 12V, LVGATE Inactive ns ns Gate High Voltage (Note 8): V CC = 5V, LVGATE Active VCC = 12V, LVGATE Inactive VCC = 12V, LVGATE Inactive, CLAMP Pin = 5V VCC = 24V, LVGATE Inactive 4.98 10.5 5.6 10.5 11.5 6.5 11.5 V V V V Gate Turn-Off Propagation Delay C GATE = 3.3nF 25mV Overdrive Applied to CSP Pin 180 ns Gate Voltage Overshoot 500 mV CLAMP Pin Threshold 1.6 V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3751E is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design characterization and correlation with statistical process controls. The LT3751I is guaranteed over the full –40°C to 125°C operating junction temperature range. Note 3: A 60V internal clamp is connected to RV TRANS, RDCM, RVOUT, UVLO1, UVLO2, OVLO1 and OVLO2. Resistors should be used such that the pin currents do not exceed the Absolute Maximum Ratings. Note 4: Currents will increase as pin voltages are taken higher than the internal clamp voltage. Note 5: Refer to Block Diagram for VTRANS and VDRAIN definitions. Note 6: Low noise regulation of the output voltage requires a resistive voltage divider from output voltage to FB pin. FB pin should not be grounded in this configuration. Refer to the Typical Application diagram for proper FB pin configuration. Note 7: The feedback pin has built-in hysteresis that defines the boundary between charge-only mode and low noise regulation mode. Note 8: LVGATE should be used in parallel with HVGATE when V CC is less than or equal to 8V (LVGATE active). When not in use, LVGATE should be tied to VCC (LVGATE inactive). Note 9: Do not apply a positive or negative voltage or current source to HVGATE, otherwise permanent damage may occur .
3751fdFor more information www.linear.com/LT3751 TYPICAL PERFORMANCE CHARACTERISTICS VCC Pin Current VTRANS Supply Current CHARGE Pin Current CHARGE Pin Minimum Enable Voltage CHARGE Pin Maximum Disable Voltage DONE, FAULT Pin Voltage Low V OUT Comparator T rip Voltage UVLO1 T rip Voltage UVLO1 T rip Current PIN VOL TAGE (V) PIN CURRENT (mA) 168 20
3751 G01
–40°C 25°C 125°C PIN VOL TAGE (V) IVTRANS CURRENT (µA) 150 145 135 120 125 140 130 115 110 4020 50
3751 G02
–40°C 25°C 125°C RVTRANS, RVOUT, RDCM = 25k VCC, CHARGE = 5V IVTRANS = IRVTRANS + IRVOUT + IRDCM PIN VOL TAGE (V) CURRENT (µA) 450 400 300 150 200 350 250 100 168 20
3751 G03
–40°C 25°C 125°C –40 CHARGE PIN VOL TAGE (V) 1.3 1.2 1.0 0.7 0.8 1.1 0.9 0.6 40 600 80 100
3751 G04
TEMPERATURE (°C) –20 VCC = 5V VCC = 12V VCC = 24V –40 CHARGE PIN VOL TAGE (V) 1.2 1.1 0.9 0.6 0.7 1.0 0.8 0.5 40 600 80 100
3751 G05
TEMPERATURE (°C) –20 VCC = 5V VCC = 12V VCC = 24V –40 PIN LOW VOL TAGE (mV) 400 350 200 250 100 300 150 40 600 80 100
3751 G06
TEMPERATURE (°C) –20 1mA SINK 100µA SINK 10µA SINK –40 VDRAIN – VTRANS VOL TAGE (V) 30.8 30.4 29.2 29.6 30.0 28.8 28.4 40 600 80 100
3751 G07
TEMPERATURE (°C) –20 RVTRANS, RVOUT = 25.5k (RTOL = 1%) RBG = 833/uni03A9 VTRANS = 5V VTRANS = 12V VTRANS = 24V VTRANS = 48V VTRANS = 72V –40 UVLO1 PIN VOL TAGE (V) 1.236 1.234 1.228 1.230 1.232 1.226 1.224 40 600 80 100
3751 G08
TEMPERATURE (°C) –20 VCC = 5V VCC = 12V VCC = 24V –40 UVLO1 PIN CURRENT (µA) 50.5 50.4 49.9 50.2 50.1 50.0 50.3 49.8 49.7 40 600 80 100
3751 G09
TEMPERATURE (°C) –20 VCC = 5V VCC = 12V VCC = 24V
3751fd For more information www.linear.com/LT3751 TYPICAL PERFORMANCE CHARACTERISTICS Current Comparator T rip Voltage (Charge Mode) Current Comparator Minimum T rip Voltage (Regulation Mode) FB Pin Regulation Mode Threshold FB Pin Regulation Mode Hysteresis FB Pin Overvoltage Mode Threshold Voltage FB Pin Overvoltage Mode Hysteresis –40 VTH VOL TAGE (mV) 109.0 108.5 107.5 108.0 107.0 40 600 80 100
3751 G10
TEMPERATURE (°C) –20 VCC = 5V VCC = 12V VCC = 24V VTH = VCSP – VCSN –40 VTH VOL TAGE (mV) 13.0 12.4 12.6 12.8 12.2 12.0 11.4 11.6 11.2 11.8 11.0 40 600 80 100
3751 G11
TEMPERATURE (°C) –20 VCC = 5V VCC = 12V VCC = 24V VTH = VCSP – VCSN FB = 1.3V –40 FB PIN VOL TAGE (V) 1.168 1.164 1.160 1.156 1.152 40 600 80 100
3751 G14
TEMPERATURE (°C) –20 VCC = 5V VCC = 12V VCC = 24V –40 HYSTERESIS (mV) 40 600 80 100
3751 G15
TEMPERATURE (°C) –20 VCC = 5V VCC = 12V VCC = 24V –40 FB PIN VOL TAGE (V) 1.356 1.354 1.352 1.350 1.348 1.346 1.344 40 600 80 100
3751 G16
TEMPERATURE (°C) –20 VCC = 5V VCC = 12V VCC = 24V –40 HYSTERESIS (mV) 61.0 60.6 60.2 59.8 59.4 59.0 40 600 80 100
3751 G17
TEMPERATURE (°C) –20 VCC = 5V VCC = 12V VCC = 24V CLAMP Pin Threshold –40 CLAMP PIN VOL TAGE (V) 1.9 1.8 1.7 1.6 1.5 1.4 400 80
3751 G18
TEMPERATURE (°C) VCC = 12V VCC = 24V FB Pin Voltage FB Pin Bias Current –40 FB PIN VOL TAGE (V) 1.223 1.222 1.220 1.221 1.219 40 600 80 100
3751 G12
TEMPERATURE (°C) –20 VCC = 5V VCC = 12V VCC = 24V –40 SOURCED PIN CURRENT (nA) 100 40 600 80 100
3751 G13
TEMPERATURE (°C) –20 MEASURED AT FB PIN VOL TAGE VCC = 12V
3751fdFor more information www.linear.com/LT3751 TYPICAL PERFORMANCE CHARACTERISTICS RVTRANS (Pin 1/Pin 19): T ransformer Supply Sense Pin. Connect a resistor between the RV TRANS pin and the VTRANS supply. Refer to Table 2 for proper sizing of the RVTRANS resistor . The minimum operation voltage for VTRANS is 4.75V. UVLO1 (Pin 2/Pin 20): VTRANS Undervoltage Lockout Pin. Senses when VTRANS drops below: VUVLO1 = 1.225 + 50µA • RUVLO1 and trips the FAUL T latch low, disabling switching. After VTRANS rises above V UVLO1, toggling the CHARGE pin reactivates switching. OVLO1 (Pin 3/Pin 1): VTRANS Overvoltage Lockout Pin. Senses when VTRANS rises above: VOVLO1 = 1.225 + 50µA • ROVLO1 and trips the FAUL T latch low, disabling switching. After VTRANS drops below V OVLO1, toggling the CHARGE pin reactivates switching. UVLO2 (Pin 4/Pin 2) : VCC Undervoltage Lockout Pin. Senses when VCC drops below: VUVLO2 = 1.225 + 50µA • RUVLO2 and trips the FAUL T latch low, disabling switching. After VCC rises above VUVLO2, toggling the CHARGE pin reac- tivates switching. OVLO2 (Pin 5/Pin 3): VCC Overvoltage Lockout Pin. Senses when VCC rises above: VOVLO2 = 1.225 + 50µA • ROVLO2 and trips the FAUL T latch low, disabling switching. After V CC drops below VOVLO2, toggling the CHARGE pin reac- tivates switching. FAULT (Pin 6/Pin 4): Open Collector Indication Pin. When either VTRANS or V CC exceeds the user-selected voltage range, or an internal UVLO condition occurs, a transistor turns on. The part will stop switching. This pin needs a proper pull-up resistor or current source. HVGATE Pin Clamp Voltage HVGATE Pin Clamp Voltage –40 HVGATE PIN VOL TAGE (V) 11.0 10.9 10.8 10.7 10.5 10.6 10.4 40 600 80 100
3751 G19
TEMPERATURE (°C) –20 VCC = 24V CLAMP = 0V –40 HVGATE PIN VOL TAGE (V) 5.70 5.65 5.60 5.55 5.50 40 600 80 100
3751 G20
TEMPERATURE (°C) –20 VCC = 12V CLAMP = 12V PIN FUNCTIONS DCM T rip Voltage (VDRAIN – VTRANS), RVTRANS = RDCM = 25kΩ –40 DCM TRIP VOL TAGE (V) 0.64 0.62 0.60 0.58 0.56 0.54 400 80
3751 G21
TEMPERATURE (°C) VTRANS = 5V VTRANS = 12V VTRANS = 24V VTRANS = 48V (TSSOP/QFN)
3751fd For more information www.linear.com/LT3751 PIN FUNCTIONS DONE (Pin 7/ Pin 5): Open Collector Indication Pin. When the target output voltage (charge mode) is reached or the FAUL T pin goes low, a transistor turns on. This pin needs a proper pull-up resistor or current source. CHARGE (Pin 8/Pin 6): Charge Pin. Initiates a new charge cycle (charge mode) or enables the part (regulation mode) when driven higher than 1.5V. Bring this pin below 0.3V to discontinue charging and put the part into shutdown. Turn-on ramp rates should be between 10ns to 10ms. CHARGE pin should not be directly ramped with V CC or LT3751 may not properly initialize. CLAMP (Pin 9/Pin 7): Internal Clamp Voltage Selection Pin. Tie this pin to V CC to activate the internal 5.6V gate driver clamp. Tie this pin to ground to activate the internal 10.5V gate driver clamp. FB (Pin 10/Pin 8): Feedback Regulation Pin. Use this pin to achieve low noise voltage regulation. FB is internally regulated to 1.22V when a resistive divider is tied from this pin to the output. FB pin should not float. Tie FB pin to either a resistor divider or ground. CSN (Pin 11/Pin 9): Negative Current Sense Pin. Senses external NMOS source current. Connect to local R SENSE ground connection for proper Kelvin sensing. The current limit is set by 106mV/RSENSE. CSP (Pin 12/Pin 10): Positive Current Sense Pin. Senses NMOS source current. Connect the NMOS source terminal and the current sense resistor to this pin. The current limit is fixed at 106mV/RSENSE in charge mode. The cur- rent limit can be reduced to a minimum 11mV/RSENSE in regulation mode. VCC (Pin 13/Pin 11): Input Supply Pin. Must be locally bypassed with high grade (X5R or better) ceramic capaci- tor . The minimum operating voltage for VCC is 4.75V. LVGATE (Pin 14/Pin 12): Low Voltage Gate Pin. Connect the NMOS gate terminal to this pin when operating V CC below 8V. The internal gate driver will drive the voltage to the VCC rail. When operating VCC higher than 8V, tie this pin directly to VCC. HVGATE (Pin 15/Pin 13): High Voltage Gate Pin. Connect NMOS gate terminal to this pin for all VCC operating volt- ages. Internal gate driver will drive the voltage to within V CC – 2V during each switch cycle. RBG (Pin 16/Pin 14): Bias Generation Pin. Generates a bias current set by 0.98V /RBG. Select R BG to achieve desired resistance for RDCM, RVOUT, and RVTRANS. NC (Pins 17, 19/Pins 15, 18): No Connection. RVOUT (Pin 18/Pin 16): Output Voltage Sense Pin. Develops a current proportional to the output capacitor voltage. Connect a resistor between this pin and the drain of NMOS such that: VOUT = 0.98 • N • RVOUT RBG ⎟ − V DIODE when RVOUT is set equal to RVTRANS, otherwise: VOUT = N • 0.98 • RVOUT RBG + VTRANS RVOUT RVTRANS − 1 − V DIODE where VDIODE = forward voltage drop of diode D1 (refer to the Block Diagram). RDCM (Pin 20/Pin 17): Discontinuous Mode Sense Pin. Senses when the external NMOS drain is equal to 20µA • RDCM + VTRANS and initiates the next switch cycle. Place a resistor equal to 0.45 times the resistor on the RVTRANS pin between this pin and VDRAIN. GND (Pin 21/Pin 21): Ground. Tie directly to local ground plane.
3751fdFor more information www.linear.com/LT3751 BLOCK DIAGRAM FB CSN CSP LVGATE HVGATE CLAMP 3751 BD START-UP ONE-SHOT CHARGE VCC OTLO MASTER LATCH S Q R Q ENABLE GATE DRIVER ONOFF DONE FAUL T 100k10µF 100k S Q R Q VCC 12V INTERNAL UVLO 3.8V VCC – 55V 55V UVLO1 OVLO1 UVLO2 OVLO2 55V 55V RUVLO1 191k RUVLO2 191k ROVLO1 240k ROVLO2 240k 1.22V REFERENCE UVLO/OVLO COMPARATORS RBG 1.33k GND RBG TO VOUT COMPARATOR VOUT COMPARATOR – DCM ONE-SHOT DCM COMPARATOR 26kHz ONE-SHOT CLOCK S R Q Q COUNTER 26kHz ONE-SHOT CLOCK SWITCH LATCH 0.98V REFERENCE DIFF . AMP COMPARATOR WITH INTERNAL 60V CLAMPS 1.22V REFERENCE GATE DRIVE CIRCUITRY 60V RVOUT 60V RDCM RESET CLK COUNT TIMING AND PEAK CURRENT CONTROL 26kHz ONE-SHOT CLOCK MODE CONTROL DIE TEMP 160ºC 1.22V REFERENCE 60V RVOUT 40.2k RDCM 18.2k VCC RSENSE 12mΩ ERROR AMP 11mV TO 106mV MODULATION 106mV 162mV RVTRANS RVTRANS 40.2k 10µF47µF D1T1 1:10PRIMARY SECONDARY VOUT 450V COUT RFBH 3.65M RFBL 10k VTRANS 12V VTRANS VCC TO CHARGE ONE-SHOT VCC VCC VDRAIN 10nF AUXILIARY MAIN FAUL T LATCH
regulation, or no-load operation (see Figure 1). Figure 1. FB Pin Modes reached or a fault condition occurs.
3751 F01
Figure 2. Idealized Charging Waveforms
3751 F02
forcing VTRANS – VDS(ON) across the primary winding.
- Secondary Energy T ransfer
enters the next phase of operation.
- Discontinuous Mode Detection
Figure 3. Start-Up Protection Circuitry Figure 4. DCM Comparator Thresholds diagram of the start-up circuitry.
3751 F03
3751 F04
ator will never fire and the start-up circuitry is dominant.
3751fd For more information www.linear.com/LT3751 OPERATION At very low output voltages, the boundary-mode switch- ing cycle period increases significantly such that the energy stored in the transformer core is not depleted before the next clock cycle. In this situation, the clock may initiate another switching cycle before the secondary winding current reaches zero and cause the LT3751 to enter continuous-mode conduction. Normally, this is not a problem; however , if the secondary energy transfer time is much longer than the CLK period, significant primary current overshoot can occur . This is due to the non-zero starting point of the primary current when the switch turns on and the finite speed of the current comparator. The LT3751 startup circuitry adds an auxiliary current comparator with a trip level 50% higher than the nomi - nal trip level. Every time the auxiliary current comparator trips, the required clock count between switching cycles is incremented by one. This allows more time for secondary energy transfer . Counter 1 in Figure 3 is set to its maximum count when the first DCM comparator one-shot is generated. If no DCM one-shot is initiated in normal boundary-mode oper- ation during a maximum count of approximately 500µs, the LT3751 re-enters start-up mode and the count is returned to zero. Note that Counter 1 is initialized to zero at start-up. Thus, the output of the startup circuitry will go high after one clock cycle. Counter 2 is reset when the gate driver goes high. This repeats until either the auxiliary cur - rent comparator increments the required clock count or until V DRAIN is high enough to sustain normal operation described in steps 2 through 4 in the previous section. Entering Normal Boundary Mode The LT3751 has two DCM comparator thresholds that are dependent on what mode the part is in, either start- up mode or normal boundary-mode, and the state of the mode latch. For boundary-mode switching, the LT3751 requires the DCM sense voltage (V DRAIN) to exceed VTRANS by the ΔDCM comparator threshold, ΔVDRAIN: ΔVDRAIN = (40µA + IOFFSET) • RDCM – 40µA • RVTRANS where IOFFSET is mode dependent. The DCM one-shot sig- nal is negative edge triggered by the switch node, VDRAIN, and indicates that the energy in the secondary winding has depleted. For this to happen, V DRAIN must exceed VTRANS + ΔVDRAIN prior to its negative edge; otherwise, the DCM comparator will not generate a one-shot to initi- ate the next switching cycle. The part would remain stuck in this state indefinitely; however , the LT3751 uses the start-up protection circuitry to jumpstart switching if the DCM comparator does not generate a one-shot after a maximum time-out of 500µs. Figure 4 shows a typical V DRAIN node waveform with a test circuit voltage clamp applied to the output. VTH1 is the start-up threshold and is set internally by forcing IOFFSET to 40μA. Once the first DCM one-shot is initiated, the mode latch is set to boundary-mode. The mode latch then sets the clock count to maximum (500µs) and lowers the DCM comparator threshold to VTH2 (IOFFSET = 20μA). This provides needed hysteresis between start-up mode and boundary-mode operation. LOW NOISE REGULATION Low noise voltage regulation can be achieved by adding a resistive divider from the output node to the LT3751 FB pin. At start-up (FB pin below 1.16V), the LT3751 enters the charge mode to rapidly charge the output capacitor . Once the FB pin is within the threshold range of 1.16V to 1.34V, the part enters into low noise regulation. The switching methodology in regulation mimics that used in the capacitor charging mode, but with the addition of peak current and duty cycle control techniques. Figure 5 shows the steady state operation for both regulation tech- niques. Figure 6 shows how both techniques are com - bined to provide stable, low noise operation over a wide load and supply range. During heavy load conditions, the LT3751 sets the peak primary current to its maximum value, 106mV/R SENSE and sets the maximum duty cycle to approximately 95%. This allows for maximum power delivery. At very light loads, the opposite occurs, and the LT3751 reduces the peak primary current to approximately one tenth its maxi- mum value while modulating the duty cycle below 10%. The LT3751 controls moderate loads with a combination of peak current mode control and duty cycle control.
Figure 5. Modes of Operation (Steady State) Figure 6. Regulation Technique
3751 F05
3751 F06
3751fd For more information www.linear.com/LT3751 OPERATION Periodic Refresh When the LT3751 enters regulation, the internal circuitry deactivates switching when the internal one-shot clock is high. The clock operates at a 1/20th duty cycle with a minimum blank time of 1.5µs. This reset pulse is timed to drastically reduce switching frequency content within the audio spectrum and is active during all loading conditions. Each reset pulse guarantees at least one energy cycle. A minimum load is required to prevent the LT3751 from entering no-load operation. Heavy Load Operation The LT3751 enters peak current mode control at higher output load conditions. The control loop maximizes the number of switch cycles between each reset pulse. Since the control scheme operates in boundary mode, the reso- nant boundary-mode period changes with varying peak primary current: Period = IPK • LPRI • 1 VTRANS + N VOUT and the power output is proportional to the peak primary current: POUT = 1/ 2 • IPK VTRANS + N VOUT Noise becomes an issue at very low load currents. The LT3751 remedies this problem by setting the lower peak current limit to one tenth the maximum level and begins to employ duty-cycle control. Light Load Operation The LT3751 uses duty cycle control to drastically reduce audible noise in both the transformer (mechanical) and the ceramic capacitors (piezoelectric effects). Internal control circuitry forces a one-shot condition at a periodic rate greater than 20kHz and out of the audio spectrum. The regulation loop then determines the number of pulses that are required to maintain the correct output voltage. Figure 5 shows the use of duty-cycle control. No-Load Operation The LT3751 can remain in low noise regulation at very low loading conditions. Below a certain load current threshold (Light Load Operation), the output voltage would continue to increase and a runaway condition could occur . This is due to the periodic one-shot forced by the periodic refresh circuitry. By design, the LT3751 has built-in overvoltage protection associated with the FB pin. When the FB pin voltage exceeds 1.34V (±20mV), the LT3751 enters no-load operation. No-load operation does not reset with the one-shot clock. Instead, the pulse train is completely load-dependent. These bursts are asynchro- nous and can contain long periods of inactivity. This allows regulation at a no-load condition but with the increase of audible noise and voltage ripple. Note that when operating with no-load, the output voltage will increase 10% above the nominal output voltage.
circuit board voltage breakdown requirements. vary output current during different loading conditions. primary current, I PK, and the primary inductance, L PRI. power output for a given VTRANS and IPK. to faster charge times and larger available output power . NMOS and increase the current through the output diode. and the initial design inputs. Figure 7. Maximum Power Output
3751 F07
time associated with the secondary winding capacitance. secondary winding, most notably the diode capacitance. Second, reduce the total required NMOS gate charge. Figure 8 shows the effect of large secondary capacitance. time like that in a capacitor charger application.
- 1 VTRANS + N VOUT Note that the LT3751 regulation scheme varies the peak current based on the output load current. The maximum I PK is only reached during charge mode or during heavy load conditions where output power is maximized.
Figure 8. Effect of Secondary Winding Capacitance
3751 F08
runaway condition and overcharge the output capacitor . result in a lower than expected maximum output power .
Figure 9. Maximum Switching Frequency
3751 F09
Table 1. Recommended T ransformers clamps by limiting the RV TRANS pin current to 250µA . Table 2. Suggested RVTRANS, RVOUT, and RDCM Values
for applications with VTRANS operating above 400V. RDCM needs to be properly sized in relation to RV TRANS. Table 3. Recommended NMOS T ransistors when operating VTRANS above 80V. enough to minimize the on-resistance. tude of the leakage inductance spike, whichever is greater . See Table 3 for recommended external NMOS transistors.
and for 5.6V operation, tie the CLAMP pin to the VCC pin. CC applications of 8V or below. should exceed IPK/2N, the average short-circuit current. Table 4. Recommended Output Diodes
100 SMA
voltages and decreases as the output voltage increases. energy is lost during the NMOS intrinsic diode conduction. voltages that have adequate reverse recovery times.
3751fd For more information www.linear.com/LT3751 APPLICATIONS INFORMATION Additionally, there is approximately a 180ns propaga- tion delay from the time that peak current limit is detected to when the gate transitions to the low state. This delay increases the peak current limit by (V TRANS) (180ns)/LPRI. Sense resistor inductance (LRSENSE) is another source of current limit error . LRSENSE creates an input offset voltage (VOS) to the current comparator and causes the current comparator to trip early. VOS can be calculated as: VOS = VTRANS • LRSENSE LPRIMARY The change in current limit becomes V OS/RSENSE. The error is more significant for applications using large di/ dt ratios in the transformer primary. It is recommended to use very low inductance (< 2nH) sense resistors. Several resistors can be placed in parallel to help reduce the inductance. Care should also be taken in placement of the sense lines. The negative return line, CSN, must be a dedicated trace to the low side resistor terminal. Haphazardly routing the CSN connection to the ground plane can cause inaccurate current limit and can also cause an undesirable discon - tinuous charging profile. DONE and FAULT Pin Design Both the DONE and FAUL T pins require proper pull-up resistors or current sources. Limit pin current to 1mA into either of these pins. 100kΩ pull-up resistors are rec- ommended for most applications. Both the DONE and FAUL T pins are latched in the low output state. Resetting either latch requires the CHARGE pin to be toggled. A fault condition will also cause the DONE pin to go low. A third, non-latching condition occurs during startup when the CHARGE pin is driven high. During this start-up condi - tion, both the DONE and FAUL T pins will go low for several micro seconds. This indicates the internal rails are still ramping to their proper levels. External RC filters may be added to both indication pins to remove start-up indica - tion. Time constants for the RC filter should be between 5µs to 20µs. Under/Over voltage Lockout The LT3751 provides user-programmable under and overvoltage lockouts for both V CC and V TRANS. Use the equations in the Pin Functions section for proper selection of resistor values. When under/overvoltage lockout com- parators are tripped, the master latch is disabled, power delivery is halted, and the FAUL T pin goes low. Adequate supply bulk capacitors should be used to reduce power supply voltage ripple that could cause false tripping during normal switching operation. Additional filtering may be required due to the high input impedance of the under/overvoltage lockout pins to prevent false tripping. Individual capacitors ranging from 100pF to 1nF may be placed between each of the UVLO1, UVLO2, OVLO1 and OVLO2 pins and ground. Disable the undervoltage lock - outs by directly connecting the UVLO1 and UVLO2 pins to VCC. Disable the overvoltage lockouts by directly con- necting the OVLO1 and OVLO2 pins to ground. The LT3751 provides internal Zener clamping diodes to protect itself in shutdown when VTRANS is operated above 55V. Supply voltages should only be applied to UVLO1, UVLO2, OVLO1 and OVLO2 with series resistance such that the Absolute Maximum pin currents are not exceeded. Pin current can be calculated using: IPIN = VAPPLIED − 55V RSERIES Note that in shutdown, RV TRANS, RVOUT, RDCM, UVLO1, UVLO2, OVLO1 and OVLO2 currents increase significantly when operating VTRANS above the Zener clamp voltages and are inversely proportional to the external series pin resistances. NMOS Snubber Design The transformer leakage inductance causes a parasitic voltage spike on the drain of the power NMOS switch dur- ing the turn-off transition. T ransformer leakage inductance effects become more apparent at high peak primary cur- rents. The worst-case magnitude of the voltage spike is determined by the energy stored in the leakage inductance and the total capacitance on the VDRAIN node.
Figure 11. Effects of RC Snubber Figure 10. RC Snubber Circuit parator or damage to the NMOS switch (see Figure 11). parator and stop charging prematurely. a lower voltage spike and faster settling time.
3751 F11
3751 F12
NMOS power switch, output diode, and sense resistor. fication for safe operation of the feedback resistors. operating with a minimum load current.
from the one-shot clock and the output voltage ripple. 6mV referred to the FB pin). ripple injected into FB pin. not arise if the large signal constraint is met.
- Provide sufficient spacing for all high voltage nodes
- Keep the electrical path formed by CVTRANS, the primary
of T1, and the drain of the NMOS as short as possible. overvoltage condition on the drain of the NMOS.
- Reduce the total node capacitance on the RV OUT and
underneath the R DCM and R VOUT pads and traces.
- Thermal vias should be added underneath the Exposed
- Isolated applications require galvanic separation of the
voltage safety requirements. Figure 13. COUT(MIN) vs Output Power
3751 F14
Figure 12. Voltage Ripple Stability Constraint
3751 F13
3751 F15
- • SECONDARY PRIMARY 1:N CVOUT1 CVOUT2DVOUT + POWER GND VOUT RFBH2 RFBH1 REMOVE COPPER FROM ALL SUB-LAYERS (SEE ITEM 4)
Figure 14. QFN Package Recommended Board Layout (Not to Scale)
Figure 15. TSSOP Package Recommended Board Layout (Not to Scale)
3751 F16
3751fdFor more information www.linear.com/LT3751 TYPICAL APPLICATIONS 42A Capacitor Charger CHARGE CLAMP VCC DONE FAUL T UVLO1 OVLO1 UVLO2 OVLO2 RDCM RV OUT HVGATE LVGATE CSP CSN FB RVTRANS T1** 1:10 D1 VOUT 500V VTRANS 12V TO 24V VCC
3751 TA02
40.2k OFF ON 1000µF 10µF VCC 12V TO 24V C1 10µF R7, 18.2k R8, 40.2k M1, M2* 2.5mΩ D2*** 1200µF 787/uni03A9 VTRANS VCC R10, 100k R11, 100k R1, 191k R2, 475k R3, 191k R4, 475k C1: 25V X5R OR X7R CERAMIC CAPACITOR C2: 25V X5R OR X7R CERAMIC CAPACITOR C3: 25V ELECTROL YTIC C4: HITACHI FX22L122Y 1200µF , 550V ELECTROL YTIC OR: CORNELL DUBILIER DCMC192T550CE2B 1900µF , 550V ELECTROL YTIC D1, D2: VISHAY GURB5H60 600V , 5A UL TRAFAST RECTIFIER M1, M2: 2 PARALLEL VISHAY SUP33N20-60P 200V , 33A NMOS R1 THRU R4, R6 THRU R11: USE 1% 0805 RESISTORS R5: USE 2 PARALLEL 5m/uni03A9 IRC LR SERIES 2512 RESISTORS T1: COILCRAFT GA3460-BL 50A SURACE MOUNT TRANSFORMER DANGER HIGH VOL TAGE! OPERATION BY HIGH VOL TAGE TRAINED PERSONNEL ONL Y FOR ANY VOUT VOL TAGE BETWEEN 50V AND 500V SELECT R9 ACCORDING TO: 4.7nF Y-RATED * M1, M2 REQUIRES PROPER HEATSINK/THERMAL DISSIPATION TO MEET MANUFACTURER’S SPECIFICATIONS THERMAL DISSIPATION OF T1 WILL LIMIT THE CHARGE/DISCHARGE DUTY CYCLE OF C4 * D2 MAY BE OMITTED FOR OUTPUT VOL TAGE OPERATION BELOW 300V R9 = 0.98 • N • 40.2k Ω VOUT + VDIODE Efficiency Output Capacitor Charge Times Charging Waveform OUTPUT VOL TAGE (V) EFFICIENCY (%) 450
3751 TA02b
VTRANS = 12V VTRANS = 24V OUTPUT CAPACITANCE (µF) 200 CHARGE TIME (ms) 1200 800 400 1000
3751 TA02c
VOUT = 500V , VTRANS = 24V VOUT = 500V , VTRANS = 12V VOUT = 300V , VTRANS = 24V VOUT = 300V , VTRANS = 12V VOUT = 100V , VTRANS = 24V VOUT = 100V , VTRANS = 12V 100ms/DIV
3751 TA02d
VOUT = 500V VTRANS = 24V C4 = 1200µF AVERAGE INPUT CURRENT 5A/DIV VOUT 100V/DIV
3751fd For more information www.linear.com/LT3751 TYPICAL APPLICATIONS Efficiency (VOUT = 500V) Load Regulation (VOUT = 500V) Steady-State Operation with 100mA Load Current High Voltage Regulator CHARGE CLAMP VCC DONE FAUL T UVLO1 OVLO1 UVLO2 OVLO2 RDCM RV OUT HVGATE LVGATE CSP CSN FB RVTRANS T1* 1:10 D1 VOUT 100V TO 500V VTRANS 5V TO 24V VCC
3751 TA04
40.2k OFF ON 680µF 5× 2.2µF 10µF R7, 18.2k R8, 40.2k M1* 6m/uni03A9 C4* 100µF VTRANS VCC R2, 475k R1, 69.8k R4, 475k R3, 69.8k C1: 25V X5R OR X7R CERAMIC C2: 25V X5R OR X7R CERAMIC C3: 25V ELECTROL YTIC C5: TDK CKG57NX7R2J474M D1: VISHAY US1M 1000V M1: FAIRCHILD FQP34N20L R1 THRU R4, R6 THRU R9, R11: USE 1% 0805 R5: IRC LR SERIES 2512 RESISTORS R10: USE 200V 1206 RESISTOR(S) T1: COILCRAFT GA3459-AL TO MICRO VCC 5V TO 24V 0.47µF R11 R10 DANGER HIGH VOL TAGE! OPERATION BY HIGH VOL TAGE TRAINED PERSONNEL ONL Y 10nF * M1 AND T1 REQUIRE PROPER HEATSINK/THERMAL DISSIPATION TO MEET MANUFACTURER’S SPECIFICATIONS DEPENDING ON DESIRED OUTPUT VOL TAGES, R10 MUST BE SPLIT INTO MUL TIPLE RESISTORS, TO MEET MANUFACTURER’S VOL TAGE SPECIFICATION. * C4 MUST BE SIZED TO MEET LARGE SIGNAL STABILITY CRITERIA DESCRIBED IN THE APPLICATIONS INFORMATION SECTION 10µs/DIV
3751 TA03b
ILOAD (mA) EFFICIENCY (%) 200
3751 TA03c
VTRANS = 24V VTRANS = 12V VTRANS = 5V ILOAD (mA) OUTPUT VOL TAGE (V) 515 510 505 500 495 200
3751 TA03d
VTRANS = 24V VTRANS = 12V VTRANS = 5V 10µs/DIV
3751 TA03e
Steady-State Operation with 1.1mA Load Current Suggested Component Values VOUT (V) IOUT(MAX) (mA) AT VTRANS = 5V, 5% VOUT DEFLECTION IOUT(MAX) (mA) AT VTRANS = 24V, 5% VOUT DEFLECTION (kΩ) R11 (kΩ) R10 (kΩ) 100 180 270 3.32 0.383 30.9 200 110 315 1.65 0.768 124 300 75 245 1.10 1.13 274 400 55 200 0.825 1.54 499 500† 40 170 Tie to GND 1.74 715 †T ransformer primary inductance limits VOUT comparator operation to VOUT = 400VMAX. RVOUT and RBG should be tied to ground when operating VOUT above 400V.
3751fdFor more information www.linear.com/LT3751 VCC DONE FAUL T UVLO1 OVLO1 UVLO2 OVLO2 CHARGE CLAMP RDCM RV OUT HVGATE LVGATE FB CSP CSN RVTRANS T1* 1:3 D1F1, 1A VOUT 50V TO 500V VTRANS 100V TO 400VDC VCC
3751 TA04a
47µF 2.2µF 10µF 417k R10 208k 20/uni03A9 R7, 96.2k M1** R13 68m/uni03A9 R12 67.3k R11 32.1k 220µF VTRANS VCC R2, 9M R1, 1.5M R4, 475k R3, 154k C1: 25V X5R OR X7R CERAMIC C2: 630V X5R OR X7R CERAMIC C3: 450V ILLINOIS CAP 476CKE450MQW C4: 50V TO 500V ELECTROL YTIC C5: TDK CKG57NX7R2J474M D1, D2: VISHAY US1M 1000V F1: BUSSMANN PCB-1-R M1: FAIRCHILD FQB4N80 R1, R2: 2 X 1206 RESISTORS IN SERIES, 1% R3 THRU R5, R9, R12: 0805 RESISTORS, 1% R6, R10: 3 X 1206 RESISTORS IN SERIES, 0.1% R7, R11: 0805 RESISTORS, 0.1% R8: 3 X 1206 RESISTORS IN SERIES, 1% R13: IRC LR SERIES 1206 RESISTOR, 1% T1: COILCRAFT HA4060-AL * T1 REQUIRES PROPER THERMAL MANAGEMENT TO ACHIEVE DESIRED OUTPUT POWER LEVELS ** M1 REQUIRES PROPER HEAT SINK/THERMAL DISSIPATION TO MEET MANUFACTURER’S SPECIFICATIONS FOR ANY OUTPUT VOL TAGE BETWEEN 50V TO 500V , SET R12 GIVEN BY: TO MICRO VCC 10V TO 24V 0.47µF DANGER HIGH VOL TAGE! OPERATION BY HIGH VOL TAGE TRAINED PERSONNEL ONL Y 4.7nF Y-RATED R12 = 0.98 VOUT,TRIP 3 • R10 +40µA • 2 INPUT VOL TAGE (V) 100 VOUT,TRIP (V) 520 510 300200 400 500 490 530 850 700 550 400 1000
3751 TA04b
VOUT,TRIP CHARGE TIME CHARGE TIME (ms) OUTPUT VOL TAGE (V) EFFICIENCY (%) 250 450150 350 100
3751 TA04c
VIN = 100V VIN = 250V VIN = 400V 100ms/DIV
3751 TA04d
VOUT = 500V VTRANS = 300V VOUT = 12V AVERAGE INPUT CURRENT 200mA/DIV CHARGE 10V/DIV VOUT 100V/DIV Output T rip Voltage and Charge Time OUT = 500V, COUT = 220µF) Efficiency Charging Waveform 1.6A High Input Voltage, Isolated Capacitor Charger TYPICAL APPLICATIONS
3751fd For more information www.linear.com/LT3751 CHARGE CLAMP VCC DONE FAUL T UVLO1 OVLO1 UVLO2 OVLO2 RDCM RV OUT HVGATE LVGATE CSP CSN FB RVTRANS T1* 1:3 D1F1, 1A VOUT 100V TO 500VVTRANS 100V TO 400VDC VCC
3751 TA05a
R6, 625k OFF ON 47µF 2.2µF 10µF R8, 417k R5, 20/uni03A9 R7, 97.6k M1** R12 68m/uni03A9 67.3k 100µF VTRANS VCC R2, 9M R1, 1.5M R4, 475k R3, 154k C1: 25V X5R OR X7R CERAMIC C2: 630V X5R OR X7R CERAMIC C3: 450V ILLINOIS CAP 476CKE450MQW C4: 50V TO 500V ELECTROL YTIC C5: TDK CKG57NX7R2J474M C6: 6.3V X5R OR X7R CERAMIC D1, D2: VISHAY US1M 1000V F1: BUSSMANN PCB-1-R M1: FAIRCHILD FQB4N80 R1, R2: 2 X 1206 RESISTORS IN SERIES, 1% R3 THRU R5, R7, R9, R11: 0805 RESISTORS, 1% R6, R8: 3 X 1206 RESISTORS IN SERIES, 1% R10: 1206 RESISTOR(S), 1% R12: IRC LR SERIES 1206 RESISTOR, 1% T1: COILCRAFT HA4060-AL * T1 REQUIRES PROPER THERMAL MANAGEMENT TO ACHIEVE DESIRED OUTPUT POWER LEVELS M1 REQUIRES PROPER HEAT SINK/THERMAL DISSIPATION TO MEET MANUFACTURER’S SPECIFICATIONS * DEPENDING ON DESIRED OUTPUT VOL TAGE, R10 MUST BE SPLIT INTO MUL TIPLE RESISTORS TO MEET MANUFACTURER’S VOL TAGE SPECIFICATION TO MICRO VCC 10V TO 24V 0.47µF R11 R10*** DANGER HIGH VOL TAGE! OPERATION BY HIGH VOL TAGE TRAINED PERSONNEL ONL Y 10nF OUTPUT CURRENT (mA) EFFICIENCY (%) 25 50
3751 TA05b
VIN = 400V VIN = 250V VIN = 100V INPUT VOL TAGE (V) 100
395 OUTPUT VOL TAGE (V)
3751 TA05c
IOUT = 25mA IOUT = 50mA IOUT = 10mA 10µs/DIV
3751 TA05d
VIN = 200V VOUT = 400V VDRAIN 100V/DIV IPRI 2A/DIV Efficiency Line Regulation Steady-State Operation with 50mA Load Current TYPICAL APPLICATIONS High Input Voltage, High Output Voltage Regulator Suggested Component Values VOUT (V) IOUT(MAX) (mA) AT VTRANS = 100V, 1% VOUT DEFLECTION IOUT(MAX) (mA) AT VTRANS = 400V, 1% VOUT DEFLECTION R10 (kΩ) R11 (kΩ) 100 55 130 30.9 0.383 200 110 150 124 0.768 300 95 175 274 1.13 400 80 130 499 1.54 500 65 140 715 1.74
3751fdFor more information www.linear.com/LT3751 Isolated 282V Voltage Regulator TYPICAL APPLICATIONS DONE FAUL T UVLO1 OVLO1 UVLO2 OVLO2 V CC CHARGE CLAMP RDCM RVOUT VIN GND OC OPTOVCC COMP FB HVGATE LVGATE FB CSP CSN RVTRANS D5 VOUT 282V 225mA VTRANS VCC
3751 TA06a
22µF 100pF 1µF 1µF 475/uni03A9 105k 210k 40m/uni03A9 R18 2.49k R17 221k R16 249k 4.7nF Y RATED 49.9k D1 D6 U2 L T4430 VTRANS VCC R10, 4.3M R9, 2.7M R2, 10/uni03A9 ISOLATION BOUNDARY Npb Np Ns Nsb R12, 442k R11, 84.5k C1, C8: 16V COG CERAMIC C2: 16V X5R OR X74 CERAMIC C3: 350V ELECTROL YTIC C4: 250V X5R OR X7R CERAMIC C5, C6, C11, C12: 630V X5R OR X7R CERAMIC C7: 350V ELECTROL YTIC C9, C10: 25V X5R OR X7R CERAMIC F1: 250V , 2A FUSE R1: 2010 RESISTOR, 1% R2, R3, R6, R16, R17: 1206 RESISTORS, 1% R4, R5: TWO 1206 RESISTORS IN SERIES, 1% R7 THRU R12, R15 THRU R20: 0805 RESISTORS, 1% D1: 12V ZENER D2: VISHAY MURS140 D3: VISHAY P6KE200A D4: VISHAY MURS160 D5: STMICROELECTRONICS STTH112A D6: VISHAY BAT54 D7: NXP SEMICONDUCTORS BAS516 M1: VISHAY IRF830 M2: STMICROELECTRONICS STB11NM60FD T1: TDK SRW24LQ (Np:Ns:Npb:Nsb = 1:2:0.08:0.08) U1: NEC PS2801-1 U2: LINEAR TECHNOLOGY L T4430 TO MICRO VTRANS 100V TO 200VDC F1, 2A 0.01µF DANGER HIGH VOL TAGE! OPERATION BY HIGH VOL TAGE TRAINED PERSONNEL ONL Y D3M1 3.3µF 22nF R19 3.16k C10 0.47µF R15 5.11/uni03A9 D7U1 R20 274/uni03A9 0.1µF 400µF IOUT (mA) –0.50 OUTPUT VOLTAGE ERROR (V) 50 100 200150 0.50 –0.25 0.25 250
3751 TA06b
EFFICIENCY (%) 100 180140
3751 TA06c
INPUT VOL TAGE (V) 120 63W OUTPUT 48W OUTPUT 25W OUTPUT 20µs/DIV
3751 TA06d
20µs/DIV
3751 TA06e
Load Regulation Efficiency Steady-State Operation with 225mA Load Current Steady-State Operation with 7.1mA Load Current
3751fd For more information www.linear.com/LT3751 –IVOUT2, IVOUT3** (mA) –VOUT2, VOUT3 (V)18
3751 TA07b
VIN = 24V VIN = 12V VIN = 5V 1 10 100 1000 **SOURCE/SINK IDENTICAL CURRENTS FROM BOTH VOUT2 AND VOUT3, RESPECTIVEL Y Wide Input Voltage Range, 15 Watt, T riple Output Voltage Regulator TYPICAL APPLICATIONS DONE FAUL T UVLO1 OVLO1 UVLO2 OVLO2 V CC CHARGE CLAMP RDCM RVOUT HVGATE LVGATE FB CSP CSN RVTRANS 2:1:3:3 (P1:S1:S2:S3) VOUT3 +15V VIN 5V TO 24V VCC
3751 TA07a
25.5k OFF ON 470µF 10µFC1 10µF
- C3 10µF R12 4.99k 25.5k 11.5k R11 25m/uni03A9 R10 100/uni03A9R8 2.21k 309/uni03A9 R4, 464k R3, 66.5k R2, 100k R1, 100k C1, C3: 25V X5R OR X7R CERAMIC C2: 25V SANYO 25ME1000AX C4, C5: 35V SANYO 35ME470AX C6: 10V KEMET T520D107M010ASE055 C7, C8: 16V CERAMIC, TDK C4532X7R1E106M C9: 6.3V CERAMIC, TDK C4532X5R0J107M D1, D2: CENTRAL SEMI CMSH2-60M D3: CENTRAL SEM1 CMSH5-40 M1: FAIRCHILD FQD12N20L R1 THRU R10, R12, R13: 0805 RESISTOR, 1% R11: 1206 RESISTOR, 1% T1: COILCRAFT HA3994-AL, 2:1:3:3 (P1:S1:S2:S3) VOUT2 –15VC5 470µF 10µF R13 4.99k D3 VOUT1 +5VC6 100µF 100µF +C2 1000µF –IVOUT2, IVOUT3** (mA) –VOUT2, VOUT3 (V)22
3751 TA07c
VIN = 24V VIN = 12V VIN = 5V 1 10 100 1000 –IVOUT2 + IVOUT3 (mA) EFFICIENCY (%) 400200 600 800
3751 TA07d
VIN = 24V VIN = 12V VIN = 5V Cross Regulation (IVOUT1 = 100mA) Efficiency VOUT1 = 500mA) Maximum Output Conditions VCC (V) POUT(MAX) (W) IOUT(MAX)* (mA) VOUT1 VOUT2 VOUT3 5 6.5 750 300 300 12 10 1750 300 300 24 13 2500 300 300 *All other output currents set to 0mA Cross Regulation VOUT1 = 500mA)
3751fdFor more information www.linear.com/LT3751 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LT3751#packaging for the most recent package drawings. FE20 (CB) TSSOP REV L 0117 0.09 – 0.20 (.0035 – .0079) 0° – 8° 0.25 REF RECOMMENDED SOLDER PAD LAYOUT 0.50 – 0.75 (.020 – .030) 4.30 – 4.50* (.169 – .177) 1 3 4 5 6 7 8 9 10 DETAIL A DETAIL A IS THE PART OF THE LEAD FRAME FEATURE FOR REFERENCE ONLY NO MEASUREMENT PURPOSE 11 12 14 13 6.40 – 6.60* (.252 – .260) 3.86 (.152) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) MAX 0.05 – 0.15 (.002 – .006) 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 2.74 (.108) 0.45 ±0.05
0.65 BSC
4.50 ±0.10 6.60 ±0.10 1.05 ±0.10 3.86 (.152) MILLIMETERS (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE SEE NOTE 4 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT 6.40 (.252) BSC 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663 Rev L) Exposed Pad Variation CB DETAIL A 0.60 (.024) REF 0.28 (.011) REF
3751fd For more information www.linear.com/LT3751 20-Pin Plastic QFN (4mm × 5mm) (Reference L TC DWG # 05-08-1711 Rev B) PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LT3751#packaging for the most recent package drawings. 4.00 ±0.10 (2 SIDES)
1.50 REF
5.00 ±0.10 (2 SIDES) NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (NOTE 6) 0.40 ±0.10 19 20 BOTTOM VIEW—EXPOSED PAD
2.50 REF
0.75 ±0.05 R = 0.115 TYP PIN 1 NOTCH R = 0.20 OR C = 0.35 0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05 (UFD20) QFN 0506 REV B RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 0.25 ±0.05 2.65 ±0.05 4.10 ±0.05 5.50 ±0.05 3.10 ±0.05 4.50 ±0.05 PACKAGE OUTLINE R = 0.05 TYP 2.65 ±0.10 3.65 ±0.10 3.65 ±0.05 20-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1711 Rev B)
3751fdFor more information www.linear.com/LT3751 Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER B 5/10 Updated FAUL T (Pin 6/Pin 4) description in Pin Functions 7 Updated DONE (Pin 7/Pin 5) description in Pin Functions 8 Updated Block Diagram 9 Revised Applications Information section 17, 18 Revised Typical Applications illustration 30 C 6/12 Revised Applications Information section 20 Corrected Schematic R8 value from 3.40k to 2.21k 30 Updated FE package drawing 31 D 12/17 Revised Absolute Maximum storage temperature range upper limit from 125°C to 150°C. 2 (Revision history begins at Rev B)
3751fd For more information www.linear.com/LT3751 ANALOG DEVICES, INC. 2017 LT 1217 REV D • PRINTED IN USA www.linear.com/LT3751 RELATED PARTS TYPICAL APPLICATION 300V Regulated Power Supply PART NUMBER DESCRIPTION COMMENTS LTC3225 150mA Supercapacitor Charger VIN: 2.75V to 5.5V, Charges Two Supercapacitors in Series to 4.8V or 5.3V LT3420/LT3420-1 1.4A/1A, Photoflash Capacitor Charger with Automatic Top-Off Charges 220µF to 320V in 3.7 Seconds from 5V, VIN: 2.2V to 16V, ISD < 1µA, 10-Lead MS Package LT3468/LT3468-1/ LT3468-2 1.4A, 1A, 0.7A, Photoflash Capacitor Charger VIN: 2.5V to 16V, Charge Time: 4.6 Seconds for LT3468 (0V to 320V, 100µF, VIN = 3.6V), ISD < 1µA, ThinSOT Package LT3484-0/LT3484-1/ LT3484-2 1.4A, 0.7A, 1A Photoflash Capacitor Charger VIN: 1.8V to 16V, Charge Time: 4.6 Seconds for LT3484-0 (0V to 320V, 100µF, VIN = 3.6V), ISD < 1µA, 2mm × 3mm 6-Lead DFN Package LT3485-0/LT3485-1/ LT3485-2/LT3485-3 1.4A, 0.7A, 1A, 2A Photoflash Capacitor Charger with Output V oltage Monitor and Integrated IGBT VIN: 1.8V to 10V, Charge Time: 3.7 Seconds for LT3485-0 (0V to 320V, 100µF, VIN = 3.6V), ISD < 1µA, 3mm × 3mm 10-Lead DFN Package LT3585-0/LT3585-1/ LT3585-2/LT3585-3 1.2A, 0.55A, 0.85A, 1.7A Photoflash Capacitor Charger with Adjustable Input Current and IGBT Drivers V IN: 1.5V to 16V, Charge Time: 3.3 Seconds for LT3585-3 (0V to 320V, 100µF, VIN = 3.6V), ISD < 1µA, 3mm × 2mm DFN-10 Package LT3750 Capacitor Charger Controller VIN: 3V to 24V, Charge Time: 300ms for (0V to 300V, 100µF) MSOP-10 Package UVLO1 OVLO1 UVLO2 OVLO2 RDCM RV TRANS 1:10 D1 VOUT 300V 0mA TO 270mA VTRANS 24V VCC 680µF
3751 TA08
40.2k OFF ON 2.2µF VCC 24V C1 10µF 18.2k 6mΩ 20µF R8* 274k * DEPENDING ON DESIRED OUTPUT VOL TAGE, R8 MUST BE SPLIT INTO MUL TIPLE RESISTORS TO MEET MANUFACTURER’S VOL TAGE SPECIFICATION. VTRANS VCC 1.13k 432k 475k 475k 432k TO MICRO C1: 25V X5R OR X7R CERAMIC CAPACITOR C2: 25V X5R OR X7R CERAMIC CAPACITOR C3: 25V ELECTROL YTIC C4: 330V RUBYCON PHOTOFLASH CAPACITOR D1: VISHAY US1M 1000V M1: FAIRCHILD FQP34N20L R1 THROUGH R4: USE 1% 0805 RESISTORS R5: IRC LR SERIES 2512 RESISTOR T1: SUMIDA PS07-299, 20A TRANSFORMER CSN FB DONE FAUL T VCC CLAMP CHARGE RVOUT HVGATE LVGATE CSP 10nF