LT3724

LT3724_15 LINER | Alldatasheet

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Technical content

FEATURES

APPLICATIONS

DESCRIPTION

High Voltage, Current Mode Switching Regulator Controller The L T®3724 is a DC/DC controller used for medium power , low part count, low cost, high efficiency supplies. It of - fers a wide 4V-60V input range (7.5V minimum startup voltage) and can implement step-down, step-up, inverting and SEPIC topologies. The L T3724 includes Burst Mode operation, which re - duces quiescent current below 100µA and maintains high efficiency at light loads. An internal high voltage bias regulator allows for simple biasing and can be back driven to increase efficiency. Additional features include fixed frequency current mode control for fast line and load transient response; a gate driver capable of driving large N-channel MOSFETs; a precision undervoltage lockout function; 10µA shutdown current; short-circuit protection; and a programmable soft-start function that directly controls output voltage slew rates at startup which limits inrush current, minimizes overshoot and facilitates supply sequencing. High Voltage Step-Down Regulator n Wide Input Range: 4V to 60V n Output Voltages up to 36V (Step-Down) n Burst Mode® Operation: <100µA Supply Current n 10µA Shutdown Supply Current n ±1.3% Reference Accuracy n 200kHz Fixed Frequency n Drives N-Channel MOSFET n Programmable Soft-Start n Programmable Undervoltage Lockout n Internal High Voltage Regulator for Gate Drive n Thermal Shutdown n Current Limit Unaffected by Duty Cycle n 16-Pin Thermally Enhanced TSSOP Package n Industrial Power Distribution n 12V and 42V Automotive and Heavy Equipment n High Voltage Single Board Systems n Distributed Power Systems n Avionics n Telecom Power Efficiency and Power Loss vs Load Current VIN SHDN CSS Burst_EN V FB VC SGND BOOST TG SW VCC PGND SENSE+ SENSE– VIN 30V TO 60V VOUT 24V 75W

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68.1k 1000pF 4.99k 93.1k 10Ω 200k 0.22µF COUT 330µF CIN 68µF 1µF 47µH 0.025Ω Si7852 SS3H9 120pF680pF 40.2k LOAD CURRENT (A) 0.1 EFFICIENCY (%) POWER LOSS (W) 1 10

3724 TA01b

VIN = 48V LOSS EFFICIENCY L, L T , L TC, L TM, Linear Technology and the Linear logo are registered trademarks and Burst Mode is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5731694, 6498466, 6611131.

PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS Differential Boost Voltage Operating Junction Temperature Range (Notes 2, 3) (Note 1) FE PACKAGE 16-LEAD PLASTIC TSSOP TOP VIEW V IN NC SHDN CSS BURST_EN VFB VC SGND BOOST TG SW NC V CC PGND SENSE SENSE– TJMAX = 125°C, θJA = 40°C/W , θJC = 10°C/W EXPOSED PAD IS SGND (PIN 17), MUST BE SOLDERED TO PCB

ELECTRICAL CHARACTERISTICS

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE L T3724EFE#PBF L T3724EFE#TRPBF 3724EFE 16-Lead Plastic TSSOP –40°C to 125°C L T3724IFE#PBF L T3724IFE#TRPBF 3724IFE 16-Lead Plastic TSSOP –40°C to 125°C LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L T3724MPFE L T3724MPFE#TR 3724MPFE 16-Lead Plastic TSSOP –55°C to 125°C Consult L TC Marketing for parts specified with wider operating temperature ranges. Consult L TC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear .com/tapeandreel/ The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 20V , VCC = BOOST = BURST_EN = 10V , SHDN = 2V , SENSE– = SENSE+ = 10V , SGND = PGND = SW = 0V , unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Operating Voltage Range (Note 4) Minimum Start Voltage UVLO Threshold (Falling) UVLO Threshold Hysteresis l l l 7.5 3.65 3.8 670 3.95 V V V mV I VIN VIN Supply Current VIN Burst Mode Current VIN Shutdown Current VCC > 9V VBURST_EN = 0V , VFB = 1.35V VSHDN = 0V µA µA µA

ELECTRICAL CHARACTERISTICSThe l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 20V , VCC = BOOST = BURST_EN = 10V , SHDN = 2V , SENSE– = SENSE+ = 10V , SGND = PGND = SW = 0V , unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VBOOST Operating Voltage Range Operating Voltage Range (Note 5) UVLO Threshold (Rising) UVLO Threshold Hysteresis V BOOST - VSW VBOOST - VSW VBOOST - VSW l l 400 V V V mV I BOOST BOOST Supply Current (Note 6) BOOST Burst Mode Current BOOST Shutdown Current V BURST_EN = 0V VSHDN = 0V 1.4 0.1 0.1 mA µA µA V CC Operating Voltage Range (Note 5) Output Voltage UVLO Threshold (Rising) UVLO Threshold Hysteresis Over Full Line and Load Range l l 6.25 500 8.3 V V V mV IVCC VCC Supply Current (Note 6) VCC Burst Mode Current VCC Shutdown Current Short-Circuit Current V BURST_EN = 0V VSHDN = 0V l l –30 1.7 –55 2.1 mA µA µA mA V FB Error Amp Reference Voltage Measured at VFB Pin l 1.224 1.215 1.231 1.238 1.245 V V I FB Feedback Input Current 25 nA VSHDN Enable Threshold (Rising) Threshold Hysteresis l 1.3 1.35 120 1.4 V mV VSENSE Common Mode Range Current Limit Sense Voltage V SENSE+ – VSENSE– l l 140 150 175 V mV ISENSE Input Current (ISENSE+ + ISENSE–) VSENSE(CM) = 0V VSENSE(CM) = 2.5V VSENSE(CM) > 4V 400 –150 µA µA µA f SW Operating Frequency MP Grade l l 190 175 165 200 200 210 220 225 kHz kHz kHz V FB(SS) Soft-Start Disable Voltage Soft-Start Disable Hysteresis V FB Rising 1.185 300 V mV ISS Soft-Start Capacitor Control Current 2 µA gm Error Amp T ransconductance l 275 340 400 µmhos AV Error Amp DC Voltage Gain 62 dB VC Error Amp Output Range Zero Current to Current Limit 1.2 V IVC Error Amp Sink/Source Current ±30 µA VTG Gate Drive Output On Voltage (Note 7) Gate Drive Output Off Voltage C LOAD = 3300pF CLOAD = 3300pF 9.8 0.1 V V t TG Gate Drive Rise/Fall Time 10% to 90% or 90% to 10%, CLOAD = 3300pF 60 ns tTG(OFF) Minimum Switch Off Time 350 ns tTG(ON) Minimum Switch On Time l 300 500 ns ISW SW Pin Sink Current VSW = 2V 300 mA

TYPICAL PERFORMANCE CHARACTERISTICS Shutdown Threshold (Rising) vs Temperature Shutdown Threshold (Falling) vs Temperature V CC vs Temperature V CC vs ICC(LOAD) V CC vs VIN I CC Current Limit vs Temperature

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SHUTDOWN THRESHOLD, RISING (V) 1.38 1.37 1.36 1.35 1.34 1.33 1.32 TEMPERATURE (°C) –50 25 75–25 0 50 100 125

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TEMPERATURE (°C) –50 SHUTDOWN THRESHOLD, FALLING (V) 1.26 1.25 1.24 1.23 1.22 1.21 1.20 25 75–25 0 50 100 125 TEMPERATURE (°C) –50 25 75–25 0 50 100 125

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8.2 8.1 8.0 7.9 7.8 7.7 7.6 7.5 VCC (V) ICC = 20mA

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ICC (LOAD) (mA) 8.2 8.1 8.0 7.9 7.8 7.7 7.6 7.5 15 255 10 20 30 35 VCC (V) TA = 25°C

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VIN (V) VCC (V) 4 6 8 95 7 10 11 12 ICC = 20mA TA = 25°C TEMPERATURE (°C) –50 25 75–25 0 50 100 125

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ICC CURRENT LIMIT (mA) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The L T3724 includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 3: The L T3724E is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the – 40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The L T3724I is guaranteed over the full –40°C to 125°C operating junction temperature range. The L T3724MP is 100% tested and guaranteed over the –55°C to 125°C operating junction temperature range. Note 4: V IN voltages below the start-up threshold (7.5V) are only supported when the VCC is externally driven above 6.5V . Note 5: Operating range is dictated by MOSFET absolute maximum VGS. Note 6: Supply current specification does not include switch drive currents. Actual supply currents will be higher . Note 7: DC measurement of gate drive output “ON” voltage is typically 8.6V . Internal dynamic bootstrap operation yields typical gate “ON” voltages of 9.8V during standard switching operation. Standard operation gate “ON” voltage is not tested but guaranteed by design. Note 8: The –1V absolute maximum on the SW pin is a transient condition. It is guaranteed by design and not subject to test.

VCC UVLO Threshold (Rising) vs Temperature ICC vs VCC (SHDN = 0V) Error Amp T ransconductance vs Temperature TYPICAL PERFORMANCE CHARACTERISTICS I(SENSE+ + SENSE–) vs VSENSE (CM) Operating Frequency vs Temperature Error Amp Reference vs Temperature Maximum Current Sense Threshold vs Temperature V IN UVLO Threshold (Rising) vs Temperature V IN UVLO Threshold (Falling) vs Temperature

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TEMPERATURE (°C) –50 25 75–25 0 50 100 125 VCC UVLO THRESHOLD, RISING (V) 6.5 6.4 6.3 6.2 6.1 6.0

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VCC (V) ICC (µA) 2 4 6 8 10 12 14 18 20 TA = 25°C TEMPERATURE (°C) –50 ERROR AMP TRANSCONDUCTANCE (µMhos) 350 345 340 335 330 325 320 25 75

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–25 0 50 100 125 VSENSE (CM) (V) I(SENSE+ + SENSE–) (µA) 400 300 200 100 –100 –200 0.5 1.0 1.5 2.0

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TA = 25°C TEMPERATURE (°C) –50 OPERATING FREQUENCY (kHz) 230 220 210 200 190 180 170 25 75

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–25 0 50 100 125 TEMPERATURE (°C) –50 25 75

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–25 0 50 100 125 1.234 1.233 1.232 1.231 1.230 1.229 1.228

1.227 ERROR AMP REFERENCE (V)

TEMPERATURE (°C) –50 25 75–25 0 50 100 125 CURRENT SENSE THRESHOLD (mV) 160 158 156 154 152 150 148 146 144 142 140

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TEMPERATURE (°C) –50 25 75–25 0 50 100 125

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4.54 4.52 4.50 4.48 4.46 4.44 4.42

4.40 VIN UVLO THRESHOLD, RISING (V)

TEMPERATURE (°C) –50 25 75–25 0 50 100 125

3724 G15

VIN UVLO THRESHOLD, FALLING (V) 3.86 3.84 3.82 3.80 3.78 3.76

VIN (Pin 1): The VIN pin is the main supply pin and should be decoupled to SGND with a low ESR capacitor located close to the pin. NC (Pin 2): No Connection. SHDN (Pin 3): The SHDN pin has a precision IC enable threshold of 1.35V (rising) with 120mV of hysteresis. It is used to implement an undervoltage lockout (UVLO) circuit. See Application Information section for implementing a UVLO function. When the SHDN pin is pulled below a transistor V BE (0.7V), a low current shutdown mode is entered, all internal circuitry is disabled and the VIN sup- ply current is reduced to approximately 10µA. Typical pin input bias current is <10µA and the pin is internally clamped to 6V . C SS (Pin 4): The soft-start pin is used to program the sup- ply soft-start function. The pin is connected to VOUT via a ceramic capacitor (CSS) and 200kΩ series resistor . During start-up, the supply output voltage slew rate is controlled to produce a 2µA average current through the soft-start coupling capacitor . Use the following formula to calculate C SS for a given output voltage slew rate: CSS = 2µA(tSS/VOUT) See the application section for more information on setting the rise time of the output voltage during start-up. Shorting this pin to SGND disables the soft-start function. BURST_EN (Pin 5): The BURST_EN pin is used to enable or disable Burst Mode operation. Connect the BURST_EN pin to ground to enable the burst mode function. Connect the pin to V CC to disable the burst mode function. VFB (Pin 6): The output voltage feedback pin, V FB, is externally connected to the supply output voltage via a resistive divider . The V FB pin is internally connected to the inverting input of the error amplifier . In regulation, V FB is 1.231V . VC (Pin 7): The VC pin is the output of the error amplifier whose voltage corresponds to the maximum (peak) switch current per oscillator cycle. The error amplifier is typically configured as an integrator circuit by connecting an RC network from the V C pin to SGND. This circuit creates the dominant pole for the converter regulation control loop. Specific integrator characteristics can be configured to optimize transient response. Connecting a 100pF or greater high frequency bypass capacitor from this pin to ground is recommended. When Burst Mode operation is enabled (see Pin 5 description), an internal low impedance clamp on the V C pin is set at 100mV below the burst threshold, which limits the negative excursion of the pin voltage. Therefore, this pin cannot be pulled low with a low imped- ance source. If the V C pin must be externally manipulated, do so through a 1kΩ series resistance. SGND (Pin 8, 17): The SGND pin is the low noise ground reference. It should be connected to the –VOUT side of the output capacitors. Careful layout of the PCB is necessary to keep high currents away from this SGND connection. See the Application Information section for helpful hints on PCB layout of grounds. SENSE – (Pin 9): The SENSE– pin is the negative input for the current sense amplifier and is connected to the VOUT side of the sense resistor for step-down applications. The sensed inductor current limit is set to 150mV across the SENSE inputs. SENSE + (Pin 10): The SENSE+ pin is the positive input for the current sense amplifier and is connected to the induc- tor side of the sense resistor for step-down applications. The sensed inductor current limit is set to 150mV across the SENSE inputs. PGND (Pin 11): The PGND pin is the high-current ground reference for internal low side switch and the V CC regulator circuit. Connect the pin directly to the negative terminal of the V CC decoupling capacitor . See the Application Informa- tion section for helpful hints on PCB layout of grounds.

VCC (Pin 12): The V CC pin is the internal bias supply decoupling node. Use a low ESR 1µF ceramic capacitor to decouple this node to PGND. Most internal IC func - tions are powered from this bias supply. An external diode connected from V CC to the BOOST pin charges the bootstrapped capacitor during the off-time of the main power switch. Back driving the V CC pin from an external DC voltage source, such as the V OUT output of the buck regulator supply, increases overall efficiency and reduces power dissipation in the IC. In shutdown mode this pin sinks 20µA until the pin voltage is discharged to 0V . NC (Pin 13): No Connection. SW (Pin 14): In step-down applications the SW pin is connected to the cathode of an external clamping Schottky diode, the source of the power MOSFET and the induc - tor . The SW node voltage swing is from V IN during the on-time of the power MOSFET , to a Schottky voltage drop below ground during the off-time of the power MOSFET . In start-up and in operating modes where there is insuf- ficient inductor current to freewheel the Schottky diode, an internal switch is turned on to pull the SW pin to ground so that the BOOST pin capacitor can be charged. Give careful consideration in choosing the Schottky diode to limit the negative voltage swing on the SW pin. TG (Pin 15): The TG pin is the bootstrapped gate drive for the top N-Channel MOSFET . Since very fast high cur- rents are driven from this pin, connect it to the gate of the power MOSFET with a short and wide, typically 0.02” width, PCB trace to minimize inductance. BOOST (Pin 16): The BOOST pin is the supply for the bootstrapped gate drive and is externally connected to a low ESR ceramic boost capacitor referenced to SW pin. The recommended value of the BOOST capacitor , C BOOST, is 50 times greater than the total input capacitance of the topside MOSFET . In most applications 0.1µF is adequate. The maximum voltage that this pin sees is V IN + V CC, ground referred. Exposed Pad (SGND) (Pin 17): The exposed leadframe is internally connected to the SGND pin. Solder the exposed pad to the PCB ground for electrical contact and optimal thermal performance.

– + – + – + VIN UVLO (<4V) BST UVLO 8V VCC REGULATOR FEEDBACK REFERENCE 1.231V 3.8V REGULATOR INTERNAL SUPPL Y RAIL VIN VCC UVLO (<6V) SHDN DRIVE CONTROL NOL SWITCH LOGIC DRIVE CONTROL BURST_EN VC CSS SENSE– VFB 1.185V ~1V 0.5V 2µA BURST MODE OPERATION SOFT-START DISABLE/BURST ENABLE R S Q OSCILLATOR SLOPE COMP GENERATOR BOOST TG (OPTIONAL) RSENSESW VCC PGND SENSE+ SGND 3724 FD BOOSTED SWITCH DRIVER CURRENT SENSE COMPARATOR gm ERROR AMP CC2 CC1 RA RB VIN CIN CSS CBOOST VOUT COUT CVCC – + RC

diode with a MOSFET in a step-down application. voltage returns to regulation. resistor (see the Typical Application on the front page). in the “Application Information” section. Figure 1. VCC Regulator Continuous Operating Conditions

3724 F01

either the start of the next cycle or until the bootstrapped capacitor is fully charged. MOSFET Driver The L T3724 contains a high speed boosted driver to turn on and off an external N-channel MOSFET switch. The MOSFET driver derives its power from the boost capacitor which is referenced to the SW pin and the source of the MOSFET . The driver provides a large pulse of current to turn on the MOSFET fast and minimize transition times. Multiple MOSFETs can be paralleled for higher current operation. To eliminate the possibility of shoot through between the MOSFET and the internal SW pull-down switch, an adap- tive nonoverlap circuit ensures that the internal pull-down switch does not turn on until the gate of the MOSFET is below its turn on threshold. Low Current Operation (Burst Mode Operation) To increase low current load efficiency, the L T3724 is capable of operating in Linear Technology’s proprietary Burst Mode operation where the external MOSFET operates intermittently based on load current demand. The Burst Mode function is disabled by connecting the BURST_EN pin to V CC and enabled by connecting the pin to SGND. When the required switch current, sensed via the VC pin voltage, is below 15% of maximum, Burst Mode operation is employed and that level of sense current is latched onto the IC control path. If the output load requires less than this latched current level, the converter will overdrive the output slightly during each switch cycle. This overdrive condition is sensed internally and forces the voltage on the V C pin to continue to drop. When the voltage on VC drops 150mV below the 15% load level, switching is disabled, and the L T3724 shuts down most of its internal circuitry, reducing total quiescent current to 100µA. When the converter output begins to fall, the V C pin voltage begins to climb. When the voltage on the VC pin climbs back to the 15% load level, the IC returns to normal operation and switching resumes. An internal clamp on the VC pin is set at 100mV below the output disable threshold, which limits the negative excursion of the pin voltage, minimizing the converter output ripple during Burst Mode operation. During Burst Mode operation, the V IN pin current is 20µA and the VCC current is reduced to 80µA. If no external drive is provided for VCC, all VCC bias currents originate from the VIN pin, giving a total VIN current of 100µA. Burst current can be reduced further when VCC is driven using an output derived source, as the V CC component of V IN current is then reduced by the converter duty cycle ratio. Start-Up The following section describes the start-up of the supply and operation down to 4V once the step-down supply is up and running. For the protection of the L T3724 and the switching supply, there are internal undervoltage lockout (UVLO) circuits with hysteresis on V IN, VCC and VBOOST, as shown in the Electrical Characteristics table. Start-up and continuous operation require that all three of these undervoltage lockout conditions be satisfied because the TG MOSFET driver is disabled during any UVLO fault condition. In startup, for most applications, V CC is powered from VIN through the high voltage linear regulator of the L T3724. This requires VIN to be high enough to drive the VCC voltage above its undervoltage lockout threshold. VCC, in turn, has to be high enough to charge the BOOST capacitor through an external diode so that the BOOST voltage is above its undervoltage lockout threshold. There is an NPN switch that pulls the SW node to ground each cycle during the TG power MOSFET off-time, ensuring the BOOST capacitor is kept fully charged. Once the supply is up and running, the output voltage of the supply can backdrive V CC through an external diode. Internal circuitry disables the high voltage regulator to conserve VIN supply current. Output voltages that are too low or too high to backdrive V CC require additional circuitry such as a voltage doubler or linear regulator . Once VCC is backdriven from a supply other than V IN, VIN can be reduced to 4V with normal operation maintained. (Refer to Functional Diagram)

The soft-start function controls the slew rate of the power supply output voltage during start-up. A controlled output voltage ramp minimizes output voltage overshoot, reduces inrush current from the V IN supply, and facilitates supply sequencing. A capacitor , CSS, connected between VOUT of the supply and the CSS pin of the IC, programs the slew rate. The capacitor provides a current to the CSS pin which is proportional to the dV/dt of the output voltage. The soft-start circuit overrides the control loop and adjusts the inductor current until the output voltage slew rate yields a 2µA current through the soft-start capacitor . If the current is greater than 2µA, then the current threshold set by the DC control voltage, V C, is decreased and the inductor current is lowered. This in turn lowers the output current and the output voltage slew rate is decreased. If the current is less than 2µA, then the current threshold set by the DC control voltage, V C, is increased and the inductor current is raised. This in turn increases the output current and the output voltage slew rate is increased. Once the output voltage is within 5% of its regulation voltage, the soft-start circuit is disabled and the main control regulates the output. The soft-start circuit is reactivated when the output voltage drops below 70% of its regulation voltage. Slope/Antislope Compensation The IC incorporates slope compensation to eliminate potential subharmonic oscillations in the current control loop. The IC’s slope compensation circuit imposes an artificial ramp on the sensed current to increase the rising slope as duty cycle increases. Unfortunately, this additional ramp typically affects the sensed current value, thereby reducing the achievable current limit value by the same amount as the added ramp represents. As such, the current limit is typically reduced as the duty cycle increases. The L T3724, however , contains antislope compensation circuitry to eliminate the current limit reduction associated with slope compensation. As the slope compensation ramp is added to the sensed current, a similar ramp is added to the current limit threshold. The end result is that the current limit is not compromised so the L T3724 can provide full power regardless of required duty cycle. Shutdown The L T3724 includes a shutdown mode where all the internal IC functions are disabled and the V IN current is reduced to less than 10µA. The shutdown pin can be used for undervoltage lockout with hysteresis, micropower shut- down or as a general purpose on/off control of the converter output. The shutdown function has two thresholds. The first threshold, a precision 1.23V threshold with 120mV of hysteresis, disables the converter from switching. The second threshold, approximately a 0.7V referenced to SGND, completely disables all internal circuitry and reduces the V IN current to less than 10µA. See the Application Information section for more information. (Refer to Functional Diagram)

The basic L T3724 step-down (buck) application, shown in the Typical Application on the front page, converts a larger positive input voltage to a lower positive or negative output voltage. This Application Information section assists selection of external components for the requirements of the power supply. R SENSE Selection The current sense resistor , RSENSE, monitors the inductor current of the supply (See Typical Application on front page). Its value is chosen based on the maximum required output load current. The L T3724 current sense amplifier has a maximum voltage threshold of, typically, 150mV . Therefore, the peak inductor current is 150mV/R SENSE. The maximum output load current, IOUT(MAX), is the peak inductor current minus half the peak-to-peak ripple cur - rent, ∆IL. Allowing adequate margin for ripple current and external component tolerances, R SENSE can be calculated as fol - lows: RSENSE = 100mV IOUT(MAX) Typical values for RSENSE are in the range of 0.005Ω to 0.05Ω. Inductor Selection The critical parameters for selection of an inductor are minimum inductance value, volt-second product, satura- tion current and/or RMS current. The minimum inductance value is calculated as follows: L ≥ VOUT • VIN(MAX) – VOUT fSW •VIN(MAX) •∆IL fSW is the switch frequency (200kHz). The typical range of values for ∆IL is (0.2 • IOUT(MAX)) to (0.5 • IOUT(MAX)), where IOUT(MAX) is the maximum load current of the supply. Using ∆IL = 0.3 • IOUT(MAX) yields a good design compromise between inductor performance versus inductor size and cost. Higher values of ∆IL will increase the peak currents, requiring more filtering on the input and output of the supply. If ∆I L is too high, the slope compensation circuit is ineffective and current mode instability may occur at duty cycles greater than 50%. Lower values of ∆I L require larger and more costly magnetics. A value of ∆IL = 0.3 • I OUT(MAX) produces a ±15% of I OUT(MAX) ripple current around the DC output current of the supply. Some magnetics vendors specify a volt-second product in their datasheet. If they do not, consult the magnetics vendor to make sure the specification is not being exceeded by your design. The volt-second product is calculated as follows: Volt-second (µsec)= (VIN(MAX) – VOUT )•VOUT VIN(MAX) •fSW The magnetics vendors specify either the saturation cur- rent, the RMS current or both. When selecting an inductor based on inductor saturation current, use the peak cur - rent through the inductor , IOUT(MAX) + ∆IL/2. The inductor saturation current specification is the current at which the inductance, measured at zero current, decreases by a specified amount, typically 30%. When selecting an inductor based on RMS current rating, use the average current through the inductor , I OUT(MAX). The RMS current specification is the RMS current at which the part has a specific temperature rise, typically 40°C, above 25°C ambient. After calculating the minimum inductance value, the volt- second product, the saturation current and the RMS current for your design, select an off-the-shelf inductor . A list of magnetics vendors can be found at www.linear .com, or contact the Linear Technology Application Department. For more detailed information on selecting an inductor , please see the “Inductor Selection” section of Linear Technology Application Note 44. Step-Down Converter: MOSFET Selection The selection criteria of the external N-channel standard level power MOSFET include on resistance(R DS(ON)), re- verse transfer capacitance (CRSS), maximum drain source voltage (V DSS), total gate charge (Q G), and maximum continuous drain current. APPLICATIONS INFORMATION

For maximum efficiency, minimize R DS(ON) and C RSS. Low RDS(ON) minimizes conduction losses while low CRSS minimizes transition losses. The problem is that RDS(ON) is inversely related to CRSS. Balancing the transition losses with the conduction losses is a good idea in sizing the MOSFET . Select the MOSFET to balance the two losses. Calculate the maximum conduction losses of the MOSFET : PCOND = (IOUT(MAX) )2 VOUT VIN (RDS(ON) ) Note that RDS(ON) has a large positive temperature depen- dence. The MOSFET manufacturer’s data sheet contains a curve, RDS(ON) vs Temperature. Calculate the maximum transition losses: PTRAN = (k)(VIN)2 (IOUT(MAX))(CRSS)(fSW) where k is a constant inversely related to the gate driver current, approximated by k = 2 for L T3724 applications. The total maximum power dissipation of the MOSFET is the sum of these two loss terms: PFET(TOTAL) = PCOND + PTRAN To achieve high supply efficiency, keep the PFET(TOTAL) to less than 3% of the total output power . Also, complete a thermal analysis to ensure that the MOSFET junction temperature is not exceeded. TJ = TA + PFET(TOTAL) • θJA where θJA is the package thermal resistance and TA is the ambient temperature. Keep the calculated T J below the maximum specified junction temperature, typically 150°C. Note that when V IN is high, the transition losses may dominate. A MOSFET with higher RDS(ON) and lower CRSS may provide higher efficiency. MOSFETs with higher volt- age VDSS specification usually have higher R DS(ON) and lower CRSS. Choose the MOSFET V DSS specification to exceed the maximum voltage across the drain to the source of the MOSFET , which is VIN(MAX) plus any additional ringing on the switch node. Ringing on the switch node can be greatly reduced with good PCB layout and, if necessary, an RC snubber . The internal V CC regulator operating range limits the maxi- mum total MOSFET gate charge, QG, to 90nC. The QG vs VGS specification is typically provided in the MOSFET data sheet. Use QG at VGS of 8V . If VCC is back driven from an external supply, the MOSFET drive current is not sourced from the internal regulator of the L T3724 and the Q G of the MOSFET is not limited by the IC. However , note that the MOSFET drive current is supplied by the internal regulator when the external supply back driving V CC is not available such as during startup or short-circuit. The manufacturer’s maximum continuous drain current specification should exceed the peak switch current, I OUT(MAX) + ∆IL/2. During the supply startup, the gate drive levels are set by the V CC voltage regulator , which is approximately 8V . Once the supply is up and running, the VCC can be back driven by an auxiliary supply such as VOUT. It is important not to exceed the manufacturer’s maximum V GS specification. A standard level threshold MOSFET typically has a V GS maximum of 20V . Step-Down Converter: Rectifier Selection The rectifier diode (D1 on the Functional Diagram) in a buck converter generates a current path for the inductor current when the main power switch is turned off. The rectifier is selected based upon the forward voltage, re- verse voltage and maximum current. A Schottky diode is recommended. Its low forward voltage yields the lowest power loss and highest efficiency. The maximum reverse voltage that the diode will see is V IN(MAX). In continuous mode operation, the average diode cur - rent is calculated at maximum output load current and maximum V IN: IDIODE(AVG) = IOUT(MAX) VIN(MAX) − VOUT VIN(MAX) To improve efficiency and to provide adequate margin for short-circuit operation, a diode rated at 1.5 to 2 times the maximum average diode current, I DIODE(AVG), is recom- mended.

Step-Down Converter: Input Capacitor Selection A local input bypass capacitor is required for buck convert- ers because the input current is pulsed with fast rise and fall times. The input capacitor selection criteria are based on the bulk capacitance and RMS current capability. The bulk capacitance will determine the supply input ripple voltage. The RMS current capability is used to keep from overheating the capacitor . The bulk capacitance is calculated based on maximum input ripple, ∆V IN: CIN(BULK) = IOUT(MAX) •VOUT ∆VIN •fSW •VIN(MIN) ∆VIN is typically chosen at a level acceptable to the user . 100mV-200mV is a good starting point. Aluminum elec- trolytic capacitors are a good choice for high voltage, bulk capacitance due to their high capacitance per unit area. The capacitor’s RMS current is: ICIN(RMS) = IOUT VOUT (VIN – VOUT ) (VIN)2 If applicable, calculate it at the worst case condition, VIN = 2V OUT. The RMS current rating of the capacitor is specified by the manufacturer and should exceed the calculated I CIN(RMS). Due to their low ESR (Equivalent Series Resistance), ceramic capacitors are a good choice for high voltage, high RMS current handling. Note that the ripple current ratings from aluminum electrolytic capacitor manufacturers are based on 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. The combination of aluminum electrolytic capacitors and ceramic capacitors is an economical approach to meet - ing the input capacitor requirements. The capacitor volt- age rating must be rated greater than V IN(MAX). Multiple capacitors may also be paralleled to meet size or height requirements in the design. Locate the capacitor very close to the MOSFET switch and use short, wide PCB traces to minimize parasitic inductance. Step-Down Converter: Output Capacitor Selection The output capacitance, C OUT, selection is based on the design’s output voltage ripple, ∆VOUT, and transient load requirements. ∆VOUT is a function of ∆I L and the C OUT ESR. It is calculated by: ∆VOUT = ∆IL • ESR + 1 (8 •fSW •COUT ) The maximum ESR required to meet a ∆VOUT design requirement can be calculated by: ESR(MAX)= (∆VOUT )(L)(fSW ) VOUT • 1– VOUT VIN(MAX) Worst-case ∆VOUT occurs at highest input voltage. Use paralleled multiple capacitors to meet the ESR require - ments. Increasing the inductance is an option to lower the ESR requirements. For extremely low ∆VOUT, an additional LC filter stage can be added to the output of the supply. Application Note 44 has some good tips on sizing an ad- ditional output filter . Output Voltage Programming A resistive divider sets the DC output voltage according to the following formula: R2= R1 VOUT 1.231V – 1 The external resistor divider is connected to the output of the converter as shown in Figure 2. Tolerance of the feedback resistors will add additional error to the output voltage. Example: V OUT = 12V; R1 = 10kΩ R2= 10kΩ 12V 1.231V − 1  = 87.48kΩ −use 86.6kΩ 1%

lockout is disabled and the supply turns on. example the VSUPPL Y(OFF) would be 13.2V . the L T3724 regulator output. IN through a large value pull-up resistor . maximum input current rating of 1mA is not exceeded. regulation is achieved, the soft-start circuit is disabled. controlled recovery from a “brown-out” condition. Figure 2. Output Voltage Feedback Divider Figure 3. Undervoltage Lockout Circuit

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RSS is typically set to 200k for most applications. reach this value before the soft-start function is engaged. Which is typically 0.64V for RSS = 200k. modulation of the VC pin before finalizing the design. soft-start cycle, converter output ripple should be reduced. tance and/or reducing output capacitor ESR. Figure 6. Desirable Soft-Start Characteristic Figure 5. Soft-Start Characteristic

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relation is useful as a worst-case scenario. may be useful even if the soft-start function is disabled. be modified by adding an additional diode and resistor .

• I MAX when VOUT = 0V . Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. Express percent efficiency as: % Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are individual loss terms as a percent- age of input power . Although all dissipative elements in the circuit produce losses, four main contributors usually account for most of the losses in L T3724 circuits: 1. L T3724 V IN and VCC current loss 2. I2R conduction losses 3. MOSFET transition loss 4. Schottky diode conduction loss 1. The V IN and VCC currents are the sum of the quiescent currents of the L T3724 and the MOSFET drive currents. The quiescent currents are in the L T3724 Electrical Char- acteristics table. The MOSFET drive current is a result of charging the gate capacitance of the power MOSFET each cycle with a packet of charge, Q G. QG is found in the MOSFET data sheet. The average charging current is calculated as Q G • fSW. The power loss term due to these currents can be reduced by backdriving VCC with a lower voltage than VIN such as VOUT.

Figure 7. Current Limit Foldback Circuit Figure 8. Current Limit Foldback Circuit for Applications

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1. I2R losses are calculated from the DC resistances of the MOSFET , the inductor , the sense resistor , and the input and output capacitors. In continuous conduction mode the aver- age output current flows through the inductor and RSENSE but is chopped between the MOSFET and the Schottky diode. The resistances of the MOSFET (R DS(ON)) and the RSENSE multiplied by the duty cycle can be summed with the resistances of the inductor and R SENSE to obtain the total series resistance of the circuit. The total conduction power loss is proportional to this resistance and usually accounts for between 2% to 5% loss in efficiency. 3. T ransition losses of the MOSFET can be substantial with input voltages greater than 20V . See MOSFET Selection section. 4. The Schottky diode can be a major contributor of power loss especially at high input to output voltage ratios (low duty cycles) where the diode conducts for the majority of the switch period. Lower V f reduces the losses. Note that oversizing the diode does not always help because as the diode heats up the V f is reduced and the diode loss term is decreased. I2R losses and the Schottky diode loss dominate at high load currents. Other losses including C IN and COUT ESR dissipative losses and inductor core losses generally ac- count for less than 2% total additional loss in efficiency. PCB Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation. These items are illustrated graphically in the layout diagram of Figure 9. 1. Keep the signal and power grounds separate. The signal ground consists of the L T3724 SGND pin, the exposed pad on the backside of the L T3724 IC and the (–) terminal of V OUT. The signal ground is the quiet ground and does not contain any high, fast currents. The power ground consists of the Schottky diode anode, the (–) terminal of the input capacitor , and the ground return of the V CC capacitor . This ground has very fast high currents and is considered the noisy ground. The two grounds are connected to each other only at the (–) terminal of V OUT. 2. Use short wide traces in the loop formed by the MOSFET , the Schottky diode and the input capacitor to minimize high frequency noise and voltage stress from parasitic inductance. Surface mount components are preferred. 3. Connect the V FB pin directly to the feedback resistors independent of any other nodes, such as the SENSE– pin. Connect the feedback resistors between the (+) and (–) terminals of COUT. Locate the feedback resistors in close proximity to the L T3724 to keep the high impedance node, V FB, as short as possible. 4. Route the SENSE – and SENSE + traces together and keep as short as possible. 5. Locate the VCC and BOOST capacitors in close proximity to the IC. These capacitors carry the MOSFET driver’s high peak currents. Place the small signal components away from high frequency switching nodes (BOOST , SW , and TG). In the layout shown in Figure 9, place all the small signal components on one side of the IC and all the power components on the other . This helps to keep the signal and power grounds separate. 6. A small decoupling capacitor (100pF) is sometimes useful for filtering high frequency noise on the feedback and sense nodes. If used, locate as close to the IC as possible. 7. The L T3724 packaging will efficiently remove heat from the IC through the exposed pad on the backside of the part. The exposed pad is soldered to a copper footprint on the PCB. Make this footprint as large as possible to improve the thermal resistance of the IC case to ambient air . This helps to keep the L T3724 at a lower temperature. 8. Make the trace connecting the gate of MOSFET M1 to the TG pin of the L T3724 short and wide.

This is only an issue for supplies with VOUT < 7V . Figure 9. L T3724 Layout Diagram (See PCB Layout Checklist).

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12V to 24V/50W Boost (Step-Up) Converter Efficiency and Power Loss vs Load Current 4.7M 40.2k 187k 10k V IN SHDN CSS BURST_EN VFB VC SGND BOOST TG SW VCC PGND SENSE+ SENSE– SBM540

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1µF 25V 1500pF 0.1µF 25V C OUT1 330µF 35V C OUT2 2.2µF x3 50V C IN = SANYO, 25SVP33M L1 = VISHAY, IHLP-5050FD-011 M1 = SILICONIX, Si7370DP C OUT1 = SANYO, 35CV330AXA COUT2 = TDK, C4532X7R1H225K D2 = DIODESINC., SBM540 R SENSE = IRC LRF2512-01-R0I5-F CIN 33µF ×2 25V VIN 8V TO16V RSENSE 0.015Ω 10µH VOUT 24V AT 50WRCSS 200k BAV99 LOAD CURRENT (A) 0.1 EFFICIENCY (%) POWER LOSS (W) 100 3.0 2.5 2.0 1.5 1.0 0.5 1 10

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VIN = 8V VIN = 12V VIN = 16V LOSS VIN = 12V

High Voltage LED Driver with Dimmer Control VIN SHDN CSS BURST_EN VFB VC SGND BOOST TG SW VCC PGND SENSE+ SENSE– ZXMN10A07F 2N7002 OPTIONAL DIMMER CONTROL 1kHz

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1µF 16V 100pF 4.7M RSENSE 0.5Ω 300µH LED VIN 8V TO 60V C1 = OPTIONAL TO REDUCE LED RIPPLE CURRENT C IN = TDK, C4532X7R2A225K D1 = DIODESINC., B170 M1 = ZETEX, ZXMN10A07F R SENSE = VISHAY, WSL2010R0150FEA L1 = COIL TRONICS, CTX300-4 ADJUST ILED: ILED = 0.15V RSENSE (OPTIONAL)C IN 22µF B170

4.5V to 20V Input to 12V at 25W Output SEPIC Converter with 60V Input T ransient Capability Efficiency and Power Loss vs Load Current RB 49.9k RA 100k 40.2k RSENSE 0.010Ω 130k 14.7k SHDN C SS 200k BURST_EN VFB VC SGND TG SW VCC PGND SENSE+ SENSE– 680pF 120pF 47k 0.1µF 390pF CIN2 25V 1µF CIN1 22µF 25V V IN 4.5V TO 20V TO 60V TRANSIENT D1A GSD2004 D1N4148 20µH 20µH D1B GSD2004 VOUT 12V AT 25W COUT2 22µF

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1µF 25V COUT1 330µF 25V 16VC6 56pF 10Ω 10Ω 22µF 25V C5, CIN1, COUT2 = TDKC453X7R1E226M COUT1 = SANYO, OS-CON 16SVP330M D2 = ON SEMI, MBRD660 L1 = COILCRAFT VERSAPAC VP5-D83 M1 = VISHAY, Si7852DP LOAD CURRENT (A) 0.1 EFFICIENCY (%) POWER LOSS (W) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 1 10

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VIN = 20V VIN = 10V VIN = 15V LOSS VIN = 15V TYPICAL APPLICATIONS

12V Step-Down with VCC Back Driven from VOUT and Ceramic Capacitor in Output Filter 49.9k 20Ω 499k 15k 130k 14.7k V IN SHDN CSS RCSS 200k BURST_EN VFB VC SGND BOOST TG SW VCC PGND SENSE+ SENSE–

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1µF 16V 0.1µF 16V 3300pF CIN 100µF 100V 2.2µF x2 100V V IN 15V TO 60V D2B BAV99 47µH D2A BAV99 RSENSE 0.020Ω VOUT 12V AT 50W COUT 33µF x3 16V C IN: TDK, C4532X7R2A225MT COUT: TDK, C4532X7R1C336MT D1: DIODESINC., PDS5100H L1: COEV DU1971-470M M1: VISHAY Si7852DP Si7852DP

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. FE16 (BC) TSSOP REV I 1210 0.09 – 0.20 (.0035 – .0079) 0° – 8° 0.25 REF 0.50 – 0.75 (.020 – .030) 4.30 – 4.50* (.169 – .177) 1 3 4 5 6 7 8 DETAIL B IS THE PART OF THE LEAD FRAME FEATURE FOR REFERENCE ONLY NO MEASUREMENT PURPOSE 4.90 – 5.10* (.193 – .201) 16 1514 13 12 11 1.10 (.0433) MAX 0.05 – 0.15 (.002 – .006) 0.65 (.0256) BSC 2.94 (.116) 0.48 (.019) REF 0.51 (.020) REF 0.195 – 0.30 (.0077 – .0118) TYP 2RECOMMENDED SOLDER PAD LAYOUT 0.45 ±0.05

0.65 BSC

4.50 ±0.10 6.60 ±0.10 1.05 ±0.10 2.94 (.116) 3.58 (.141) 3.58 (.141) MILLIMETERS (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE SEE NOTE 4 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT 6.40 (.252) BSC 16-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663 Rev I) Exposed Pad Variation BC DETAIL B PACKAGE DESCRIPTION

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER D 3/11 Deleted last paragraph of Description Minor text edits made to SW and BOOST pin descriptions in Pin Functions section Minor text edits made to Main Control Loop and Current Limit/Short Circuit sections in Operations Revised High Voltage LED Driver with Dimmer Control in Typical Applications Revised Typical Application drawing and Related Parts list (Revision history begins at Rev D)

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com  LINEAR TECHNOLOGY CORPORATION 2005 LT 0311 REV D • PRINTED IN USA RELATED PARTS TYPICAL APPLICATION Inverting –12V 1.5A Converter CC2 680pF CC1 120pF R6, 40.2k CSS 1000pF RCSS 200k 10.2k 88.7k 0.1µF 0.1µF 16V 1µF 16V V IN 18V TO 36V VIN SHDN CSS VFB VC GND BOOST TG SW VCC PGND SENSE+ SENSE– VOUT –12V 1.5A COUT1 330µF 16V C IN1 220µF 50V 47µH D2D1BD1A R SENSE 0.040Ω D1 = BAV99 D2 = ON SEMI, MBRD350 L1 = COEV , DU1311-470M M1 = VISHAY, Si7370DP C IN1 = SANYO, 50CV220KX COUT1 = SANYO, 16SVP330M

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PART NUMBER DESCRIPTION COMMENTS L T3845A 60V , Low IQ, High Voltage Synchronous Step-Down DC/DC Controller Adjustable Fixed Frequency 100kHz to 500kHz, 4V≤ VIN ≤ 60V , 1.23V ≤ VOUT ≤ 36V , IQ = 120µA, TSSOP-16 L TC3891 60V , Low IQ, High Voltage Synchronous Step-Down DC/DC Controller Phase-Lockable Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 60V , 0.8V ≤ VOUT ≤ 24V , IQ = 50µA L T3844 60V , Low IQ, Single Output Step-Down DC/DC Controller Synchronizable Fixed Frequency 50kHz to 600kHz, 4V≤ VIN ≤ 60V , 1.23V ≤ VOUT ≤ 36V , IQ = 120µA, TSSOP-16 L T3741 High Power , Constant Current, Constant Voltage, Step-Down Controller Fixed 200kHz to 1MHz Operating Frequency, ±6% Current Regulation, 6V≤ V IN ≤ 36V , VOUT Up to (VIN - 2V) L TC3824 60V , Low IQ, Step-Down DC/DC Controller with 100% Duty Cycle Selectable Fixed Frequency 200kHz to 600kHz, 4V≤ VIN ≤ 60V , 0.8V ≤ VOUT ≤ VIN, IQ = 40µA, MSOP-10E L TC3834/L TC3834-1 L TC3835/L TC3835-1 Low I Q, Single Output Synchronous Step-Down DC/DC Controller with 99% Duty Cycle Phase-Lockable Fixed Frequency 140kHz to 650kHz, 4V≤ VIN ≤ 36V , 0.8V ≤ VOUT ≤ 10V , IQ = 30µA/80µA L TC3859 Low IQ, T riple Output Buck/Buck/Boost Synchronous DC/DC Controller All Outputs Remain in Regulation Through Cold Crank 2.5V≤ VIN ≤ 38V , VOUT(BUCKS) Up to 24V , VOUT(BOOST) Up to 60V , IQ = 55µA