LT3710

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ary winding, multiple output power supplies. tinuous conduction mode improves light load efficiency. , LTC and LT are registered trademarks of Linear Technology Corporation. Figure 1. Simplified Single Secondary Winding 3.3V and 1.8V Output Isolated DC/DC Converter

3710 F01

Operating Junction Temperature Range Note: If higher than 30V on SYNC pin is needed, add a 10k resistor in series with the pin. ORDER PART NUMBER TJMAX = 125°C, qJA = 38°C/W EXPOSED PAD IS SGND (PIN 17) MUST BE CONNECTED TO PGND AND SOLDERED TO PCB Consult LTC Marketing for parts specified with wider operating temperature ranges. LT3710EFE ABSOLUTE AXI U RATI GSW WW U PACKAGE/ORDER I FOR ATIOUU W (Note 1) ELECTRICAL CHARACTERISTICSThe l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 11V, operating maximum VCC = 24V, no load on any outputs unless otherwise noted. TOP VIEW FE PACKAGE 16-LEAD PLASTIC TSSOP BOOST TGATE SW CSET SYNC ILCOMP SS V FB GBIAS BGATE PGND V CC CL– CL+ VAOUT BGS PARAMETER CONDITIONS MIN TYP MAX UNITS Overall Supply Voltage (VCC) l 82 4 V Supply Current (IVCC) V A OUT £ 1.2V (Switching Off) 7 12 mA Boost Pin Current V BOOST = VSW + 8V, 0V £ VSW £ 24V TGATE High 2 3 mA TGATE Low 2 3 mA Voltage Amplifier VA Reference Voltage (VREF) 0.788 0.8 0.812 V l 0.780 0.820 V FB Pin Input Current V FB = VREF 0.2 0.5 mA VAOUT High 4.5 V VAOUT Low 0.8 V VAOUT Source Current l 100 300 mA Open-Loop Gain 100 dB Gain Bandwidth Product 10 MHz Soft-Start Current 51 2 1 8 mA Current Limit Amplifier CA1 Current Limit Threshold at (VCL+ – VCL–) Common Mode Voltage from 0V to V CC – 2.5V l 50 70 85 mV BGATE Off Threshold at (VCL+ – VCL–), BGS Pin Float Common Mode Voltage from 0V to V CC – 2.5V 0 8 15 mV Switching Off Threshold at ILCOMP V ILCOMP 0.15 V Input Current (CL+, CL–)V CL+ = VCL– 100 mA FE PART MARKING 3710EFE

Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT3710E is guaranteed to meet performance specifications from 0°C to 125°C. Specifications over the –40 °C to 125°C operating temperature range are assured by design, characterization and correlation with statistical process controls. PARAMETER CONDITIONS MIN TYP MAX UNITS ELECTRICAL CHARACTERISTICSThe l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 11V, operating maximum VCC = 24V, no load on any outputs unless otherwise noted. Oscillator Switching Frequency C S = 500pF (No SYNC) l 170 200 240 kHz CS = 333pF (No SYNC) l 240 280 340 kHz Synchronization Frequency Range C S = 500pF l 245 400 kHz CS = 333pF l 345 500 kHz CSET Ramp Valley Voltage C S = 1000pF (No SYNC) 0.90 1.15 1.4 V CSET Peak-to-Peak Voltage C S = 1000pF (No SYNC) 2.4 V Synchronization Pulse Threshold on SYNC Pin Falling Edge V SYNC 2.5 V Maximum Duty Cycle V FB = VREF – 5mV, CS > 500pF l 85 90 % Gate Drivers (TGATE, BGATE) VGBIAS IGBIAS < 25mA l 7.5 8.0 8.5 V VTGATE High (VTGATE – VSW)I TGATE < 50mA, VBOOST = VGBIAS – 0.5V l 567 V VBGATE High I BGATE < 50mA l 5 6 7.5 V VTGATE Low (VTGATE – VSW)I TGATE < –50mA l 0.5 V VBGATE Low I BGATE < –50mA l 0.5 V Peak Gate Drive Current 10nF Load 1 A Gate Drive Rise and Fall Time 1nF Load 25 ns TYPICAL PERFOR A CE CHARACTERISTICSUW IGBIAS (mA) VGBIAS (V) 8.1 8.0 7.9 7.8 7.7

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–40°C 25°C 125°C VCC (V) 8 1 01 21 41 61 82 02 22 4 ICC (mA)

3710 G02

TA = 25°C FREQUENCY (Hz) GAIN (dB) 120 –20 PHASE (DEG) –50 –100 –150 –180

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0dB, 10MHz (–111°) GAIN 100 1k 10k 100k 1M 10M 100M TA = 25°C VGBIAS vs IGBIAS over Junction Temperature I CC vs VCC (Switching Off) Voltage Amplifier VA Gain and Phase Note 3: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability.

TYPICAL PERFOR A CE CHARACTERISTICSUW VCC (V) 10 15 20 25 ∆VREF (mV) ∆FREQ (kHz)1

3710 G04

∆VREF CSET = 500pF TA = 25°C ∆FREQ JUNCTION TEMPERATURE (°C) –20–40 25 07 5 50 125 VREF (V) 0.801 0.800 0.799 0.798

3710 G05

CSET = 500pF CSET (pF) 400200 600 800 1000 FREQUENCY (kHz) 500 400 300 200 100 MAXIMUM DUTY CYCLE 1.00 0.95 0.90 0.85 0.80 0.75 0.70

3710 G07

TA = 25°C TIME IGBIAS (mA) 300 250 200 150 100 VGBIAS (V) 500µs

3710 G08

CGBIAS = 2.2µF IGBIAS VCL+ – VCL– (mV) 6050 70 80 90 VAOUT (V)

3710 G09

VCC = 11V VCLN = 5V TA = 25°C CSET VALLEY DVREF vs VCC, DFREQ vs VCC VREF vs Temperature CSET vs Switching Frequency GBIAS vs IGBIAS (Charging 2.2mF) Current Limit Amplifier CA1 Gain at VCC = 11V, VCL– = 5V JUNCTION TEMPERATURE (°C) –20–40 25 07 5 50 125 SWITCHING FREQUENCY (kHz) 195 200 205 210 215

3710 G06

CSET = 500pF Frequency vs Temperature

BOOST (Pin 1): Topside (Boosted) Driver Supply. This pin is used to bootstrap and supply the topside power switch gate drive circuitry. In normal operation VBOOST is powered from the internally generated 8V GBIAS, VBOOST = VSW + 8.2V when TGATE is on. TGATE (Pin 2): Topside (Boosted) N-Channel MOSFET Driver. When TGATE is on, the voltage is equal to VSW + 6V. SW (Pin 3): Switch Node Connection to Inductor. CSET (Pin 4): Oscillator Timing Pin. The capacitor on this pin sets the PWM switching frequency. SYNC (Pin 5): Synchronization Input. This pin should be connected to the secondary side output of the power transformer with a series resistor. A filtering capacitor of 10pF is recommended. ILCOMP (Pin 6): Current Limit Amplifier Compensation Node. At current limit, CA1 pulls down on this pin to regulate the output current. SS (Pin 7): Soft-Start. A capacitor on this pin sets the output ramp up rate. The typical time for SS to reach the programmed level is (C • 0.8V)/10mA. V FB (Pin 8): Voltage Amplifier Inverting Input. A resistor divider to this pin sets the output voltage. Nominal voltage at this pin is 0.8V. PI FU CTIO S UU U BGS (Pin 9): Bottom Gate Switching Control. CA2 moni- tors the inductor current and prohibits BGATE from turn- ing on when the inductor current is low (below 8mV across the current sense resistor RS1) to allow discontinous mode operation. Grounding this pin disables comparator CA2. VA OUT (Pin 10): Voltage Amplifier Output. CL+ (Pin 11): Current Limit Amplifier Positive Input. The threshold is set at 70mV. CL– (Pin 12): Current Limit Amplifier Negative Input. When used, CL– is connected to the output capacitor side of the current + sense resistor and CL+ is connected to the inductor side of the current sense resistor. VCC (Pin 13): Supply of the IC. For proper bypassing, a low ESR capacitor is required. PGND (Pin 14): Ground of the Bottom Side N-Channel MOSFET Driver. BGATE (Pin 15): Bottom Side N-Channel MOSFET Driver. GBIAS (Pin 16): 8V Regulator Output for Boostrapping VBOOST . A bypass capacitor of at least 2mF is needed. Exposed Pad (Pin 17): Connect to PGND (Pin 14).

1.6V 8mV A10 PWM 3.5V 2.5V 70mV VA CA1 BGATE 2.5V TGATE2 SW3 GBIAS 2µF BOOST1 BGATE15 PGND14 BGS9 IL RS1 0.3µF CL+ CL– VAOUT10 VFB8 SYNC 5 CSET 4 2nF 500pF COUT 100µF VOUT2 D4I1 10µA D7 VREF 0.8V 5nF SS 500pF NOTE: EXPOSED PAD (PIN 17) IS SGND AND MUST BE CONNECTED TO PGND (PIN 14).SGND CS 10pF 2µF VS VCC 13 ONE SHOT OSC RS RESET CA2 ILCOMP6 100pF 3710 BD +D5 200µA E2 SHUTDOWN RS 10k IO BLOCK DIAGRA W

3710 F02

Figure 2. Leading Edge Modulation, former primary side peak current sensing undisturbed. tolerances taken into account. because all of the power is processed in series. top MOSFET M1 and turning on the bottom MOSFET M2. 0.8 is the tolerance of fOSC. fOSC should be set below 136kHz. For fOSC = 100kHz, CSET = 1022.5pF. voltage becomes zero. The next cycle repeats.

Output N-Channel MOSFET Drivers The LT3710 employs high speed N-channel MOSFET synchronous drivers to achieve high system efficiency. GBIAS is the 8V regulator output to bias and supply the drivers and should be properly bypassed with a low ESR capacitor to ground plane. A Schottky catch diode is required on the switch node. Light Load Operation If the BGS pin is grounded, the LT3710 stays in continuous mode independent of load condition except in soft-start operation (see Soft-Start section). If the BGS pin is left open, under light load and V RS1 drops below 8mV, BGATE will be turned off(see comparator CA2 of Block Diagram) and the LT3710 goes into discontinous mode operation. Current Limit Current limit is set by the 70mV threshold across CL+ and CL–, the inputs of the amplifier CA1. By connecting an external resistor RS1(see Block Diagram), the current limit is set for 70mV/R S1. R6 and C6 stablize the current limit loop. If current limit is not used, both CL + and CL – should be grounded and the BGS pin should also be grounded to disable comparator CA2. Soft-Start and Shutdown During soft-start, VSS is the reference voltage that controls the output voltage and the output ramps up following VSS. The effective range of VSS is from 0V to VREF. The typical time for the output to reach the programmed level is (C • 0.8V)/10mA. During start up, BGATE will stay off until V SS gets up to 1.6V. This prevents the bottom MOSFET from turning on if the output is precharged. To shut down the LT3710, the SS pin should be pulled below 50mV by a VN2222 type N-channel transistor. Note that during shutdown BGATE will be locked off when V SS drops below 0.6V. This prevents the bottom MOSFET from APPLICATIO S I FOR ATIOWU UU discharging the output, which would cause the output to undershoot below ground. Layout Considerations For maximum efficiency, the switching rise and fall times are less than 20ns. To prevent radiation, the power MOSFETs, SW pin and input bypass capacitor leads should be kept as short as possible. A ground plane should be used under the switching circuitry to prevent interplane coupling and to act as a thermal spreading path. Note that the bottom metal of the package is the heat sink, as well as the IC signal ground, and must be soldered to the ground plane. Output Voltage Programming The feedback reference voltage is 0.8V. The output voltage can be easily programmed by the resistor divider, R3 and R4, as shown in the Block Diagram. V R ROUT2 08 1 3 4=+ æ Łç ö ł÷.· Filtering on the SYNC Input It is necessary to add RC filtering on the SYNC input of the LT3710 to eliminate the negative glitch at the turn on of the top MOSFET. When the top MOSFET M1 turns on, the transformer secondary current instantly changes from the original first output inductor current to the sum of two output inductor currents. The high di/dt on the trans- former leakage inductance causes the transformer sec- ondary voltage V S to drop for a short interval. If the leakage inductance is large enough, the VS dip will be lower than the synchronization threshold (about 2.5V), falsely trig- gering the synchronization. The top MOSFET is turned off immediately. As a result, the output voltage will not be regulated properly. A filter circuit is needed to ensure proper operation. A small RC filter with R S = 10k and CS = 10pF are typical.

The key parameters for choosing the inductor include inductance, RMS and saturation current ratings and DCR. The inductance must be selected to achieve a reasonable value of ripple current, which is determined by: D= -()I VD fLL OUT2 12· Typically, the inductor ripple current is designed to be 20% to 40% of the maximum output current. The RMS current rating must be high enough to deliver the maximum output current. A sufficient saturation current rating should prevent the inductor core from saturating. These two current ratings can be determined by: II I II I RMS O LMAX SAT O LMAX ‡+ D ‡+ D 2 2 where IO is the maximum output current and DILMAX is the maximum peak-to-peak inductor ripple current. To optimize the efficiency, we usually choose the inductor with the minimum DCR if the inductance and current ratings are the same. Power MOSFET Selection The LT3710 drives two external N-channel MOSFETs to deliver high currents at high efficiency. The gate drive voltage is typically 6.5V. The key parameters for choos- ing MOSFETs include drain to source voltage rating VDSS and RDS(ON) at 6.5V gate drive. Note that the transformer secondary voltage waveform will overshoot at its rising edge due to the ringing between transformer leakage inductance and parasitic capacitance. The V DSS of both top and bottom MOSFETs must be sufficiently higher than the maximum overshoot. It is recommended that an RC snubber or a voltage clamping circuitry be placed across the transformer secondary winding to limit the V S overshoot. The RDS(ON) of the MOSFETs should be selected to deliver the required current at the desired efficiency as well as to meet the thermal requirement of the MOSFET package. The conduction power losses of the MOSFETs are: P M1 @ IO2 • RDS(ON)M1 • D2 PM2 @ IO2 • RDS(ON)M2 • (1 – D2) where IO is the maximum output current of LT3710 circuit, RDS(ON)M1 and RDS(ON)M2 are the on-resistance for the top and bottom MOSFETs, respectively. The RDS(ON) must be determined with 6.5V gate drive and the expected operat- ing temperature. A good number of high performance power MOSFET selections are available from Siliconix, International Rec- tifier and Fairchild. If the VDSS and RDS(ON) ratings are the same, the MOSFETs with the lowest gate charge QG should be chosen to minimize the power loss associated with the MOSFET gate drives, the switching transitions and the controller bias supply. Output Capacitor Selection The selection of the output capacitor is determined by the output ripple and load transient requirements. In low output voltage applications, always choose capacitors with low ESR. The output ripple voltage is approximated by: D» D + æ Łç ö ł÷V I ESR fCOUT L OUT where DIL is the inductor peak-to-peak ripple current. A partial list of low ESR high performance capacitor types includes SP capacitors from Panasonic and Cornell Dubilier, POSCAPs and OS-CON capacitors from Sanyo, T510 and T520 surface mount capacitors from Kemet. Design Example Figure 3 shows an application example for the LT3710. It is a dual output, high efficiency, isolated DC/DC power supply with 36V to 72V input, 3.3V/10A and 1.8V/10A outputs. The basic power stage topology is a 2-transistor APPLICATIO S I FOR ATIOWU UU

Figure 3a. 36V to 72V DC to 3.3V/10A and 1.8V/10A (or 2.5V/10A) Dual Output Isolated Power Supply-Basic Circuit (Part 1 of 2, See Next Page) APPLICATIO S I FOR ATIOWU UU VCC 1µF 82pF 1nF OVLO SHDN 1.24k 73.2k 20k 11V MMSZ5241B FZT 853 B0540W 10k 1N4148 270k 4.7µF 5VREF FSET 4.7nF SS BAS21 BAT54 T2 PULSE P2033 BAS21 BAT54 BAT54 ZVN3310F 9VC PGND VFB 37 4 THERM LT3781 SYNC SGND 52.3k 10Ω 470Ω 4.7k FZT690B 4.7µF 0.22µF NOTE UNLESS NOTED: ALL CAPS 25V ALL RESISTORS 0.1W, 5% Q1, Q2 SILICONIX Si7456DP V CCS CMPZ5240B 10V 3.3Ω 5VREF 143 3.3nF 4.7nF 0.1µF 5VREF 12SG 0.1µF ON/OFF SENSE BG BSTREF TG BAS21 DO1608C-105 VBST 220pF 1.5µF 100V 1.2µH COILCRAFT D01813P-122HC 1.5µF 100V 22nF 1nF

• • SYNC V FB OVPIN MARGIN ICOMP VDD OPTODRV VAUX 0.1µF0.01µF VOUT1 ISNS ISNSGND FG CG PGND GND LTC1698 PWRGD 1.24k 1.78k 2.43k 1043 V COMP VOUT1 TRIM

3710 F03a

3.01k B0540W 0.025Ω 1/2W 1nF 100V 2.2nF 250VAC 1nF 100V Si7440DP Si7440DP 470µF POSCAPMUR120S MUR120S

• • PULSE PA0191 VIN+ VIN– VOUT1+ 3.3V AT 10A VOUT RTN 10Ω 10Ω SEC 2.5µH SUMIDA CEP125-2R5 470µF POSCAP 1µF B0540W 1µF 0.1µF 330pF 10k

forward converter with synchronous rectification. The primary side controller uses an LT3781, a current mode 2-transistor forward controller with built-in MOSFET driv- ers. On the secondary side, an LTC1698 is used to provide the voltage feedback for the 3.3V output, as well as the gate drive for the synchronous MOSFETs. The error amplifier output is fed into the optocoupler and then relayed to LT3781 on the primary side to complete the 3.3V regula- tion. The 1.8V output is generated by the LT3710 circuit. A planar transformer PA0191 built by Pulse Engineering is employed as the power transformer in this design. This transformer is constructed on a PQ20 core with a nine turn primary winding, two turn secondary winding and seven turn auxiliary winding for the LT3781 bias supply. Because the maximum secondary voltage V SP is about 16V, 30V MOSFETs are chosen with the consideration that the secondary voltage overshoot is typically 20% to 30% of V SP. In this particular design, Si7440DP is selected due to its low R SD(ON), 30V V DSS rating and its compact and thermally enhanced PowerPak SO-8 package. The switching frequency of the circuit is about 230kHz. 1500V input to output isolation is provided. Additional features of this design include primary side on/off control, –5% secondary side trimming on the 3.3V output, input overvoltage protection and undervoltage lockout. The complete design will mount within a standard half brick PC board with about half inch height.Figure 3b. 36V to 72V DC to 3.3V/10A and 1.8V/10A Dual Output Isolated Power Supply (Part 2 of 2, See Previous Page) SYNC GBIAS BOOST VAOUT LT3710 3.3k0.033µF 0.01µF B340A VOUT2 1.8V/10A 1.8µH SUMIDA CEP125-IR8 0.006Ω 1%TGATE VFB SS SW 3VCC BGATE 15CSET4 BGS 9PGND14 CL+ 11ILCOMP6 CL– 12 PGND17 0.01µF 10pF 1µF VCCS 0.1µF 16V Si7440DP Si7440DP 220Ω

3710 F03b

4.7µF 16V CMDSH-3 CMDSH-3 10Ω 10k 10k180pF C37 680pF SEC 2.32k 3.01k 680µF POSCAP + 680µF POSCAP 4700pF APPLICATIO S I FOR ATIOWU UU Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 l FAX: (408) 434-0507 l www.linear.com ª LINEAR TECHNOLOGY CORPORATION 2002 LT/TP 0803 1K • PRINTED IN USA RELATED PARTS PACKAGE DESCRIPTIO U PART NUMBER DESCRIPTION COMMENTS LT1339 High Power Synchronous DC/DC Controller Operation Up to 60V Maximum LT1425 Isolated Flyback Switching Regulator General Purpose with External Application Resistor LT1431 Programmable Reference 0.4% Initial Voltage Tolerance LT1680 High Power DC/DC Step-Up Controller Operation Up to 60V Maximum LT3781 Dual Transistor Synchronous Forward Controller Operation Up to 72V Maximum LT1725 General Purpose Isolated Flyback Controller Drives External Power MOSFET with External I SENSE Resistor LT1737 High Power Isolated Flyback Controller Sense Output Voltage Directly from Primary-Side Winding LT1950 PWM Controller for Flyback, Forward and SEPIC 15W to 500W, Isolated and Nonisolated Power Supply 50% Smaller Applications Transformer, Protects MOSFET LT3804 Secondary Side Dual Output Controller Regulates Two Outputs, Optocoupler Feedback Driver and Second Output with Optodriver Synchronous Driver Controller 16-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation BA FE16 (BA) TSSOP 0203 0.09 – 0.20 (.0036 – .0079) 0° – 8° 0.45 – 0.75 (.018 – .030) 4.30 – 4.50* (.169 – .177) 6.40 BSC 13 4 5 6 7 8 10 9 4.90 – 5.10* (.193 – .201) 16 1514 13 12 11 1.10 (.0433) MAX 0.05 – 0.15 (.002 – .006) 0.65 (.0256) BSC 2.74 (.108) 2.74 (.108) 0.195 – 0.30 (.0077 – .0118) MILLIMETERS (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN RECOMMENDED SOLDER PAD LAYOUT 3. DRAWING NOT TO SCALE 0.45 –0.05

0.65 BSC

4.50 –0.10 6.60 –0.10 1.05 –0.10 2.74 (.108) 2.74 (.108) SEE NOTE 4 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT