LT3640IFETRPBF

LT3640 LINER | Alldatasheet

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Technical content

DESCRIPTION

The L T®3640 is a dual channel, current mode monolithic buck switching regulator with a power-on reset and a watchdog timer . Both regulators are synchronized to a single oscillator with an adjustable frequency (350kHz to 2.5MHz). At light loads, both regulators operate in low ripple Burst Mode ® to maintain high efﬁ ciency and low output ripple. The high voltage channel is a nonsynchronous buck with an internal 2.4A top switch that operates from an input of 4V to 36V; a 38V OVLO protects the device to 55V . The low voltage channel operates from an input of 2.5V to 5.5V . Internal synchronous power switches provide high efﬁ ciency without the need of external Schottky diode. Both channels have cycle-by-cycle current limit, providing protection against shorted outputs. The power-on reset and watchdog timeout periods are both adjustable using external capacitors. The window mode watchdog timer ﬂ ags when the μP pulses group too close together or too far apart. The L T3640 is available in a 28-pin 4mm × 5mm QFN package and 28-pin TSSOP package. Both packages have an exposed pad for low thermal resistance. 2MHz 3.3V/0.8A and 1.8V/0.8A Step Down Regulators

FEATURES

APPLICATIONS

n High Voltage Buck Regulator: 4V to 36V Operating Range 1.3A Output Current n OVLO Protects Input to 55V n Low Voltage Synchronous Buck Regulator: 2.5V to 5.5V Input Voltage Range 1A Output Current n Synchronizable, Adjustable 350kHz to 2.5MHz Switching Frequency n Programmable Power-On Reset Timer n Programmable Window Mode Watchdog Timer n Quiescent Current: 275μA n Short-Circuit Robust n Programmable Soft-Start n Low Shutdown Current: I Q < 1μA n Available in Thermally Enhanced 28-Lead (4mm × 5mm) QFN and 28-Lead TSSOP Packages n Industrial Power Supplies n Automotive Electronic Control Units

3640 TA01a

1nF1.5nF1.5nF 32.4k VOUT2 1.8V/0.8A VOUT1 3.3V/0.8A 47μF 10μF 100k RST2 EN2 WDO WDI FB2CWDT CPOR RT GND SS2 SS1 RST1 SW2 SW1EN/UVLO V IN VIN 5V TO 34V SW L T3640 BST VIN2 FB1 1μH 100k VOUT1 μP 100k 49.9k 80.6k 49.9k 3.3μH 0.22μF DA 10μF 22μF HV Channel Efﬁ ciency, 2MHz, VOUT1 = 3.3V L, L T , L TC, L TM, Linear Technology, Burst Mode and the Linear logo are registered trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. LV Channel Efﬁ ciency, 2MHz, VOUT2 = 1.8V VOUT1 CURRENT (A)

70 EFFICIENCY (%)

1.2

3640 TA01b

VIN = 12V VOUT2 CURRENT (A) 0.2 0.4 0.8 0.6 1

3640 TA01c

VIN2 = 3.3V Electrical Specifications Subject to Change

V IN2, SYNC, EN2, PGOOD, WDI, SS1, SS2, FB1, FB2, RT , CWDT , (Note 1) TOP VIEW FE PACKAGE 28-LEAD PLASTIC TSSOP FB2 PGOOD EN/UVLO SYNC SS1 FB1 RT RST2 RST1 WDO CWDT CPOR WDE WDI SS2 EN2 GND SW2 V IN2 GND V IN BST SW SW1 DA NC GND GND θJA = 30°C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB 9 10 TOP VIEW UFD PACKAGE 28-LEAD (4mm s 5mm) PLASTIC QFN 11 12 13 28 27 26 25 24 1SYNC SS1 FB1 RT RST2 RST1 WDO CWDT SW2 V IN2 GND V IN BST SW SW1 DA EN/UVLO PGOOD FB2 SS2 EN2 GND CPOR WDE WDI GND GND NC 8 15 GND θJA = 34°C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB PIN CONFIGURATION ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L T3640EFE#PBF L T3640EFE#TRPBF L T3640FE 28-Lead Plastic TSSOP –40°C to 125°C L T3640IFE#PBF L T3640IFE#TRPBF L T3640FE 28-Lead Plastic TSSOP –40°C to 125°C L T3640EUFD#PBF L T3640EUFD#TRPBF 3640 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C L T3640IUFD#PBF L T3640IUFD#TRPBF 3640 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C Consult L TC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the shipping container . Consult L TC Marketing for information on non-standard lead based ﬁ nish parts. For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel speciﬁ cations, go to: http://www.linear .com/tapeandreel/ Operating Junction Temperature Range (Note 2) Lead Temperature, FE Only (Soldering, 10 sec) .... 300°C

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. VIN = 12V , VIN2 = 3.3V , EN/UVLO = 12V , EN2 = 3.3V , unless otherwise noted.

ELECTRICAL CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Undervoltage Lockout Threshold l 3.6 4 V VIN Undervoltage Release Threshold l 3.8 4.2 V VIN Overvoltage Lockout Threshold l 35 36.5 38 V VIN Overvoltage Release Threshold l 34 35.5 37 V Quiescent Current from VIN EN/UVLO = 0.3V Not Switching 0.1 275 375 μA μA EN/UVLO Threshold Voltage 1.2 1.26 1.3 V EN/UVLO High Bias Current EN/UVLO = Threshold + 60mV 2 μA EN/UVLO Low Bias Current EN/UVLO = Threshold – 60mV 0.1 μA SYNC Input Frequency 0.35 2.5 MHz SYNC Threshold Voltage 0.4 0.8 1 V Switching Frequency RT = 32.4k RT = 182k l l 1.75 450 500 2.35 550 MHz kHz FB1 Voltage l 1.24 1.265 1.29 V FB1 Bias Current FB1 = 1.265V 30 100 nA FB1 Line Regulation 5V < V IN < 30V 0.001 %/V SW1 Minimum Off-Time 70 ns SW1 VCESAT ISW1 = 800mA 400 mV SW1 Leakage Current 0.1 1 μA SW1 Current Limit FB1 = 1V (Note 3) FB1 = 0.1V l 2.2 2.8 1.8 3.3 A A DA Current limit FB1 = 1V (Note 4) FB1 = 0.1V l 1.1 1.35 0.8 1.7 A A BST Pin Current I SW1 = 800mA 30 50 mA Minimum BST-SW Voltage 2 2.7 V ΔFB1 to Start LV Channel 80 100 130 mV ΔFB1 Hysteresis to Stop LV Channel 30 50 90 mV VIN2 Minimum Operating Voltage l 2.3 2.5 V VIN2 Maximum Operating Voltage l 5.5 V EN2 Threshold Voltage 0.3 1 1.5 V FB2 Voltage l 588 600 612 mV FB2 Bias Current FB2 = 0.6V 0 100 nA FB2 Line Regulation 2.5V < V SW2 Minimum Off-Time 70 ns SW2 PMOS Current Limit (Note 5) l 1.5 1.9 2.2 A SW2 NMOS Current Limit (Note 5) l 0.9 1.1 1.3 A SW2 PMOS RDS(ON) ISW2 = 0.5A (Note 6) 275 mΩ SW2 NMOS RDS(ON) ISW2 = 0.5A (Note 6) 200 mΩ ΔFB2 to Enable PGOOD 20 40 80 mV ΔFB2 Hysteresis to Disable PGOOD 20 40 80 mV PGOOD Voltage FB2 = 0.6V , I PGOOD = 1mA 200 320 mV

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The L T3640E is guaranteed to meet performance speciﬁ cations from 0°C to 125°C junction temperature. Speciﬁ cations over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The L T3640I is guaranteed and tested over the full –40°C to 125°C operating junction temperature range. PARAMETER CONDITIONS MIN TYP MAX UNITS SS1 to FB1 Offset Voltage SS1 = 0.6V 5 30 mV SS2 to FB2 Offset Voltage SS2 = 0.3V 5 30 mV RST1 Threshold as Percentage of V FB l 90 92 94 % RST2 Threshold as Percentage of VFB l 89 92 94 % Undervoltage to RST Assert Time 20 μs RST1, RST2, WDO Pull-Up Current RST1, RST2, WDO = 0V 5 15 30 μA RST1, RST2, WDO Output Voltage I RST1, IRST2, IWDO = 2mA 150 250 mV RST1, RST2 Timeout Period (tRST) CPOR = 220pF l 8 9.5 11 ms Watchdog Start Delay Time (tDL Y) CWDT = 820pF 14 16 18 ms Watchdog Upper Boundary (tWDU) CWDT = 820pF l 27 32 35 ms Watchdog Lower Boundary (tWDL) CWDT = 820pF l 1.68 2 2.2 ms WDI Pull-Up Current WDI = 1.2V 2 μA WDI Voltage Threshold 0.55 0.85 1.15 V WDI Low Minimum Pulse Width 300 ns WDI High Minimum Pulse Width 300 ns WDE Pull-Down Current WDE = 2V 1 μA WDE Threshold l 0.5 0.7 0.9 V The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. VIN = 12V , VIN2 = 3.3V , EN/UVLO = 12V , EN2 = 3.3V , unless otherwise noted. Note 3: SW1, SW2 current limit is guaranteed by design and/or correlation to static test. Slope compensation reduces current limit at higher duty cycle. Note 4: The oscillator cycle is extended when DA current exceeds its limit. DA current limit is ﬂ at over duty cycle. Note 5: If the SW2 NMOS current exceeds its limit at the start of an oscillator cycle, the PMOS will not be turned on in the cycle. Note 6: The QFN switch R DS(ON) is guaranteed by correlation to wafer level measurement. Note 7: Absolute maximum voltage at VIN and RUN/SS pin is 55V for nonrepetitive one second transients, and 36V for continuous operation.

TYPICAL PERFORMANCE CHARACTERISTICS LV Channel Efﬁ ciency (2MHz, VOUT2 = 1.8V) Quiescent Current vs VIN Quiescent Current vs Temperature HV Channel Efﬁ ciency (2MHz, VOUT1 = 3.3V) HV Channel Efﬁ ciency (2MHz, VOUT1 = 5V) LV Channel Efﬁ ciency (2MHz, VOUT2 = 1.2V) TA = 25°C, unless otherwise noted. FB1 Voltage vs Temperature FB1 Voltage vs SS1 FB2 Voltage vs Temperature VOUT1 CURRENT (A) EFFICIENCY (%) 1.2

3640 G01

VIN = 12V VIN = 24V VIN = 16V VOUT1 CURRENT (A) EFFICIENCY (%) 1.2

3640 G02

VIN = 12V VIN = 24V VIN = 16V VOUT2 CURRENT (A) EFFICIENCY (%)

3640 G04

VIN2 = 3.3V VIN2 = 5V VIN VOL TAGE (V) VIN QUIESCENT CURRENT (mA) 0.20 0.25 0.30 0.15 0.10 2010 30 40 0.05 0.00 0.35

3640 G05

TEMPERATURE (°C) –50 VIN QUIESCENT CURRENT (μA) 200 250 300 150 100 500 100 150 350

3640 G06

TEMPERATURE (°C) –50 FB1 VOL TAGE (V) 500 100 150

3640 G07

1.00 1.10 1.20 1.30 1.40 1.05 1.15 1.25 1.35 REGULATION RST1 THRESHOLD SS1 VOL TAGE (V) FB1 VOL TAGE (V) 1.00 0.5 1.5 2.0

3640 G08

0.0 0.4 0.8 1.2 1.4 0.2 0.6 1.0 TEMPERATURE (°C) –50 FB2 VOL TAGE (V) 500 100 150

3640 G09

0.45 0.55 0.65 0.70 0.50

0.60 REGULATION

VOUT2 CURRENT (A) EFFICIENCY (%)

3640 G03

VIN2 = 3.3V VIN2 = 5V

TYPICAL PERFORMANCE CHARACTERISTICS FB2 Voltage vs SS2 Switching Frequency vs Temperature HV Channel Current Limit vs Duty Cycle VOUT1 Minimum Load to Run at Full Frequency (VOUT1 = 3.3V) HV Channel Switching Frequency (VOUT1 = 3.3V) LV Channel Switching Frequency (VOUT2 = 1.8V) LV Channel Peak Current Limit vs Duty Cycle LV Channel Switch Voltage Drop vs Current (VIN2 = 3.3V) TA = 25°C, unless otherwise noted. SS2 VOL TAGE (mV) FB2 VOL TAGE (mV)

3640 G10

TEMPERATURE (°C) –50 SWITCHING FREQUENCY (MHz) 500 100 150

3640 G11

0.48 0.50 0.52 0.49 0.51 DUTY CYCLE (%) SW1 PEAK CURRENT LIMIT (A)

3640 G12

0.0 1.0 2.0 2.5 0.5 1.5 DUTY CYCLE (%) SW2 PEAK CURRENT LIMIT (A)

3640 G13

0.0 1.0 2.0 0.5 1.5 SW2 CURRENT (A) SW2 VOL TAGE DROP (mV) 300 350 400 250 200 0.5 1 1.5 150 450 100

3640 G14

VIN VOL TAGE (V) VOUT1 CURRENT (A) 0.30 0.35 0.40 0.25 0.20 51 5 10 20 25 30 0.05 0.15 0.45 0.10

3640 G15

2.5MHz VOUT1 CURRENT (A) SWITCHING FREQUENCY (MHz)

3640 G16

1.0 2.0 2.5 0.5 1.5 VIN = 12V VIN = 24V VIN = 16V VOUT2 CURRENT (A) SWITCHING FREQUENCY (MHz)

3640 G17

1.0 2.0 2.5 0.5 1.5 VIN2 = 3.3V VIN2 = 5V

TYPICAL PERFORMANCE CHARACTERISTICS Full Frequency Waveforms PFM Operation Waveforms TA = 25°C, unless otherwise noted. Watchdog Upper Boundary Period vs CWDT Watchdog Upper Boundary Period vs Temperature RST/WDO Pull-Up Current 200ns/DIV SW1 10V/DIV IL1 0.5A/DIV SW2 5V/DIV IL2 0.5A/DIV

3640 G18

VIN1 = 12V VOUT1 = 3.3V/0.5A VIN2 = VOUT1 VOUT2 = 1.8V/0.5A 200ns/DIV SW1 10V/DIV IL1 0.5A/DIV SW2 5V/DIV IL2 0.5A/DIV

3640 G19

VIN1 = 12V VOUT1 = 3.3V/25mA VIN2 = VOUT1 VOUT2 = 1.8V/30mA CWDT CAPACITANCE (pF) WATCHDOG UPPER BOUNDARY PERIOD (ms) 120 140 160 100 20001000 3000 4000 5000 180

3640 G20

TEMPERATURE (°C) –50 WATCHDOG UPPER BOUNDARY PERIOD (ms) 500 100 150

3640 G21

RST/WDO VOL TAGE (V) RST/WDO PULL-UP CURRENT (μA) 10.5 1.5 2

3640 G22

FB2 (Pin 1/Pin 26): The low voltage converter regulates the FB2 pin to 600mV . Connect the feedback resistor divider tap to this pin to set output voltage. PGOOD (Pin 2/Pin 27): Open-drain logic output that starts to sink current when FB2 is in regulation. EN/UVLO (Pin 3/Pin 28): Pull this pin below 0.3V to shut down the L T3640. The 1.26V threshold can function as an accurate undervoltage lockout, preventing the L T3640 from operating until V IN voltage has reached the programmed level. SYNC (Pin 4/Pin 1): Driving the SYNC pin with an external clock signal synchronizes both converters to the applied frequency. The lowest external clock frequency should be 20% higher than the internal oscillator frequency. SS1 (Pin 5/Pin 2): The SS1 pin sets the FB1 voltage ex- ternally between 0V and 1.265V , providing soft-start and tracking. Tie this pin 1.5V or higher to use the internal 1.265V reference. A capacitor to ground at this pin sets the ramp time to regulated output voltage for the high voltage converter . Use a resistor divider to track another supply. FB1 (Pin 6/Pin 3): The high voltage converter regulates the FB1 pin to 1.265V . Connect the feedback resistor divider tap to this pin to set output voltage. RT (Pin 7/Pin 4): Oscillator Resistor Input. Connecting a resistor to ground from this pin sets the internal oscillator frequency. RST2 (Pin 8/Pin 5): Open-drain logic output that remains asserted for the period set by the CPOR pin capacitor after FB2 goes above 550mV . RST1 (Pin 9/Pin 6): Open-drain logic output that remains asserted for the period set by the CPOR pin capacitor after FB1 goes above 1.165V . WDO (Pin 10/Pin 7): Open-drain logic output that remains asserted for the period set by the CPOR pin capacitor if WDE is enabled and WDI pin is not driven by an appropri- ate signal. CWDT (Pin 11/Pin 8): Connect a capacitor to ground at this pin to set watchdog timer . CPOR (Pin 12/Pin 9): Connect a capacitor to ground at this pin to set the power-on reset timer and WDO output timer . WDE (Pin 13/Pin 10): Watchdog Enable Pin. WDI (Pin 14/Pin 11): The WDI pin receives watchdog signals from a microprocessor . GND (Pins 15, 16, 23, 26, Exposed Pad 29/Pins 12, 13, 20, 23, Exposed Pad 29): Ground. These pins must be soldered to PCB ground. NC (Pin 17/Pin 14): Not Connected. DA (Pin 18/Pin 15): The DA pin is used to sense the catch diode current for current limit and protection. Connect this pin to catch diode anode. SW1 (Pin 19/Pin 16): Output of the High Voltage Internal Power Switch. Connect this pin to the inductor and catch diode cathode. SW (Pin 20/Pin 17): The SW pin is used to charge the boost capacitor . Connect this pin to the boost capacitor . BST (Pin 21/Pin 18): The BST pin is used to provide a drive voltage, higher than V IN pin voltage, to the high voltage channel internal power switch. Connect an external boost diode to this pin. V IN (Pin 22/Pin 19): The V IN pin supplies current to the L T3640’s internal circuitry and to the high voltage channel internal power switch. This pin must be locally bypassed. V IN2 (Pin 24/Pin 21): The VIN2 pin supplies current to the internal power MOSFET of the low voltage converter and to the L T3640’s internal circuitry when V IN2 is above 3V . SW2 (Pin 25/Pin 22): Switch Node of the Low Voltage Converter . Connect this pin to an inductor . EN2 (Pin 27/Pin 24): Low Voltage Converter Enable Pin. Pull this pin below 0.3V to shut down the low voltage converter . Pull this pin above 1.5V to enable the low volt- age converter . SS2 (Pin 28/Pin 25): The SS2 pin sets the FB2 voltage externally between 0V and 0.6V , providing soft-start and tracking. Tie this pin 0.8V or higher to use the internal 0.6V reference. A capacitor to ground at this pin sets the ramp time to regulated output voltage for the low voltage converter . Use a resistor divider to track another supply. (FE/QFN)

2μA R2 FB1 SS1 EN/ UVLO ENABLE 5.5V BST SW SW1 DRIVER DA RT SYNC SW2 2μA 2μA gm1 2μA 2μA R4 FB2 50mV PGOOD SS2 CPOR VREF 1.265V RAMP GENERATOR POR TIMER WATCHDOG TIMER OSCILLATOR S LOGIC CIRCUIT RQ S RQ –A6 VIN CIN VOUT1 VOUT2 VIN2 CIN2 CBST COUT1 COUT2 DBST EN2 CWDT RST1 RST2 WDE WDI WDO

The L T3640 is a dual channel, constant-frequency, current mode monolithic buck switching regulator with power-on reset and watchdog timer . Both channels are synchronized to a single oscillator with frequency set by RT . Operation can be best understood by referring to the Block Diagram. Buck Regulators The high voltage channel is a nonsynchronous buck regulator that operates from the V IN pin. The start of each oscillator cycle sets an SR latch and turns on the internal NPN power switch. An ampliﬁ er and comparator monitor the current ﬂ owing between the V IN and SW1 pins, turning the switch off when this current reaches a level determined by the voltage at VC1 node. An error ampliﬁ er measures the output voltage through an external resistor divider tied to the FB1 pin and servos the VC1 node. The reference of the error ampliﬁ er is determined by the lower of the internal reference and the voltage at the SS1 pin. If the error ampliﬁ er’s output increases, more current is delivered to the output; if it decreases, less current is delivered. OPERATION An active clamp (not shown) on the VC1 node provides peak current limit. A DA pin current comparator extends the oscillator cycle until the catch diode current is below the valley current limit. Both the peak and valley current limits help to control the inductor current in fault condi- tions such as shorted output with high V IN. Both current limits are reduced when the voltage at the FB1 pin is below 0.2V . This current foldback helps to control the inductor current during start-up and overload. The NPN power switch driver operates from either the V IN pin or the BST pin. An external capacitor and diode are used to generate a voltage between the BST and SW pins. During the power-up of the L T3640, an internal 5mA current source charges the external BST capacitor . The regulator starts switching when the (BST-SW) voltage reaches the 2V threshold. The internal NPN power switch can be fully saturated for efﬁ cient operation when the (BST-SW) volt- age is between 2.3V and 5.5V . The low voltage channel is a synchronous buck regulator that operates from the V IN2 pin. It starts switching only FB RST WDI WDO 3640 TD tRSTtUV t < tWDL tRST tDL Y t < tWDU tWDL < t < tWDU tWDU tRST Power-On Reset Timing Watchdog Timing

when the V IN2 pin voltage is above 2.3V , the EN2 pin is pulled high and the FB1 pin voltage is above 1.165V . The internal top power MOSFET is turned on each cycle at the beginning of each oscillator cycle, and turned off when the current ﬂ owing through the top MOSFET reaches a level determined by the voltage at the VC2 node. An error ampliﬁ er measures the output voltage through an external resistor divider tied to the FB2 pin and servos the VC2 node. The reference of the error ampliﬁ er is determined by the lower of the internal 600mV reference and the voltage at the SS2 pin. While the top MOSFET is off, the bottom MOSFET is turned on in an oscillator cycle until the inductor current starts to reverse. If the inductor current is higher than the valley current limit at the beginning of an oscillator cycle, the top MOSFET will not turn on in this cycle, limiting inductor current in shorted output fault. An internal regulator provides power to the control circuitry. The regulator draws most power from the V IN2 pin and a small portion of power from the VIN pin when the VIN2 pin voltage is higher than 3V . If the voltage at VIN2 pin is lower than 3V , the regulator draws all power from the VIN pin. The EN/UVLO pin is used to put the L T3640 in shutdown, reducing the input current to less than 1μA. The accurate 1.26V threshold of the EN/UVLO pin provides a program- mable V IN undervoltage lockout through an external resistor divider tied to the EN/UVLO pin. A 2μA hysteresis current on the EN/UVLO pin prevents switching noise from shut- ting down the L T3640. The L T3640 has an overvoltage protection feature which disables switching action in both channels when the V IN pin voltage goes above 36V . When switching is disabled, the L T3640 can sustain V IN voltages up to 55V for one second. Internal 2μA current sources charge the SS1 pin and the SS2 pin up to about 2V . Soft-start or output voltage tracking of the two channels can be independently imple- mented with capacitors from the SS1 pin and the SS2 pin to ground. Any overvoltage or undervoltage condition on the V IN pin triggers an internal latch that discharges the SS1 pin to below 100mV before it is released. If the EN2 pin goes low, the V IN2 voltage falls below 2.2V or the FB1 pin goes below 1.165V , the SS2 pin will be discharged to below 100mV before it is released. To optimize efﬁ ciency, the L T3640 switches to low ripple Burst Mode operation in light load situations. Between switching pulses, control-circuitry current is minimized. A power good comparator with 40mV of hysteresis trips when the low voltage channel is enabled and the FB2 pin is above 550mV . The PGOOD pin is an open-drain output that is pulled low when both the outputs are in regulation. Power-On Reset and Watchdog Timer The L T3640 includes one power-on reset timer for each buck regulator and one common watchdog timer . Power- on reset and watchdog timers are both adjustable using external capacitors. Operation can be best understood by referring to the Timing Diagram. The RST1, RST2 and WDO pins are all open-drain outputs with weak internal pull-ups to about 2V . The RST1 and RST2 pins are pulled low when the L T3640 is enabled and V IN is above 3.6V . Once the FB1 pin rises above 1.165V , the high voltage channel reset timer is started and RST1 is released after the reset timeout period. The low voltage channel reset timer is started once the FB2 pin rises above 550mV , and releases RST2 after the reset timeout period. The watchdog circuit monitors a μP’s activity. As soon as both RST1 and RST2 are released, a delay timer is started. The watchdog timer is started after the delay timer times out. The L T3640 implements windowed watchdog function for higher system reliability. The watchdog timer detects falling edges on the WDI pin. If the falling edges are grouped too close together or too far apart, the WDO pin is pulled down and the reset timer is started. When the reset timer times out, WDO is released and the watchdog timer is again started after the delay period. OPERATION

Table 1. Switching Frequency vs RT Value increases when switching frequency decreases. for appropriate hysteresis voltage. voltage, output will lose regulation.

Figure 1. Lower Switching Frequency Occurs in High IN voltage transients up to 55V for one second. output for a two-stage power regulator . will be disabled. The SS2 pin will be discharged as well. Figure 2. VIN Overvoltage Lockout

3640 F01

3640 F02

following the same principle as the high voltage channel. saturation current should be at least 2.5A. Table 2. Inductor Vendors tion, which is okay, but reduces maximum load current.

For duty cycles greater than 50%, there is a minimum

inductance required to avoid subharmonic oscillations. See the Linear Technology Application Note 19. (see the PCB Layout section). concerns the maximum input voltage rating of the L T3640.

(see the Linear Technology Application Note 80). provide low output ripple and good transient response. input capacitor is not necessary for the VIN2 pin. operating conditions (applied voltage and temperature). electrolytic capacitors can be used for the output capacitor . Table 3. Capacitor Vendors 4 lists several Schottky diodes and their manufacturers. Table 4. Diode Vendors

output voltage for most of the load range. output ramping linearly from 0V to the regulated voltage. At power-up, a latch is set to discharge the SS1 pin. Figure 3. High Voltage Channel Minimum Input Voltage for VOUT1 = 3.3V

3640 F03a

3640 F03b

soft-start latch is set, triggering a start-up sequence. latch is set, triggering a start-up sequence. up current should not exceed 100μA for either SS pin. channel operation under shorted output. off in this cycle (similar to pulse-skipping operation). robustness in shorted output condition (Figure 6). Figure 4. Soft-Start of L T3640 Figure 5. The High Voltage Channel Reduces Frequency Figure 6. The Low Voltage Channel Operates in

3640 F04

3640 F05

3640 F06

voltage channel, and 550mV for the low voltage channel. pulled out of the VIN2 pin (Figure 7). Figure 8. PFM Operation the output voltage ripples small. and starts monitoring their corresponding feedback voltages. Figure 7. Diodes Prevent Shorted Inputs from

3640 F07

3640 F08a

3640 F08b

3640 F08c

conﬁ guration allows wired-OR connections. released, the watchdog again starts the delay period. as probe capacitance, can affect the watchdog timer . Figure 9. Power-On Reset and Watchdog Timing

3640 F09a

64 CYCLES 64 CYCLES

3640 F09b

3640 F09c

3640 F10

and tWDU. The WDI falling edge resets the CWDT oscillator . The CPOR oscillator is disabled and WDO remains high. tRST when the watchdog upper boundary, tWDU, expires. local, unbroken ground plane below these components. The BST and SW nodes should be as small as possible. the VIN2 pin, the input capacitor (C IN2) and the ground. board and on the bottom side. Figure 10. Recommended PCB Layout, FE28 Package

3640 TA03

1nF1.5nF 1.5nF 32.4k VOUT2 1.2V/1A VOUT1 5V/0.8A 47μF 4.7μF RST1 RST2 EN2 WDO FB2 CWDT CPOR RT GND SS2 SS1 SW2 SW1EN/UVLO V IN VIN 7V TO 34V SW L T3640 BST VIN2 FB1 1μH 453k100k 100k OUT1 49.9k 49.9k 301k 100k 4.7μH 0.22μF D2 DA 10μF 10μF 100k 100k 100k L1: VISHAY IHLP-2020 L2: VISHAY IHLP-1616 D1: DIODES B240A D2: CENTRAL SEMI CMDSH-4E TYPICAL APPLICATIONS 2MHz 3.3V/1.3A and 1.2V/1A Buck Regulators 2MHz 5V/0.8A and 1.2V/1A Buck Regulators

3640 TA02

1nF1.5nF 1.5nF 32.4k VOUT2 1.8V/1A VOUT1 3.3V/1.3A VIN2 2.5V TO 5.5V 47μF 4.7μF RST1 RST2 EN2 WDO WDI L1: VISHAY IHLP-2020 L2: VISHAY IHLP-1616 D1: DIODES B240A D2: CENTRAL SEMI CMDSH-4E FB2 CWDT CPOR RT GND SS2 SS1 SW2 SW1EN/UVLO V IN VIN 5V TO 34V SW L T3640 BST VIN2 FB1 1μH 301k100k 49.9k 100k 80.6k 49.9k 3.3μH D20.22μF DA 4.7μF 10μF

3640 TA04

1nF1.5nF 1.5nF 100μF 4.7μF RST1 RST2 WDO WDI FB2 CWDT CPOR RT GND SS2 SS1 SW2 SW1EN/UVLO V IN SW L T3640 BST VIN2 FB1 100k 100k 0.22μF DA 22μF EN2 32.4k VOUT2 0.6V/1A VOUT1 2.5V/0.8A VIN 3.6V TO 25V 1μH 3.3μH L1: VISHAY IHLP-2020 L2: VISHAY IHLP-1616 D1: ON SEMI MBRS230 D2: CENTRAL SEMI CMDSH2-3 2MHz 2.5V/0.8A and 0.6V/1A Buck Regulators

28-Lead Plastic TSSOP (4.4mm) (Reference L TC DWG # 05-08-1663) Exposed Pad Variation EB FE28 (EB) TSSOP 0204 0.09 – 0.20 (.0035 – .0079) 0° – 8° 0.25 REF 0.50 – 0.75 (.020 – .030) 4.30 – 4.50* (.169 – .177) 13 4 5 6 7 89 1 0 11 12 13 14 192022 21 15 1618 17 9.60 – 9.80* (.378 – .386) 4.75 (.187) 2.74 (.108) 28 2726 25 24 23 1.20 (.047) MAX 0.05 – 0.15 (.002 – .006) 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 2RECOMMENDED SOLDER PAD LAYOUT EXPOSED PAD HEAT SINK ON BOTTOM OF PACKAGE0.45 ±0.05

0.65 BSC

4.50 ±0.10 6.60 ±0.10 1.05 ±0.10 4.75 (.187) 2.74 (.108) MILLIMETERS (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE SEE NOTE 4 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT 6.40 (.252) BSC

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 4.00 ± 0.10 (2 SIDES)

2.50 REF

5.00 ± 0.10 (2 SIDES) NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (NOTE 6) 0.40 ± 0.10 27 28 BOTTOM VIEW—EXPOSED PAD

3.50 REF

0.75 ± 0.05 R = 0.115 TYP R = 0.05 TYP PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER 0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05 (UFD28) QFN 0506 REV B RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 0.25 ±0.05 4.10 ± 0.05 5.50 ± 0.05 2.65 ± 0.05 3.10 ± 0.05 4.50 ± 0.05 PACKAGE OUTLINE 2.65 ± 0.10 3.65 ± 0.10 3.65 ± 0.05 28-Lead Plastic QFN (4mm × 5mm) (Reference L TC DWG # 05-08-1712 Rev B) PACKAGE DESCRIPTION

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com © LINEAR TECHNOLOGY CORPORATION 2010 LT 0110 • PRINTED IN USA RELATED PARTS TYPICAL APPLICATION 2MHz 3.3V/0.8A and 0.8V/1.2A Buck Regulators

3640 TA05

1nF1.5nF 1.5nF 32.4k VOUT2 0.8V/1.2A VOUT1 3.3V/0.8A 68μF RST1 RST2 WDO WDI FB2 CWDT CPOR RT GND SS2 SS1 SW2 SW1EN/UVLO V IN SW L T3640 BST VIN2 FB1 1μH 49.9k 16.5k 80.6k 49.9k 4.7μH 0.1μF DA 22μF 4.7μF VIN 4V TO 34V EN2 PART NUMBER DESCRIPTION COMMENTS L T1933 500mA (I OUT), 500kHz Step-Down Switching Regulator in SOT-23 V IN: 3.6V to 36V, VOUT(MIN) = 1.2V, IQ = 1.6mA, ISD < 1μA, ThinSOTTM Package L T1936 36V , 1.4A (I OUT), 500kHz, High Efﬁ ciency Step-Down DC/DC Converter VIN: 3.6V to 36V, VOUT(MIN) = 1.2V, IQ = 1.9mA, ISD < 1μA, L T1940 Dual 25V , 1.4A (I OUT), 1.1MHz, High Efﬁ ciency Step-Down DC/DC Converter VIN: 3.6V to 25V, VOUT(MIN) = 1.2V, IQ = 3.8mA, ISD < 30μA, L T1976/L T1967 60V, 1.2A (I OUT), 200kHz/500kHz, High Efﬁ ciency Step-Down DC/DC Converters with Burst Mode Operation VIN: 3.3V to 60V, VOUT(MIN) = 1.2V, IQ = 100μA, ISD < 1μA, L T3434/L T3435 60V, 2.4A (I OUT), 200kHz/500kHz, High Efﬁ ciency Step-Down DC/DC Converters with Burst Mode Operation VIN: 3.3V to 60V, VOUT(MIN) = 1.2V, IQ = 100μA, ISD < 1μA, L T3437 60V, 400mA (I OUT), Micropower Step-Down DC/DC Converter with Burst Mode Operation VIN: 3.3V to 60V, VOUT(MIN) = 1.25V, IQ = 100μA, ISD < 1μA, 3mm × 3mm DFN10 and TSSOP16E Packages L T3480 36V with T ransient Protection to 60V, 2A (I OUT), 2.4MHz, High Efﬁ ciency Step-Down DC/DC Converter with Burst Mode Operation VIN: 3.6V to 38V, VOUT(MIN) = 0.78V, IQ = 70μA, ISD < 1μA, 3mm × 3mm DFN10 and MSOP10E Packages L T3481 34V with T ransient Protection to 36V, 2A (I OUT), 2.8MHz, High Efﬁ ciency Step-Down DC/DC Converter with Burst Mode Operation VIN: 3.6V to 34V, VOUT(MIN) = 1.26V, IQ = 50μA, ISD < 1μA, 3mm × 3mm DFN10 and MSOP10E Packages L T3493 36V, 1.4A (I OUT), 750kHz High Efﬁ ciency Step-Down DC/DC Converter VIN: 3.6V to 36V, VOUT(MIN) = 0.8V, IQ = 1.9mA, ISD < 1μA, 2mm × 3mm DFN6 Package L T3505 36V with T ransient Protection to 40V, 1.4A (I OUT), 3MHz, High Efﬁ ciency Step-Down DC/DC Converter VIN: 3.6V to 34V, VOUT(MIN) = 0.78V, IQ = 2mA, ISD = 2μA, 3mm × 3mm DFN8 and MSOP8E Packages L T3508 36V with T ransient Protection to 40V, Dual 1.4A (I OUT), 3MHz, High Efﬁ ciency Step-Down DC/DC Converter VIN: 3.7V to 37V, VOUT(MIN) = 0.8V, IQ = 4.6mA, ISD = 1μA, 4mm × 4mm QFN24 and TSSOP16E Packages L T3680 36V , 3.5A, 2.4MHz, Low Quiescent Current (<75μA) Step-Down DC/DC Converter VIN: 3.6V to 36V, VOUT(MIN) = 0.8V, IQ = 75μA, ISD < 1μA, 3mm × 3mm DFN10, MS10E Package L T3684 34V with T ransient Protection to 36V, 2A (I OUT), 2.8MHz, High Efﬁ ciency Step-Down DC/DC Converter VIN: 3.6V to 34V, VOUT(MIN) = 1.26V, IQ = 850μA, ISD < 1μA, 3mm × 3mm DFN10 and MSOP10E Packages L T3685 36V with T ransient Protection to 60V, Dual 2A (I OUT), 2.4MHz, High Efﬁ ciency Step-Down DC/DC Converter VIN: 3.6V to 38V, VOUT(MIN) = 0.78V, IQ = 70μA, ISD < 1μA, 3mm × 3mm DFN10 and MSOP10E Packages 3mm × 3mm DFN10, MS10E Package

Summary

Dual Monolithic Buck Regulator with Power-On Reset and Watchdog Timer

Description