LT3626

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Technical content

n 3.6V to 20V Input Voltage Range n 3A Output Current per Channel n Up to 95% Effi ciency n Low Duty Cycle Operation: 5% at 2.25MHz n Selectable 0°/180° Phase Shift Between Channels n Adjustable Switching Frequency: 500kHz to 4MHz n External Frequency Synchronization n Current Mode Operation for Excellent Line and Load T ransient Response n 0.6V Reference Allows Low Output Voltages n User Selectable Burst Mode ® Operation or Forced Continuous Mode Operation n Output Voltage T racking and Soft-Start Capability n Short-Circuit Protected n Overvoltage Input and Overtemperature Protection n Power Good Status Outputs n L TC3633: 16V Absolute Maximum VIN n L TC3633A: 20V Absolute Maximum VIN, Pin Compatible with L TC3633 n Low Profi le (4mm × 5mm) QFN-28 and 28-Lead TSSOP Packages TYPICAL APPLICATION

DESCRIPTION

Dual Channel 3A, 20V Monolithic Synchronous Step-Down Regulator The L TC®3633A is a high effi ciency, dual-channel monolithic synchronous buck regulator using a controlled on-time, current mode architecture, with phase lockable switching frequency. The two channels can run 180° out of phase to relax the requirements for input and output capacitance. The operating supply voltage range is from 3.6V to 20V , making it suitable for lithium-ion battery stacks as well as point of load power supply applications from a 12V or 5V supply. The operating frequency is programmable from 500kHz to 4MHz with an external resistor and may be synchronized to an external clock signal. The high frequency capabil- ity allows the use of small surface mount inductors and capacitors. The unique constant frequency/controlled on- time architecture is ideal for high step-down ratio applica- tions that operate at high frequency while demanding fast transient response. An internal phase locked loop servos the on-time of the internal one-shot timer to match the frequency of the internal clock or an applied external clock. The L TC3633A can select between forced continuous mode and high effi ciency Burst Mode operation. The L TC3633A and L TC3633A-1 differ in their output voltage sense range (refer to Table 1 in the Operation section for a description of the entire L TC3633A product family).

FEATURES

APPLICATIONS

n Distributed Power Systems n Battery Powered Instruments n Point of Load Power Supplies Effi ciency vs Load Current L, L T , L TC, L TM, Burst Mode, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611. 0.001 EFFICIENCY (%) 0.1 10 3633a TA01b 100 0.01 1 VOUT = 5V VOUT = 3.3V LOAD CURRENT (A) Burst Mode OPERATION VIN = 12V RUN1 RUN2 TRACKSS2 PGOOD2 L TC3633A BOOST2 0.1μF1.5μH 73.2k 10k SW2 VON2 VIN2 PGNDSGND VIN1 VFB2 PHMODE TRACKSS1 PGOOD1 BOOST1 SW1 VON1 VFB1 22μF VOUT2 5V AT 3A 0.1μF 1μH 45.3k10k 22μF VOUT1 3.3V AT 3A VIN 6V TO 20V 47μF MODE/SYNC V2P5 RT ITH1 ITH2 INTVCC 2.2μF 3633a TA01a

V2P5, INTV (Note 1) ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3633AEUFD#PBF LTC3633AEUFD#TRPBF 3633A 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C LTC3633AIUFD#PBF LTC3633AIUFD#TRPBF 3633A 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C LTC3633AEFE#PBF LTC3633AEFE#TRPBF LTC3633AFE 28-Lead Plastic TSSOP –40°C to 125°C LTC3633AIFE#PBF LTC3633AIFE#TRPBF LTC3633AFE 28-Lead Plastic TSSOP –40°C to 125°C LTC3633AEUFD-1#PBF LTC3633AEUFD-1#TRPBF 633A1 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C LTC3633AIUFD-1#PBF LTC3633AIUFD-1#TRPBF 633A1 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C LTC3633AEFE-1#PBF LTC3633AEFE-1#TRPBF LTC3633AFE-1 28-Lead Plastic TSSOP –40°C to 125°C LTC3633AIFE-1#PBF LTC3633AIFE-1#TRPBF LTC3633AFE-1 28-Lead Plastic TSSOP –40°C to 125°C Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based fi nish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ Fo r more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/ Operating Junction Temperature Range 9 10 TOP VIEW UFD PACKAGE 28-LEAD (4mm × 5mm) PLASTIC QFN 11 12 13 28 27 26 25 24 1PGOOD1 PHMODE RUN1 MODE/SYNC RT RUN2 SGND PGOOD2 VIN1 VIN1 BOOST1 INTVCC V2P5 BOOST2 V IN2 VIN2 VFB1 TRACKSS1 ITH1 V ON1 SW1 SW1 V FB2 TRACKSS2 ITH2 VON2 SW2 SW2 8 15 PGND TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 29) IS PGND, MUST BE SOLDERED TO PCB TOP VIEW FE PACKAGE 28-LEAD PLASTIC TSSOP ITH1 TRACKSS1 V FB1 PGOOD1 PHMODE RUN1 MODE/SYNC RT RUN2 SGND PGOOD2 VFB2 TRACKSS2 ITH2 VON1 SW1 SW1 V IN1 VIN1 BOOST1 INTV CC V2P5 BOOST2 V IN2 VIN2 SW2 SW2 V ON2 PGND TJMAX = 125°C, θJA = 30°C/W EXPOSED PAD (PIN 29) IS PGND, MUST BE SOLDERED TO PCB

The l denotes the specifi cations which apply over the full operating junction temperature range, otherwise specifi cations are at TJ = 25°C (Note 2). VIN1 = VIN2 = 12V , unless otherwise noted.

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN1 Supply Range l 3.6 20 V VIN1 Supply Range VIN2 Supply Range 3.6V < VIN1 < 20V l l 3.6 1.5 V V Output Voltage Range (Note 4) LTC3633A, V ON = VOUT LTC3633A-1, VON = VOUT 0.6 1.5 V V I Q Input DC Supply Current (V IN1 + VIN2) Both Channels Active (Note 5) Sleep Current Shutdown MODE = 0V MODE = INTV CC, VFB1, VFB2 > 0.6 RUN1 = RUN2 = 0V 1.3 500 mA μA μA V FB Feedback Reference Voltage l 0.594 0.6 0.606 V ΔVLINE_REG Reference Voltage Line Regulation V IN = 3.6V to 20V 0.002 %/V ΔVLOAD_REG Output Voltage Load Regulation ITH = 0.8V to 1.6V 0.05 % IFB Feedback Pin Input Current ±30 nA gm(EA) Error Amplifi er Transconductance ITH = 1.2V 1.8 mS tON Minimum On Time VON = 0.6V, VIN = 4V 20 ns tOFF Minimum Off Time VIN = 6V 45 ns fOSC Oscillator Frequency VRT = INTVCC RT = 162k RT = 80.6k 1.4 1.7 3.4 2.6 2.3 4.6 MHz MHz MHz I LIM Valley Switch Current Limit 2.6 3.5 4.5 A RDS(ON) Top Switch On-Resistance Bottom Switch On-Resistance 130 mΩ mΩ I SW(LKG) Switch Leakage Current VIN = 20V, VRUN = 0V 0.01 ±1 μA VVIN-OV VIN Overvoltage Lockout Threshold V IN Rising VIN Falling 20.3 22.5 21.5 22.5 V V INTV CC Voltage 3.6V < VIN < 20V, 0mA Load 3.1 3.3 3.5 V INTVCC Load Regulation 0mA to 50mA Load, VIN = 4V to 20V 1.3 % RUN Threshold Rising RUN Threshold Falling l l 1.18 0.98 1.22 1.01 1.26 1.04 V V RUN Leakage Current V IN = 20V 0 ±3 μA V2P5 Voltage ILOAD = 0mA to 10mA l 2.46 2.5 2.54 V PGOOD Good-to-Bad Threshold V FB Rising VFB Falling –10 PGOOD Bad-to-Good Threshold V FB Rising VFB Falling R PGOOD PGOOD Pull-Down Resistance 10mA Load 20 Ω tPGOOD Power Good Filter Time 20 40 μs tSS Internal Soft-Start Time 10% to 90% Rise Time 400 700 μs VFB During Tracking TRACKSS = 0.3V 0.28 0.3 0.315 V ITRACKSS TRACKSS Pull-Up Current 1.4 μA

The l denotes the specifi cations which apply over the full operating junction temperature range, otherwise specifi cations are at TJ = 25°C (Note 2). VIN1 = VIN2 = 12V , unless otherwise noted. Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The L TC3633A is tested under pulsed load conditions such that T J ≈ TA. The L TC3633AE is guaranteed to meet specifi cations from 0°C to 85°C junction temperature. Specifi cations over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The L TC3633AI is guaranteed over the full –40°C to 125°C operating junction temperature range. Note that the maximum ambient temperature consistent with these specifi cations is determined by specifi c operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. The junction temperature SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VPHMODE PHMODE Threshold Voltage PHMODE VIH PHMODE VIL 0.3 V V VMODE/SYNC MODE/SYNC Threshold Voltage MODE V IH MODE VIL 0.4 V V SYNC Threshold Voltage SYNC V IH 0.95 V IMODE MODE/SYNC Input Current MODE = 0V MODE = INTV CC 1.5 –1.5 μA μA J, in °C) is calculated from the ambient temperature (TA, in °C) and power dissipation (PD, in Watts) according to the formula: T J = TA + (PD • θJA), where θJA (in °C/W) is the package thermal impedance. Note 3: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specifi ed maximum operating junction temperature may impair device reliability. Note 4: Output voltages outside the specifi ed range are not optimized for controlled on-time operation. Refer to the Applications Information section for further discussions related to the output voltage range. Note 5: Dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency.

TYPICAL PERFORMANCE CHARACTERISTICS Effi ciency vs Load Current Burst Mode Operation Effi ciency vs Input Voltage Burst Mode Operation Load Regulation Oscillator Frequency vs Temperature Effi ciency vs Load Current Burst Mode Operation Effi ciency vs Load Current Forced Continuous Mode Operation Effi ciency vs Load Current T J = 25°C, VIN1 = VIN2 = 12V , fSW = 1MHz, L = 1μH unless otherwise noted. Oscillator Internal Set Frequency vs Temperature Reference Voltage vs Temperature 0.001 EFFICIENCY (%) 0.1 10 3633a G01 100 0.01 1 LOAD CURRENT (A) VOUT = 1.8V VIN = 20V VIN = 12V VIN = 8V VIN = 4V 0.001 EFFICIENCY (%) 0.1 10 3633a G02 100 0.01 1 LOAD CURRENT (A) VIN = 20V VIN = 12V VIN = 8V VIN = 4V VOUT = 1.8V 0.001 EFFICIENCY (%) 0.1 10 3633a G03 100 0.01 1 LOAD CURRENT (A) Burst Mode OPERATION FORCED CONTINUOUS OPERATION VOUT = 3.3V VOUT = 5V VOUT = 3.3V VOUT = 5V L = 2.2μH EFFICIENCY (%) 8 20 3633a G05 100 6 1 01 21 41 61 8 ILOAD = 10mA ILOAD = 100mA ILOAD = 1A ILOAD = 3A INPUT VOL TAGE (V) VOUT = 1.8V 0.0001 0.001 EFFICIENCY (%) 0.1 10 3633a G04 100 0.01 1 LOAD CURRENT (A) VIN = 20V VIN =15V VIN = 12V VIN = 8V VIN = 4V VOUT = 1.2V –50 VFB (V) 0.597 0.599 50 150 3633a G06 0.595 0.601 0.605 0.603 25–25 0 75 100 125 TEMPERATURE (°C) ΔVOUT/VOUT (%) 0.0 0.4 1.5 3 3633a G07 –0.4 0.8 1.6 1.2 1 0.5 2 2.5 ILOAD (A) Burst Mode OPERATION FORCED CONTINUOUS VOUT = 1.8V –50 FREQUENCY VARIATION (%) 25 125 3633a G08 –10 0 –25 50 75 100 TEMPERATURE (°C) –50 FREQUENCY (MHz) 1.6 1.8 2.0 2.2 2.4 25 125 3633a G09 1.4 2.6 0 –25 50 75 100 TEMPERATURE (°C) RT = INTVCC

Internal MOSFET RDS(ON) vs Temperature Quiescent Current vs VIN Burst Mode Operation Switch Leakage vs Temperature Valley Current Limit vs Temperature TRACKSS Pull-Up Current vs Temperature TYPICAL PERFORMANCE CHARACTERISTICS Shutdown Current vs VIN V2P5 Load Regulation Load Step IQ (μA) 100 200 300 500 8 20 3633a G11 600 900 800 700 400 61 0 1 2 1 6 14 18 90°C 25°C –40°C VIN (V) IQ (μA) 8 20 3633a G12 6 1 01 21 41 61 8 V IN (V) –50 LEAKAGE CURRENT (nA) 1000 2000 3000 5000 0 150100 125 3633a G13 6000 10000 9000 8000 7000 4000 –25 25 50 75 TEMPERATURE (°C) SYNCHRONOUS SWITCH MAIN SWITCH TJ = 25°C, VIN1 = VIN2 = 12V , fSW = 1MHz, L = 1μH unless otherwise noted. TEMPERATURE (°C) –50 1.4 1.6 2.0 25 75 3633a G15 1.2 1.0 –25 0 50 100 125 0.8 0.6 1.8 ITRACKSS (μA) –50 ILIM (A) 3.4 3.5 3633a G14 3.3 3.7 3.6 3.9 3.8 25–25 0 75 100 125 TEMPERATURE (°C) V2P5(V) 2.496 2.498 3633a G16 2.494 2.502 2.500 2.506 2.504 428 1 0 ILOAD (mA) IL 1A/DIV SW 10V/DIV 5μs/DIV 3633a G17 VOUT 50mV/DIV VOUT = 1.8V ILOAD = 100mA IL 2A/DIV 20μs/DIV 3633a G18 VOUT AC-COUPLED 100mV/DIV VOUT = 1.8V ILOAD = 100mA to 3A CITH = 220pF RITH = 13kΩ –50 –25 RDS(ON) (mΩ) 100 140 50 125 3633a G10 160 200 180 120 0 25 75 100 TEMPERATURE (°C) TOP SWITCH BOTTOM SWITCH

TYPICAL PERFORMANCE CHARACTERISTICS Start-Up into Prebiased Output (Forced Continuous Mode) Load Step (Internal Compensation) Start-Up into Prebiased Output (Burst Mode Operation) Start-Up (Burst Mode Operation) T J = 25°C, VIN1 = VIN2 = 12V , fSW = 1MHz, L = 1μH unless otherwise noted. Start-Up (Forced Continuous Mode) IL 2A/DIV 20μs/DIV 3633a G19 VOUT AC-COUPLED 100mV/DIV VOUT = 1.8V ILOAD = 100mA to 3A ITH = INTVCC IL 2A/DIV 400μs/DIV 3633a G20 RUN 2V/DIV VOUT 1V/DIV VOUT = 1.8V CSS = 4.7nF ILOAD = 150mA IL 1A/DIV 400μs/DIV 3633a G21 RUN 2V/DIV VOUT 1V/DIV VOUT = 1.8V CSS = 4.7nF ILOAD = 150mA IL 1A/DIV 200μs/DIV 3633a G22 RUN 2V/DIV VOUT 1.8V 1V/DIV ILOAD = 0mA IL 2A/DIV 1ms/DIV 3633a G22 RUN 2V/DIV VOUT 1.8V 1V/DIV ILOAD = 0mA

PGOOD1 (Pin 1/Pin 4): Channel 1 Open-Drain Power Good Output Pin. PGOOD1 is pulled to ground when the voltage on the V FB1 pin is not within ±8% (typical) of the internal 0.6V reference. PGOOD1 becomes high imped- ance once the V FB1 pin returns to within ±5% (typical) of the internal reference. PHMODE (Pin 2/Pin 5): Phase Select Input. Tie this pin to ground to force both channels to switch in phase. Tie this pin to INTV CC to force both channels to switch 180° out of phase. Do not fl oat this pin. RUN1 (Pin 3/Pin 6): Channel 1 Regulator Enable Pin. Enables channel 1 operation by tying RUN1 above 1.22V . Tying it below 1V places channel 1 into shutdown. Do not fl oat this pin. MODE/SYNC (Pin 4/Pin 7): Mode Select and External Synchronization Input. Tie this pin to ground to force continuous synchronous operation at all output loads. Floating this pin or tying it to INTV CC enables high effi - ciency Burst Mode operation at light loads. Drive this pin with a clock to synchronize the L TC3633A switching. An internal phase-locked loop will force the bottom power NMOS’s turn on signal to be synchronized with the rising edge of the CLKIN signal. When this pin is driven with a clock, forced continuous mode is automatically selected. RT (Pin 5/Pin 8): Oscillator Frequency Program Pin. Connect an external resistor (between 80k to 640k) from this pin to SGND in order to program the frequency from 500kHz to 4MHz. When RT is tied to INTV CC, the switching frequency will default to 2MHz. RUN2 (Pin 6/Pin 9): Channel 2 Regulator Enable Pin. Enables channel 2 operation by tying RUN2 above 1.22V . Tying it below 1V places channel 2 into shutdown. Do not fl oat this pin. SGND (Pin 7/Pin 10): Signal Ground Pin. This pin should have a low noise connection to reference ground. The feedback resistor network, external compensation network, and RT resistor should be connected to this ground. PGOOD2 (Pin 8/Pin 11): Channel 2 Open-Drain Power Good Output Pin. PGOOD2 is pulled to ground when the voltage on the V FB2 pin is not within ±8% (typical) of the internal 0.6V reference. PGOOD2 becomes high imped- ance once the VFB2 pin returns to within ±5% (typical) of the internal reference. VFB2 (Pin 9/Pin 12): Channel 2 Output Feedback Voltage Pin. Input to the error amplifi er that compares the feedback voltage to the internal 0.6V reference voltage. Connect this pin to a resistor divider network to program the desired output voltage. TRACKSS2 (Pin 10/Pin 13): Output T racking and Soft-Start Input Pin for Channel 2. Forcing a voltage below 0.6V on this pin bypasses the internal reference input to the error amplifi er . The L TC3633A will servo the FB pin to the TRACK voltage under this condition. Above 0.6V , the tracking func- tion stops and the internal reference resumes control of the error amplifi er . An internal 1.4μA pull up current from INTV CC allows a soft start function to be implemented by connecting a capacitor between this pin and SGND. ITH2 (Pin 11/Pin 14): Channel 2 Error Amplifi er Output and Switching Regulator Compensation Pin. Connect this pin to appropriate external components to compensate the regulator loop frequency response. Connect this pin to INTV CC to use the default internal compensation. VON2 (Pin 12/Pin 15): On-Time Voltage Input for Chan- nel 2. This pin sets the voltage trip point for the on-time comparator . Tying this pin to the output voltage makes the on-time proportional to V OUT2 when V OUT2 is within the VON2 sense range (0.6V – 6V for L TC3633A, 1.5V – 12V for L TC3633A-1). When VOUT2 is outside the VON2 sense range, the switching frequency may deviate from the programmed frequency. The pin impedance is nominally 140kΩ. SW2 (Pins 13, 14/Pins 16, 17): Channel 2 Switch Node Connection to External Inductor . Voltage swing of SW is from a diode voltage drop below ground to V IN. VIN2 (Pins 15, 16/Pins 18, 19): Power Supply Input for Channel 2. Input voltage to the on chip power MOSFETs on channel 2. This input is capable of operating from a different supply voltage than V IN1. BOOST2 (Pin 17/Pin 20): Boosted Floating Driver Supply for Channel 2. The (+) terminal of the bootstrap capacitor connects to this pin while the (–) terminal connects to the SW pin. The normal operation voltage swing of this pin ranges from a diode voltage drop below INTV CC up to VIN+INTVCC. (QFN/TSSOP)

(QFN/TSSOP)PIN FUNCTIONS V2P5 (Pin 18/Pin 21): 2.5V Regulator Output. Outputs a regulated 2.5V supply voltage capable of supplying 10mA. Bypass this pin with a minimum of 1μF low ESR ceramic capacitor . Tie this pin to INTV CC when this output is not being used in the application. INTVCC (Pin 19/Pin 22): Internal 3.3V Regulator Output. The internal power drivers and control circuits are powered from this voltage. The internal regulator is disabled when both channel 1 and channel 2 are disabled with the RUN1/ RUN2 inputs. Decouple this pin to power ground with a minimum of 1μF low ESR ceramic capacitor . BOOST1 (Pin 20/Pin 23): Boosted Floating Driver Supply for Channel 1. The (+) terminal of the bootstrap capacitor connects to this pin while the (–) terminal connects to the SW pin. The normal operation voltage swing of this pin ranges from a diode voltage drop below INTV CC up to VIN + INTVCC. VIN1 (Pins 21,22/Pins 24, 25): Power Supply Input for Channel 1. Input voltage to the on chip power MOSFETs on channel 1. The internal LDO for INTV CC is powered off of this pin. SW1 (Pins 23,24/Pins 26, 27): Channel 1 Switch Node Connection to External Inductor . Voltage swing of SW is from a diode voltage drop below ground to V IN. VON1 (Pin 25/Pin 28): On-Time Voltage Input for Chan- nel 1. This pin sets the voltage trip point for the on-time comparator . Tying this pin to the regulated output voltage makes the on-time proportional to V OUT1 when VOUT1 is within the V ON1 sense range (0.6V – 6V for L TC3633A, 1.5V – 12V for L TC3633A-1). When VOUT is outside the VON sense range, the switching frequency may deviate from the programmed frequency. The pin impedance is nominally 140kΩ. ITH1 (Pin 26/Pin 1): Channel 1 Error Amplifi er Output and Switching Regulator Compensation Pin. Connect this pin to appropriate external components to compensate the regulator loop frequency response. Connect this pin to INTV CC to use the default internal compensation. TRACKSS1 (Pin 27/Pin 2): Output T racking and Soft-Start Input Pin for Channel 1. Forcing a voltage below 0.6V on this pin bypasses the internal reference input to the error amplifi er . The L TC3633A will servo the FB pin to the TRACK voltage. Above 0.6V , the tracking function stops and the internal reference resumes control of the error amplifi er . An internal 1.4μA pull up current from INTV CC allows a soft-start function to be implemented by connecting a capacitor between this pin and SGND. V FB1 (Pin 28/Pin 3): Channel 1 Output Feedback Voltage Pin. Input to the error amplifi er that compares the feedback voltage to the internal 0.6V reference voltage. Connect this pin to a resistor divider network to program the desired output voltage. PGND (Exposed Pad Pin 29/Exposed Pad Pin 29): Power Ground Pin. The (–) terminal of the input bypass capaci- tor , C IN, and the (–) terminal of the output capacitor , COUT, should be tied to this pin with a low impedance connec- tion. This pin must be soldered to the PCB to provide low impedance electrical contact to power ground and good thermal contact to the PCB.

6V (L TC3633A) 12V (L TC3633A-1) 0.6V (L TC3633A) 1.5V (L TC3633A-1) VON VIN CIN 1.22V INTVCC INTVCC RUN ITH PGOOD AV = 1 tON = VVON IION ION VIN ICMP IREV OSC1 140k ON TG M1 BOOST SW PGND FB SENSE– SENSE+ 1.4μA 0.6V REF M2BG SWITCH LOGIC AND ANTI- SHOOT THROUGH ION CONTROLLER COMP SELECT OSC OSC PLL-SYNC PHASE SELECT MODE SELECT R SQ CBOOST COUT – –+ EA CC1 RC 0.648V 0.552V TRACK 0.48V AT START-UP 0.10V AFTER START-UPCHANNEL 1 CHANNEL 2 (SAME AS CHANNEL 1) 3633a BD OSC1 OSC2 RT RRT PHMODE INTERNAL SOFT-START IDEAL DIODES BURSTFC 3.3V REG VIN1 MODE/SYNC TRACKSS V2P5 SGND INTVCC CVCC 2.5V REG CSS RUN RUN UV SS

the L TC3633A-1 has a VON sense range of 1.5V to 12V . acteristics of those products. Table 1. LTC3633A Family Features the SW and PGND nodes of the bottom power MOSFET . current matches that of the load current. ing in discontinuous operation and increased effi ciency. rises above the zero current level to initiate another cycle. synchronous operation regardless of output load current. its soft-start function when exiting an overvoltage condition. signifi cant advantage to running both channels out of phase. drawn from the input capacitor and supply at the same time.

and reduces the voltage noise on the supply line. resistors are selected to set the desired output voltage. tracking/soft-start, input UVLO, and PGOOD. allows the use of smaller inductor and capacitor values. where RRT is in Ω and f is in Hz. operating frequency determine the inductor ripple current. Figure 1. Switching Frequency vs RT

sampling of available surface mount inductors. Table 1. Inductor Selection Table dal wave current at the drain of the top power MOSFET .

Several capacitors may also be paralleled to meet size or height requirements in the design. For low input voltage applications, suffi cient bulk input capacitance is needed to minimize transient effects during output load changes. Even though the L TC3633A design includes an overvoltage protection circuit, care must always be taken to ensure input voltage transients do not pose an overvoltage hazard to the part. The selection of C OUT is determined by the effective series resistance (ESR) that is required to minimize voltage ripple and load step transients as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response. The output ripple, ΔV OUT, is approximated by: ΔVOUT < ΔIL ESR + 1 8•f•C OUT When using low-ESR ceramic capacitors, it is more useful to choose the output capacitor value to fulfi ll a charge stor- age requirement. During a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. The time required for the feedback loop to respond is dependent on the compensation and the output capacitor size. Typically, 3 to 4 cycles are required to respond to a load step, but only in the fi rst cycle does the output drop linearly. The output droop, V DROOP, is usually about 3 times the linear drop of the fi rst cycle. Thus, a good place to start is with the output capacitor size of approximately: COUT ≈ 3• ΔIOUT f•V DROOP Though this equation provides a good approximation, more capacitance may be required depending on the duty cycle and load step requirements. The actual V DROOP should be verifi ed by applying a load step to the output. Using Ceramic Input and Output Capacitors Higher values, lower cost ceramic capacitors are available in small case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regula- tor applications. However , due to the self-resonant and high-Q characteristics of some types of ceramic capaci- tors, care must be taken when these capacitors are used at the input. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the V IN input. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at V IN large enough to damage the part. For a more detailed discussion, refer to Application Note 88. When choosing the input and output ceramic capacitors, choose the X5R and X7R dielectric formulations. These dielectrics have the best temperature and voltage charac- teristics of all the ceramics for a given value and size. INTV CC Regulator Bypass Capacitor An internal low dropout (LDO) regulator draws power from the V IN1 input and produces the 3.3V supply that powers the internal bias circuitry and drives the gate of the internal MOSFET switches. The INTV CC pin connects to the output of this regulator and must have a minimum of 1μF ceramic decoupling capacitance to ground. The decoupling capacitor should have low impedance electrical connections to the INTV CC and PGND pins to provide the transient currents required by the L TC3633A. This supply is intended only to supply additional DC load currents as desired and not intended to regulate large transient or AC behavior , as this may impact L TC3633A operation. Boost Capacitor The L TC3633A uses a “bootstrap” circuit to create a voltage rail above the applied input voltage V IN. Specifi cally, a boost capacitor , CBOOST, is charged to a voltage approximately equal to INTVCC each time the bottom power MOSFET is turned on. The charge on this capacitor is then used to supply the required transient current during the remainder of the switching cycle. When the top MOSFET is turned on, the BOOST pin voltage will be equal to approximately V IN + 3.3V . For most applications, a 0.1μF ceramic capacitor closely connected between the BOOST and SW pins will provide adequate performance.

Figure 2. Setting the Output Voltage CC to disable the regulator. trace away from any noise source, such as the SW trace. from the programmed frequency. minimum duty cycle constraint.

what is limiting the effi ciency and which change would produce the most improvement. Percent effi ciency can be expressed as: % Effi ciency = 100% – (L1 + L2 + L3 +…) where L1, L2, etc. are the individual losses as a percent- age of input power . Although all dissipative elements in the circuit produce losses, three main sources usually account for most of the losses in L TC3633A circuits: 1) I 2R losses, 2) switch- ing losses and quiescent power loss 3) transition losses and other losses. 1. I 2R losses are calculated from the DC resistances of the internal switches, RSW, and external inductor , RL. In continuous mode, the average output current fl ows through inductor L but is “chopped” between the internal top and bottom power MOSFETs. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET R DS(ON) and the duty cycle (DC) as follows: R SW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) The R DS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus to obtain I 2R losses: I 2R losses = IOUT2(RSW + RL) 2. The internal LDO supplies the power to the INTVCC rail. The total power loss here is the sum of the switching losses and quiescent current losses from the control circuitry. Each time a power MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from V IN to ground. The resulting dQ/dt is a current out of INTVCC that is typically much larger than the DC control bias current. In continuous mode, IGATECHG = f(QT + QB), where QT and QB are the gate charges of the internal top and bottom power MOSFETs and f is the switching frequency. For estimation purposes, (Q T + QB) on each L TC3633A regulator channel is approximately 2.3nC. To calculate the total power loss from the LDO load, simply add the gate charge current and quiescent cur- rent and multiply by V IN: P LDO = (IGATECHG + IQ) • VIN 3. Other “hidden” losses such as transition loss, cop- per trace resistances, and internal load currents can account for additional effi ciency degradations in the overall power system. T ransition loss arises from the brief amount of time the top power MOSFET spends in the saturated region during switch node transitions. The L TC3633A internal power devices switch quickly enough that these losses are not signifi cant compared to other sources. Other losses, including diode conduction losses during dead-time and inductor core losses, generally account for less than 2% total additional loss. Thermal Considerations The L TC3633A requires the exposed package backplane metal (PGND) to be well soldered to the PC board to provide good thermal contact. This gives the QFN and TSSOP packages exceptional thermal properties, which are necessary to prevent excessive self-heating of the part in normal operation. In a majority of applications, the L TC3633A does not dis- sipate much heat due to its high effi ciency and low thermal resistance of its exposed-back QFN package. However , in applications where the L TC3633A is running at high ambi- ent temperature, high V IN, high switching frequency, and maximum output current load, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150°C, both power switches will be turned off until temperature returns to 140°C. To prevent the L TC3633A from exceeding the maximum junction temperature of 125°C, the user will need to do some thermal analysis. The goal of the thermal analysis

switch on-resistance is nominally 70mΩ at 70°C ambient. part by using a heat sink or air fl ow. operating junction temperature of 125°C. Figure 7. Temperature Derating Curve for DC1347 Demo Circuit change based on ambient temperature change.

3633 F07

of power loss in the package with corresponding output load current. Although making this measurement with this method does violate absolute maximum voltage ratings on the PGOOD pin, the applied power is so low that there should be no signifi cant risk of damaging the device. Board Layout Considerations When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the L TC3633A. Check the following in your layout: 1) Do the input capacitors connect to the V IN and PGND pins as close as possible? These capacitors provide the AC current to the internal power MOSFETs and their drivers. 2) The output capacitor , C OUT, and inductor L should be closely connected to minimize loss. The (–) plate of C OUT should be closely connected to both PGND and the (–) plate of CIN. 3) The resistive divider , (e.g. R1 to R4 in Figure 8) must be connected between the (+) plate of COUT and a ground line terminated near SGND. The feedback signal V FB should be routed away from noisy components and traces, such as the SW line, and its trace length should be minimized. In addition, the R T resistor and loop compensation components should be terminated to SGND. 4) Keep sensitive components away from the SW pin. The R T resistor , the compensation components, the feedback resistors, and the INTV CC bypass capacitor should all be routed away from the SW trace and the inductor L. 5) A ground plane is preferred, but if not available, the signal and power grounds should be segregated with both connecting to a common, low noise reference point. The connection to the PGND pin should be made with a minimal resistance trace from the reference point. APPLICATIONS INFORMATION 6) Flood all unused areas on all layers with copper in order to reduce the temperature rise of power components. These copper areas should be connected to the exposed backside of the package (PGND). Refer to Figures 9 and 10 for board layout examples. Design Example As a design example, consider using the L TC3633A in an application with the following specifi cations: V IN(MAX) = 13.2V , VOUT1 = 1.8V , VOUT2 = 3.3V , IOUT(MAX) = 3A, IOUT(MIN) = 10mA, f = 2MHz, VDROOP ~ (5% • VOUT). The following discussion will use equations from the previous sections. Because effi ciency is important at both high and low load current, Burst Mode operation will be utilized. First, the correct RT resistor value for 2MHz switching fre- quency must be chosen. Based on the equation discussed earlier , RT should be 160k; the closest standard value is 162k. RT can be tied to INTV CC if switching frequency accuracy is not critical. Next, determine the channel 1 inductor value for about 40% ripple current at maximum VIN: L1= 1.8V 2MHz •1.2A ⎝⎜ ⎞ ⎠⎟ 1− 1.8V 13.2V ⎝⎜ ⎞ ⎠⎟= 0.64μH A standard value of 0.68μH should work well here. Solv- ing the same equation for channel 2 results in a 1μH inductor . C OUT will be selected based on the charge storage require- ment. For a VDROOP of 90mV for a 3A load step: COUT1 ≈ 3• ΔIOUT f•V DROOP = 3•( 3 A ) (2MHz)(90mV) = 50μF

A 47μF ceramic capacitor should be suffi cient for channel 1. the closest standard value). The fi nal circuit is shown in Figure 8. Figure 8. Design Example Circuit

1.8V/2.5V 4MHz Buck Regulator RUN1 RUN2 RT L TC3633A BOOST2 3633a TA02 0.1μF 0.82μH 31.6k 10k SW2 VON2 VIN2 VIN1 VFB2 BOOST1 MODE/SYNC SW1 VON1 VFB1 COUT2 22μF VOUT2 2.5V AT 3A 0.1μF 0.68μH 24.3k 12.1k COUT1 47μF VOUT1 1.8V AT 3A VIN 12V 22μF 220pF 10pF 80.6k ITH2 V2P5 PHMODE 6.98k ITH1 INTVCC 2.2μF220pF 6.98k 10pF PGNDSGND 3.3V/1.8V Sequenced Regulator with 6V Input UVLO (V OUT1 Enabled After V OUT2) RUN1 PGOOD2 RUN2 RT L TC3633A BOOST2 3633a TA03 0.1μF 1μH 54.9k 12.1k SW2 VON2 VIN2 VIN1 VFB2 BOOST1 SW1 VON1 VFB1 COUT2 22μF VOUT2 3.3V AT 3A 0.1μF 0.68μH 24.3k 12.1k COUT1 47μF VOUT1 1.8V AT 3A VIN 6V TO 20V 47μF 162k 154k 40k V2P5 ITH1 ITH2 INTVCC 2.2μF MODE/SYNC PHMODE 100k PGNDSGND

1.2V/1.8V Buck Regulator with Coincident Tracking and 6V Input UVLO RUN1 RUN2 RT L TC3633A BOOST2 3633a TA04 0.1μF 0.47μH 10k 10k SW2 VON2 VIN2 VIN1 VFB2 BOOST1 SW1 VON1 VFB1 COUT2 68μF VOUT2 1.2V AT 3A 0.1μF 0.68μH 4.99k 10k COUT1 47μF VOUT1 1.8V AT 3A VIN 6V TO 20V 47μF 196k 154k 40k TRACKSS2 15k MODE/SYNC ITH1 ITH2 INTVCC 2.2μF V2P5 PHMODE PGNDSGND VIN1 VIN2 INTVCC L TC3633A ITH2 ITH1 MODE/SYNC 3633a TA06 RT VON1 VON2 VFB1 VFB2 29.4k 1μH VIN 3.6V TO 20V C1 22μF 2.2μF RUN1 RUN2 V2P5 PHMODE BOOST1 SW1 0.1μF BOOST2 SW2 0.1μF PGNDSGND 1μH COUT 47μF 19.6k VOUT 1.5V AT 6A 6.04k 1nF 324k 1.5V 1MHz Dual Phase Buck Regulator

Please refer to http://www.linear .com/designtools/packaging/ for the most recent package drawings. FE28 (EB) TSSOP REV I 0211 0.09 – 0.20 (.0035 – .0079) 0° – 8° 0.25 REF 0.50 – 0.75 (.020 – .030) 4.30 – 4.50* (.169 – .177) 13 4 5 6 7 89 1 0 11 12 13 14 19 20 22 21 15 16 18 17 9.60 – 9.80* (.378 – .386) 4.75 (.187) 2.74 (.108) 28 27 26 2524 23 1.20 (.047) MAX 0.05 – 0.15 (.002 – .006) 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 2RECOMMENDED SOLDER PAD LAYOUT EXPOSED PAD HEAT SINK ON BOTTOM OF PACKAGE0.45 ±0.05

0.65 BSC

4.50 ±0.10 6.60 ±0.10 1.05 ±0.10 4.75 (.187) 2.74 (.108) MILLIMETERS (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE SEE NOTE 4 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT 6.40 (.252) BSC 28-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663 Rev I) Exposed Pad Variation EB

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION 4.00 ± 0.10 (2 SIDES)

2.50 REF

5.00 ± 0.10 (2 SIDES) NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (NOTE 6) 0.40 ± 0.10 27 28 BOTTOM VIEW—EXPOSED PAD

3.50 REF

0.75 ± 0.05 R = 0.115 TYP R = 0.05 TYP PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER 0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05 (UFD28) QFN 0506 REV B RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 0.25 ±0.05 4.10 ± 0.05 5.50 ± 0.05 2.65 ± 0.05 3.10 ± 0.05 4.50 ± 0.05 PACKAGE OUTLINE 2.65 ± 0.10 3.65 ± 0.10 3.65 ± 0.05 28-Lead Plastic QFN (4mm × 5mm) (Reference L TC DWG # 05-08-1712 Rev B) Please refer to http://www.linear .com/designtools/packaging/ for the most recent package drawings.

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com © LINEAR TECHNOLOGY CORPORATION 2012 LT 0912 • PRINTED IN USA RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS LTC3633 15V, Dual 3A (I OUT), 4MHz Synchronous Step-Down DC/DC Converter 95% Effi ciency, VIN: 3.6V to 15V, VOUT(MIN) = 0.6V, IQ = 500μA, I SD < 13μA, 4mm × 5mm QFN-28, TSSOP-28E LTC3605 15V, 5A (I OUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Effi ciency, VIN: 4V to 15V, VOUT(MIN) = 0.6V, IQ = 2mA, ISD < 15μA, 4mm × 4mm QFN-24 LTC3603 15V, 2.5A (I OUT), 3MHz, Synchronous Step-Down DC/DC Converter 95% Effi ciency, VIN: 4.5V to 15V, VOUT(MIN) = 0.6V, IQ = 75μA, ISD < 1μA, 4mm × 4mm QFN-20, MSOP-16E LTC3602 10V, 2.5A (I OUT), 3MHz, Synchronous Step-Down DC/DC Converter 95% Effi ciency, VIN: 4.5V to 10V, VOUT(MIN) = 0.6V, IQ = 75μA, ISD < 1μA, 3mm × 3mm QFN-16, MSOP-16E LTC3601 15V, 1.5A (I OUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Effi ciency, VIN: 4.5V to 15V, VOUT(MIN) = 0.6V, IQ = 300μA, I SD < 1μA, 4mm × 4mm QFN-20, MSOP-16E LTC3605A 20V, 5A (I OUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Effi ciency, VIN: 4V to 20V, VOUT(MIN) = 0.6V, IQ = 2mA, ISD < 15μA, 4mm × 4mm QFN-24 LTC3604 15V, 2.5A (I OUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Effi ciency, VIN: 3.6V to 15V, VOUT(MIN) = 0.6V, IQ = 300μA, I SD < 15μA, 3mm × 3mm QFN-16, MSOP-16E LT3626 20V, 2.5A Synchronous Monolithic Step-Down Regulator with Current and Temperature Monitoring 95% Effi ciency, VIN: 3.6V to 20V, VOUT(MIN) = 0.6V, IQ = 300μA, ISD < 15μA, 3mm × 4mm QFN-20 3.3V/1.8V Buck Regulator with 2.5V LDO Output RUN1 RUN2 RT L TC3633A BOOST2 3633a TA07 0.1μF 0.68μH 20k 10k SW2 VON2 VIN2 VIN1 VFB2 BOOST1 SW1 VON1 VFB1 COUT2 47μF VOUT2 1.8V AT 3A 0.1μF 1μF 1μH 45.3k 10k COUT1 22μF VOUT1 3.3V AT 3A 2.5V AT 10mA VIN 12V 47μF 162k V2P5 ITH1 PHMODE ITH2 MODE/SYNC INTVCC 2.2μF PGNDSGND