LT3510EFE-TRPBF

LT3510 LINER | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 28

Technical content

FEATURES

APPLICATIONS

DESCRIPTION

The L T®3510 is a dual current mode PWM step-down DC/DC converter with two internal 2.5A switches. Inde- pendent input voltage, feedback, soft-start and power good pins for each channel simplify complex power supply tracking/sequencing requirements. Both converters are synchronized to either a common external clock input or a resistor programmable ﬁ xed 250kHz to 1.5MHz internal oscillator . At all frequencies, a 180° phase relationship between channels is maintained, reducing voltage ripple and component size. Programmable frequency allows for optimization between efﬁ ciency and external component size. Minimum input-to-output voltage ratios are improved by allowing the switch to stay on through multiple clock cycles, only switching off when the boost capacitor needs recharging, resulting in ~95% maximum duty cycle. Each output can be independently disabled using its own soft-start pin, or by using the SHDN pin the entire part can be placed in a low quiescent current shutdown mode. The L T3510 is available in a 20-lead TSSOP package with exposed leadframe for low thermal resistance. n DSP Power Supplies n Disc Drives n DSL/Cable Modems n Wall T ransformer Regulation n Distributed Power Regulation n PCI Cards n Wide Input Range: 3.1V to 25V n T wo Switching Regulators with 2A Output Capability n Independent Supply to Each Regulator n Adjustable/Synchronizable Fixed Frequency Operation from 250kHz to 1.5MHz n Antiphase Switching n Outputs Can be Paralleled n Independent, Sequential, Ratiometric or Absolute T racking Between Outputs n Independent Soft-Start and Power Good Pins n Enhanced Short-Circuit Protection n Low Dropout: 95% Maximum Duty Cycle n Low Shutdown Current: <10μA n 20-Lead TSSOP Package with Exposed Leadframe 3.3V and 1.8V Dual 2A Step-Down Converter with Output T racking , LT, LTC, and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Efﬁ ciency SHDN 4.7μF 47μF 100μF24.9k 61.9k 8.06k 470pF 10pF 47pF40.2k 4.7μH 3.3μH VOUT1 3.3V VOUT2 1.8V VIN 12V 0.47μF B360A B360A 0.47μF PMEG4005 PMEG4005 VIN1 VIN2 LT3510 GND BST1 SW1 IND1 VOUT1 PG1 FB1 VC1 SS/TRACK1 RT/SYNC BST2 SW2 IND2 VOUT2 PG2 FB2 VC2 SS/TRACK2 10k 8.06k

3510 TA01a

0.1μF 470pF 40.2k LOAD CURRENT (A) EFFICIENCY (%) 0.5 1 1.5

3510 TA01b

2VOUT = 5V VOUT = 3.3V VOUT = 2.5VVOUT = 1.8V VIN = 12V IOUT2 = 0A FREQUENCY = 500kHz

ELECTRICAL CHARACTERISTICS

V Operating Junction Temperature Range (Note 1) The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TJ = 25°C. VVIN1/2 = 15V , VBST1/2 = open, VRT/SYNC = 2V , VVOUT1/2 = open, unless otherwise speciﬁ ed. PARAMETER CONDITIONS MIN TYP MAX UNITS SHDN Threshold V OUT1/2 = 0V , RT/SYNC = 133k l 1.23 1.28 1.37 V SHDN Input Current V SHDN = 1.375V VSHDN = 1.225V μA μA Minimum Input Voltage Ch 1 (Note 3) V FB1/2 = 0V , VVOUT1/2 = 0V , VIND1/2 = 0V , RT/SYNC = 133k 2.8 3 V Minimum Input Voltage Ch 2 V FB1/2 = 0V , VVOUT1/2 = 0V , VIND1/2 = 0V 2.8 3 V Supply Shutdown Current Ch 1 V SHDN = 0V l 93 0 μ A Supply Shutdown Current Ch 2 V SHDN = 0V 0 5 μA Supply Quiescent Current Ch 1 V FB1/2 = 0.9V 3.5 5 mA Supply Quiescent Current Ch 2 V FB1/2 = 0.9V 200 500 μA Feedback Voltage Ch 1/2 V VC1/2 = 1V l 0.784 0.8 0.816 V PIN CONFIGURATION FE PACKAGE 20-LEAD PLASTIC TSSOP TOP VIEW V IN1 SW1 IND1 VOUT1 PG1 PG2 V OUT2 IND2 SW2 VIN2 BST1 SS/TRACK1 V FB1 R T/SYNC SHDN FB2 V SS/TRACK2 BST2 TJMAX = 125°C, θJA = 45°C/W , θJC(PAD) = 10°C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L T3510EFE#PBF L T3510EFE#TRPBF L T3510FE 20-Lead TSSOP –40°C to 125°C L T3510IFE#PBF L T3510IFE#TRPBF L T3510FE 20-Lead TSSOP –40°C to 125°C LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L T3510EFE L T3510EFE#TR L T3510FE 20-Lead TSSOP –40°C to 125°C L T3510IFE L T3510IFE#TR L T3510FE 20-Lead TSSOP –40°C to 125°C Consult L TC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel speciﬁ cations, go to: http://www.linear .com/tapeandreel/

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. PARAMETER CONDITIONS MIN TYP MAX UNITS Feedback Voltage Line Regulation V VIN1/2 = 3V to 25V l –1 0 1 % Feedback Voltage Offset Ch 1 to Ch 2 V VC1/2 = 1V l –16 0 16 mV Feedback Bias Current Ch 1/2 V FB1/2 = 0.8V , VVC1/2 = 1V l –200 75 200 nA Error Ampliﬁ er gm Ch 1/2 V VC1/2 = 1V , IVC1/2 = ±5μA l 150 275 450 μmho Error Ampliﬁ er Gain Ch 1/2 1000 V/V Error Ampliﬁ er to Switch Gain Ch 1/2 2.2 A/V Error Ampliﬁ er Source Current Ch 1/2 V FB1/2 = 0.6V , VVC1/2 = 1V 10 15 25 μA Error Ampliﬁ er Sink Current Ch 1/2 V FB1/2 = 1V , VVC1/2 = 1V 15 20 30 μA Error Ampliﬁ er High Clamp Ch 1/2 V FB1/2 = 0.7V 1.75 2.0 2.25 V Error Ampliﬁ er Switching Threshold Ch 1/2 V OUT1/2 = 5V , RT/SYNC = 133k 0.5 0.7 1.0 V Soft-Start Source Current Ch 1/2 V FB1/2 = 0.6V , VSS1/2 = 0.4V l 2.5 3.25 4 μA Soft-Start VOH Ch 1/2 V FB1/2 = 0.9V 1.9 2 2.4 V Soft-Start Sink Current Ch 1/2 V FB1/2 = 0.6V , VSS1/2 = 1V 200 600 1000 μA Soft-Start VOL Ch 1/2 V FB1/2 = 0V 50 80 125 mV Soft-Start to Feedback Offset Ch 1/2 V VC1/2 = 1V , VSS1/2 = 0.4V l –16 0 16 mV Soft-Start Sink Current Ch 1/2 POR V SS1/2 = 0.4V (Note 4), VVC = 1V 0.5 1.5 2 mA Soft-Start POR Threshold Ch 1/2 V FB1/2 = 0V (Note 4) 55 80 105 mV Soft-Start Switching Threshold Ch 1/2 V FB1/2 = 0V 30 50 70 mV Power Good Leakage Ch 1/2 V FB1/2 = 0.9V , VPG1/2 = 25V , VVIN1/2 = 25V , VOUT = 5V 0 1 μA Power Good Threshold Ch 1/2 V FB1/2 Rising, PG1/2 = 20k to 5V l 87 90 93 % Power Good Hysteresis Ch 1/2 V FB1/2 Falling, PG1/2 = 20k to 5V 20 30 50 mV Power Good Sink Current Ch 1/2 V FB1/2 = 0.65V , VPG1/2 = 0.4V 400 800 1200 μA Power Good Shutdown Sink Current Ch 1/2 V VIN1/2 = 2V , VFB1/2 = 0V , VPG1/2 = 0.4V 10 50 100 μA RT/SYNC Reference Voltage V FB1/2 = 0.9V , IRT/SYNC = –40μA 0.93 0.975 1 V Switching Frequency R T/SYNC = 133k, VFB1/2 = 0.6V , VBST1/2 = VSW + 3V RT/SYNC = 15.4k, VFB1/2 = 0.6V , VBST1/2 = VSW + 3V 200 1.2 250 1.5 300 1.8 kHz MHz Switching Phase Angle Ch A to Ch B R T/SYNC = 133k, VFB1/2 = 0.6V , VBST1/2 = VSW + 3V 120 180 210 Deg Minimum Boost for 100% Duty Cycle Ch 1/2 V FB1/2 = 0.7V , IRT/SYNC = –35μA (Note 5), VOUT = 0V 1.7 2 V SYNC Frequency Range V BST1/2 = VSW + 3V 250 1500 kHz SYNC Switching Phase Angle Ch A to Ch B SYNC = 250kHz, V BST1/2 = VSW + 3V 120 180 210 Deg IND + VOUT Current Ch 1/2 V VOUT1/2 = 0V , VFB1/2 = 0.9V VVOUT1/2 = 5V 40 70 100 μA μA IND to VOUT Maximum Current Ch 1/2 V VOUT1/2 = 0.5V (Note 6), VFB1/2 = 0.7V , VBST1/2 = 20V VVOUT1/2 = 5V (Note 6), RT/SYNC = 133k, VBST1/2 = 20V 2.25 2.5 2.8 2.8 A A Switch Leakage Current Ch 1/2 V SW1/2 = 0V , VVIN1/2 = 25V l 05 0 μ A Switch Saturation Voltage Ch 1/2 I SW1/2 = 2A, VBST1/2 = 20V , VFB1/2 = 0.7V l 250 400 mV Boost Current Ch 1/2 I SW1/2 = 2A, VBST1/2 = 20V , VFB1/2 = 0.7V 25 50 100 mA Minimum Boost Voltage Ch 1/2 I SW1/2 = 2A, VBST1/2 = 20V , VFB1/2 = 0.7V (Note 7) 1.4 2.5 V Note 2: The L T3510EFE is guaranteed to meet performance speciﬁ cations from 0°C to 125°C junction temperature. Speciﬁ cations over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TJ = 25°C. VVIN1/2 = 15V , VBST1/2 = open, VRT/SYNC = 2V , VVOUT1/2 = open, unless otherwise speciﬁ ed.

TYPICAL PERFORMANCE CHARACTERISTICS L T3510IFE is guaranteed and tested over the full –40°C to 125°C operating junction temperature range. Note 3: Minimum input voltage is deﬁ ned as the voltage where internal bias lines are regulated so that the reference voltage and oscillator remain constant. Actual minimum input voltage to maintain a regulated output will depend upon output voltage and load current. See Applications Information. Note 4: An internal power-on reset (POR) latch is set on the positive transition of the SHDN pin through its threshold. The output of the latch activates current sources on each SS pin which typically sink 1.5mA, discharging the SS capacitor . The latch is reset when both SS pins are driven below the soft-start POR threshold or the SHDN pin is taken below its threshold. Note 5: To enhance dropout operation, the output switch will be turned off for the minimum off time only when the voltage across the boost capacitor drops below the minimum boost for 100% duty cycle threshold. Note 6: The IND to V OUT maximum current is deﬁ ned as the value of current ﬂ owing from the IND pin to the VOUT pin which resets the switch latch when the VC pin is at its high clamp. Note 7: This is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch. Note 8: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the speciﬁ ed maximum operating junction temperature may impair device reliability. Feedback Voltage vs Temperature R T/SYNC Voltage vs Temperature Shutdown Threshold and Minimum Input Voltage vs Temperature Shutdown Quiescent Current vs Temperature Soft-Start Source Current vs Temperature TEMPERATURE (°C) –50 VOLTAGE (V) 0.806 0.811 0.816 25 75

3510 G02

0.801 0.796 –25 0 50 100 125 0.791 0.786 TEMPERATURE (°C) –50 –25 0.95 VOLTAGE (V)0.99 1.05 0 50 75

3510 G03

0.97 1.03 1.01 25 100 125 TEMPERATURE (°C) –50 VOLTAGE (V) 2.0 2.5 3.0 25 75

3510 G04

1.5 1.0 –25 0 50 100 125 0.5 MINIMUM INPUT VOLTAGE SHUTDOWN THRESHOLD VOLTAGE TEMPERATURE (°C) –50 CURRENT (μA)

3510 G05

–25 0 50 75 100 125 VVIN1 VVIN2 TEMPERATURE (°C) –50 2.0 CURRENT (μA) 2.2 2.6 2.8 3.0 4.0 3.4 0 50 75

3510 G07

2.4 3.6 3.8 3.2 –25 25 100 125 IND to VOUT Maximum Current vs Temperature TEMPERATURE (°C) –50 2.0 CURRENT (A) 2.2 2.6 2.8 3.0 4.0 3.4 –10 30 50

3510 G30

2.4 3.6 3.8 3.2 –30 10 70 VOUT = 5V VOUT = 0V 90 110

TYPICAL PERFORMANCE CHARACTERISTICS Soft-Start to Feedback Offset Voltage vs Temperature VC Switching Threshold Voltage vs Temperature Power Good Threshold Voltage vs Temperature Power Good Sink Current vs Temperature Minimum Switching Times vs Temperature Switching Frequency and Channel Phase vs Temperature Switching Frequency and Channel Phase vs Temperature Synchronization Clock Frequency Range vs Temperature Channel Phase vs Temperature with External Synchronization TEMPERATURE (°C) –50 VOLTAGE (mV)

3510 G08

–25 0 50 75 100 125 TEMPERATURE (°C) –50 VOLTAGE (V) 800 900 1000 25 75

3510 G09

–25 0 50 100 125 500 400 VOUT = 5V VOUT = 0V TEMPERATURE (°C) –50

600 VOLTAGE (V)

3510 G10

–25 25 100 125 RISING FALLING TEMPERATURE (°C) –50

500 CURRENT (μA)

3510 G11

–25 25 100 125 TEMPERATURE (°C) –50 TIME (ns) 110 130 150 250 190 0 50 75

3510 G12

–25 25 100 125 MINIMUM ON TIME MINIMUM OFF TIME TEMPERATURE (°C) –50

200 FREQUENCY (kHz)

PHASE (DEG) 210 230 240 250 300 270 0 50 75

3510 G13

–25 25 100 125 PHASE FREQUENCY RT/SYNC = 133k TEMPERATURE (°C) –50 FREQUENCY (kHz) PHASE (DEG)1550 1600 1650 25 75

3510 G14

–25 0 50 100 125 1400 1350 190 195 200 185 180 175 170 165 160 155 150 FREQUENCY PHASE RRT/SYNC = 15.4k TEMPERATURE (°C) –50 –25 FREQUENCY (kHz) 1000 2500 0 50 75

3510 G15

TEMPERATURE (°C) –50

168 PHASE (DEG)

3510 G16

–25 25 100 125 SYNCHRONIZATION FREQUENCY = 250kHz SYNCHRONIZATION FREQUENCY = 1500kHz

TYPICAL PERFORMANCE CHARACTERISTICS External Sync Duty Cycle Range vs External Sync Frequency Frequency and Phase vs RT/SYNC Pin Resistance Switch Saturation Voltage vs Switch Current Minimum Boost Voltage vs Temperature VOUT + IND Current vs Temperature VOUT + IND Current vs VOUT Voltage Minimum Input Voltage vs Load Current Minimum Input Voltage vs Load Current Minimum Input Voltage vs Load Current FREQUENCY (kHz) 250 DUTY CYCLE (%) 100 1250

3510 G17

RESISTANCE (kΩ) 0 20 40 60 80 100 120 140 FREQUENCY (kHz) PHASE (DEG) 800 1200

3510 G18

CURRENT (A) 0.5 VOL TAGE (mV) 150 200 250 1.1 1.5

3510 G19

125°C 25°C –50°C TEMPERATURE (°C) –50 –25 VOLTAGE (V)1.0 2.5 0 50 75

3510 G21

0.5 2.0 1.5 25 100 125 TEMPERATURE (°C) –50

50 CURRENT (μA)

3510 G22

–25 25 100 125 VOLTAGE (V) CURRENT (μA) 100 1.6

3510 G23

CURRENT (mA)

2.0 VOLTAGE (V)

2.5 3.0 3.5 4.0 4.5 5.0 10 100 1000 10000

3510 G24

VOUT = 2.5V RUNNING CURRENT (mA) 4.5 VOLTAGE (V) 5.0 5.5 6.0 6.5 7.0 7.5 10 100 1000 10000

3510 G26

VOUT = 5V RUNNING CURRENT (mA) 3.0 VOLTAGE (V) 3.5 4.0 4.5 5.0 5.5 6.0 10 100 1000 10000

3510 G25

VOUT = 3.3V RUNNING

TYPICAL PERFORMANCE CHARACTERISTICS VIN1 (Pin 1): The V IN1 pin powers the internal control circuitry for both channels and is monitored by the undervoltage lockout comparator . The V IN1 pin is also connected to the collector of channel 1’s on-chip power NPN switch. The V IN1 pin has high dI/dt edges and must be decoupled to ground close to the pin of the device. SW1/SW2 (Pins 2, 9): The SW pin is the emitter of the on- chip power NPN. At switch off, the inductor will drive this pin below ground with a high dV/dt. An external Schottky catch diode to ground, close to the SW pin and respective V IN decoupling capacitor’s ground, must be used to prevent this pin from excessive negative voltages. IND1/IND2 (Pins 3, 8): The IND pin is the input to the on-chip sense resistor that measures current ﬂ owing in the inductor . When the current in the resistor exceeds the current dictated by the V C pin, the SW latch is held in reset, disabling the output switch. Bias current ﬂ ows out of the IND pin when IND is less than 1.6V . VOUT1/VOUT2 (Pins 4, 7): The V OUT pin is the output to the on-chip sense resistor that measures current ﬂ owing in the inductor . When the current in the resistor exceeds the current dictated by the V C pin, the SW latch is held in reset, disabling the output switch. Bias current ﬂ ows out of the VOUT pin when VOUT is less than 1.6V . PG1/PG2 (Pins 5, 6): The power good pin is an open-col- lector output that sinks current when the feedback falls below 90% of its nominal regulating voltage. For V IN1 above 1V , its output state remains true, although during shutdown, V IN1 undervoltage lockout or thermal shutdown, its current sink capability is reduced. The PG pins can be left open circuit or tied together to form a single power good signal. V IN2 (Pin 10): The VIN2 pin is the collector of channel 2’s on-chip power NPN switch. This pin is independent of VIN1 and may be connected to the same or a separate supply. In either case, high dI/dt edges are present and decoupling to ground must be used close to this pin. SS1/SS2 (Pins 19, 12): The SS1/2 pins control the soft- start and sequence of their respective outputs. A single capacitor from the SS pin to ground determines the outpt ramp rate. For soft-start and output tracking/sequencing details, see the Applications Information section. V C1/VC2 (Pins 18, 13): The V C pin is the output of the error ampliﬁ er and the input to the peak switch current comparator . It is normally used for frequency compensa- tion, but can also be used as a current clamp or control loop override. If the error ampliﬁ er drives V C above the maximum switch current level, a voltage clamp activates. Dropout Operation Inductor Value vs Frequency for 2A Maximum Load Current Inductor Value vs Frequency for 2A Maximum Load Current INPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 34 5 6

3510 G27

2.5 3.5 4.5 5.5 FREQUENCY 1.5MHz 250kHz LOAD = 1A VOUT = 5V VOUT = 3.3V INPUT VOLTAGE (V) 250 FREQUENCY (kHz) 500 1000 1250 1500 11 15 17 25

3510 G28

L = 2.2μH L = 3.3μH L = 4.7μH L = 6.8μH VOUT = 3.3V IRIPPLE = 1A INPUT VOLTAGE (V) 250 FREQUENCY (kHz) 500 750 1000 1250 1500 12.5 15 17.5 20

3510 G29

22.5 25 VOUT = 5V IRIPPLE = 1AL = 2.2μH L = 3.3μH L = 4.7μH L = 6.8μH L = 10μH

This indicates that the output is overloaded and current is pulled from the SS pin, reducing the regulation point. FB1/FB2 (Pins 17, 14): The FB pin is the negative input to the error ampliﬁ er . The output switches regulate this pin to 0.8V , with respect to the exposed ground pad. Bias current ﬂ ows out of the FB pin. SHDN (Pin 15): The shutdown pin is used to turn off both channels and control circuitry to reduce quiescent current to a typical value of 9μA. The accurate 1.28V threshold and input current hysteresis can be used as an undervoltage lockout, preventing the regulator from operating until the input voltage has reached a predetermined level. Force the SHDN pin above its threshold or let it ﬂ oat for normal operation. R T/SYNC (Pin 16): This RT/SYNC pin provides two modes of setting the constant switch frequency. Connecting a resistor from the R T/SYNC pin to ground will set the RT/SYNC pin to a typical value of 0.975V . The resultant switching frequency will be set by the resistor value. The minimum value of 15.4k and maximum value of 133k sets the switching frequency to 1.5MHz and 250kHz respectively. Driving the R T/SYNC pin with an external clock signal will synchronize the switch to the applied frequency. Synchro- nization occurs on the rising edge of the clock signal after the clock signal is detected, with switch 1 in phase with the synchronization signal. Each rising clock edge initiates an oscillator ramp reset. A gain control loop servos the oscillator charging current to maintain a constant oscillator amplitude. Hence, the slope compensation and channel phase relationship remain unchanged. If the clock signal is removed, the oscillator reverts to resistor mode and reapplies the 0.975V bias to the R T/SYNC pin after the synchronization detection circuitry times out. The clock source impedance should be set such that the current out of the R T/SYNC pin in resistor mode generates a frequency roughly equivalent to the synchronization frequency. BST1/BST2 (Pins 20, 11): The BST pin provides a higher than VIN base drive to the power NPN to ensure a low switch drop. A comparator to V IN imposes a minimum off time on the SW pin if the BST pin voltage drops too low. Forcing a SW off time allows the boost capacitor to recharge. Exposed Pad (Pin 21): GND. The Exposed Pad GND pin is the only ground connection for the device. The Exposed Pad should be soldered to a large copper area to reduce thermal resistance. The GND pin is common to both chan- nels and also serves as small-signal ground. For ideal operation all small-signal ground paths should connect to the GND pin at a single point, avoiding any high current ground returns.

Figure 1. Block Diagram (One of T wo Switching Regulators Shown) L T3510 will be placed in a low quiescent current mode. and a POR signal which sets the soft-start latch.

will be generated at the incoming frequency on the rising edge of the synchronization pulse with switch 1 in phase with the synchronization signal. In addition, the internal slope compensation will be automatically adjusted to pre- vent subharmonic oscillation during synchronization. The two regulators are constant frequency, current mode step-down converters. Current mode regulators are con- trolled by an internal clock and two feedback loops that control the duty cycle of the power switch. In addition to the normal error ampliﬁ er , there is a current sense ampliﬁ er that monitors switch current on a cycle-by-cycle basis. This technique means that the error ampliﬁ er commands current to be delivered to the output rather than voltage. A voltage fed system will have low phase shift up to the resonant frequency of the inductor and output capacitor , then an abrupt 180°, shift will occur . The current fed sys- tem will have 90° phase shift at a much lower frequency, but will not have the additional 90° shift until well beyond the LC resonant frequency. This makes it much easier to frequency compensate the feedback loop and also gives much quicker transient response. The Block Diagram in Figure 1 shows only one of the switching regulators whose operation will be discussed below. The additional regulator will operate in a similar manner with the exception that its clock will be 180° out of phase with the other regulator . When, during power up, the POR signal sets the soft-start latch, both SS pins will be discharged to ground to ensure proper start-up operation. When the SS pin voltage drops below 80mV , the V C pin is driven low disabling switching and the soft-start latch is reset. Once the latch is reset the soft-start capacitor starts to charge with a typical value of 3.25μA. As the voltage rises above 80mV on the SS pin, the V C pin will be driven high by the error ampliﬁ er . When the voltage on the VC pin exceeds 0.7V , the clock set pulse sets the driver ﬂ ip-ﬂ op which turns on the internal power NPN switch. This causes current from V IN, through the NPN switch, inductor and internal sense resistor , to increase. When the voltage drop across the internal sense resistor exceeds a predetermined level set by the voltage on the V C pin, the ﬂ ip-ﬂ op is reset and the internal NPN switch is turned off. Once the switch is turned off the inductor will drive the voltage at the SW pin low until the external Schottky diode starts to conduct, decreasing the current in the inductor . The cycle is repeated with the start of each clock cycle. However , if the internal sense resistor voltage exceeds the predetermined level at the start of a clock cycle, the ﬂ ip-ﬂ op will not be set resulting in a further decrease in inductor current. Since the output current is controlled by the V C voltage, output regulation is achieved by the error ampliﬁ er continually adjusting the VC pin voltage. The error ampliﬁ er is a transconductance ampliﬁ er that compares the FB voltage to the lowest voltage present at either the SS pin or an internal 0.8V reference. Compensa- tion of the loop is easily achieved with a simple capacitor or series resistor/capacitor from the V C pin to ground. Since the SS pin is driven by a constant current source, a single capacitor on the soft-start pin will generate controlled linear ramp on the output voltage. If the current demanded by the output exceeds the maxi- mum current dictated by the V C pin clamp, the SS pin will be discharged, lowering the regulation point until the output voltage can be supported by the maximum current. When overload is removed, the output will soft-start from the overload regulation point. V IN1 undervoltage detection or thermal shutdown will set the soft-start latch, resulting in a complete soft-start sequence. The switch driver operates from either the V IN or BST volt- age. An external diode and capacitor are used to generate a drive voltage higher than V IN to saturate the output NPN and maintain high efﬁ ciency. If the BST capacitor voltage is sufﬁ cient, the switch is allowed to operate to 100% duty cycle. If the boost capacitor discharges towards a level insufﬁ cient to drive the output NPN, a BST pin compara- tor forces a minimum cycle off time, allowing the boost capacitor to recharge. A power good comparator with 30mV of hysteresis trips at 90% of regulated output voltage. The PG output is an open-collector NPN that is off when the output is in regu- lation allowing a resistor to pull the PG pin to a desired voltage.

ence designators refer to the Block Diagram in Figure 1. Figure 1. The RT/SYNC pin is internally regulated at 0.975V . illustrates the tradeoffs of switch frequency selection. input voltage range of the regulator can be determined. Figure 2. Frequency and Phase vs RT/SYNC Resistance Table 1. Efﬁ ciency and Size Comparisons for Different RRT/SYNC Values. 3.3V †VIN(MAX) is deﬁ ned as the highest input voltage that maintains constant output voltage ripple. *Inductor and capacitor values chosen for stability and constant ripple current.

3510 F02

the Electrical Characteristics. where VSW is the voltage drop of the internal switch. IN and BST pins are not violated. where f is frequency in MHz and L is in μH. Figure 3. Minimum Input Voltage vs Load Current

3510 F03

current less than 40% of peak switch current. with a lower DCR resulting in higher efﬁ ciency. size restrictions and efﬁ ciency goals. equations assume that the inductor current is continuous. Figure 4. Inductor Values for 2A Maximum Load Current

3510 F04

may result in discontinuous mode operation, which is okay, but further reduces maximum load current. For details of maximum output current and discontinuous mode operation, see Linear Technology Application Note 44. Finally, for duty cycles greater than 50% (V OUT/VIN > 0.5), there is a minimum inductance required to avoid subharmonic oscillations. See Application Note 19 for more information. Input Capacitor Selection Bypass the inputs of the L T3510 circuit with a 4.7μF or higher ceramic capacitor of X7R or X5R type. A lower value or a less expensive Y5V type can be used if there is additional bypassing provided by bulk electrolytic or tantalum capacitors. The following paragraphs describe the input capacitor considerations in more detail. Step-down regulators draw current from the input supply in pulses with very fast rise and fall times. The input capaci- tor is required to reduce the resulting voltage ripple at the L T3510 and to force this very high frequency switching current into a tight local loop, minimizing EMI. The input capacitor must have low impedance at the switching fre- quency to do this effectively, and it must have an adequate ripple current rating. With two switchers operating at the same frequency but with different phases and duty cycles, calculating the input capacitor RMS current is not simple. However , a conservative value is the RMS input current for the channel that is delivering most power (V OUT • IOUT). This is given by: I IV V V V I CIN RMS OUT OUT IN OUT IN OUT

–= () < 2 and is largest when V IN = 2V OUT (50% duty cycle). As the second, lower power channel draws input current, the input capacitor’s RMS current actually decreases as the out-of-phase current cancels the current drawn by the higher power channel. Considering that the maximum load current from a single channel is ~2A, RMS ripple current will always be less than 1A. The frequency, V IN to VOUT ratio, and maximum load cur- rent requirement of the L T3510 along with the input supply source impedance, determine the energy storage require- ments of the input capacitor . Determine the worst-case condition for input ripple current and then size the input capacitor such that it reduces input voltage ripple to an acceptable level. Typical values for input capacitors run from 10μF at low frequencies to 2.2μF at higher frequencies. The combination of small size and low impedance (low equivalent series resistance or ESR) of ceramic capacitors make them the preferred choice. The low ESR results in very low voltage ripple and the capacitors can handle plenty of ripple current. They are also comparatively robust and can be used in this application at their rated voltage. X5R and X7R types are stable over temperature and applied voltage, and give dependable service. Other types (Y5V and Z5U) have very large temperature and voltage coefﬁ cients of capacitance, so they may have only a small fraction of their nominal capacitance in your application. While they will still handle the RMS ripple current, the input voltage ripple may become fairly large, and the ripple current may end up ﬂ owing from your input supply or from other by- pass capacitors in your system, as opposed to being fully sourced from the local input capacitor . An alternative to a high value ceramic capacitor is a lower value along with a larger electrolytic capacitor , for example a 1μF ceramic capacitor in parallel with a low ESR tantalum capacitor . For the electrolytic capacitor , a value larger than 10μF will be required to meet the ESR and ripple current require- ments. Because the input capacitor is likely to see high surge currents when the input source is applied, tantalum capacitors should be surge rated. The manufacturer may also recommend operation below the rated voltage of the capacitor . Be sure to place the 1μF ceramic as close as possible to the V IN and GND pins on the IC for optimal noise immunity. When the L T3510’s input supplies are operated at different input voltages, an input capacitor sized for that channel should be placed as close as possible to the respective V IN pins. A ﬁ nal caution regarding the use of ceramic capacitors at the input. A ceramic input capacitor can combine with stray inductance to form a resonant tank circuit. If power is applied quickly (for example by plugging the circuit into a live power source) this tank can ring, doubling the input voltage and damaging the L T3510. The solution is to APPLICATIONS INFORMATION

either clamp the input voltage or dampen the tank circuit by adding a lossy capacitor in parallel with the ceramic capacitor . For details, see Application Note 88. Output Capacitor Selection Typically step-down regulators are easily compensated with an output crossover frequency that is 1/10 of the switch- ing frequency. This means that the time that the output capacitor must supply the output load during a transient step is ~2 or 3 switching periods. With an allowable 5% drop in output voltage during the step, a good starting value for the output capacitor can be expressed by: C Max Load Step Frequency VVOUT OUT = •. •00 5 Example: VOUT = 3.3V , Frequency = 1MHz, Max Load Step = 2A C eV FVOUT == 2 16 00 5 33 12•. •. μ The calculated value is only a suggested starting value. Increase the value if transient response needs improvement or reduce the capacitance if size is a priority. The output capacitor ﬁ lters the inductor current to generate an output with low voltage ripple. It also stores energy in order to satisfy transient loads and to stabilize the L T3510’s control loop. The switching frequency of the L T3510 deter- mines the value of output capacitance required. Also, the current mode control loop doesn’t require the presence of output capacitor series resistance (ESR). For these reasons, you are free to use ceramic capacitors to achieve very low output ripple and small circuit size. Estimate output ripple with the following equations: V RIPPLE = ΔIL/(8f COUT) for ceramic capacitors, and VRIPPLE = ΔIL ESR for electrolytic capacitors (tantalum and aluminum) where ΔIL is the peak-to-peak ripple current in the inductor . The RMS content of this ripple is very low, and the RMS current rating of the output capacitor is usually not of concern. Another constraint on the output capacitor is that it must have greater energy storage than the inductor; if the stored energy in the inductor is transferred to the output, you would like the resulting voltage step to be small compared to the regulation voltage. For a 5% overshoot, this require- ment becomes: CL I VOUT LIM OUT > ⎛ ⎠⎟10 Finally, there must be enough capacitance for good transient performance. The last equation gives a good starting point. Alternatively, you can start with one of the designs in this data sheet and experiment to get the desired performance. This topic is covered more thoroughly in the section on loop compensation. The high performance (low ESR), small size and robustness of ceramic capacitors make them the preferred type for L T3510 applications. However , all ceramic capacitors are not the same. As mentioned above, many of the high value capacitors use poor dielectrics with high temperature and voltage coefﬁ cients. In particular , Y5V and Z5U types lose a large fraction of their capacitance with applied voltage and temperature extremes. Because the loop stability and transient response depend on the value of C OUT, you may not be able to tolerate this loss. Use X7R and X5R types. You can also use electrolytic capacitors. The ESRs of most aluminum electrolytics are too large to deliver low output ripple. Tantalum and newer , lower ESR organic electrolytic capacitors intended for power supply use, are suitable and the manufacturers will specify the ESR. The choice of capacitor value will be based on the ESR required for low ripple. Because the volume of the capacitor determines its ESR, both the size and the value will be larger than a ceramic capacitor that would give you similar ripple per- formance. One beneﬁ t is that the larger capacitance may give better transient response for large changes in load current. Table 2 lists several capacitor vendors. APPLICATIONS INFORMATION

Taiyo Yuden Ceramic X5R, X7R AVX Ceramic X5R, X7R Tantalum Kemet Tantalum TA Organic AL Organic T491, T494, T495 T520 A700 Sanyo TA/AL Organic POSCAP Panasonic AL Organic SP CAP TDK Ceramic X5R, X7R Catch Diode The diode D1 conducts current only during switch off time. Use a Schottky diode to limit forward voltage drop to increase efﬁ ciency. The Schottky diode must have a peak reverse voltage that is equal to regulator input voltage and sized for average forward current in normal operation. Average forward current can be calculated from: I I V VVD AVG OUT IN IN OUT() •–= () The only reason to consider a larger diode is the worst- case condition of a high input voltage and shorted output. With a shorted condition, diode current will increase to a typical value of 3A, determined by the peak switch current limit of the L T3510. This is safe for short periods of time, but it would be prudent to check with the diode manu- facturer if continuous operation under these conditions can be tolerated. BST Pin Considerations The capacitor and diode tied to the BST pin generate a voltage that is higher than the input voltage. In most cases a 0.47μF capacitor and fast switching diode (such as the CMDSH-3 or FMMD914) will work well. Almost any type of ﬁ lm or ceramic capacitor is suitable, but the ESR should be <1 Ω to ensure it can be fully recharged during the off time of the switch. The capacitor value can be approximated by: C ID C BV V fBST OUT MAX OUT BST MIN

– • where I OUT(MAX) is the maximum load current, and VBST(MIN) is the minimum boost voltage to fully saturate the switch. Figure 5 shows four ways to arrange the boost circuit. The BST pin must be more than 1.4V above the SW pin for full efﬁ ciency. Generally, for outputs of 3.3V and higher the standard circuit (Figure 5a) is the best. For outputs between 2.8V and 3.3V , replace the D2 with a small Schottky diode such as the PMEG4005. For lower output voltages the boost diode can be tied to the input (Figure 5b). The circuit in Figure 5a is more efﬁ cient because the BST pin current comes from a lower voltage source. Figure 5c shows the boost voltage source from available DC sources that are greater than 3V . The highest efﬁ ciency is attained by choosing the lowest boost voltage above 3V . For example, if you are generating 3.3V and 1.8V and the 3.3V is on whenever the 1.8V is on, the 1.8V boost diode can be connected to the 3.3V output. In any case, you must also be sure that the maximum voltage at the BST pin is less than the maximum speciﬁ ed in the Absolute Maximum Ratings section. The boost circuit can also run directly from a DC voltage that is higher than the input voltage by more than 3V , as in Figure 5d. The diode is used to prevent damage to the L T3510 in case V X is held low while V IN is present. The circuit saves several components (both BST pins can be tied to D2). However , efﬁ ciency may be lower and dissipa- tion in the L T3510 may be higher . Also, if V X is absent, the L T3510 will still attempt to regulate the output, but will do so with very low efﬁ ciency and high dissipation because the switch will not be able to saturate, dropping 1.5V to 2V in conduction. The minimum input voltage of an L T3510 application is limited by the minimum operating voltage (<3V) and by the maximum duty cycle as outlined above. For proper start-up, the minimum input voltage is also limited by the boost circuit. If the input voltage is ramped slowly, or the L T3510 is turned on with its SS pin when the output is already in regulation, then the boost capacitor may not be fully charged. Because the boost capacitor is charged with the energy stored in the inductor , the circuit will rely on some minimum load current to get the boost circuit running properly. This minimum load will depend on APPLICATIONS INFORMATION

achieve low output ripple and small circuit size. including load current, input voltage and temperature. stability using a transient load. Figure 5. BST Pin Considerations

3510 F05

of these parameters will cause erratic switching behavior . Figure 6. Model for Loop Response Figure 7. Synchronous Signal Powered from Regulator’s Output

3510 F06

3510 F07

Figure 8. Undervoltage Lockout pin to ground will set the start-up frequency. where these problems might occur . present before channel 2 is allowed to switch. 4.75V and is to stop if the input falls below 3.75V . present at either the SS pin or an internal 0.8V reference.

3510 F08

(9a) LT3510 VOUT1 PG1 PG2 VOUT2SS2 0.1μF 0.22μF 1.8V 3.3V VOUT1 0.5V/DIV VOUT2 0.5V/DIV 5ms/DIV VOUT1 0.5V/DIV VOUT2 0.5V/DIV VOUT1 0.5V/DIV VOUT2 0.5V/DIV 10ms/DIV 10ms/DIV SS1 (9b) LT3510 VOUT1 PG1 VOUT2SS2 0.1μF 1.8V 3.3V SS1 (9e) LT3510 VOUT1 PG1 VOUT2SS2 1.8V 3.3V Independent Start-Up Ratiometric Start-Up Absolute Start-Up SS1 (9d) LT3510 VOUT1 PG1 VOUT2SS2 0.1μF 0.1μF 1.8V 3.3V 25k EXTERNAL SOURCE Output Sequencing Controlled Power Up and Down SS1 (9c) LT3510 VOUT1 PG1 VOUT2SS2 0.22μF 1.8V 3.3V 13.7k 8.08k PG2 PG2 PG1 VOUT1 0.5V/DIV VOUT2 0.5V/DIV VOUT1 0.5V/DIV VOUT2 0.5V/DIV 10ms/DIV 10ms/DIV PG1PG1 PG2 PG2 PG1 PG1 SS1/2 PG2 PG2 PG2 PG2

3510 F09

Figure 10. 5V and 1.2V 2-Stage Step-Down Converter with Output Sequencing

. . μ == () ≥51 2 1 2 51 2 07 6–. •.
. .MHz Hμ SHDN 4.7μF 47μF 42.3k 100k 26.7k PMEG4005 8.06k PMEG4005 10pF 470pF 3.3μH 1μH VOUT1 VOUT2 1.2V VIN 6V TO 24V 0.47μF 47μF 0.47μF 10pF B360A B360A VIN1 VIN2 LT3510 GND BST1 SW1 IND1 VOUT1 PG1 FB1 VC1 SS/TRACK1 FSET BST2 SW2 IND2 VOUT2 PG2 FB2 VC2 SS/TRACK2 40.2k 8.06k

3510 F10

Figure 11. Subtracting the Current when the Switch is On (11a) from the Current when the Switch is Off (11b) Reveals the Path of the the high di/dt paths in the buck regulator circuit. by these components should be as small as possible. board and their connections should be made on that layer . component placement and trace routing. these layers will spread the heat dissipated by the L T3510. Figure 12. Topside PCB Layout

3510 F11

to the internal planes with vias can further reduce ther- mal resistance. With these steps, the thermal resistance from die (or junction) to ambient can be reduced to θ JA = 45°C/W . The power dissipation in the other power components such as catch diodes, boost diodes and inductors, cause additional copper heating and can further increase what the IC sees as ambient temperature. See the L T1767 data sheet’s Thermal Considerations section. Single, Low Ripple 4A Output The L T3510 can generate a single, low ripple 4A output if the outputs of the two switching regulators are tied together and share a single output capacitor . By tying the two FB pins together and the two V C pins together , the two channels will share the load current. There are several advantages to this 2-phase buck regulator . Ripple currents at the input and output are reduced, reducing voltage ripple and allowing the use of smaller , less expensive capacitors. Although two inductors are required, each will be smaller than the inductor required for a single-phase regulator . This may be important when there are tight height restrictions on the circuit. There is one special consideration regarding the 2-phase circuit. When the difference between the input voltage and output voltage is less than 2.5V , then the boost circuits may prevent the two channels from properly sharing current. If, for example, channel 1 gets started ﬁ rst, it can supply the load current, while channel 2 never switches enough current to get its boost capacitor charged. In this case, channel 1 will supply the load until it reaches current limit, the output voltage drops, and channel 2 gets started. T wo solutions to this problem are shown in the Typical Applications section. The single 3.3V/4A output converter generates a boost sup- ply from either SW that will service both switch pins. The synchronized 3.3V/8A output converter utilizes undervoltage lockout to prevent the start-up condition. Other Linear Technology Publications detailed descriptions and design information for buck regulators and other switching regulators. The L T1376 data sheet has a more extensive discussion of output ripple, loop compensation and stability testing. Design Note DN100 shows how to generate a dual (+ and –) output supply using a buck regulator . APPLICATIONS INFORMATION

5V and 2.5V with Absolute T racking 1.25MHz Single 3.3V/4A Low Ripple Output SHDN 4.7μF 47μF 42.3k 100k 100k 26.7k 8.06k 470pF 10pF 40.2k 10pF40.2k 3.3μH 2.2μH VOUT1 VOUT2 2.5V VIN 12V 0.47μF B360A B360A 47μF 0.47μF PMEG4005 PMEG4005 VIN1 VIN2 LT3510 GND BST1 SW1 IND1 VOUT1 PG1 FB1 V SS/TRACK1 RT/SYNC BST2 SW2 IND2 VOUT2 PG2 FB2 VC2 SS/TRACK2 16.9k 8.06k

3510 TA02

0.1μF 7.68k 16.9k 470pF SHDN 4.7μF 47μF 20.5k 8.06k 1000pF 22pF 1.5μH 1.5μH VOUT1 3.3V VIN 6V TO 25V 0.47μF 0.47μF B360A B360A PMEG4005PMEG4005 VIN1 VIN2 LT3510 GND BST1 SW1 IND1 VOUT1 PG1 FB1 VC1 SS/TRACK1 RT/SYNC BST2 SW2 IND2 VOUT2 PG2 FB2 VC2 SS/TRACK2 100k 17.8k 24.9k

3510 TA03

0.1μF TYPICAL APPLICATIONS

Dual L T3510 Synchronized 3.3V/8A Output, 3MHz Effective Switch Frequency SHDN 10μF 47μF s4 24.9k 8.06k 3300pF 47pF 5.3k 3.3μH 3.3μH VOUT1 3.3V VIN 5.5V TO 24V 0.47μF B360A 3.3μH 0.47μF B360A B360A 0.47μF PMEG4005 PMEG4005 PMEG4005PMEG4005 VIN1 VIN2 LT3510 GND BST1 SW1 IND1 VOUT1 PG1 FB1 VC1 SS/TRACK1 RT/SYNC BST2 SW2 IND2 VOUT2 PG2 FB2 VC2 SS/TRACK2 36.5k 49.9k 49.9k 133k 49.9k 49.9k 0.1MF SHDN VIN1 VIN2 LT3510 GND BST1 SW1 IND1 VOUT1 PG1 FB1 VC1 SS/TRACK1 RT/SYNC BST2 SW2 IND2 VOUT2 PG2 FB2 VC2

3510 TA05

3.3μH B360A 0.47μF LTC6908-1 SET MOD GND OUT1 OUT2 143k TYPICAL APPLICATIONS 1.25MHz Single 3.3V/4A Low Ripple Output SHDN 47μF 20.5k 8.06k 1000pF 22pF 1.5μH 1.5μH VOUT1 3.3V VIN 4.5V TO 6V 0.47μF 0.47μF B360A PMEG4005PMEG4005 VIN1 VIN2 LT3510 GND BST1 SW1 IND1 VOUT1 PG1 FB1 VC1 SS/TRACK1 RT/SYNC BST2 SW2 IND2 VOUT2 PG2 FB2 VC2 SS/TRACK2 100k 17.8k 24.9k

3510 TA04

0.1μF 4.7μF 1μF* B360A PMEG4005* *ADDITIONAL COMPONENTS ADDED TO SHARE THE BOOST VOLTAGE WHEN VIN <6V. THIS IS REQUIRED TO ENSURE LOAD SHARING BETWEEN THE TWO CHANNELS. PMEG4005*

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation CA FE20 (CA) TSSOP 0204 0.09 – 0.20 (.0035 – .0079) 0° – 8° 0.25 REF RECOMMENDED SOLDER PAD LAYOUT 0.50 – 0.75 (.020 – .030) 4.30 – 4.50* (.169 – .177) 13 4 5 6 7 89 1 0 111214 13 6.40 – 6.60* (.252 – .260) 4.95 (.195) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) MAX 0.05 – 0.15 (.002 – .006) 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 2.74 (.108) 0.45 ±0.05

0.65 BSC

4.50 ±0.10 6.60 ±0.10 1.05 ±0.10 4.95 (.195) MILLIMETERS (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE SEE NOTE 4 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT 6.40 (.252) BSC PACKAGE DESCRIPTION

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006 LT 1008 REV C • PRINTED IN USA PART NUMBER DESCRIPTION COMMENTS L T1766 60V , 1.2A (I OUT), 200kHz High Efﬁ ciency Step-Down DC/DC Converter VIN: 5.5V to 60V , VOUT(MIN) = 1.20V , IQ = 2.5mA, ISD = 25μA, 16-Lead TSSOPE Package L T1933 500mA (I OUT), 500kHz Step-Down Switching Regulator in SOT-23 VIN: 3.6V to 36V , VOUT(MIN) = 1.2V , IQ = 1.6mA, ISD <1μA, ThinSOT TM Package L T1936 36V , 1.4A (I OUT), 500kHz High Efﬁ ciency Step-Down DC/DC Converter VIN: 3.6V to 36V , VOUT(MIN) = 1.2V , IQ = 1.9mA, ISD <1μA, 8-Lead MS8E Package L T1940 Dual 25V , 1.4A (I OUT), 1.1MHz High Efﬁ ciency Step-Down DC/DC Converter VIN: 3.6V to 25V , VOUT(MIN) = 1.20V , IQ = 3.8mA, ISD <30μA, 16-Lead TSSOPE Package L T1976/L T1977 60V , 1.2A (I OUT), 200kHz/500kHz High Efﬁ ciency Step-Down DC/DC Converters with Burst Mode Operation VIN: 3.3V to 60V , VOUT(MIN) = 1.20V , IQ = 100μA, ISD <1μA, 16-Lead TSSOPE Package LT C 3407/L TC3407-2 Dual 600mA/800mA, 1.5MHz/2.25MHz Synchronous Step-Down DC/DC Converters VIN: 2.5V to 5.5V , VOUT(MIN) = 0.6V , IQ = 40μA, ISD <1μA, 3mm × 3mm DFN and 10-Lead MSE Packages L T3434/L T3435 60V , 2.4A (I OUT), 200kHz/500kHz High Efﬁ ciency Step-Down DC/DC Converters with Burst Mode Operation VIN: 3.3V to 60V , VOUT(MIN) = 1.20V , IQ = 100μA, ISD <1μA, 16-Lead TSSOPE Package L T3437 60V , 400mA (I OUT), Micropower Step-Down DC/DC Converter with Burst Mode Operation VIN: 3.3V to 60V , VOUT(MIN) = 1.25V , IQ = 100μA, ISD <1μA, L T3493 36V , 1.4A (I OUT), 750kHz High Efﬁ ciency Step-Down DC/DC Converter VIN: 3.6V to 36V , VOUT(MIN) = 0.8V , IQ = 1.9mA, ISD <1μA, L T3501 Dual 25V , 2A (I OUT), 1.5MHz High Efﬁ ciency Step-Down DC/DC Converter VIN: 3.3V to 25V , VOUT(MIN) = 0.8V , IQ = 3.5mA, ISD <1μA, 20-Lead TSSOPE Package L T3505 36V , 1.2A (I OUT), 3MHz High Efﬁ ciency Step-Down DC/DC Converter VIN: 3.6V to 36V , VOUT(MIN) = 0.78V , IQ = 2mA, ISD <2μA, 3mm × 3mm DFN and 8-Lead MSE Packages L T3506/L T3506A Dual 25V , 1.6A (I OUT), 575kHz/1.1MHz High Efﬁ ciency Step-Down DC/DC Converters VIN: 3.6V to 25V , VOUT(MIN) = 0.8V , IQ = 3.8mA, ISD <30μA, 4mm × 5mm DFN Package L TC3548 Dual 400mA/800mA, 2.25MHz Synchronous Step-Down DC/DC Converters VIN: 2.5V to 5.5V , VOUT(MIN) = 0.6V , IQ = 40μA, ISD <1μA, 3mm × 3mm DFN and 10-Lead MSE Packages Burst Mode is a registered trademark of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation. RELATED PARTS

Summary

Monolithic Dual Tracking 2A Step-Down Switching Regulator

Description