Power Management

LT3507

Linear Technology

40V 400mA Step-Down Switching Regulator with Dual Fault Protected Tracking LDOs

Manufacturer: Linear Technology

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3667fbFor more information www.linear .com/L T3667 TYPICAL APPLICATION FEATURES DESCRIPTION 40V 400mA Step-Down Switching Regulator with Dual Fault Protected LDOs The LT®3667 is a monolithic triple power supply composed of a 400mA buck switching regulator and two 200mA low dropout linear regulators (LDOs). The buck regulator includes a high efficiency switch, a boost diode, and the necessary oscillator, control and logic circuitry. Current mode topology is used for fast transient response and good loop stability. Low ripple Burst Mode operation maintains high efficiency at low output currents while keeping output ripple below 15mV in a typical application. Each LDO supplies 200mA of output current with a typical dropout voltage of 340mV, and each LDO has an accurate resistor programmable current limit. Internal protection circuitry includes reverse-battery protection, current limiting, thermal limiting and reverse current protection. The LT3667 is available in a thermally-enhanced 16-Lead MSOP and a 24-Pin 3mm x 5mm QFN package with ex - posed pad for low thermal resistance. No-Load Supply Current

APPLICATIONS

n T riple Output Supply from a Single Input Requires Only One Inductor n IQ = 50μA at 12VIN to 5V, 3.3V and 2.5V with No Load n Buck Regulator: Low Ripple (<15mVP-P) Burst Mode Operation® 400mA Output with Internal Power Switch 4.3 V to 40V Input Operation Range (60V Max) n Dual Low Dropout Linear Regulators 200mA Outputs with Programmable Current Limits 1.6 V to 45V Input Range Fault Protected to ±45V n Adjustable 250kHz to 2.2MHz Switching Frequency n Synchronizable Between 300kHz and 2.2MHz n Programmable Under voltage Lockout n Power Good Indicators n Available in a Thermally-Enhanced 16-Lead MSOP and 24-Lead (3mm × 5mm) QFN Packages n Automotive Batter y Regulation n Power for Portable Instrumentation n Industrial Supplies n Fault-Protected Sensor Supply L, LT, LT C, LT M, Burst Mode, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. EN2/ILIM2 EN3/ILIM3GND IN1 L T3667 BOOST SW DA FB1 IN2 BD 2.5V 100mA IN3 OUT3 FB3

3667 TA01a

4.7µF 0.22µF 22pF 22µH 931k 200mA 3.3V 100mA 294k 340k 158k 499k 158k 174k VIN 6V TO 40V TRANSIENT TO 60V 22µF 4.7µF 2.2µF INPUT VOLTAGE (V) SUPPLY CURRENT (µA) 100 15 25 30

3667 TA01b

3667fb For more information www.linear .com/L T3667 ABSOLUTE MAXIMUM RATINGS 45V 45V 45V V IN1 0.3V IN3/BD (M BD (QF B B (Notes 1, 2) SW BOOST EN RT IN3/BD OUT3 FB3 FB1 DA IN1 PG EN3/ILIM3 EN2/ILIM2 IN2 OUT2 FB2 TOP VIEW GND MSE PACKAGE 16-LEAD PLASTIC MSOP θJA = 40°C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB 24 23 22 21 9 10 TOP VIEW GND UDD PACKAGE 24-LEAD (3mm × 5mm) PLASTIC QFN 11 12 20BOOST SYNC EN RT BD IN3 OUT3 FB3 IN1 UVLO1 PG EN3/ILIM3 EN2/ILIM2 IN2 OUT2 FB2 SW DA NC NC PG1 FB1 PG2 PG3 147 138 θJA = 46°C/W EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB PIN CONFIGURATION V V P SY V Operating Junction Temperature Range (Notes 4, 5) E-, 40°C to 125°C H-Gr 40°C to 150°C 65°C to 150°C Lead Temperature (Soldering, 10 sec) MS

3667fbFor more information www.linear .com/L T3667 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LT3667EMSE#PBF LT3667EMSE#TRPBF 3667 16-Lead Plastic MSOP –40°C to 125°C LT3667IMSE#PBF LT3667IMSE#TRPBF 3667 16-Lead Plastic MSOP –40°C to 125°C LT3667HMSE#PBF LT3667HMSE#TRPBF 3667 16-Lead Plastic MSOP –40°C to 150°C LT3667EUDD#PBF LT3667EUDD#TRPBF LGFH 24-Lead (3mm × 5mm) Plastic QFN –40°C to 125°C LT3667IUDD#PBF LT3667IUDD#TRPBF LGFH 24-Lead (3mm × 5mm) Plastic QFN –40°C to 125°C LT3667HUDD#PBF LT3667HUDD#TRPBF LGFH 24-Lead (3mm × 5mm) Plastic QFN –40°C to 150°C Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LT C Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN1 = 12V unless otherwise noted. (Note 4) PARAMETER CONDITIONS MIN TYP MAX UNITS VIN1 Undervoltage Lockout (Note 6) VIN2 = 0V, VIN3 = 0V l 4 4.3 V VIN1 Overvoltage Lockout l 40 42 44 V VIN2 Undervoltage Lockout (Note 6) VIN1 = 3.5V, VIN3 = 0V l 4 4.3 V UVLO1 Threshold Voltage Pin Voltage Falling l 0.95 1 1.05 V UVLO1 Pin Hysteresis 75 mV UVLO1 Pin Current VUVLO1 = 1V 1 30 nA Quiescent Current from IN1 VEN = 0.3V VEN = 12V, VIN2 = 0V, Not Switching l 0.01 µA µA Quiescent Current from IN2 VEN = 0.3V VEN = 12V, VIN1 = 0V, VIN2 = 5V l 0.01 µA µA Quiescent Current from IN1 + IN2 VEN = 0.3V, VIN2 = 5V VEN = 12V, VIN2 = 5V, Not Switching l 0.01 µA µA Quiescent Current from IN3 VEN = 0.3V, VIN3 = 5V VEN = 12V, VIN3 = 5V l 0.01 µA µA EN Pin Current VEN = 12V 0.6 2 µA EN Input Threshold 0.3 1.1 V Power Good Pins PG (MSOP), PG1, PG2, PG3 (QFN) Leakage Current VPG = 5V, VPG1/2/3 = 5V 0.1 1 µA Output Voltage Low IPG = 40µA, IPG1/2/3 = 40µA l 0.2 0.3 V Threshold as % of VFB (FB1, FB2, FB3) Pin Voltage Falling Pin Voltage Rising 108 110 112 PG1 Threshold Hysteresis Measured at FB1 Pin 30 mV PG2/PG3 Threshold Hysteresis Measured at FB2/FB3 Pin 20 mV

3667fbFor more information www.linear .com/L T3667 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN1 = 12V unless otherwise noted. (Note 4) PARAMETER CONDITIONS MIN TYP MAX UNITS Reverse Output Current (Note 13) VOUT2 = 1.2V, VIN1 = VIN2 = VIN3 = 0V VOUT3 = 1.2V, VIN1 = VIN2 = VIN3 = 0V µA µA Input Reverse Leakage Current LDO2 Input Reverse Leakage Current LDO3 (QFN) V IN2 = –45V, VIN1 = VIN3 = VOUT2 = 0V VIN3 = –45V, VIN1 = VIN2 = VOUT3 = 0V l l 300 300 µA µA Internal Current Limit (Note 12) VIN2 = 2.2V, VOUT2 = 0V, EN2/ILIM2 Pin Grounded 300 mA ∆VOUT2 = –5% l 220 mA VIN3 = 2.2V, VOUT3 = 0V, EN3/ILIM3 Pin Grounded 300 mA ∆VOUT3 = –5% l 220 mA Externally Programmed Current Limit REN/ILIM = 31.6k, VOUT2/3 = 5V, VIN2/3 ≥ 5.6V REN/ILIM = 6.19k, VOUT2/3 = 5V, VIN2/3 ≥ 5.6V REN/ILIM = 6.19k, VOUT2/3 = 5V, 5.6V ≤ VIN2/3 ≤ 15V REN/ILIM = 1.54k, VOUT2/3 = 5V, 5.6V ≤ VIN2/3 ≤ 15V l l l l 9.5 48.45 176 197 10.5 53.55 230 mA mA mA mA LDO Disable Threshold V EN/ILIM Rising 0.9 1 1.2 V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Positive currents flow into pins, negative currents flow out of pins. Minimum and maximum values refer to absolute values. Note 3: Absolute maximum voltage at the IN1, UVLO1 and EN pins is 60V for nonrepetitive 1 second transients, and 40V for continuous operation. Note 4: The LT3667E is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the −40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3667I is guaranteed over the full −40°C to 125°C operating junction temperature range. The LT3667H is guaranteed over the full −40°C to 150°C operating junction temperature range. Note 5: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 6: This is the voltage necessary to keep the internal bias circuitry in regulation. Note 7: Current limit guaranteed by design and/or correlation to static test. Slope compensation reduces current limit at higher duty cycles. Note 8: This is the minimum voltage across the boost capacitor needed to guarantee full saturation of the switch. Note 9: Dropout voltage is the minimum input-to-output voltage differential needed for an LDO to maintain regulation at a specified output current. When an LDO is in dropout, its output voltage will be equal to V IN – VDROP. Note 10: To satisfy minimum input voltage requirements, the LT3667 is tested and specified for these conditions with an external resistor divider (80.6k bottom, 422k top) which sets V OUT to 5V. The external resistor divider adds 9.93μA of DC load on the output. This external current is not factored into GND pin current. Note 11: GND pin current is tested with V IN = VOUT(NOMINAL) + 0.6V and a current source load. GND pin current increases in dropout. Note 12: The LT3667 is tested and specified for these conditions with FB2 (FB3) pin connected to the OUT2 (OUT3) pin. Note 13: Reverse output current is tested with the IN2 (IN3) pin grounded and the OUT2 (OUT3) pin forced to the rated output voltage. This current flows into the OUT2 (OUT3) pin and out of the GND pin.

3667fb For more information www.linear .com/L T3667 TYPICAL PERFORMANCE CHARACTERISTICS No-Load Supply Current No-Load Supply Current Maximum Load Current Maximum Load Current Switching Regulator Load Regulation Efficiency, VOUT = 3.3V Efficiency, VOUT = 5V VFB1/2/3 vs Temperature Switch Current Limit TA = 25°C, unless otherwise noted. TEMPERATURE (°C) –50

1.10 VFB1 (V)

VFB2/3 (mV) 1.15 1.20 1.25 1.30 784 792 800 808 816 –25 0 25 50

3667 G03

LOAD CURRENT (mA) EFFICIENCY (%) 0.01 1 10

3667 G01

0.1 100 VIN1 = 12V VIN1 = 36V VIN1 = 24V FRONT PAGE APPLICATION BUCK REGULATOR ONLY V OUT1 = 3.3V L: MSS7341-223MLB LOAD CURRENT (mA) EFFICIENCY (%) 0.01 1 10

3667 G02

0.1 100 VIN1 = 12V VIN1 = 36V FRONT PAGE APPLICATION BUCK REGULATOR ONLY V OUT1 = 5V L: MSS7341-223MLB VIN1 = 24V INPUT VOLTAGE (V) SUPPLY CURRENT (µA) 100 15 25 30 35

3667 G04

TEMPERATURE (°C) –50 –25 0 SUPPLY CURRENT (A) 100µ INCREASED SUPPLY CURRENT DUE TO CATCH DIODE LEAKAGE AT HIGH TEMPERATURE FRONT PAGE APPLICATION CATCH DIODE: CMMSH1-60 25 50 75 100 125 150

3667 G05

10µ INPUT VOLTAGE (V) LOAD CURRENT (mA) 600 650 700 20 30

3667 G06

VOUT1 = 3.3V TYPICAL MINIMUM INPUT VOLTAGE (V) LOAD CURRENT (mA) 600 650 700 20 30

3667 G07

VOUT1 = 5V TYPICAL MINIMUM LOAD CURRENT (mA) –0.10 LOAD REGULATION (%) –0.08 –0.04 –0.02 0.10 0.04 100 200 250

3667 G08

–0.06 0.06 0.08 0.02 50 150 300 350 400 FRONT PAGE APPLICATION REFERENCED FROM VOUT1 AT 200mA LOAD DUTY CYCLE (%) SWITCH CURRENT LIMIT (mA) 600 700

3667 G09

CATCH DIODE VALLEY CURRENT LIMIT

3667fbFor more information www.linear .com/L T3667 TYPICAL PERFORMANCE CHARACTERISTICS Minimum Switch On-Time/ Switch-Off Time Switch VCESAT BOOST Pin Current Minimum Input Voltage, V OUT = 3.3V Minimum Input Voltage, V OUT = 5V Switch Current Limit Switching Frequency TA = 25°C, unless otherwise noted. T ransient Load Response, Load Step 10mA to 140mA T ransient Load Response Load Step 150mA to 300mA TEMPERATURE (°C) –50 SWITCH CURRENT LIMIT (mA) 700 800 900 25 75 150

3667 G10

–25 0 50 100 125 0% DUTY CYCLE 100% DUTY CYCLE CATCH DIODE VALLEY CURRENT LIMIT TEMPERATURE (°C) –50 FREQUENCY (MHz) 1.2 1.8 2.0 150

3667 G11

1.0 0.8 0 50 100–25 25 75 125 0.4 2.4 2.2 1.6 1.4 0.6 0.2 RT = 37.4k RT = 95.3k RT = 487k TEMPERATURE (°C) –50 SWITCH ON-TIME/SWITCH OFF-TIME (ns)20 100 200 140 0 50 75

3667 G12

–25 25 100 125 150 MINIMUM OFF-TIME MINIMUM ON-TIME LOAD CURRENT = 200mA SWITCH CURRENT (mA) SWITCH VCESAT (mV)400 500 600 300 500

3667 G13

TJ = –50°C TJ = 25°C TJ = 125°C TJ = 150°C SWITCH CURRENT (mA) BOOST PIN CURRENT (mA) 400

3667 G14

TA = 150°C TA = 25°C TA = –50°C LOAD CURRENT IOUT1 (mA) INPUT VOLTAGE VIN1 (V) 4.0 4.5 5.0 150 250 400

3667 G15

3.5 3.0 3.5 50 100 200 300 350 TO START TO RUN FRONT PAGE APPLICATION VEN = VIN1, VOUT1 = 3.3V LOAD CURRENT IOUT1 (mA) INPUT VOLTAGE VIN1 (V) 5.5 6.0 6.5 150 250 400

3667 G16

5.0 4.5 4.0 50 100 200 300 350 TO START TO RUN FRONT PAGE APPLICATION VEN = VIN1, VOUT1 = 5V

3667 G17

100µs/DIV VOUT1 100mV/DIV IL 100mA/DIV FRONT PAGE APPLICATION

3667 G18

100µs/DIV VOUT1 100mV/DIV IL 150mA/DIV FRONT PAGE APPLICATION

3667fb For more information www.linear .com/L T3667 TYPICAL PERFORMANCE CHARACTERISTICS Switching Waveforms, Burst Mode Operation Switching Waveforms, Full Frequency Continuous Operation EN Threshold EN Pin Current LDOs: Typical Dropout Voltage LDOs: Guaranteed Dropout Voltage LDOs: IN2, IN3 Quiescent Current LDOs: 5V Quiescent Current IN2 LDOs: 5V Quiescent Current IN3 T A = 25°C, unless otherwise noted. EN PIN VOLTAGE (V) EN PIN CURRENT (µA) 0.6 0.8 1.0 15 25 40

3667 G22

0.4 0.2 5 10 20 30 35

3667 G19

1µs/DIV VSW 5V/DIV VOUT1 5mV/DIV IL 100mA/DIV ILOAD = 10mA FRONT PAGE APPLICATION

3667 G20

1µs/DIV VSW 5V/DIV VOUT1 5mV/DIV IL 200mA/DIV ILOAD = 400mA, FRONT PAGE APPLICATION TEMPERATURE (°C) –50 THRESHOLD VOLTAGE (V) 0.1 0.3 0.4 0.5 1.0 0.7 0 50 75

3667 G21

0.2 0.8 0.9 0.6 –25 25 100 125 150 OUTPUT CURRENT (mA) DROPOUT VOLTAGE (mV) 300 400 500 600 160

3667 G23

40 80 12020 18060 100 140 200 TA = –50°C TA = 25°C TA = 125°C TA = 150°C OUTPUT CURRENT (mA) DROPOUT VOLTAGE (mV) 400 500 600 180 160

3667 G24

TJ = 150°C TJ = 25°C 700 = TEST POINTS TEMPERATURE (°C) –50 QUIESCENT CURRENT (µA) 0 50 100 150

3667 G25

–25 25 75 125 VIN2/3 = 5V VEN = 0.3V VIN2/3 = 5V VEN = 2V, VIN1 = 0 VOUT2/3 = 0.8V ILOAD = 5µA VIN2 (V) QUIESCENT CURRENT IIN2 (µA) 100 30 35 40 180

3667 G26

VIN1 = VEN = 12V VEN2/ILIM2 = 0V VEN2/ILIM2 = 2V VIN3 (V) QUIESCENT CURRENT IIN3 (µA) 100 30 35 40 180

3667 G27

VIN1 = VEN = 12V VEN3/ILIM3 = 0V VEN3/ILIM3 = 2V

3667fbFor more information www.linear .com/L T3667 TYPICAL PERFORMANCE CHARACTERISTICS FB2, FB3 Pin Bias Current LDOs: Internal Current Limit LDOs: Internal Current Limit LDOs: Reverse Output Current LDOs: Reverse Output Current LDOs: Input Ripple Rejection T A = 25°C, unless otherwise noted. LDOs: Minimum Input Voltage LDOs: Load Regulation LDOs: Output Noise Spectral Density TEMPERATURE (°C) –50 FB2/3 PIN BIAS CURRENT (nA) 25 75 150

3667 G28

–25 0 50 100 FB3 FB2 125 TEMPERATURE (°C) –50 MINIMUM INPUT VOLTAGE (V) 0.6 1.8 2.0 2.2 0 50 75 100

3667 G34

0.2 1.4 1.0 0.4 1.6 1.2 0.8 –25 25 125 150 IL = 200mA VOUT2/3 = 0.8V VIN1 = 5V INPUT/OUTPUT DIFFERENTIAL (V) CURRENT LIMIT (mA) 150 200 250 350 5 25 35

3667 G29

TA = 140°C TA = 125°C TA = 25°C TA = –50°C OUTPUT VOLTAGE (V)

200 CURRENT LIMIT (mA)

3667 G30

TA = 140°C TA = 125°C TA = 25°C TA = –50°C VIN2/3-VOUT2/3(NOMINAL) = 1V VOUT2/3 (V) IOUT2/3 (nA) 0.1 0.3 0.4 0.5 1.0 0.7 10 20 25 45

3667 G31

0.2 0.8 0.9 0.6 5 15 30 35 40 ALL PINS GROUNDED EXCEPT FOR OUT2/3 TEMPERATURE (°C) –50 CURRENT (µA) 0 50 75 150

3667 G32

–25 25 100 125 VOUT2/3 = VFB2/3 = 2V VIN2/3 = 0V IFB2/3 IOUT2/3 FREQUENCY (Hz) 10 100 INPUT RIPPLE REJECTION (dB) 1k 10k 100k 1M 10M

3667 G33

IOUT2/3 = 200mA VOUT2/3 = 5V VIN2/3 = 5.8V + 50mVRMS RIPPLE OUT3 (VIN1 = 12V) OUT2 (VIN1 = 12V) TEMPERATURE (°C) –50 LOAD REGULATION (mV) 0 50 100 150

3667 G35

–25 25 75 125 ∆IOUT2/3 = 1mA TO 200mA VOUT2/3 = 0.8V VIN2/3 = 2.2V VIN1 = 5V FREQUENCY (Hz) 0.1 OUTPUT NOISE SPECTRAL DENSITY (µV/√Hz) 10 1k 10k 100k

3667 G36

0.01 100 VOUT2/3 = 5V VOUT2/3 = 3.3V VOUT2/3 = 2.5V VOUT2/3 = 1.8V VOUT2/3 = 1.5V VOUT2/3 = 1.2V VOUT2/3 = 0.8V COUT = 10µF IL = 200mA

3667fb For more information www.linear .com/L T3667 TYPICAL PERFORMANCE CHARACTERISTICS LDOs: RMS Output Noise LDOs: Channel-to-Channel Isolation LDOs: T ransient Response LDOs: External Current Limit, R EN/ILIM = 1.54k LDOs: External Current Limit, R EN/ILIM = 6.19k LDOs: External Current Limit, R EN/ILIM = 31.6k TA = 25°C, unless otherwise noted. LOAD CURRENT (mA) 100OUTPUT NOISE VOLTAGE (µVRMS) 200 250 350 400 0.01 1 10 100

3667 G37

0.1 300 150 VOUT2/3 = 5V VOUT2/3 = 3.3V VOUT2/3 = 2.5V VOUT2/3 = 1.8V VOUT2/3 = 1.2V VOUT2/3 = 0.8V VOUT2/3 = 1.5V COUT = 10µF fOUT = 10Hz TO 100kHz

3667 G38

200µs/DIV VIN2/3 = 6V, VOUT2/3 = 5V CIN2/3 = COUT2/3 = 10µF VOUT2/3 50mV/DIV VOUT3/2 50mV/DIV IOUT2/3 = 20mA TO 200mA IOUT3/2 = 20mA

3667 G39

100µs/DIV VOUT2/3 100mV/DIV IOUT2/3 100mV/DIV IOUT2/3 = 20mA TO 200mA VIN2/3 = 6V, VOUT2/3 = 5V CIN2/3 = COUT2/3 = 10µF TEMPERATURE (°C) –50 CURRENT LIMIT (mA) 190 200 150

3667 G40

0 50 100–25 25 75 125

210 VOUT2/3 = 5V

VIN2/3 = 5.6V VIN2/3 = 15V VIN2/3 = 10V TEMPERATURE (°C) –50 CURRENT LIMIT (mA) 50.0 51.0 150

3667 G41

49.0 48.0 0 50 100–25 25 75 125

52.0 VOUT2/3 = 5V

49.5 50.5 48.5 51.5 VIN2/3 = 5.6V VIN2/3 = 15V VIN2/3 = 10V TEMPERATURE (°C) –50 9.8 CURRENT LIMIT (mA)9.9 10.0 10.1 10.2 –25 0 25 50

3667 G42

VOUT2/3 = 5V VIN2/3 = 5.6V VIN2/3 = 15V VIN2/3 = 10V

3667fbFor more information www.linear .com/L T3667 PIN FUNCTIONS (MSOP/QFN) SW (Pin 1/Pin 24): The SW pin is the output of the internal power switch. Connect this pin to the inductor, the catch diode and the boost capacitor. BOOST (Pin 2/Pin 1): This pin is used to provide a drive voltage, higher than the input voltage, to the internal bipolar NPN power switch of the switching regulator. Connect a capacitor (typically 0.22μF) between BOOST and SW. SYNC (Pin 2, QFN Only): This is the external clock syn - chronization input. Ground this pin for low ripple Burst Mode operation at low output loads. Tie to a clock source for synchronization. Refer to Synchronization section in Applications Information for more details. EN (Pin 3/Pin 3): The EN pin is used to put the LT3667 in shutdown mode. Tie to ground to shut down the LT3667. Tie to 1V or more for normal operation. If the EN pin is to be pulled below ground, use a series resistor to limit the pin current to 1mA. RT (Pin 4/Pin 4): Oscillator Resistor Input. Connect a resis- tor from this pin to ground to set the switching frequency. BD (Pin 5, QFN Only): This pin connects to the anode of the internal boost diode. This pin also supplies current to the LT3667’s internal regulator when BD is above 3.2V. OUT 3 (Pin 6/Pin 7), OUT2 (Pin 10/Pin 14): These are the outputs of the two LDOs. Stability requirements demand a minimum 2.2μF ceramic output capacitor to prevent oscillations. FB3 (Pin 7/Pin 8), FB2 (Pin 9/Pin 13): The two LDOs of the LT3667 regulate the FB2 and FB3 pins to 0.8V. Connect the feedback resistor divider taps to these pins. FB1 (Pin 8/Pin 10): The switching regulator of the LT3667 regulates the FB1 pin to 1.2V. Connect the feedback resis- tor divider tap to this pin. PG1 (Pin 9, QFN Only): The PG1 pin is the open-drain output of an internal window comparator. PG1 remains low until the FB1 pin is within ±10% of its final regulation voltage. PG1 output is valid when VIN1 or VIN2 are above the minimum input voltage and EN is high. IN2 (Pin 11/Pin 15), IN3/BD (Pin 5, MSOP), IN3 (Pin 6, QFN): These pins are the inputs of the two LDOs. IN3/BD also connects to the anode of the internal boost diode and also supplies current to the LT3667’s internal regulator when IN3/BD is above 3.2V. PG2 (Pin 11, QFN Only): The PG2 pin is the open-drain output of an internal window comparator. PG2 remains low until the FB2 pin is within ±10% of its final regulation voltage. PG2 output is valid when VIN1 or VIN2 are above the minimum input voltage and EN is high. EN2/ILIM2 (Pin 12/Pin 16), EN3/ILIM3 (Pin 13/Pin 17): Precision current limit programming pins. They connect to collectors of current mirror PNPs which are 1/799th the size of the output power PNPs of the two LDOs. These pins are also the inputs to the current limit amplifiers. Current limit thresholds are set by connecting resistors between the EN2/ILIM2 pin and GND and between the EN3/ILIM3 pin and GND. Stability requirements demand 47nF capacitors in parallel to these resistors. For detailed information on how to set the pin resistor values, see the Operation section. If any of these pins is not used, tie it to GND. To disable an LDO, pull its EN/ILIM pin above 1.2V. PG3 (Pin 12, QFN Only): The PG3 pin is the open-drain output of an internal window comparator. PG3 remains low until the FB3 pin is within ±10% of its final regulation voltage. PG3 output is valid when V IN1 or VIN2 are above the minimum input voltage and EN is high. PG (Pin 14/Pin 18): The PG pin is the open-drain output of an internal window comparator. PG remains low until the FB1, FB2, and FB3 pin are within ±10% of their final regulation voltages. PG output is valid when VIN1 or VIN2 are above the minimum input voltage and EN is high.

3667fb For more information www.linear .com/L T3667 PIN FUNCTIONS (MSOP/QFN) IN1 (Pin 15/Pin 20): The IN1 pin supplies current to the internal regulator and to the internal power switch. This pin must be locally bypassed. DA (Pin 16/Pin 23): Connect the anode of the catch diode (D1 in Block Diagrams) to this pin. Internal circuitry senses the current through the catch diode providing frequency foldback in overload conditions. GND (Exposed Pad Pin 17/Exposed Pad Pin 25): This is the ground of all internal circuitry, as well as the power ground used by the catch diode (D1). The exposed pad must be soldered to the PCB. UVLO1 (Pin 19, QFN Only): The precise 1V threshold volt- age of this pin can function as an accurate undervoltage lockout (UVLO). The switching regulator only operates when the voltage at the UVLO1 pin exceeds this threshold. The LDOs are not affected by this pin. NC (Pins 21, 22, QFN only): These pins are not connected internally and can be left floating or tied to ground.

3667fbFor more information www.linear .com/L T3667 BLOCK DIAGRAM (MSOP) ERROR AMPLIFIER 0.88V 0.72V OUT3 EN3/ ILIM3 0.4V 0.4V 80/uni03A980/uni03A9 LDO DISABLE LDO DISABLE OUT2 PG IN2 FB2 FB3 VOUT2 VIN1 VOUT3 0.72V ERROR AMPLIFIER R3 R4 R6 R5 CURRENT LIMIT AMPLIFIER CURRENT LIMIT AMPLIFIER+ – + – LDO DRIVER ERROR AMPLIFIER 9 7 IN3/ BD 511 EN2/ ILIM2 B00ST SW

3667 BD MSOP

0.8V INTERNAL REF SLOPE COMP Burst Mode DETECT OSCILLATOR 250kHz TO 2.2MHz 1.2V IN115 EN 1.32V VC RT RT 1.08V R S Q BOOST DIODE CATCH DIODE CURRENT LIMIT VOUT1 FB1 R2 R1 GND

3667fb For more information www.linear .com/L T3667 BLOCK DIAGRAM (QFN) ERROR AMPLIFIER 0.88V 0.72V OUT3 EN3/ ILIM3 0.4V 0.4V 80/uni03A980/uni03A9 LDO DISABLE LDO DISABLE OUT2 PG IN2 FB2 FB3 VOUT2 VIN1 VOUT3 0.72V ERROR AMPLIFIER R3 R4 R6 R5 CURRENT LIMIT AMPLIFIER CURRENT LIMIT AMPLIFIER+ – + – LDO DRIVER ERROR AMPLIFIER 13 8 IN3 615 EN2/ ILIM2 BD B00ST SW

3667 BD QFN

0.8V INTERNAL REF SLOPE COMP Burst Mode DETECT OSCILLATOR 250kHz TO 2.2MHz 1.2V IN120 UVLO1 EN 1.32V VC RT SYNC RT 1.08V R S Q BOOST DIODE CATCH DIODE CURRENT LIMIT VOUT1 FB1 R2 R1 GND

3667fbFor more information www.linear .com/L T3667 OPERATION The LT3667 combines a 400mA buck switching regulator and two 200mA low dropout linear regulators. Operation is best understood by referring to the Block Diagrams. The buck regulator part is a constant frequency, current mode step-down regulator. An oscillator, with frequency set by R T, sets an RS flip-flop, turning on the internal power switch. An amplifier and comparator monitor the current flowing between the IN1 and SW pins, turning the switch off when this current reaches a level determined by the voltage at VC. An error amplifier measures the output voltage through an external resistor divider tied to the FB1 pin and servos the VC node. If the error amplifier’s output increases, more current is delivered to the output; if it decreases, less current is delivered. Another comparator monitors the current flowing through the catch diode and reduces the operating frequency when the current exceeds the 500mA bottom current limit. This foldback in frequency helps to control the output current in fault conditions such as a shorted output with high input voltage. Maximum deliverable current to the output is therefore limited by both switch current limit and catch diode current limit. An internal regulator provides power to the control circuitry. The bias regulator normally draws power from the IN1 pin, but if the IN3/BD (MSOP) or BD (QFN) pin is connected to an external voltage higher than 3.2V, bias power will be drawn from the external source (typically the regulated output voltage). This improves efficiency. The switch driver operates from either IN1 or from the BOOST pin. An external capacitor is used to generate a voltage at the BOOST pin that is higher than the input supply. This allows the driver to fully saturate the internal NPN power switch for efficient operation. To further optimize efficiency, the LT3667 automatically switches to Burst Mode operation in light load situations. Between bursts, all circuitry associated with controlling the output switch is shut down, reducing the input supply current to 50μA (including the current drawn by the LDOs). The switching regulator has an overvoltage protection feature which disables switching action when IN1 goes above 42V (typical) during transients. It can then safely sustain transient input voltages up to 60V. The switching regulator can also be separately shut down via the UVLO1 pin, which can be used to implement a programmable undervoltage lockout with an external resistive divider. The LDO blocks are micropower, low noise 200mA linear regulators with low dropout voltage and current limit, which provide fast transient response with minimum low ESR 2.2µF ceramic output capacitors. Each output cur - rent limit can be programmed individually with a single resistor, and pulling the EN2/ILIM2 or EN3/ILIM3 pin high shuts down the corresponding LDO. Internal protection circuitry includes reverse-battery protection, reverse- output protection, reverse-current protection, and current limit with foldback. The internal reference voltage circuitry is supplied by the IN1 and IN2 pins. This allows the LDO at IN2 to run independently and supply the switching regulator with its output OUT2. The EN pin is used to place the LT3667 in shutdown, thereby reducing the input current to less than 1μA. The LT3667 contains three power good window com - parators that indicate whether the output voltages are within ±10% of their nominal value. The outputs of these comparators are open-drain transistors which are off when their corresponding output is in regulation, allowing external resistors to pull the power good pins high. The PG pin provides a combined power good signal, while the QFN package additionally allows access to the individual power good signals through pins PG1, PG2 and PG3. Power good is valid if the LT3667 is enabled and IN1 or IN2 are above their minimum input voltages. Internal thermal limiting protects the LT3667 during overload conditions.

3667fb For more information www.linear .com/L T3667 APPLICATIONS INFORMATION SWITCHING REGULATOR FB1 Resistor Network The switching regulator output voltage of the LT3667 is programmed with a resistor divider between the output of the switching regulator and the FB1 pin. Choose the resistor values according to: R1=R2 VOUT1 1.2V –1   Reference designators refer to the Block Diagram of the LT3667. 1% resistors are recommended to maintain output voltage accuracy. Note that choosing larger resistors will decrease the quiescent current of the application circuit. Setting the Switching Frequency The LT3667 regulator uses a constant frequency PWM architecture that can be programmed to switch from 250kHz to 2.2MHz by using a resistor tied from the RT pin to ground. Table 1 shows the necessary RT value for a desired switching frequency. Table 1: Switching Frequency vs RT Value SWITCHING FREQUENCY (MHz) RT VALUE (kΩ) 0.25 475 0.3 383 0.4 274 0.5 215 0.6 174 0.8 124 1 95.3 1.2 75 1.4 61.9 1.6 51.1 1.8 43.2 2 37.4 2.2 32.4 Operating Frequency T rade-Offs Selection of the operating frequency is a trade-off between efficiency, component size, minimum dropout voltage, and maximum input voltage. The advantage of high frequency operation is that smaller inductor and capacitor values may be used. The disadvantages are lower efficiency, lower maximum input voltage, and higher dropout voltage. The highest acceptable switching frequency (f SW(MAX)) for a given application can be calculated as follows: fSW(MAX) = VOUT1 + VD tON(MIN) VIN1 – VSW + VD( ) where VIN1 is the typical input voltage, VOUT1 is the output voltage, VD is the catch diode drop (~0.5V) and VSW is the internal switch drop (~0.5V at max load). This equation shows that slower switching frequency is necessary to accommodate high V IN1/VOUT1 ratio. Lower frequency also allows a lower dropout voltage. Input voltage range depends on the switching frequency because the LT3667 switch has finite minimum on and off times. The switch can turn on for a minimum of ~150ns and turn off for a minimum of ~170ns (note that the minimum on- time is a strong function of temperature). The minimum and maximum duty cycles that can be achieved taking minimum on and off times into account are: DCMIN = fSW • tON(MIN) DCMAX = 1 − fSW • tOFF(MIN) where f SW is the switching frequency, t ON(MIN) is the minimum switch on-time (~150ns), and t OFF(MIN) is the minimum switch off-time (~170ns). These equations show that the duty cycle range increases when the switching frequency is decreased. A good choice of switching frequency should allow an adequate input voltage range (see Input Voltage Range section) and keep the inductor and capacitor values small.

tON(MIN) is the minimum switch on-time (~150ns). lowing the output to fall out of regulation. with higher inductance and higher switching frequency. tions. Table 2 lists several vendors. Table 2. Inductor Vendors

3667fb For more information www.linear .com/L T3667 APPLICATIONS INFORMATION This simple design guide will not always result in the optimum inductor selection for a given application. As a general rule, lower output voltages and higher switching frequency will require smaller inductor values. If the ap - plication requires less than 400mA load current, then a lesser inductor value may be acceptable. This allows the use of a physically smaller inductor, or one with a lower DCR resulting in higher efficiency. However, the inductance should in general not be smaller than 10µH. Be aware that if the inductance differs from the simple rule above, then the maximum load current will depend on input voltage. In addition, low inductance may result in discontinuous mode operation, which further reduces maximum load current. For details of maximum output current and discontinuous mode operation, see Linear Technology’s Application Note 44. Finally, for duty cycles greater than 50% (V OUT1/VIN1 > 0.5), a minimum inductance is required to avoid sub-harmonic oscillations: LMIN = VOUT1 + VD( ) • 2 fSW where fSW is the switching frequency in MHz, V OUT1 is the output voltage, V D is the catch diode drop (~0.5V) and LMIN is the inductor value in µH. Catch Diode The catch diode (D1 from block diagram) conducts current only during switch off-time. Use a 1A Schottky diode for best performance. Peak reverse voltage is equal to V IN1 if it is below the overvoltage protection threshold. This feature keeps the switch off for VIN1 > OVLO (44V maximum). For inputs up to the maximum operating voltage of 40V, use a diode with a reverse voltage rating greater than the input voltage. If transients at the input of up to 60V are expected, use a diode with a reverse voltage rating only higher than the maximum OVLO of 44V. If operating at high ambient temperatures, consider using a Schottky with low reverse leakage. For example, Diodes Inc. SBR1U40LP or DFLS160, ON Semi MBRM140, and Central Semiconductor CMMSH1-60 are good choices for the catch diode. Input Capacitor Bypass the input of the LT3667 circuit with a ceramic capacitor of X7R or X5R type. Y5V types have poor performance over temperature and applied voltage, and should not be used. A 1μF to 4.7μF ceramic capacitor is adequate to bypass the LT3667 and will easily handle the ripple current. Note that a larger input capacitance is required when a lower switching frequency is used (due to longer on-times). If the input power source has high impedance, or there is significant inductance due to long wires or cables, additional bulk capacitance may be necessary. This can be provided with a low performance electrolytic capacitor. Step-down regulators draw current from the input supply in pulses with very fast rise and fall times. The input capacitor is required to reduce the resulting voltage ripple at the LT3667 and to force this very high frequency switching current into a tight local loop, minimizing EMI. A 1μF capacitor is capable of this task, but only if it is placed close to the LT3667 (see the PCB Layout section). A second precaution regarding the ceramic input capacitor concerns the maximum input voltage rating of the LT3667. A ceramic input capacitor combined with trace or cable inductance forms a high quality (under damped) tank circuit. If the LT3667 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the LT3667’s voltage rating. This situation is easily avoided (see the Hot Plugging Safely section). Output Capacitor and Output Ripple The output capacitor has two essential functions. Along with the inductor, it filters the square wave generated by the LT3667 to produce the DC output. In this role it determines the output ripple, and low impedance at the switching frequency is important. The second function is to store energy in order to satisfy transient loads and stabilize the switching regulator’s control loop. Ceramic capacitors have very low equivalent series resistance (ESR) and provide the best ripple performance. A good starting value is: COUT1 = 50 VOUT1 • fSW

Figure 1. Burst Mode Operation provide low output ripple and good transient response. save space and cost but transient performance will suffer. operating conditions (applied voltage and temperature). capacitor at audio frequencies, generating audible noise. electrolytic capacitor at the output. will be lower than the programmed switching frequency.

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2.2V and above, the standard circuit (Figure 2a) is best. pin quiescent current come from a lower voltage source. BOOST and BD pins are not exceeded. worst-case situation where VIN1 is ramping very slowly. the absolute maximum rating of the BOOST pin. Figure 2. Two Circuits for Generating the Boost Voltage

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Figure 3. The Minimum Input Voltage Depends on

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Figure 4. The square wave amplitude should have valleys Figure 5 can be used to shorten the clock signal's on-time. from SYNC to ground which will draw current. frequency 20% below the lowest synchronization input. Figure 6. UVLO1 Pin Allows Programmable Undervoltage

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Figure 4. Synchronization Waveforms Figure 5. Example of AC Coupling of SYNC Clock Signal

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Figure 7. Diode D1 Prevents a Shorted Input from Discharging Figure 8. Setting the Output Voltage of Each LDO in the Applications Information section of the LDOs. error, caused by the FB2/FB3 pin current, is minimized. quiescent current of the application circuit.

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the switching regulator input IN1 to the LDO output OUT2. and letting the regulator enter dropout. the cause and not a result of LDO instability. capacitors at the input in place of ceramic capacitors. tion, the ESR of the output capacitor must not exceed 3Ω. transient response is a function of output capacitance. can masquerade as increased output voltage noise. Figure 9. Noise Resulting from Tapping On a Ceramic Capacitor

3667 F092ms/DIV

3667fb For more information www.linear .com/L T3667 APPLICATIONS INFORMATION External Programmable Current Limit, Enable Each EN/ILIM pin (EN2/ILIM2 and EN3/ILIM3) is the col- lector of a PNP which mirrors the corresponding LDO’s output at a ratio of 1:799 (see Block Diagram). The EN2/ ILIM2 and EN3/ILIM3 pins are also the inputs to preci - sion current limit amplifiers. If an output load increases to the point where it causes the corresponding current limit amplifier input voltage to reach 0.4V, the current limit amplifier takes control of output regulation so that its input clamps at 0.4V, regardless of the output voltage. The current limit threshold (I LIMIT) of an LDO is set by attaching a resistor (RIMAX) from the corresponding EN/ ILIM pin to ground: RIMAX = 799 •0.4V ILIM – 80Ω In order to maintain stability, each EN/ILIM pin requires a 47nF capacitor from that pin to ground. In cases where the input to output voltage differential exceeds 10V, foldback current limit will lower the inter - nal current level limit, possibly causing it to preempt the external programmable current limit. See the Internal Current Limit vs Input/Output Differential graph in the Typical Performance Characteristics section. If an external current limit is not needed, the correspond- ing EN/ILIM pin must be connected to ground, in which case no capacitor is required. Each LDO can be individually shut down by pulling its EN/ ILIM pin above 1.2V (1V typical). Note that in this case this pin will draw up to 500µA in certain operating conditions until the LDO is shut down, which the circuit driving this pin must be able to deliver. When an EN/ILIM pin is only used to enable/disable an LDO, no capacitor is required on this pin. Overload Recovery Each LDO of the LT3667 has a safe operating area pro - tection, which decreases current limit as input-to-output voltage increases, and keeps the power transistor inside a safe operating region for all values of input-to-output voltage. Each LDO provides some output current at all values of input-to-output voltage up to the device break- down. When power is first applied to an LDO, the input voltage rises and the output follows the input; allowing the regulator to start-up into very heavy loads. During start-up, as the input voltage is rising, the input-to-output voltage differential is small, allowing the regulator to supply large output currents. With a high input voltage, a problem can occur wherein the removal of an output short will not allow the output to recover. The problem occurs with a heavy output load when the input voltage is high and the output voltage is low. Common situations are: immediately after the removal of a short-circuit or if an LDO is enabled via its EN/ILIM pin after the input voltage is already turned on. In such cases, the regulator would have to operate its power device outside its safe operating are (high voltage and high current) in order to bring up the output voltage. Since this is prevented by the safe operating area protec- tion, the output gets stuck at a low voltage. Essentially, the load line for such a load intersects the output current curve at two points, resulting in two stable output operating points for the regulator. With this double intersection, the input power supply needs to be cycled down to zero and brought up again to make the output recover. Protection Features The LT3667 LDO’s protect against reverse-input volt - ages, reverse-output voltages and reverse output-to-input voltages. Current limit protection and thermal overload protection protect the LDOs against current overload conditions at their outputs. For normal operation, do not exceed the maximum operating junction temperature. The LT3667 IN2 and IN3 (QFN only) pins withstand reverse voltages of 45V. The device limits current flow to less than 300μA (typically less than 10μA) and no negative voltages appear at OUT2 or OUT3. The LDOs incur no damage if their outputs are pulled below ground. If an input is left open circuit or grounded, the corresponding output can be pulled below ground by 45V. No current flows through the pass transistor from the output. However, current flows in (but is limited by) the corresponding resistor divider that sets the output voltage. Current flows from the bottom resistor in the divider and from the FB2/FB3 pin’s internal clamp through the top resistor in the divider to the external circuitry pulling OUT2/OUT3 below ground. If the input is powered by a voltage source, the output sources cur -

extra consideration to the use of ceramic capacitors. The SW and BOOST nodes should be as small as possible. traces will shield them from the SW and BOOST nodes. Figure 10. Ceramic Capacitor DC Bias Characteristics Figure 11. Ceramic Capacitor Temperature Characteristics

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1210 CASE SIZE, 10µF

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limits its power handling capability. efficiency measurement and subtracting inductor loss. escent current of the switching regulator. Figure 12. Good PCB Layout Ensures Figure 13. Good PCB Layout Ensures

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3667fbFor more information www.linear .com/L T3667 APPLICATIONS INFORMATION The power dissipation of each LDO is comprised of two components. Each power device dissipates: PPASS = (VIN − VOUT) • IOUT where PPASS is the power, V IN the input voltage, V OUT the output voltage, and IOUT the output current. The base currents of the LDO power PNP transistors flow to ground internally and are the major component of the ground current. For each LDO, this causes a power dissipation PGND of: PGND = VIN • IGND where VIN is the input voltage and IGND the ground current generated by the corresponding power device. GND pin current is determined by the current gain of the power PNP, which has a typical value of 40 for the purpose of this calculation: IGND = IOUT The total power dissipation equals the sum of the power loss in the switching regulator and the two LDO compo- nents listed above. The LT3667 has internal thermal limiting that protects the device during overload conditions. If the junction temperature reaches the thermal shutdown threshold, the LT3667 will shut down the LDOs and stop switching to prevent internal damage due to overheating. For continuous normal conditions, do not exceed the maximum operat - ing junction temperature. Carefully consider all sources of thermal resistance from junction-to-ambient including other nearby heat sources. Both LT3667 packages have exposed pads that must be soldered to a ground plane to act as heat sink. To keep thermal resistance low, extend the ground plane as much as possible, and add thermal vias under and near the LT3667 to additional ground planes within the circuit board and on the bottom side. The die temperature rise is calculated by multiplying the power dissipation of the LT3667 by the thermal resistance from junction to ambient. Example: Given the front page application with maximum output current, an input voltage of 12V and a maximum ambient temperature of 85°C, what will the maximum junction temperature be? As can be seen from the Typical Performance Characteris- tics, the switching regulator efficiency approaches 85% at 400mA output current. This leads to a power loss, PLOSS, of: PLOSS = 5V • 400mA • 1 0.85 –1    = 353mW (For the sake of simplicity and as a conservative estimate assume that all of this power is dissipated in the LT3667.) The power dissipations of the LDO power devices are: PPASS2 = (5V − 2.5V) • 100mA = 250mW PPASS3 = (5V − 3.3V) • 100mA = 170mW For 100mA load current a maximum ground current of 2.5mA is to be expected. Thus, the corresponding power dissipations are: PGND2 = PGND3 = 5V • 2.5mA = 12.5mW Finally, the total power dissipation is: PTOT = PLOSS + PPASS2 + PPASS3 + PGND2 + PGND3 = 786mW Using the MSOP package, which has a thermal resistance of approximately 40°C/W, this total power dissipation would raise the junction temperature above ambient by: 0.786 W • 40°C/W = 32°C With the assumed maximum ambient temperature of 85°C, this puts the maximum junction temperature at: TJMAX = 85°C + 32°C = 117°C Other Linear Technology Publications Application Notes 19, 35 and 44 contain more detailed descriptions and design information for buck regulators and other switching regulators. The LT1376 data sheet has a more extensive discussion of output ripple, loop compensation and stability testing. Design Note 318 shows how to generate a bipolar output supply using a buck regulator.

3667fb For more information www.linear .com/L T3667 EN2/ILIM2 EN3/ILIM3GND IN1 L T3667 BOOST SW DA FB1 IN2 BD 2.5V 100mA f = 600kHz IN3 OUT3 FB3

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C1-C5: X5R OR X7R L1: CDRH4D22/HP UVLO1 4.7µF 0.22µF DFLS160 22pF 22µH 931k 200mA 3.3V 100mA 294kR3 340k 158k 499k 158k RT 174k VIN 6V TO 40V TRANSIENT TO 60V 22µF 4.7µF 2.2µF TYPICAL APPLICATIONS 5V, 3.3V and 2.5V Step-Down Converter Dual 5V/200mA Step-Down Converter EN2/ILIM2 EN3/ILIM3GND IN1 L T3667 BOOST SW DA FB1 IN2 BD 200mA IN3 OUT3 FB3

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f = 600kHz FB2 C1-C5: X5R OR X7R L1: CDRH4D22/HP UVLO1 4.7µF 0.22µF DFLS160 22pF 22µH 6V 1020k 200mA 255kR3 787k 150k 787k 150k RT 174k VIN 7V TO 40V TRANSIENT TO 60V 22µF 2.2µF 2.2µF

3667fbFor more information www.linear .com/L T3667 TYPICAL APPLICATIONS 5V, 3.3V and 2.5V Step-Down Converter with 100mA LDO Current Limits Programming LDO Current Limits with a Digital/Analog Converter EN2/ILIM2 EN3/ILIM3GND IN1 L T3667 BOOST SW DA FB1 IN2 BD 2.5V* IN3 OUT3 FB3

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f = 2MHz FB2 *100mA CURRENT LIMIT C1-C5: X5R OR X7R L1: CDRH4D22/HP UVLO1 4.7µF 0.1µF DFLS160 22pF 10µH 931k 200mA 3.3V* 294kR3 340k 158k 3.09k 3.09k 499k 158k RT 37.4k VIN 8.5V TO 16V TRANSIENT TO 60V 10µF 4.7µF 47nF 47nF 2.2µF 3.01k 3.01kVDAC DAC OUTPUT 0V TO 0.8V 47nF EN2/ILIM2 L T3667 CURRENT LIMIT = 799 0.8V – VDAC 3.01k/uni03A9 + 160/uni03A9 1.5kIDAC DAC OUTPUT 0µA TO 267µA 47nF

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CURRENT LIMIT = 7990.4V – IDAC 1.5k/uni03A9 1.5k/uni03A9 + 80/uni03A9

3667fb For more information www.linear .com/L T3667 TYPICAL APPLICATIONS This application allows a small input current to support a high current pulsed load. The switching regulator is supplied by the LDO2 at OUT2, which is programmed to limit its current to 3.5mA. PG2 serves as “READY” signal to tell a controller (not shown) that C6 is charged to 17V, the regulation voltage of LDO2. It can then turn on a load drawing high current out of the switching regulator. Since LDO2 can only supply 3.5mA, this quickly discharges C6 and decreases VOUT2 (=VIN1). The switching regulator will maintain its programmed output voltage until V IN1 drops below the undervoltage lockout threshold of 5.5V set by R3 and R4. Pulsed Power Supply for 4mA to 20mA Current Loops. OUT2 Supplies the Switching Regulator, Which Is Kept Off at Lower Voltages by UVLO1 EN2/ILIM2 EN3/ILIM3GND EN L T3667 BOOST LDO2 Input SW DA FB1 IN3 PG2 BD OUT3 FB3

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f = 600kHz FB2 3.5mA Current Limit C1-C5: X5R OR X7R L1: CDRH4D22/HP IN2 1µF 2.2µF 0.22µF DFLS160 22pF 22µH 442k 3.3V 100mA READY 1.8V 100mA 249k R10 150k 90.9k 3010k 150k 200k 158k RT 174k 4.5MThreshold 5.5V Regulation Voltage 17V PG2 Indicates when C6 is Charged Big Capacitor Here to Accumulate Energy V IN 18V TO 45V TRANSIENTS DOWN TO –28V 22µF 1000µF 47nF 10µF LDO2 Output BUCK Input 0 1 2 3 4 TIME (SECONDS)

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100 IIN2 (mA)ILOAD (mA) VOUT2 (V)VPG2 (V)

VOUT2 Rises as C6 is Charged by the Constant Current I OUT2 C6 is Quickly Discharged by High Load Current PG2 Signals That VOUT2 is High Enough Controller Decides to Activate Load IIN2 Drops as VOUT2 Reaches Programmed Value

3667fbFor more information www.linear .com/L T3667 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MSOP (MSE16) 0213 REV F 0.53 ±0.152 (.021 ±.006) SEATING PLANE 0.18 (.007) 1.10 (.043) MAX 0.17 –/uni00A00.27 (.007 – .011) TYP 0.86 (.034) REF 0.50 (.0197) BSC 16151413121110 1 2 3 4 5 6 7 8 1 8 NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED 0.254mm (.010") PER SIDE. 0.254 (.010) 0° – 6° TYP DETAIL “A” DETAIL “A” GAUGE PLANE 5.10 (.201) MIN 3.20 – 3.45 (.126 – .136) 0.889 ±0.127 (.035 ±.005) RECOMMENDED SOLDER PAD LAYOUT 0.305 ±0.038 (.0120 ±.0015) TYP 0.50 (.0197) BSC BOTTOM VIEW OF EXPOSED PAD OPTION 2.845 ±0.102 (.112 ±.004) 2.845 ±0.102 (.112 ±.004) 4.039 ±0.102 (.159 ±.004) (NOTE 3) 1.651 ±0.102 (.065 ±.004) 1.651 ±0.102 (.065 ±.004) 0.1016 ±0.0508 (.004 ±.002) 3.00 ±0.102 (.118 ±.004) (NOTE 4) 0.280 ±0.076 (.011 ±.003) REF 4.90 ±0.152 (.193 ±.006) DETAIL “B” DETAIL “B” CORNER TAIL IS PART OF THE LEADFRAME FEATURE. FOR REFERENCE ONL Y NO MEASUREMENT PURPOSE

0.12 REF

0.35 REF 16-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1667 Rev F)

3667fb For more information www.linear .com/L T3667 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 3.00 ± 0.10 1.50 REF 5.00 ± 0.10 NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (NOTE 6) 0.40 ± 0.10 23 24 BOTTOM VIEW—EXPOSED PAD

3.50 REF

0.75 ± 0.05 R = 0.115 TYP PIN 1 NOTCH R = 0.20 OR 0.25 × 45° CHAMFER 0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05 (UDD24) QFN 0808 REV Ø RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 0.25 ±0.05 4.10 ± 0.05 5.50 ± 0.05

1.50 REF

2.10 ± 0.05 3.50 ± 0.05 PACKAGE OUTLINE R = 0.05 TYP 1.65 ± 0.10 3.65 ± 0.10 1.65 ± 0.05 24-Lead Plastic QFN (3mm × 5mm) (Reference LTC DWG # 05-08-1833 Rev Ø) 3.65 ± 0.05

3667fbFor more information www.linear .com/L T3667 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 4/14 Added H-grade in MS16E package to Order Information 3 B 11/14 Clarified Externally Programmable Current Limit specifications Grammatical correction in Setting the Switching Frequency description Clarified Typical Application schematic

3667fb For more information www.linear .com/L T3667  LINEAR TECHNOLOGY CORPORATION 2014 LT 1114 REV B • PRINTED IN USA Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com/L T3667 EN2/ILIM2 EN3/ILIM3GND IN3 L T3667 BOOST SW DA FB1 BD OUT3 FB3

3667 TA07

f = 600kHz FB2 *DERATE OUTPUT CURRENT AT HIGHER AMBIENT TEMPERATURES AND INPUT VOL TAGES TO MAINTAIN JUNCTION TEMPERATURE BELOW THE ABSOLUTE MAXIMUM 51mA* IN2 2.2µF 0.22µF DFLS160 22pF 22µH 931k 400mA 3.3V* 200mA 249k 6.19k C1-C7: X5R OR X7R L1: CDRH4D22/HP 499k 158k RT 174k VIN* 6V TO 40V 1µF 1µF 22µF 47nF 10µF 10µF 5V, 3.3V and 51mA Regulator RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS LT3500 36V (40VMAX), 2A (IOUT), 2.2MHz Step-Down Switching Regulator with LDO Controller VIN: 3V to 36V, VOUT(MIN) = 0.8V, IQ = 2.5mA, ISD < 12µA, 3mm × 3mm DFN-10, MSOP-16E LT1939 25V, 2A (IOUT), 2.2MHz Step-Down Switching Regulator with LDO Controller VIN: 3V to 25V, VOUT(MIN) = 0.8V, IQ = 2.5mA, ISD < 12µA, 3mm × 3mm DFN-10, MSOP-16E LT3694 36V (70VMAX), 2.6A (IOUT), 2.5MHz Step-Down Switching Regulator with Dual LDO Controller VIN: 4V to 36V, VOUT(MIN) = 0.8V, IQ = 1mA, ISD < 1µA, 4mm × 5mm QFN-28, TSSOP-20E LT3507/LT3507A 36V, 2.5MHz, T riple (2.4A + 1.5A + 1.5A (IOUT) with LDO Controller High Efficiency Step-Down DC/DC Converter VIN: 4V to 36V, VOUT(MIN) = 0.8V, IQ = 7mA, ISD = 1µA, 5mm × 7mm QFN-38 LT3970 40V, 350mA (IOUT), 2.2MHz Step-Down Switching Regulator with IQ = 2.5µA VIN: 4.2V to 40V, VOUT(MIN) = 1.2V, IQ = 2.5µA, ISD < 1µA, 3mm × 2mm DFN, MSOP-10 LT3502/LT3502A 40V, 500mA (IOUT), 1.1MHz/2.2MHz Step-Down Switching Regulator VIN: 3V to 40V, VOUT(MIN) = 0.8V, IQ = 1.5mA, ISD < 1µA, 2mm × 2mm DFN-8, MSOP-10E

Product Information

LT3507 specifications and overview.

Summary

40V 400mA Step-Down Switching Regulator with Dual Fault Protected Tracking LDOs

Description

40V 400mA Step-Down Switching Regulator with Dual Fault Protected Tracking LDOs

Source title LT3507 Datasheet(PDF) - Linear Technology

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