LT3507

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FEATURES

APPLICATIONS

DESCRIPTION

Triple Monolithic Step-Down Regulator with LDO The L T®3507 is a triple, current mode, DC/DC converter with internal power switches and a low dropout regulator . The switching converters are step-down converters capable of generating one 2.4A output and two 1.5A outputs. All three converters are synchronized to a single oscillator . The 2.4A output runs with opposite phase to the other two converters, reducing input ripple current. Each regulator has independent shutdown and soft-start circuits, and generates a power good signal when its output is in regu- lation, easing power supply sequencing and interfacing with microcontrollers and DSPs. The switching frequency is set with a single resistor yielding a range of 250kHz to 2.5MHz. The high switching frequency allows the use of small inductors and capacitors resulting in a very small triple output supply. The constant switching frequency, combined with low impedance ceramic capaci- tors, results in low, predictable output ripple. With its wide input voltage range of 4V to 36V , the L T3507 regulates a broad array of power sources including 5V logic rails, unregulated wall transformers, lead acid batteries and distributed power supplies. n Wide Input Range: 4V to 36V n One 2.4A and T wo 1.5A Output Switching Regulators with Internal Power Switches n Low Dropout Linear Regulator with External T ransistor n Antiphase Switching Reduces Ripple n Independent Run, T racking/Soft-Start, and Power Good Indicators Ease Supply Sequencing n Uses Small Inductors and Ceramic Capacitors n Adjustable, 250kHz to 2.5MHz Switching Frequency, Synchronizable Over the Full Range n User Programmable Overvoltage and Undervoltage Lockouts n Thermally Enhanced, 38-Lead 5mm × 7mm QFN Package n DSL and Cable Modems n Distributed Power Regulation n DSP Power n Automotive TYPICAL APPLICATION VIN1 BOOST1 BOOST3 SW3 FB3 VC3 BIAS DRIVE FB4 SW1 FB1 VC1 BOOST2 0.22μF 10.2k 53.6k VIN 6V TO 36V VOUT3 1.5A VIN2 VIN3 SW2 FB2 VC2 GND L T3507 22μF 24.3k

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107k 11.5k VOUT2 3.3V 1.3A VOUT4 2.5V 0.2ART/SYNC 680pF 15μH 2.2μF 22μF fSW = 450kHz 0.22μF 0.22μF 15k 18.7k VOUT1 1.8V 2.4A 100μF 18.7k 680pF 4.7μH 24.3k 1000pF 16.2k 11.5k 35.7k 10μH 22μF VOUT2 Start-Up Waveforms—Coincident T racking5V , 3.3V , 2.5V and 1.8V Step-Down Regulator 1V/DIV VOUT1 VOUT2 VOUT3 VOUT4 1ms/DIV

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L, L T , L TC, L TM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.

PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS TRK/SS, V Operating Junction Temperature Range (Notes 2, 5) (Note 1) 13 14 15 16 TOP VIEW UHF PACKAGE 38-LEAD (5mm × 7mm) PLASTIC QFN 17 18 19 38 37 36 35 34 33 32

1 BOOST1

V IN1 VIN1 VINSW OVLO UVLO VC1 TRK/SS1 FB1 PGOOD1 PGOOD2 PGOOD3 V IN2 VIN2 SW2 SW2 BOOST2 TRK/SS4 FB4 DRIVE V FB2 TRK/SS2 FB3 SW1 SW1 V IN3 VIN3 SW3 SW3 BOOST3 R T/SYNC RUN1 RUN2 RUN3 BIAS TRK/SS3 V θJA = 34°C/W EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB PARAMETER CONDITIONS MIN TYP MAX UNITS Minimum Operating Voltage Internal UVLO on VIN1 l 3.8 4 V Input Quiescent Current Not Switching, VBIAS = 3.3V 2 3.5 mA Bias Quiescent Current Not Switching, VBIAS = 3.3V 5 7.5 mA Shutdown Current VRUN1,2,3 = 0V 1 μA Reference Voltage Line Regulation 5V < VIN1 < 36V 0.01 %/V The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VIN1, VIN2, VIN3 = 12V , VBOOST1, VBOOST2, VBOOST3 = 17V , unless otherwise noted. (Note 2) LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L T3507EUHF#PBF L T3507IUHF#PBF L T3507HUHF#PBF L T3507EUHF#TRPBF L T3507IUHF#TRPBF L T3507HUHF#TRPBF 3507 3507 3507 38-Lead (5mm × 7mm) Plastic QFN 38-Lead (5mm × 7mm) Plastic QFN 38-Lead (5mm × 7mm) Plastic QFN –40°C to 125°C –40°C to 125°C –40°C to 150°C Consult L TC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container . *For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear .com/tapeandreel/ ORDER INFORMATION

ELECTRICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VIN1, VIN2, VIN3 = 12V , VBOOST1, VBOOST2, VBOOST3 = 17V , unless otherwise noted. (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS VC Source Current V C = 0.6V 20 μA VC Sink Current V C = 0.6V 30 μA VC Clamp Voltage 1.7 V Switching Frequency R T = 40.2k l 0.9 1.1 MHz Switching Phase SW1 to SW2,3, R T = 40.2k 180 Deg Foldback Frequency V FB = 0V , RT = 40.2k 120 kHz Frequency Shift Threshold on FB 0.4 V RUN Threshold 1 1.5 V PGOOD Output Voltage Low I PGOOD = 200μA 0.2 0.4 V PGOOD Pin Leakage V PGOOD = 2V 10 400 nA PGOOD Threshold Offset V FB Rising 58 80 105 mV Feedback Pin Voltage l 788 800 812 mV Feedback Pin Bias Current l –50 –500 nA Error Amplifi er T ransconductance 330 μS Error Amplifi er Voltage Gain 500 V/V VC Switching Threshold 0.9 V Switch Leakage Current 0.01 10 μA Minimum Boost Voltage Above Switch (Note 4) 1.8 2.5 V Converter 1 V C1 to Switch Current Gain 5A / V Switch 1 Current Limit (Note 3) Duty Cycle = 15% l 3 4.3 6 A Switch 1 VCESAT ISW1 = 2A 400 600 mV BOOST1 Operating Current I SW1 = 2A 40 60 mA Converter 2 V C2 to Switch Current Gain 3.6 A/V Switch 2 Current Limit (Note 3) Duty Cycle = 15% l 2 2.9 4 A Switch 2 VCESAT ISW2 = 1.5A 350 500 mV BOOST2 Operating Current I SW2 = 1.5A 40 60 mA Converter 3 V C3 to Switch Current Gain 3.6 A/V Switch 3 Current Limit (Note 3) Duty Cycle = 15% l 2 2.9 4 A Switch 3 VCESAT ISW3 = 1.5A 350 500 mV BOOST3 Operating Current I SW3 = 1.5A 40 60 mA LDO Regulator Feedback Pin Voltage l 788 800 812 mV Feedback Pin Bias Current –150 –500 nA Error Amplifi er Voltage Gain 1100 V/V Line Regulation V IN from 5V to 36V 0.05 %/V

ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VIN1, VIN2, VIN3 = 12V , VBOOST1, VBOOST2, VBOOST3 = 17V , unless otherwise noted (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS Load Regulation I DRIVE from 0.1mA to 10mA 0.005 %/mA DRIVE Output Current Limit l 10 15 22.5 mA Dropout Voltage, VIN1 to DRIVE I DRIVE = 10mA 1.7 2.0 V Dropout Voltage, BIAS to DRIVE I DRIVE = 10mA 0.5 0.8 V Over/Undervoltage Lockout Undervoltage Lockout Threshold 1.15 1.20 1.25 V Overvoltage Lockout Threhold 1.15 1.20 1.25 V Undervoltage Lockout Hysteresis Current V(UVLO) < 1.2V 7 10 13 μA Overvoltage Lockout Hysteresis Current V(OVLO) > 1.2V –7 –10 –13 μA Input Bias Current (OVLO and UVLO) –100 –200 nA Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The L T3507E is guaranteed to meet performance specifi cations from 0°C to 125°C junction temperature. Specifi cations over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The L T3507I is guaranteed to meet performance specifi cations from –40°C to 125°C junction temperature. The L T3507H is guaranteed over the full –40°C to 150°C operating junction temperature range. High junction temperatures degrade operating lifetimes. Operating lifetime is derated at junction temperatures greater than 125°C. Note 3: Current limit is guaranteed by design and/or correlation to static test. Slope compensation reduces current limit at higher duty cycles. Note 4: This is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch. Note 5: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed the maximum operating range when overtemperature protection is active. Continuous operation above the specifi ed maximum operating junction temperature may impair device reliability.

TYPICAL PERFORMANCE CHARACTERISTICS VFB vs Temperature Frequency vs R T Frequency vs Temperature Frequency vs VFB (Foldback) I TRK/SS vs Temperature Effi ciency vs Load Current, Channel 1, VOUT = 1.8V Switch VCESAT vs Switch Current, Channels 1, 2 and 3 BOOST Pin Current vs Switch Current, Channels 1, 2 and 3 Effi ciency vs Load Current, Channels 2 and 3, VOUT = 3.3V IOUT (A) EFFICIENCY (%)

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2.51.50.5 VIN = 6V VIN = 12V VIN = 36V TA = 25°C fSW = 450kHz IOUT (A) EFFICIENCY (%) 100 1.20.6

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1.50.90.3 VIN = 6V VIN = 12V VIN = 36V TA = 25°C fSW = 450kHz ISW (A) VSW (V) 0.6 0.4 0.5 0.2 0.3 0.1 2.51

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31.5 20.5 CHANNELS 2 & 3 CHANNEL 1 TA = 25°C ISW (A) IBOOST (mA) 100 2.51

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31.5 20.5 CHANNELS 2 & 3 CHANNEL 1 TA = 25°C TEMPERATURE (°C) –50 VFB (mV) 805 803 802 801 800 799 804 797 798 796 795 130–10

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15090705030 110–30 RT (kΩ) FREQUENCY (MHz)

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2.5 0.25 10 100 TA = 25°C TEMPERATURE (°C) –50 FREQUENCY DEVIATION (%) 0.5 –0.5 –1.0 –1.5 0.0 –2.0 130–10

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15090705030 110–30 VFB (V) FRERQUENCY (kHz) 1200 800 600 400 200 1000 0.80.4

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10.60.2 RT = 40.2k TA = 25°C TEMPERATURE (°C) –50 ITRK/SS (μA) 1.30 1.26 1.24 1.22 1.28 1.20 130–10

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15090705030 110–30

TYPICAL PERFORMANCE CHARACTERISTICS VIN1-VINSW Voltage Drop vs IVINSW Current Limit vs Duty Cycle Minimum On-Time vs ISW RUN Threshold vs Temperature Minimum Off-Time vs ISW TEMPERATURE (°C) –50 RUN THRESHOLD (V) 1.2 1.0 0.6 0.4 0.2 0.8 0.0 130–10

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15090705030 110–30 IVINSW (mA) VIN–VINSW (V) 0.40 0.20 0.30 0.35 0.25 0.15 0.05 0.10 0.00 0.80.4

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1.00.60.2 TA = 25°C DUTY CYCLE (%) ILIM (A) 4.5 2.0 3.0 3.5 4.0 2.5 1.5 0.5 1.0 0.0 8040

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CHANNELS 2 & 3 TA = 25°C ISW (A) MINIMUM ON-TIME (ns) 250 150 200 100

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150°C 25°C –40°C ISW (A) MINIMUM OFF-TIME (ns) 200 150 100 2 2.51

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31.50.5 150°C 25°C –40°C

BOOST1, BOOST2, BOOST3 (Pins 1, 27, 32): The BOOST pins are used to provide drive voltages, higher than the input voltage, to the internal bipolar NPN power switches. These pins must be tied through a diode from V OUT, VIN or another supply greater than 2.5V . VIN1 (Pins 2, 3): The VIN1 pins supply power to the internal switch of the 2.4A regulator and to the L T3507’s internal reference and start-up circuitry. These pins must be locally bypassed (Note 6). V INSW (Pin 4): The VINSW pin is a switched V IN1 for the user programmable undervoltage and overvoltage detec- tion. It is connected to V IN1 when any of the RUN pins are pulled high, and high impedance when all RUN pins are low or open. OVLO (Pin 5): The L T3507 goes into overvoltage shutdown when this pin goes above 1.2V . If unused, the OVLO pin should be tied to GND. UVLO (Pin 6): The L T3507 goes into undervoltage shutdown when this pin drops below 1.2V . If unused, the UVLO pin should be tied to V INSW. VC1, VC2, VC3 (Pins 7, 23, 19): The VC pins are the outputs of the internal error amps. The voltages on these pins control the peak switch currents. These pins are normally used to compensate the control loops. Each switching regulator can be shut down by pulling its respective V C pin to ground with an NMOS or NPN transistor . TRK/SS1, TRK/SS2, TRK/SS3, TRK/SS4 (Pins 8, 21, 18, 26): The TRK/SS pins allow a regulator to track the output of another regulator . When the TRK/SS pin is below 0.8V , the FB pin regulates to the TRK/SS voltage. This pin can also be used as a soft-start by connecting a capacitor from TRK/SS to ground. The TRK/SS pins should be left open if neither feature is used. FB1, FB2, FB3 (Pins 9, 22, 20): The FB pins are the nega- tive inputs of the error amplifi ers. The L T3507 regulates each feedback pin to the lesser of 0.8V or the TRK/SS pin voltage. Connect the feedback resistor divider taps to these pins. Note 6: VINX pins that are connected together may share a bypass capacitor . PGOOD1, PGOOD2, PGOOD3 (Pins 10, 11, 12): The PGOOD pins are the open-collector outputs of an internal comparator . PGOOD remains low until the FB pin is within 10% of the fi nal regulation voltage. As well as indicating output regulation, the PGOOD pins can sequence the switching regulators. These pins must be left unconnected if unused. The PGOOD outputs are valid when V IN is greater than 3.5V and any of the RUN pins are high. They are not valid when all RUN pins are low. R T/SYNC (Pin 13): The RT/SYNC pin requires a resistor to ground or a clock signal to set the operating frequency of the L T3507. RUN1, RUN2, RUN3 (Pins 14, 15, 16): The RUN pins are used to shut down the individual switching regulators. When all three RUN pins are low, the L T3507 shuts down and draws less than 1μA from V IN1. BIAS (Pin 17): The BIAS pin supplies the current to the L T3507’s internal regulator . This pin should be tied to the lowest available voltage source above 3V (either V IN, VOUT or any other available supply). The LDO pass transistor’s base current is supplied from the BIAS pin if it is at least 0.8V above the LDO DRIVE output. DRIVE (Pin 24): The DRIVE pin provides the base drive for an external NPN transistor used for the LDO regulator . FB4 (Pin 25): The FB4 pin is the negative input to the LDO error amplifi er . It is regulated to 0.8V through the LDO feedback resistor divider . V IN2 (Pins 30, 31)/VIN3 (Pins 35, 36 ): The VIN2 and VIN3 pins supply power to the internal switches of the 1.5A con- verters. These pins must be locally bypassed (Note 6). SW1 (Pins 37, 38)/SW2 (Pins 28, 29)/SW3 (Pins 33, 34): The SW pins are the outputs of the internal power switches. Connect these pins to the inductors and switch- ing diodes. Exposed Pad (Pin 39): Ground. The underside Exposed Pad metal of the package provides both electrical contact to ground and good thermal contact to the printed circuit board. The Exposed Pad must be soldered to a grounded pad on the circuit board for proper operation.

Figure 1. L T3507 Block Diagram with Typical External Components

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The L T3507 contains three independent, constant fre- quency, current mode, switching regulators with internal power switches plus a low dropout linear regulator . The three regulators share common circuitry including input source, voltage reference and oscillator , but are otherwise independent. Operation can be best understood by refer- ring to the Block Diagram (Figure 1). If the RUN pins are tied to ground, the L T3507 is shut down and draws <1μA from the input source tied to V IN1. If any of the RUN pins are driven above 1V , the internal bias circuits turn on, including the internal regulator , reference, and master oscillator . Each switching regulator will only begin to operate when its corresponding RUN pin reaches >1.25V . The master oscillator generates three clock signals, with the signal for Channel 1 out of phase by 180°. The three switchers are current mode regulators. Instead of directly modulating the duty cycle of the power switch, the feedback loop controls the peak current in the switch during each cycle. Compared to voltage mode control, cur- rent mode control improves loop dynamics and provides cycle-by-cycle current limit. The Block Diagram shows only one of the three step-down switching regulators. A pulse from the slave oscillator sets the RS fl ip-fl op and turns on the internal NPN bipo- lar power switch. Current in the switch and the external inductor begins to increase. When this current exceeds a level determined by the voltage at V C, current comparator C1 resets the fl ip-fl op, turning off the switch. The current in the inductor fl ows through the external Schottky diode and begins to decrease. The cycle begins again at the next pulse from the oscillator . In this way, the voltage on the V C pin controls the current through the inductor to the output. The internal error amplifi er regulates the output voltage by continually adjusting the V C pin voltage. The threshold for switching on the VC pin is >1V and an active clamp of 1.8V limits the output current. Each switcher contains an extra, independent oscillator to perform frequency foldback during overload conditions. This slave oscillator is normally synchronized to the master oscillator . A comparator senses when V FB is less than 50% of its regulated value and switches the regulator from the master oscillator to a slower slave oscillator . V FB is less than 50% of its regulated value during start-up, short-circuit and overload conditions. Frequency foldback helps limit switch current under these conditions. The TRK/SS pins override the 0.8V reference for the FB pins when the TRK/SS pins are below 0.8V . This allows either coincident or ratiometric supply tracking on start-up as well as a soft-start capability. The switch drivers operate either from V IN or from the BOOST pin. An external capacitor and diode are used to generate a voltage at the BOOST pin that is higher than the input supply. This allows the driver to saturate the internal bipolar NPN power switch for effi cient operation. The BIAS pin allows the internal circuitry to draw its current from a lower voltage supply than the input, also reducing power dissipation and increasing effi ciency. If the voltage on the BIAS pin falls below 3V , then its quiescent current will fl ow from V IN. A power good comparator trips when the FB pin is at 90% of its regulated value. The PGOOD output is an open-collector transistor that is off when the output is in regulation, allowing an external resistor to pull the PGOOD pin high. Power good is valid when the L T3507 is enabled and V IN > 3.5V . The LDO regulator uses an external NPN pass transistor to form a linear regulator . The loop is internally compensated to be stable with a load capacitance of 2.2μF or greater . The LDO is disabled when all three of the RUN pins are low. The overvoltage and undervoltage detection shuts down the L T3507 if the input voltage goes above or below re- sistor programmable thresholds. The hysteresis of these detectors is also resistor programmable.

The output voltage is programmed with a resistor divider (refer to the Block Diagram) between the output and the FB pin. Choose the resistors according to: R1=R2 VOUT 800mV –1⎛ The parallel combination of R1 and R2 should be 10k or less to avoid bias current errors. Input Voltage Range The minimum operating voltage is determined either by the L T3507’s internal undervoltage lockout (4V on VIN1, 3V on VIN2 and VIN3) or by its maximum duty cycle. The duty cycle is the fraction of time that the internal switch is on and is determined by the input and output voltages: DC= VOUT + VF VIN –V SW + VF where VF is the forward voltage drop of the catch diode (~0.4V) and VSW is the voltage drop of the internal switch (~0.3V at maximum load). This leads to a minimum input voltage of: VIN(MIN) = VOUT + VF DCMAX –V F + VSW The duty cycle is the fraction of time that the internal switch is on during a clock cycle. The maximum duty cycle is generally given by DC MAX = 1– t OFF(MIN)• fSW. However, unlike most fi xed frequency regulators, the L T3507 will not switch off at the end of each clock cycle if there is suffi cient voltage across the boost capacitor (C3 in Figure 1) to fully saturate the output switch. Forced switch off for a minimum time will only occur at the end of a clock cycle when the boost capacitor needs to be recharged. This operation has the same effect as lowering the clock frequency for a fi xed off time, resulting in a higher duty cycle and lower minimum input voltage. The resultant duty cycle depends on the charging times of the boost capacitor and can be approximated by the following equation: DCMAX = 1 1+ 1 B where B is the output current capacity divided by the typical boost current from the BOOST pin current vs switch current in the Typical Performance Characteristics section. The maximum operating voltage without pulse-skipping is determined by the minimum duty cycle DC MIN: VIN(PS) = VOUT + VF DCMIN –V F + VSW with DCMIN = tON(MIN) • fSW. Thus both the maximum and minimum input voltages are a function of the switching frequency and output voltages. Therefore the maximum switching frequency must be set to a value that accommodates all the input and output voltage parameters and must meet both of the following criteria for each channel: fMAX1 = VOUT + VF VIN(PS) –V SW + VF ⎠⎟  1 tON(MIN) fMAX2 = 1– VOUT + VF VIN(MIN) –V SW + VF ⎠⎟  1 tOFF(MIN) The values of tON(MIN) and tOFF(MIN) are functions of ISW and temperature (see chart in the Typical Performance Characteristics section). Worst-case values for switch currents greater than 0.5A are t ON(MIN) = 130ns (for TJ > 125°C tON(MIN) = 155ns) and tOFF(MIN) = 170ns. fMAX1 is the frequency at which the minimum duty cycle is exceeded. The regulator will skip ON pulses in order to reduce the overall duty cycle at frequencies above f MAX1. It will continue to regulate but with increased inductor current and greatly increased output ripple. The increased peak inductor current in pulse-skipping will also stress the switch transistor at high voltages and high switch- ing frequency. If the L T3507 is allowed to pulse-skip and the input voltage is greater than 20V , then the switching frequency must be kept below 1.1MHz to prevent damage to the L T3507.

and greatly increased output ripple. the absolute maximum rating. where fSW is in MHz and RT is in kΩ. pulls high or low at some intermediate supply voltage. isolating the clock sync circuit until the clock is operating. the BAS70 from On Semi or CMOD6263 from Central Semi. the inductor value and the input and output voltages. large output capacitors to keep output voltage ripple low. Figure 2. Clock Powered from L T3507 Output

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several vendors and types that are suitable. Table 1. Inductors with LMIN in μH and fSW in MHz. the presence of output capacitor series resistance (ESR). and small circuit size, are therefore an option. where ΔIL is the peak-to-peak ripple current in the inductor . may be unacceptable. Use X7R and X5R types.

Table 2. Low ESR Surface Mount Capacitors reverse voltage is equal to the regulator input voltage. Table 3. Schottky Diodes 3.3V , use a small Schottky diode (such as the BAT54). output (see Output Voltage T racking). between the BOOST and SW pins is less than 25V .

a load to the switcher that will allow it to start. Figure 3. Generating the Boost Voltage Figure 4. The Minimum Input Voltage Depends on Output Voltage, Load Current and Boost Circuit

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3507 F04b

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from a shorted or reversed input. of the same value. Use X5R and X7R types. ceramic capacitor . For details, see Application Note 88. Figure 5. Diode D4 Prevents a Shorted Input from

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achieve low output ripple and small circuit size. Note 76 is an excellent source as well. may improve the transient response. Figure 6. Loop Response Model

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The L T3507 outputs can be sequenced in several ways. shut down the three channels turn off simultaneously. does require three logic inputs. away, just at a slower rate than the faster channels. puts. In Figure 7c, the PG pins drive the RUN pins directly. and channel 3 is held off until channel 2 is in regulation. are held low during shutdown. Figure 7. Output Sequencing

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Figure 8. T wo Different Modes of Output Voltage T racking Figure 9. Setup for Coincident and Ratiometric T racking Figure 10. Equivalent Input Circuit of Error Amplifi er circuit or a collapsing input voltage). dently or ratiometrically track any other channel output. OUT1 must be set higher than VOUT2. Figure 10. At the input stage of the error amplifi er , two

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any channel may be set up to track any other channel. inductor current and therefore input current during start-up. where COUT is the value of the output capacitor . to the VIN pins as possible. the 3.3V input to VIN2 and VIN3. NPN transistors with their saturation specifi cations. The base drive voltage has a maximum voltage of 5V . voltage of the pass transistor . Table 4. NPN Pass T ransistors and Saturation Characteristics always on when the other channels are on.

less to avoid bias current errors. trip levels and hysteresis can be set by resistor values. the resistance of the divider string. Figure 11. Undervoltage and Overvoltage Lockout Circuit

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example of proper PCB layout.

Figure 12. Subtracting the Current When the Switch is ON (12a) From the Current When the Switch is OFF (12b) Reveals the Path of Figure 13. Power Path Components and Topside Layout

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in airfl ow will lead to lower thermal resistance.

The maximum allowed power dissipation by the L T3507 can be determined by: PDISS(MAX) = TJ(MAX) –T A θJA where TJMAX is the maximum die temperature of 125°C (150°C for H-grade). However , take care in determining T A since the catch diodes also dissipate power and must be located close to the L T3507. Another potential heat source is the LDO pass transistor . In a compact layout the pass transistor will be located close to the L T3507. The inductors will also dissipate some power due to their series resistance and they must be close to the L T3507. All of these heat sources will increase the effective ambient temperature seen by the L T3507. A thorough analysis of eight heat sources in a small PCB area is beyond the scope of this data sheet, however a number of thermal analysis programs are available to calculate the temperature rise in each component (such as PCAnalyze from K&K Associates or BETAsoft from Mentor). The power dissipation of each component will be needed to accurately calculate the thermal characteristics of the system. The contributors to power dissipation inside the L T3507 are switch DC loss, switch AC loss, boost current, quiescent current and LDO drive current. The total dissipation within the L T3507 can be expressed as: PDISS = PSWDCi +PSWACi +PBSTi() +PQ +PLDO i=1 The switch DC and AC losses in channel i are: PSWDCi = RSWi IOUTi() VOUTi VINi PSWACi = 17ns IOUTi() VINi() f() APPLICATIONS INFORMATION where RSWi is the equivalent switch resistance (0.18Ω for channel 1 and 0.22Ω for channels 2 and 3) and f is the operating frequency. The boost loss in channel i is: PBSTi = VOUTi VBOOSTi() IOUTi 50 + 0.02A⎛ VINi The quiescent loss is: P Q = VIN1(IQ(VIN1)) + VBIAS(IQ(BIAS)) If the BIAS pin does not have a voltage of at least 3V ap- plied, then VIN1 must replace VBIAS in the equation. Also, IQ(VIN1) can be reduced by 0.2mA (typ) if the LDO is shut off (see the LDO section). The LDO drive loss is: PLDO =(VBIAS −VLDO(OUT) − 0.7V) IOUT(LDO) βPASS ⎠⎟ , if VBIAS ≥ VLDO(OUT) + 1.5V or PLDO =(VIN1 −VLDO(OUT) − 0.7V) IOUT(LDO) βPASS ⎠⎟ , if VBIAS <VLDO(OUT) + 1.5V where βPASS is the current gain of the external pass transistor . Next, the power in the external components must be taken into account. The diode power is given by: PDIODE = VF VIN –V OUT –V F() IOUT VIN where VF is the forward drop of the diode at IOUT. The inductor power is: P IND = (IOUT)2 ESRIND where ESRIND is the inductor equivalent series resistance.

The LDO pass transistor power is: P NPN = IOUTLDO(VC – VOUTLDO) where VC is the collector voltage on the NPN pass tran- sistor . Example: An L T3507 design requirements are: V IN = 8V, f= 500kHz V1 = 2.5V at I1 = 1.6A V2 = 3.3V at I2 = 0.8A (used for boost, bias and V4) V3 = 1.2V at I3 = 1A V4 = 3V at I4 = 0.2A (from 3.3V output) T A = 50°C, TJMAX = 125°C θJA = 34°C/W Schottky V F = 0.45V and Inductor ESR = 0.05Ω PDISS(MAX) = 125°C–5 0 °C 34°C/W = 2.2W PSWDC1 = 0.18Ω 1.6A() 2 2.5V 8V = 0.14W PSWAC1 = 17ns 1.6A() 8V() 500k() = 0.11W PBST1 = 2.5V 3.3V() 1.6A 50 + 0.02A⎛ 8V = 0.06W Similarly, PSWDC2 = 0.09W , P SWAC2 = 0.07W , P BST2 = 0.06W, PSWDC3 = 0.03W , PSWAC3 = 0.07W and P BST2 = 0.03W. Remember, the total current from channel 2 is I2 + I4 since the LDO pass transistor draws from V2. Ignore bias and boost currents. PLDO = 8V 0.2A 100 ⎠⎟ = 0.02W APPLICATIONS INFORMATION The total dissipation on the L T3507 is the sum of all these and is equal to 0.73W . Note that this is less than half of P DISS(MAX). Next, the power dissipation of the external components are: PDIODE1 = 0.45V 8V – 2.5V – 0.45() 1.6A 8V = 0.46W PIND1 = 1.6A() 2 0.05Ω= 0.13W Similarly, PDIODE2 = 0.24W , PIND2 = 0.05W , PDIODE3 = 0.36W and PIND3 = 0.05W . And fi nally: P NPN = 0.2A(3.3V – 3V) = 0.06W Thus the total power dissipated by the L T3507 and external components is 2.08W . The thermal analysis will use these power dissipations to calculate the internal component temperatures. Make sure that none of the components exceed their rated temperature limits. RELATED LINEAR TECHNOLOGY PUBLICATIONS Application Notes 19, 35, 44, 76 and 88 contain more detailed descriptions and design information for buck regulators and other switching regulators. The L T1375 data sheet has a more extensive discussion of output ripple, loop compensation, and stability testing. Design Note 318 shows how to generate a dual polarity output supply using a buck regulator .

3.3V , 5V and 12V from a 24V Input with Ratiometric T racking VIN1 BOOST1 UVLO OVLO BOOST3 SW3 FB3 VC3 BIAS DRIVE FB4 PGOOD1 PGOOD2 PGOOD3 PGOOD1 PGOOD2 PGOOD3 SW1 FB1 V TRK/SS1 TRK/SS2 TRK/SS3 BOOST2 0.1μF 10μF 50V 22μF D1 16.2k 1000pF 1.5nF 41.2k L1 3.3μHVOUT1 3.3V VIN 21V TO 27V VOUT2 1.2A L2 6.8μH L3 10μH BAT54 VIN2 VIN3 VINSW 100k 49.9k 4.53k OVLO = 29V UVLO = 16V 100k 4.32k VOUT1 13.3k 41.2k BAT54 BAT54 18.2k SW2 FB2 VC2 RT/SYNC TRK/SS4 GND L T3507 RUN1 RUN2 RUN3 0.1μF 0.1μF 22μF 10μF 24.3k 26.7k SHDN 470nF 470pF61.9k 68.1kNC VOUT1 D1: ON SEMI MBRS230L T3 D2, D3: ON SEMI MBRA130L T3 L1: COILCRAFT DO1813H-332ML L1: COILCRAFT DO1813H-682ML L1: COILCRAFT DO1813H-103ML 10.7k

3507 TA02

54.9k fSW = 800kHz 11.8k 100k 100k VOUT3 12V 1A150k VOUT1

5V , 3.3V , 2.5V and 1.8V with Coincident T racking VIN1 BOOST1 UVLO OVLO BOOST2 SW2 FB2 VC2 BIAS DRIVE FB4 PGOOD1 PGOOD2 PGOOD3 PGOOD1 PGOOD2 PGOOD3 SW1 FB1 V TRK/SS1 BOOST3 0.22μF 22μF 100μF D1 18.7k 680pF 18.7k 4.7μHVOUT1 1.8V 2.4A VIN 6V TO 36V VOUT3 1.5A 15μH 10μH VIN2 VIN3 VINSW 49.9k 18.2k 100k VOUT1 15k SW3 FB3 VC3 RT/SYNC TRK/SS4 GND L T3507 RUN1 RUN2 RUN3 0.22μF 0.22μF 22μF 22μF 24.3k 16.2k SHDN 680pF 0.01μF 1000pF 53.6k L1: WÜRTH WE-PD 744 778 9004 L2: WÜRTH WE-PD 744 778 9115 L3: WÜRTH WE-PD 744 778 910 D1, D2, D3: DIODES, INC. B240A Q1: ON SEMICONDUCTOR NSS30101L T1G 11.5k 11.5k 24.3k

3507 TA03

fSW = 450kHz 10.2k 2.2nF 22μF 100k 100k VOUT2 3.3V 1.3A VOUT4 2.5V 0.2A 35.7k TRK/SS3 TRK/SS2 TRK/SS2 VOUT2 VOUT2 15k 18.7k 35.7k 11.5k TRK/SS2

15V , 1.8V and 1.2V 2-Stage Step Down VIN1 BOOST1 UVLO OVLO PGOOD2 PGOOD3 BOOST 2 SW2 FB2 VC2 BOOST3 SW3 FB3 TRK/SS2 TRK/SS3 PGOOD1 SW1 FB1 VC1 TRK/SS1 BIAS 0.1μF 22μF 68.1k 31.6k 220pF 0.01μF 187k L1 10μHVOUT1 15V 0.4A VBST VIN 21V TO 36V L2 3.3μH VIN2 VIN3 VINSW 49.9k 3.4k UVLO = 19V 11.5k 10.5k 10μF DRIVE FB4 TRK/SS4 RT/SYNC VC3 GND L T3507 RUN1 RUN2 RUN3 0.1μF 33μF PGOOD V BST 13.3k SHDN 1000pF D1: DIODES, INC. B140A D2, D3: DIODES, INC. B240A L1: TDK L TF5022T-100M1R4 L2: TDK VLCF5020T-3R3N2R0-1 L3: TDK VLCF5020T-2R2N1R7 Q1: DIODES INC. BC817-16 18.2k 100k

3507 TA04

54.9k fSW = 800kHz VOUT2 1.8V 1.5A22.6k VOUT2 L3 2.2μH0.1μF 47μF VBST 12.7k 1000pF 30.1k 270pF 2.2μF VOUT3 1.2V 1.5A15.0k

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION 38-Lead Plastic QFN (5mm × 7mm) (Reference L TC DWG # 05-08-1701) 5.00 ± 0.10 (2 SIDES) NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE M0-220 VARIATION WHKD 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS PIN 1 TOP MARK (SEE NOTE 6) 0.40 ± 0.10 BOTTOM VIEW—EXPOSED PAD 5.15 ± 0.10 (2 SIDES) 7.00 ± 0.10 (2 SIDES) 0.75 ± 0.05 R = 0.115 TYP 0.25 ± 0.05 (UH) QFN 0205 0.50 BSC0.200 REF

0.200 REF

0.00 – 0.05 RECOMMENDED SOLDER PAD LAYOUT 3.15 ± 0.10 (2 SIDES) 0.40 ±0.10 0.70 ± 0.05

0.50 BSC

5.15 ± 0.05 (2 SIDES) 3.15 ± 0.05 (2 SIDES) 4.10 ± 0.05 (2 SIDES) 5.50 ± 0.05 (2 SIDES) 6.10 ± 0.05 (2 SIDES) 7.50 ± 0.05 (2 SIDES) 0.25 ± 0.05 PACKAGE OUTLINE 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008 LT 0509 REV A • PRINTED IN USA TYPICAL APPLICATIONS PART NUMBER DESCRIPTION COMMENTS L T1939 25V , 2A, 2.5MHz High Effi ciency DC/DC Converter and LDO Controller V IN(MIN) = 3.6V , VIN(MAX) = 25V , VOUT(MIN) = 0.8V , IQ = 2.5mA, ISD < 10μA, 3 × 3 DFN-10 Package L T1940 Dual 25V , 1.4A (I OUT), 1.1MHz, High Effi ciency Step-Down DC/DC Converter VIN(MIN) = 3.3V , VIN(MAX) = 25V , VOUT(MIN) = 1.20V , IQ = 3.8mA, ISD < 30μA, TSSOP16E Package L T3480 36V with T ransient Protection to 60V , 2A (I OUT), 2.4MHz, High Effi ciency Step-Down DC/DC Converter with Burst Mode Operation VIN(MIN) = 3.6V , VIN(MAX) = 38V , VOUT(MIN) = 0.78V , IQ = 70μA, ISD < 1μA, 3 × 3 DFN-10, MSOP-10E Package L T3481 34V with T ransient Protection to 36V , 2A (I OUT), 2.8MHz, High Effi ciency Step-Down DC/DC Converter with Burst Mode Operation VIN(MIN) = 3.6V , VIN(MAX) = 34V , VOUT(MIN) = 1.26V , IQ = 50μA, ISD < 1μA, 3 × 3 DFN-10, MSOP-10E Package L T3493 36V , 1.4A (I OUT), 750kHz High Effi ciency Step-Down DC/DC Converter V IN(MIN) = 3.6V , VIN(MAX) = 36V , VOUT(MIN) = 0.8V , IQ = 1.9mA, ISD < 1μA, 2 × 3 DFN-6 Package L T3500 36V , 40Vmax, 2A, 2.5MHz High Effi ciency DC/DC Converter and LDO Controller VIN(MIN) = 3.6V , VIN(MAX) = 36V , VOUT(MIN) = 0.8V , IQ = 2.5mA, ISD < 10μA, 3 × 3 DFN-10 Package L T3501/10 25V , Dual 3A/2A (I OUT), 1.5MHz High Effi ciency Step-Down DC/DC Converter VIN(MIN) = 3.3V , VIN(MAX) = 25V , VOUT(MIN) = 0.8V , IQ = 3.7mA, ISD = 10μA, TSSOP-20E Package L T3505 36V with T ransient Protection to 40V , 1.4A (I OUT), 3MHz, High Effi ciency Step-Down DC/DC Converter VIN(MIN) = 3.6V , VIN(MAX) = 34V , VOUT(MIN) = 0.78V , IQ = 2mA, ISD = 2μA, 3 × 3 DFN-8, MSOP-8E Package L T3506/A 25V , Dual 1.6A (I OUT), 575kHz/1.1MHz High Effi ciency Step-Down DC/DC Converter VIN(MIN) = 3.6V , VIN(MAX) = 25V , VOUT(MIN) = 0.8V , IQ = 3.8mA, ISD = 30μA, TSSOP-16E, 5 × 4 DFN-16 Package L T3508 36V with T ransient Protection to 40V , Dual 1.4A (I OUT), 3MHz, High Effi ciency Step-Down DC/DC Converter VIN(MIN) = 3.7V , VIN(MAX) = 37V , VOUT(MIN) = 0.8V , IQ = 4.6mA, ISD = 1μA, 4 × 4 QFN-24, TSSOP-16E Package L T3684 34V with T ransient Protection to 36V , 2A (I OUT), 2.8MHz, High Effi ciency Step-Down DC/DC Converter VIN(MIN) = 3.6V , VIN(MAX) = 34V , VOUT(MIN) = 1.26V , IQ = 850μA, ISD < 1μA, 3 × 3 DFN-10, MSOP-10E Package L T3685 36V with T ransient Protection to 60V , 2A (I OUT), 2.4MHz, High Effi ciency Step-Down DC/DC Converter VIN(MIN) = 3.6V , VIN(MAX) = 38V , VOUT(MIN) = 0.78V , IQ = 70μA, ISD < 1μA, 3 × 3 DFN-10, MSOP-10E Package ThinSOT is a trademark of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation. 12V to 5V , 3.3V , 1.8V and 1.6V with 1.5mm Maximum Height RELATED PARTS VIN1 BOOST1 UVLO OVLO BOOST3 SW3 FB3 VC3 TRK/SS3 BIAS DRIVE FB4 PGOOD1 PGOOD2 PGOOD3 PGOOD1 PGOOD2 PGOOD3 SW1 FB1 V TRK/SS1 BOOST2 0.1μF 10μF 33μF D1 13.3k 1000pF 1.5nF 22.6k L1 2μHVOUT1 1.8V VIN 8V TO 16V VOUT2 3.3V 1.5A D1: DIODES, INC. DFLS220L D2, D3: DIODES, INC. DFLS120L L1: COOPER SD14-2R0-R L2, L3: COOPER SD14-4R5-R Q1: ON SEMI NSS30071MR6T1G L2 4.5μH L3 4.5μH V IN2 VIN3 VINSW 49.9k 49.9k 4.02k OVLO = 17V UVLO = 7V 100k 11.3k VOUT1 VOUT2 18.2k SW2 FB2 VC2 TRK/SS2 RT/SYNC TRK/SS4 GND L T3507 RUN1 RUN2 RUN3 0.1μF 0.1μF 10μF D2 7.32k 11.3k SHDN 2000pF 1200pF 1.5nF 1.5nF 41.2k 11.8k VOUT2 VOUT2 VOUT1 20.0k 20.0k 31.6k fSW = 1.25MHz 2.2nF 13.3k 100k 100k VOUT3 1.4A VOUT4 1.6V 0.2A 22μF 10μF 61.9k