LT3500

LT3500 LINER | Alldatasheet

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Technical content

FEATURES

APPLICATIONS

DESCRIPTION

The L T®3500 is a current mode PWM step-down DC/DC converter with an internal 2.3A switch. The wide input range of 3V to 40V makes the L T3500 suitable for regulating power from a wide variety of sources, including automo- tive batteries, 24V industrial supplies and unregulated wall adapters. Resistor-programmable 250kHz to 2.2MHz frequency range and synchronization capability enable optimization between effi ciency and external component size. Cycle- by-cycle current limit, frequency foldback and thermal shutdown provide protection against a shorted output. The soft-start feature controls the ramp rate of the output voltage, eliminating input current surge during start-up, and also provides output tracking. The L T3500 contains an internal NPN transistor with feed- back control which can be confi gured as a linear regulator or as a linear regulator controller . The L T3500’s low current shutdown mode (<12μA) enables easy power management in battery-powered systems. n Wide Input Range: 3V to 36V Operating, 40V Maximum n Short-Circuit Protected Over Full Input Range n 2A Output Current Capability n Adjustable/Synchronizable Fixed Frequency Operation from 250kHz to 2.2MHz n Soft-Start/T racking Capability n Output Adjustable Down to 0.8V n Adjustable Linear Regulator/Driver with 13mA Output Capability n Power Good Comparator with Complimentary Outputs n Low Shutdown Current: 12μA n Thermally Enhanced 3mm × 3mm DFN or 16-Pin n Automotive Battery Regulation n Industrial Control n Wall T ransformer Regulation n Distributed Power Regulation Dual Step-Down Converters Output Voltage RippleSwitching Converter Effi ciency L, L T , L TC and L TM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 6.8μH 0.47μF 22μF 22μF 42.2k 8.06k 2.2μF 0.47μF VIN 6V TO 36V 40.2k 53.6k 330pF

3500 TA01a

3.3V B240A BSTVIN SW FB SHDN SS L T3500 RT/SYNC VC LDRV LFB PG PG 8.06k 24.9k LOAD CURRENT (A) EFFICIENCY (%) 1.6

3500 TA01b

VIN = 12V IOUT2 = 0A FREQUENCY = 800kHz 500ns/DIV 3500 TA01c VOUT1 = 5V AT 1A AC COUPLED 2mV/DIV VOUT2 = 3.3V AT 1A AC COUPLED 2mV/DIV

FB, LFB, R (Note 1) TOP VIEW DD PACKAGE 12-LEAD (3mm × 3mm) PLASTIC DFN 1 SW BST LDRV LFB FB PG V IN SHDN SS PG VC RT/SYNC 6 7 θJA = 45°C/W , θJC(PAD) = 10°C/W EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB NC1 V IN SHDN SS PG VC RT/SYNC NC8 NC16 SW BST LDRV LFB FB PG NC9 TOP VIEW MSE PACKAGE 16-LEAD PLASTIC MSE θJA = 45°C/W , θJC(PAD) = 10°C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB PIN CONFIGURATION ORDER INFORMATION Operating Junction Temperature Range LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L T3500EDD#PBF L T3500EDD#TRPBF LCRN 12-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C L T3500IDD#PBF L T3500IDD#TRPBF LCRN 12-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C L T3500HDD#PBF L T3500HDD#TRPBF LDCY 12-Lead (3mm × 3mm) Plastic DFN –40°C to 150°C L T3500EMSE#PBF L T3500EMSE#TRPBF 3500 16-Lead Plastic MSE –40°C to 125°C L T3500IMSE#PBF L T3500IMSE#TRPBF 3500 16-Lead Plastic MSE –40°C to 125°C L T3500HMSE#PBF L T3500HMSE#TRPBF 3500 16-Lead Plastic MSE –40°C to 150°C Consult L TC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container . Consult L TC Marketing for information on non-standard lead based fi nish parts. For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear .com/tapeandreel/

The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TJ = 25°C. VVIN = 15V , VRT/SYNC = 2V , unless otherwise specifi ed. PARAMETER CONDITIONS MIN TYP MAX UNITS SHDN Threshold l 710 760 780 mV SHDN Source Current V SHDN = 0.62V 1.5 2.5 3.5 μA SHDN Current Hysterisis 1.25 2 3.25 μA Minimum Input Voltage (Note 3) V FB = 0V l 2.4 2.8 V Supply Shutdown Current V SHDN = 0V l 12 30 μA Supply Quiescent Current V FB = 0.9V 2.5 3.5 mA FB Voltage V VC = 1V VVC = 0.8V to 1.6V , VIN = 3V to 40V l l 0.784 0.776 0.8 0.8 0.816 0.824 V V FB Bias Current V FB = 0.8V , VVC = 1V 50 150 nA Error Amplifi er gm VVC = 1V , IVC = ±10μA 150 250 350 μmho Error Amplifi er Source Current V FB = 0.6V , VVC = 1V 12 16 20 μA Error Amplifi er Sink Current V FB = 1V , VVC = 1V 14 18 22 μA Error Amplifi er High Clamp V FB = 0.6V 1.8 2.0 2.2 V Error Amplifi er Switching Threshold V FB = 0.6V 0.6 0.8 1.0 V SS Sink Current V FB = 0V , VSS = 2V 300 600 900 μA SS POR Sink Current (Note 4) V FB = 0V , VSS = 2V , Cycle SHDN 400 600 800 μA SS POR Threshold 50 100 150 mV SS to FB Offset (VSS – VFB)V VC = VFS, VSS = 0.4V 70 100 120 mV PG/PG Leakage V FB = 0.9V , VPG/VPG = 40V 0.1 1 μA PG/PG Threshold (Rising) V PG = 0.4V 0.685 0.708 0.730 V PG/PG Hysteresis (Falling) V PG = 0.4V 20 30 40 mV PG Sink Current V PG = 0.4V , VFB = 0.7V 250 500 750 μA PG Sink Current V PG = 0.4V , VFB = 0.9V 500 800 1100 μA RT/SYNC Reference Voltage V FB = 0.9V , RRT/SYNC = 15k 0.75 0.850 0.975 V Switching Frequency R RT/SYNC = 90.9k RRT/SYNC = 90.9k RRT/SYNC = 15k l 450 425 500 500 2.4 550 625 2.8 kHz kHz MHz SYNC Frequency Range l 250 2500 kHz Minimum Switch On Time V FB = 0.7V , RRT/SYNC = 90.9k 140 ns Minimum Switch Off Time V FB = 0.7V , RRT/SYNC = 90.9k 120 ns Switch Leakage Current V SW = 0V 1 10 μA Switch Saturation Voltage I SW = 2A, VBST = 18V , VFB = 0.7V 450 mV Switch Peak Current DD Package V BST = 18V , VFB = 0.7V l 2.3 2.1 2.8 2.8 3.5 3.5 A A Switch Peak Current MSE Package V BST = 18V , VFB = 0.7V l 2.3 2.1 2.9 2.9 3.5 3.7 A A Boost Current I SW = 2A, VBST = 20V , VFB = 0.7V 20 30 45 mA Minimum Boost Voltage (Note 5) I SW = 2A, VFB = 0.7V 2.2 3 V

ELECTRICAL CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITS LFB Voltage V LDRV = VLFB l 0.784 0.8 0.816 V LFB Line/Load Regulation V VIN = 3V to 40V , VLDRV = VLFB l 0.776 0.8 0.824 V SS to LFB Offset (VSS – VLFB)V SS = 0.8V , VLDRV = VLFB 90 115 140 mV LFB Bias Current V LFB = 0.8V 115 300 nA LDRV Dropout (VVIN – VLDRV)V LDRV = 3V , ILDRV = 5mA l 0.8 1.2 1.6 V LDRV Maximum Current V LDRV = 0V l 91 3 1 8m A ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TJ = 25°C. VVIN = 15V , VRT/SYNC = 2V , unless otherwise specifi ed. Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note2: The L T3500EDD/L T3500EMSE is guaranteed to meet performance specifi cations from 0°C to 125°C junction temperature. Specifi cations over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The L T3500IDD/L T3500IMSE is guaranteed over the full –40°C to 125°C operating junction temperature range. The L T3500HDD/L T3500HMSE is guaranteed over the full –40°C to 150°C operating junction temperature range. High junction temperatures degrade operating lifetimes. Operating lifetime is derated at junction temperatures greater than 125°C. Note 3: Minimum input voltage is defi ned as the voltage where internal bias lines are regulated so that the reference voltage and oscillator remain constant. Actual minimum input voltage to maintain a regulated output will depend upon output voltage and load current. See Applications Information. Note 4: An internal power-on reset (POR) latch is set on the positive transition of the SHDN pin through its threshold. The output of the latch activates a current source on the SS pin which typically sinks 600μA, discharging the SS capacitor . The latch is reset when the SS pin is driven below the soft-start POR threshold or the SHDN pin is taken below its threshold. Note 5: This is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch. Note 6: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. Continuous operation above the specifi ed maximum operating junction temperature may impair device reliability. TYPICAL PERFORMANCE CHARACTERISTICS Feedback Voltage vs Temperature RT/SYNC Voltage vs Temperature Shutdown Threshold and Minimum Input Voltage vs Temperature TEMPERATURE (°C) –50 VOL TAGE (V) 0.800 FB LFB 0.810 150

3500 G01

0.790 0.780 0 50 100–25 25 75 125 0.820 0.795 0.805 0.785 0.815 TEMPERATURE (°C) –50

0.90 VOLTAGE (V)

0.92 0.96 0.98 1.00 1.10 1.04 0 50 75

3500 G02

0.94 1.06 1.08 1.02 –25 25 100 125 150 RRT/SYNC = 90.9k RRT/SYNC = 15k TEMPERATURE (°C) –50 VOLTAGE (V) 2.0 2.5 3.0 25 75

3500 G03

1.5 1.0 –25 0 50 100 150 125 0.5 MINIMUM INPUT VOLTAGE SHUTDOWN THRESHOLD

TYPICAL PERFORMANCE CHARACTERISTICS Shutdown Input Currents vs Temperature Shutdown Quiescent Current vs Temperature Error Amplifi er gm vs Temperature Soft-Start Source Current vs Temperature Soft-Start Feedback Offset vs Temperature VC Switching Threshold vs Temperature TEMPERATURE (°C) –50 CURRENT (μA) 05 0 100 150

3500 G04

–25 25 75 125 VSHDN = 0.7V VSHDN = 0.9V TEMPERATURE (°C) –50 CURRENT (μA) 2.5 5.0 7.5 10.0 05 0 100 150

3500 G05

12.5 15.0 –25 25 75 125 TEMPERATURE (°C) –50

100 TRANSCONDUCTANCE (μmhos)150

3500 G06

–25 25 75 125 TEMPERATURE (°C) –50 1.5 CURRENT (μA) 1.7 2.1 2.3 2.5 3.5 2.9 0 50 75

3500 G07

1.9 3.1 3.3 2.7 –25 25 100 125 150 TEMPERATURE (°C) –50 VOLTAGE (mV) 100 125 150 LFB FB –25 0 25 50

3500 G08

TEMPERATURE (°C) –50

0.50 VOLTAGE (V)

0.55 0.65 0.70 0.75 0.95

3500 G09

0.60 0–25 75 10025 150 125 0.80 0.85 0.90 Power Good Thresholds vs Temperature Power Good Sink Currents vs Temperature Frequency vs Temperature TEMPERATURE (°C) –50 0.65 VOLTAGE (V) 0.66 0.68 0.69 0.70 0.75 0.72 0 50 75

3500 G10

0.67 0.73 0.74 0.71 –25 25 100 150125 RISING EDGE FALLING EDGE TEMPERATURE (°C) –50 CURRENT (μA) 100 300 400 500 1000 700 0 50 75

3500 G11

–25 25 100 150125 TEMPERATURE (°C) –50

400 FREQUENCY (kHz)

3500 G12

–25 25 100 150125 RRT/SYNC = 90.9k

Boost Current vs Switch Current Minimum Boost Voltages vs Temperature Minimum Input Voltage SWITCH CURRENT (A) BOOST CURRENT (mA) 1.6

3500 G19

150°C 25°C –50°C TEMPERATURE (°C) –50 1.5 BOOST VOLTAGE (V) 1.7 1.9 2.1 2.3 05 0 100 150

3500 G20

2.5 2.7 –25 25 75 125 MINIMUM BOOST FOR SWITCH SATURATION LOAD CURRENT (A) INPUT VOLTAGE (V) 1.6

3500 G21

VOUT1 = 5V VOUT1 = 3.3V TA = 25°C fSW = 1MHz L = 3.3μH TYPICAL PERFORMANCE CHARACTERISTICS Peak Switch Current vs Temperature LDRV Short-Circuit Current vs Temperature External Sync Duty Cycle Range vs External Sync Frequency Minimum Switching Times Frequency vs R RT/SYNC Switch Saturation Voltage vs Switch Current TEMPERATURE (°C) –50

2.5 CURRENT (A)

2.6 2.8 2.9 3.0 3.5 3.2 0 50 75

3500 G13

2.7 3.3 3.4 3.1 –25 25 100 150125 MSE PACKAGE DD PACKAGE TEMPERATURE (°C) –50 CURRENT (mA) 0 50 75

3500 G14

–25 25 100 150125 SYNCHRONIZATION FREQUENCY (kHz) 250 DUTY CYCLE (%) 100 750 1250

3500 G15

TA = 25°C TEMPERATURE (°C) –50 TIME (ns) 125 150 175 300 225 0 50 75

3500 G16

–25 25 100 125 150 MINIMUM ON TIME MINIMUM OFF TIME RRT/SYNC (kΩ) FREQUENCY (kHz) 1500 2000 2500 160

3500 G17

4020 8060 120 140 180100 200 TA = 25°C SWITCH CURRENT (A) SWITCH SATURATION VOLTAGE (mV) 200 400 600 100 300 500 0.4 0.8 1.2 1.6

3500 G18

–50°C 150°C 25°C

TYPICAL PERFORMANCE CHARACTERISTICS LDRV Dropout Voltage vs Temperature Inductor Value for 2A Maximum Load Current (VOUT1 = 3.3V , IRIPPLE = 250mA) VIN: The VIN pin powers the internal control circuitry and is monitored by an undervoltage comparator . The VIN pin is also connected to the collectors of the internal power NPN switch and linear output NPN. The V IN pin has high dI/dt edges and must be decoupled to ground close to the pin of the device. SHDN: The SHDN pin is used to shut down the L T3500 and reduce quiescent current to a typical value of 12μA. The accurate 0.76V threshold and input current hysteresis can be used as an undervoltage lockout, prevent- ing the regulator from operating until the input voltage has reached a predetermined level. Force the SHDN pin above its threshold or let it fl oat for normal operation. SS: The SS pin is used to control the slew rate of the output of both the switching and linear regulators. A single capacitor from the SS pin to ground determines the regulators’ ramp rate. For soft-start details see the Applications Information section. PG: The power good pin is an open-collector output that sinks current when the FB or LFB falls below 90% of its nominal regulating voltage. For V IN above 2V , its output state remains true, although during SHDN, VIN undervoltage lockout, or thermal shutdown, its current sink capability is reduced V C: The VC pin is the output of the error amplifi er and the input to the peak switch current comparator . It is normally used for frequency compensation, but can also be used as a current clamp or control loop override. If the error amplifi er drives V C above the maximum switch current level, a voltage clamp activates. This indicates that the output is overloaded and current to be pulled from the SS pin reducing the regulation point. R T/SYNC: This RT/SYNC pin provides two modes of setting the constant switch frequency. Connecting a resistor from the R T/SYNC pin to ground will set the R T/SYNC pin to a typical value of 1V . The resultant switching frequency will be set by the resistor value. The minimum value of 15kΩ and maximum value of 200kΩ set the switching frequency to 2.5MHz and 250kHz respectively. Switcher Dropout Operation TEMPERATURE (°C) –50 1.00 VOLTAGE (V) 1.05 1.15 1.20 1.25 1.50 1.35 0 50 75

3500 G22

1.10 1.40 1.45 1.30 –25 25 100 125 150 ILDRV = 5mA INPUT VOLTAGE (V) 2.5 OUTPUT VOLTAGE (V) 3.0 3.5 4.0 4.5

3500 G23

5.0 5.5 IVOUT1 = 1A TA = 25°C VVOUT1 = 5V VVOUT1 = 3.3V INPUT VOLTAGE (V) 250 FREQUENCY (kHz) 500 1000 1250 1500 2500

3500 G24

L = 1.5μH L = 2.2μH L = 4.7μH L = 6.8μH L = 10μH L = 3.3μH L = 1μH TA = 25°C PIN FUNCTIONS

Driving the R T/SYNC pin with an external clock signal will synchronize the switch to the applied frequency. Synchronization occurs on the rising edge of the clock signal after the clock signal is detected. Each rising clock edge initiates an oscillator ramp reset. A gain control loop servos the oscillator charging current to maintain a con- stant oscillator amplitude. Hence, the slope compensation remains unchanged. If the clock signal is removed, the oscillator reverts to resistor mode and reapplies the 1V bias to the R T/SYNC pin after the synchronization detection circuitry times out. The clock source impedance should be set such that the current out of the R T/SYNC pin in resistor mode generates a frequency roughly equivalent to the synchronization frequency. Floating or holding the R T/SYNC pin above 1.1V will not damage the device, but will halt oscillation. PG: The power good bar pin is an open-collector output that sinks current when the FB or LFB rises above 90% of its nominal regulating voltage. FB: The FB pin is the negative input to the switcher error amplifi er . The output switches to regulate this pin to 0.8V with respect to the exposed ground pad. Bias current fl ows out of the FB pin. LFB: The LFB pin is the negative input to the linear error amplifi er . The L DRV pin servo’s to regulate this pin to 0.8V with respect to the exposed ground pad. Bias current fl ows out of the LFB pin. LDRV: The LDRV pin is the emitter of an internal NPN that can be confi gured as an output of a linear regulator or as the drive for an external NPN high current regulator . Cur- rent fl ows out of the LDRV pin when the LFB pin voltage is below 0.8V . The LDRV pin has a typical maximum current capability of 13mA. BST : The BST pin provides a higher than V IN base drive to the power NPN to ensure a low switch drop. A compara- tor to V IN imposes a minimum off time on the SW pin if the BST pin voltage drops too low. Forcing a SW off time allows the boost capacitor to recharge. SW: The SW pin is the emitter of the on-chip power NPN. At switch off, the inductor will drive this pin below ground with a high dV/dt. An external catch diode to ground, close to the SW pin and respective V IN decoupling capacitor’s ground, must be used to prevent this pin from excessive negative voltages. Exposed Pad: GND. The Exposed Pad is the only ground connection for the device. The Exposed Pad should be soldered to a large copper area to reduce thermal resis- tance. The GND pin also serves as small-signal ground. For ideal operation all small-signal ground paths should connect to the GND pin at a single point, avoiding any high current ground returns. NC Pins (MSE Package Only): No Connection. The NC pins are electrically isolated from the L T3500. The NC pins may be connected to PCB traces to aid PCB layout.

Figure 1. L T3500 Block Diagram

The L T3500 is a constant frequency, current mode buck converter with an internal 2.3A switch plus a linear regula- tor with 13mA output capability. Control of both outputs is achieved with a common SHDN pin, internal regulator , oscillator , undervoltage detect, soft-start, thermal shut- down and power-on reset. If the SHDN pin is taken below its 0.8V threshold, the L T3500 will be placed in a low quiescent current mode. In this mode the L T3500 typically draws 12μA from the V IN pin. When the SHDN pin is fl oated or driven above 0.76V , the internal bias circuits turn on generating an internal regu- lated voltage, 0.8(V FB) and 1V(RT/SYNC) references, and a POR signal which sets the soft-start latch. As the RT/SYNC pin reaches its 1V regulation point, the internal oscillator will start generating a clock signal at a frequency determined by the resistor from the R T/SYNC pin to ground. Alternatively, if a synchronization signal is detected by the L T3500 at the R T/SYNC pin, a clock signal will be generated at the incoming frequency on the rising edge of the synchronization pulse. In addition, the internal slope compensation will be automatically adjusted to pre- vent subharmonic oscillation during synchronization. The L T3500 is a constant frequency, current mode step- down converter . Current mode regulators are controlled by an internal clock and two feedback loops that control the duty cycle of the power switch. In addition to the normal error amplifi er , there is a current sense amplifi er that monitors switch current on a cycle-by-cycle basis. This technique means that the error amplifi er commands current to be delivered to the output rather than voltage. A voltage fed system will have low phase shift up to the resonant frequency of the inductor and output capacitor , then an abrupt 180° shift will occur . The current fed system will have 90° phase shift at a much lower frequency, but will not have the additional 90° shift until well beyond the LC resonant frequency. This makes it much easier to frequency compensate the feedback loop and also gives much quicker transient response. During power up, the POR signal sets the soft-start latch, which discharges the SS pin to ensure proper start-up operation. When the SS pin voltage drops below 100mV , the V C pin is driven low disabling switching and the soft- start latch is reset. Once the latch is reset the soft-start capacitor starts to charge with a typical value of 2.75μA. As the voltage rises above 100mV on the SS pin, the V C pin will be driven high by the error amplifi er . When the voltage on the VC pin exceeds 0.8V , the clock set-pulse sets the driver fl ip-fl op which turns on the internal power NPN switch. This causes current from V IN, through the NPN switch, inductor and internal sense resistor , to increase. When the voltage drop across the internal sense resistor exceeds a predetermined level set by the voltage on the V C pin, the fl ip-fl op is reset and the internal NPN switch is turned off. Once the switch is turned off the inductor will drive the voltage at the SW pin low until the external Schottky diode starts to conduct, decreasing the current in the inductor . The cycle is repeated with the start of each clock cycle. However , if the internal sense resistor voltage exceeds the predetermined level at the start of a clock cycle, the fl ip-fl op will not be set resulting in a further decrease in inductor current. Since the output current is controlled by the V C voltage, output regulation is achieved by the error amplifi er continually adjusting the VC pin voltage. The error amplifi er is a transconductance amplifi er that compares the FB voltage to either the SS pin voltage minus 100mV or an internally regulated 800mV , whichever is lowest. Compensation of the loop is easily achieved with a simple capacitor or series resistor/capacitor from the V C pin to ground. Since the SS pin is driven by a constant current source, a single capacitor on the soft-start pin will generate controlled linear ramp on the output voltage. If the current demanded by the output exceeds the maxi- mum current dictated by the V C pin clamp, the SS pin will be discharged, lowering the regulation point until the output voltage can be supported by the maximum current. When overload is removed, the output will soft-start from the overload regulation point.

and maintain high effi ciency. provide a linear regulator with higher current capability. or inverted power good logic. R2 should be 10.0k or less to avoid bias current errors. Figure 1. The R T/SYNC pin is internally regulated at 1V . switch, all at maximum load current. Figure 2. Frequency vs RT/SYNC Resistance

3500 F02

Table 1. Effi ciency and Size Comparisons for Different RRT/SYNC Values, VOUT1 = 3.3V illustrates the tradeoffs of switch frequency selection. input voltage range of the regulator can be determined. DC MAX = 1 – tOFF(MIN) • Frequency. vs load current for 3.3V and 5V applications. frequency and minimum duty cycle. Figure 3. Minimum Input Voltage vs Load Current

3500 F03

Note that the L T3500 will regulate if the input voltage is taken above the calculated maximum voltage as long as maximum ratings of the V IN and BST pins are not violated. However operation in this region of input voltage will exhibit pulse skipping behavior . Example: V OUT1 = 3.3V , IOUT1 = 1A, Frequency = 1MHz, Temperature = 25°C, V SW = 0.3V , VD = 0.4V , tON(MIN) = 150ns, tOFF(MIN) = 110ns DCMAX = 1−(110ns)1MHz= 89% VIN(MIN) = 3.3 + 0.4 DCMIN = tON(MIN) Frequency = 15% VIN(MAX) = 3.3 + 0.4 Inductor Selection and Maximum Output Current A good fi rst choice for the inductor value is: L = (VIN − VOUT1)V OUT1 VIN f where f is frequency in MHz and L is in μH. With this value the maximum load current will be ~2A, independent of input voltage. The inductor’s RMS current rating must be greater than your maximum load current and its saturation current should be about 30% higher . To keep effi ciency high, the series resistance (DCR) should be less than 0.05Ω. For applications with a duty cycle of about 50%, the induc- tor value should be chosen to obtain an inductor ripple current less than 40% of peak switch current. Of course, such a simple design guide will not always result in the optimum inductor for your application. A larger value provides a slightly higher maximum load current, and will reduce the output voltage ripple. If your load is lower than 1.5A, then you can decrease the value of the inductor and operate with higher ripple current. This allows you to use a physically smaller inductor , or one with a lower DCR resulting in higher effi ciency. The current in the inductor is a triangle wave with an average value equal to the load current. The peak switch current is equal to the output current plus half the peak-to peak inductor ripple current. The L T3500 limits its switch current in order to protect itself and the system from overload faults. Therefore, the maximum output current that the L T3500 will deliver depends on the current limit, the inductor value, switch frequency, and the input and output voltages. The inductor is chosen based on output current requirements, output voltage ripple requirements, size restrictions and effi ciency goals. When the switch is off, the inductor sees the output volt- age plus the catch diode drop. This gives the peak-to-peak ripple current in the inductor: ΔIL = 1−DC() VOUT1 + VD() Lf where f is the switching frequency of the L T3500 and L is the value of the inductor . The peak inductor and switch current is: ISW(PK) =ILPK =IOUT1 + ΔIL

equations assume that the inductor current is continuous.

1. Finally, for duty cycles greater than 50% (V

the input capacitor considerations in more detail. switching current into a tight local loop, minimizing EMI. have an adequate ripple current rating. and is largest when VIN = 2VOUT1 (50% duty cycle). Figure 4. Inductor Values for 2A Maximum Load Current

3500 F04

The frequency, V IN to V OUT1 ratio, and maximum load current requirement of the L T3500 along with the input supply source impedance, determine the energy storage requirements of the input capacitor . Determine the worst- case condition for input ripple current and then size the input capacitor such that it reduces input voltage ripple to an acceptable level. Typical values for input capacitors run from 10μF at low frequencies to 2.2μF at higher frequencies. The combination of small size and low impedance (low equivalent series resistance or ESR) of ceramic capacitors make them the preferred choice. The low ESR results in very low voltage ripple and the capacitors can handle plenty of ripple current. They are also comparatively robust and can be used in this application at their rated voltage. X5R and X7R types are stable over temperature and applied voltage, and give dependable service. Other types (Y5V and Z5U) have very large temperature and voltage coeffi cients of capacitance, so they may have only a small fraction of their nominal capacitance in your application. While they will still handle the RMS ripple current, the input voltage ripple may become fairly large, and the ripple current may end up fl owing from your input supply or from other by- pass capacitors in your system, as opposed to being fully sourced from the local input capacitor . An alternative to a high value ceramic capacitor is a lower value along with a larger electrolytic capacitor , for example a 1μF ceramic capacitor in parallel with a low ESR tantalum capacitor . For the electrolytic capacitor , a value larger than 10μF will be required to meet the ESR and ripple current require- ments. Because the input capacitor is likely to see high surge currents when the input source is applied, tantalum capacitors should be surge rated. The manufacturer may also recommend operation below the rated voltage of the capacitor . Be sure to place the 1μF ceramic as close as possible to the V IN and GND pins on the IC for optimal noise immunity. A fi nal caution regarding the use of ceramic capacitors for input bypassing. A ceramic input capacitor can combine with stray inductance to form a resonant tank circuit. If power is applied quickly (for example, by plugging the circuit into a live power source) this tank can ring, doubling the input voltage and damaging the L T3500. The solution is to either clamp the input voltage or dampen the tank circuit by adding a lossy capacitor in parallel with the ceramic capacitor . For details see Application Note 88. Output Capacitor Selection Typically step-down regulators are easily compensated with an output crossover frequency that is 1/10 of the switch- ing frequency. This means that the time that the output capacitor must supply the output load during a transient step is ~2 or 3 switching periods. With an allowable 5% drop in output voltage during the step, a good starting value for the output capacitor can be expressed by: CVOUT1 = Max Load Step Frequency  0.05  VOUT1 Example: V OUT1 = 3.3V , Frequency = 1MHz, Max Load Step = CVOUT1 = 2 1MHz  0.05  3.3= 12μF The calculated value is only a suggested starting value. Increase the value if transient response needs improvement or reduce the capacitance if size is a priority. The output capacitor fi lters the inductor current to generate an output with low voltage ripple. It also stores energy in order to satisfy transient loads and to stabilize the L T3500’s control loop. The switching frequency of the L T3500 determines APPLICATIONS INFORMATION

the value of output capacitance required. Also, the current mode control loop doesn’t require the presence of output capacitor series resistance (ESR). For these reasons, you are free to use ceramic capacitors to achieve very low output ripple and small circuit size. Estimate output ripple with the following equations: VRIPPLE = ΔIL 8 Frequency  COUT1 For ceramic capacitors and, V RIPPLE = ΔIL • ESR For electrolytic (tantalum and aluminum) where ΔIL is the peak-to-peak ripple current in the inductor . The RMS content of this ripple is very low, and the RMS current rating of the output capacitor is usually not of concern. Another constraint on the output capacitor is that it must have greater energy storage than the inductor; if the stored energy in the inductor is transferred to the output, you would like the resulting voltage step to be small compared to the regulation voltage. For a 5% overshoot, this require- ment becomes: COUT1>10 L ILIM VOUT1 Finally, there must be enough capacitance for good transient performance. The last equation gives a good starting point. Alternatively, you can start with one of the designs in this data sheet and experiment to get the desired performance. This topic is covered more thoroughly in the section on loop compensation. The high performance (low ESR), small size and robust- ness of ceramic capacitors make them the preferred type for L T3500 applications. However , all ceramic capacitors are not the same. As mentioned above, many of the high value capacitors use poor dielectrics with high tempera- ture and voltage coeffi cients. In particular , Y5V and Z5U types lose a large fraction of their capacitance with ap- plied voltage and temperature extremes. Because the loop stability and transient response depend on the value of C OUT1, you may not be able to tolerate this loss. Use X7R and X5R types. You can also use electrolytic capacitors. The ESRs of most aluminum electrolytics are too large to deliver low output ripple. Tantalum and newer , lower ESR organic electrolytic capacitors intended for power supply use, are suitable and the manufacturers will specify the ESR. The choice of capacitor value will be based on the ESR required for low ripple. Because the volume of the capacitor determines its ESR, both the size and the value will be larger than a ceramic capacitor that would give you similar ripple performance. One benefi t is that the larger capacitance may give better transient response for large changes in load current. Catch Diode The diode D1 conducts current only during switch off time. Use a Schottky diode to limit forward voltage drop to increase effi ciency. The Schottky diode must have a peak reverse voltage that is equal to regulator input voltage and sized for average forward current in normal operation. Average forward current can be calculated from: ID(AVG) = IOUT1 VIN V IN − VOUT1() APPLICATIONS INFORMATION

Figure 5. BST Pin Considerations

3500 F05

case condition of a high input voltage and shorted output. Figure 5 shows four ways to arrange the boost circuit. in the Absolute Maximum Ratings section.

Use a Schottky diode for the lowest start-up voltage. including load current, input voltage and temperature. stability using a transient load. Figure 6. Model for Loop Response

3500 F06

Figure 7. Synchronous Signal Powered from Regulator’s Output

3500 F07

to avoid subharmonic oscillation. of these parameters will cause erratic switching behavior . above 1.1V at any time, switching will be disabled. pin to ground will set the start-up frequency.

where these problems might occur . 4.75V and is to stop if the input falls below 3.75V . Figure 8. Undervoltage Lockout

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response with a 0.47μF output capacitor . erly is 2V plus the base emitter drop of the external NPN. Figure 9. Linear Regulator T ransient Response proximately 10 degrees rise in die temperature. pin should be shorted to the LFB Pin. shows the high di/dt paths in the buck regulator circuit. by these components should be as small as possible. board and their connections should be made on that layer . Figure 10. Linear Controller

3500 F10

Figure 11. Subtracting the Current when the Switch is On (11a) from the Current when the Switch is Off (11b) Reveals the Path of the Figure 12. L T3500 Demonstration Circuit Board DC1069A

3500 F11

proper component placement and trace routing. sheet’s Thermal Considerations section. supply using a buck regulator .

High Effi ciency Linear Regulator 3.3μH 0.47μF 22μF 22μF 25.5k R2 8.06k 2.2μF 0.47μF 4.5V TO 36V 49.9k 40.2k 220pF

3500 TA02a

3.3V BAT54 B240A BSTVIN SW FB SHDN SS L T3500 GND RT/SYNC VC LDRV PG LFB PG 8.06k 10kR3 24.9k ZXMN2A03E6 Effi ciency vs Load Current LOAD CURRENT (A) 0 0.2 EFFICIENCY (%) 0.4 0.8 1.0

3500 TA02b

0.6 1.2 1.4

5V/1.5A, 3.3V/0.5A Step-Down with Output Disconnect 5V/2A Step-Down with Power Good LED 4.7μH 0.47μF 22μF 22μF 42.2k 100kR2 8.06k 2.2μF 0.47μF 6V TO 32V 49.9k 40.2k 220pF

3500 TA03

1.5A V OUT2 3.3V 0.5A BAT54 B240A BSTVIN SW FB SHDN SS L T3500 GND RT/SYNC VC LDRV PG LFB PG 8.06k 24.9k ZXTCM322 I89 ZXMP3A17E6 4.7μH 0.47μF 22μF ZXM61N02F 42.2k R2 8.06k 2.2μF 0.47μF 6V TO 32V 49.9k 40.2k 220pF

3500 TA04

42.2k BSTVIN SW FB SHDN SS L T3500 GND RT/SYNC VC LDRV PG LFB PG 100k 8.06k 8.06k 1μF

12-Lead Plastic DFN (3mm × 3mm) (Reference L TC DWG # 05-08-1725 Rev A) 3.00 ±0.10 (4 SIDES) NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.40 ± 0.10 BOTTOM VIEW—EXPOSED PAD 1.65 ± 0.10 0.75 ±0.05 R = 0.115 TYP 127 PIN 1 TOP MARK (SEE NOTE 6)

0.200 REF

0.00 – 0.05 (DD12) DFN 0106 REV A RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.23 ± 0.05 0.25 ± 0.05

2.25 REF

2.38 ±0.05 0.70 ±0.05 3.50 ±0.05 PACKAGE OUTLINE PIN 1 NOTCH R = 0.20 OR 0.25 × 45° CHAMFER 2.38 ±0.10

0.45 BSC

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION 16-Lead Plastic MSOP, Exposed Die Pad (Reference L TC DWG # 05-08-1667 Rev A) MSOP (MSE16) 0608 REV A 0.53 p 0.152 (.021 p .006) SEATING PLANE 0.18 (.007) 1.10 (.043) MAX 0.17 – 0.27 (.007 – .011) TYP 0.86 (.034) REF 0.50 (.0197) BSC 16151413121110 12345678 1 8 NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.254 (.010) 0o – 6o TYP DETAIL “A” DETAIL “A” GAUGE PLANE 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 0.889 p 0.127 (.035 p .005) RECOMMENDED SOLDER PAD LAYOUT 0.305 p 0.038 (.0120 p .0015) TYP 0.50 (.0197) BSC BOTTOM VIEW OF EXPOSED PAD OPTION 2.845 p 0.102 (.112 p .004) 2.845 p 0.102 (.112 p .004) 4.039 p 0.102 (.159 p .004) (NOTE 3) 1.651 p 0.102 (.065 p .004) 1.651 p 0.102 (.065 p .004) 0.1016 p 0.0508 (.004 p .002) 3.00 p 0.102 (.118 p .004) (NOTE 4) 0.280 p 0.076 (.011 p .003) REF 4.90 p 0.152 (.193 p .006) DETAIL “B” DETAIL “B” CORNER TAIL IS PART OF THE LEADFRAME FEATURE. FOR REFERENCE ONL Y NO MEASUREMENT PURPOSE

0.12 REF

0.35 REF

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com © LINEAR TECHNOLOGY CORPORATION 2007 LT 1008 REV B • PRINTED IN USA TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS L T1766 60V , 1.2A (I OUT), 200kHz High Effi ciency Step-Down DC/DC Converter VIN: 5.5V to 60V , VOUT(MIN) = 1.20V , IQ = 2.5mA, ISD = 25μA, 16-Lead TSSOPE Package L T1933 36V , 500mA (I OUT), 500kHz Step-Down Switching Regulator in SOT-23 VIN: 3.6V to 36V , VOUT(MIN) = 1.2V , IQ = 1.6mA, ISD < 1μA, ThinSOT™ Package L T1936 36V , 1.4A (I OUT), 500kHz High Effi ciency Step-Down DC/DC Converter VIN: 3.6V to 36V , VOUT(MIN) = 1.2V , IQ = 1.9mA, ISD < 1μA, 8-Lead MS8E Package L T1940 Dual 25V , 1.4A (I OUT), 1.1MHz High Effi ciency Step-Down DC/DC Converter VIN: 3.6V to 25V , VOUT(MIN) = 1.20V , IQ = 3.8mA, ISD < 30μA, 16-Lead TSSOPE Package L TC3407/L TC3407-2 Dual 600mA/800mA, 1.5MHz/2.25MHz Synchronous Step-Down DC/DC Converter VIN: 2.5V to 5.5V , VOUT(MIN) = 0.6V , IQ = 40μA, ISD < 1μA, 3mm × 3mm DFN and 10-Lead MS10E Packages L T3434/L T3435 60V , 2.4A (I OUT), 200kHz/500kHz High Effi ciency Step-Down DC/DC Converters with Burst Mode Operation VIN: 3.3V to 60V , VOUT(MIN) = 1.20V , IQ = 100μA, ISD < 1μA, 16-Lead TSSOPE Package L T3437 60V , 400mA (I OUT), Micropower Step-Down DC/DC Converter with Burst Mode Operation VIN: 3.3V to 60V , VOUT(MIN) = 1.25V , IQ = 100μA, ISD < 1μA, 10-Lead 3mm × 3mm DFN, 16-Lead TSSOPE Package L T3493 36V , 1.4A (I OUT), 750kHz High Effi ciency Step-Down DC/DC Converter VIN: 3.6V to 36V , VOUT(MIN) = 0.8V , IQ = 1.9mA, ISD < 1μA, 6-Lead 2mm × 3mm DFN Package L T3501 Dual 25V , 3A (I OUT), 1.5MHz High Effi ciency Step-Down DC/DC Converter VIN: 3.3V to 25V , VOUT(MIN) = 0.8V , IQ = 3.7mA, ISD < 10μA, 20-Lead TSSOPE Package L T3502/L T3502A 40V , 500mA (I OUT), 1.1MHz/2.2MHz High Effi ciency Step-Down DC/DC Converter VIN: 3V to 40V , VOUT(MIN) = 0.8V , IQ = 1.5mA, ISD < 2μA, 8-Lead 2mm × 2mm DFN Package L T3503 20V , 1A (I OUT), 2.2MHz High Effi ciency Step-Down DC/DC Converter V IN: 3.6V to 20V , VOUT(MIN) = 0.78V , IQ = 1.9mA, ISD < 1μA, 6-Lead 2mm × 3mm DFN Package L T3505 36V , 1.2A (I OUT), 3MHz High Effi ciency Step-Down DC/DC Converter V IN: 3.6V to 36V , VOUT(MIN) = 0.78V , IQ = 2mA, ISD < 2μA, 8-Lead 3mm × 3mm DFN and MSE Packages L T3506/L T3506A Dual 25V , 1.6A (I OUT), 575kHz/1.1MHz High Effi ciency Step-Down DC/DC Converters VIN: 3.6V to 25V , VOUT(MIN) = 0.8V , IQ = 3.8mA, ISD < 30μA, 16-Lead 4mm × 5mm DFN and TSSOPE Packages L T3508 Dual 36V , 1.4A (I OUT), 2.5MHz High Effi ciency Step-Down DC/DC Converter VIN: 3.6V to 36V , VOUT(MIN) = 0.8V , IQ = 4.3mA, ISD < 1μA, 24-Lead 4mm × 4mm QFN and 16-Lead TSSOPE Packages L T3510 Dual 25V , 2A (I OUT), 1.5MHz High Effi ciency Step-Down DC/DC Converter VIN: 3.3V to 25V , VOUT(MIN) = 0.8V , IQ = 3.7mA, ISD < 10μA, 20-Lead TSSOPE Package L TC3548 Dual 400mA/800mA, 2.25MHz Synchronous Step-Down DC/DC Converter VIN: 2.5V to 5.5V , VOUT(MIN) = 0.6V , IQ = 40μA, ISD < 1μA, 3mm × 3mm DFN and 10-Lead MSE Packages L T3680 36V , 3.5A (I OUT), 2.4MHz High Effi ciency Step-Down DC/DC Converter VIN: 3.6V to 36V , VOUT(MIN) = 0.79V , IQ = 75μA, ISD < 1μA, 3mm × 3mm DFN and MS10E Packages ThinSOT is a trademark of Linear Technology Corporation 1.8V/2A Step-Down Regulator 2.2μH 2.2μF 0.47μF 0.47μF 22μF 220pF 40.2k 8.06k 49.9k 10k 24.9k 8.06k 4.5V TO 36V 1μF

3500 TA05

1.8V V OUT2 3.3V 10mA LDRVVIN LFB BST SHDN SS L T3500 RT/SYNC VC SW FB PG PG RELATED PARTS