LT3437 LINER | Alldatasheet
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, LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. *Protected by U.S. Patents including 6498466. **See Burst Mode Operation section for conditions. LOAD DUMP COLD CRANK VIN 20V/DIV VOUT 20mV/DIV AC COUPLED VIN
3437 TA03
■ High Voltage Power Conversion ■ 14V and 42V Automotive Systems ■ Industrial Power Systems ■ Distributed Power Systems ■ Battery-Powered Systems ■ Powered Ethernet ■ Wide Input Range: 3.3V to 60V ■ Load Dump (Input Transient) Protection to 80V ■ 500mA Peak Switch Current ■ Burst Mode Operation: 100µA Quiescent Current** ■ Low Shutdown Current: IQ < 1µA ■ Burst Mode Operation Defeat ■ 200kHz Switching Frequency ■ Saturating Switch Design: 0.8Ω On-Resistance ■ Peak Switch Current Maintained Over Full Duty Cycle Range* ■ 1.25V Feedback Reference Voltage ■ Easily Synchronizable ■ Soft-Start Capability ■ Small 10-Pin Thermally Enhanced DFN Package High Voltage 500mA, 200kHz Step-Down Switching Regulator with 100µA Quiescent Current The LT 3437 is a 200kHz monolithic buck switching regulator that accepts input voltages up to 80V. A high efficiency 500mA, 0.8Ω switch is included on the die along with all the necessary oscillator, control and logic cir- cuitry. Current mode topology is used for fast transient response and good loop stability. Innovative design techniques along with a new high volt- age process achieve high efficiency over a wide input range. Efficiency is maintained over a wide output current range by employing Burst Mode operation at low currents, utilizing the output to bias the internal circuitry, and by using a supply boost capacitor to fully saturate the power switch. Burst Mode operation can be defeated by a logic high signal on the SYNC pin which results in lower light load ripple at the expense of light load efficiency. Patented circuitry maintains peak switch current over the full duty cycle range.* Shutdown reduces input supply current to less than 1 µA. External synchronization can be imple- mented by driving the SYNC pin with logic-level inputs. A single capacitor from the C SS pin to the output provides a controlled output voltage ramp (soft-start). The LT3437 is available in a low profile (0.75mm) 3mm × 3mm 10-pin DFN package or a 16-Pin TSSOP Package both with exposed pad leadframes for low thermal resistance. VIN SHDN BOOST VBIAS LT3437 2.2µF 100V CER 330pF 0.1µF 0.1µF 100µH BAS21 SYNC GND 100µF 6.3V TANT VOUT 3.3V 400mA V IN 4.5V TO 80V* 10MQ100N 1500pF 25k 165k 100k
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*FOR INPUT VOLTAGES ABOVE 60V RESTRICTIONS APPLY 14V to 3.3V Step-Down Converter with 100µA No Load Quiescent Current Supply Current vs Input Voltage DESCRIPTIO UFEATURES APPLICATIO SU TYPICAL APPLICATIO U INPUT VOLTAGE (V) SUPPLY CURRENT (µA) 100 10 20 30 40
3435 TA02
Consult LTC Marketing for parts specified with wider operating temperature ranges. DD PART MARKING ORDER PART NUMBER FE PART MARKING Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ (Note 1) SYNC, C ABSOLUTE AXI U RATI GSW WW U PACKAGE/ORDER I FOR ATIOUU W ELECTRICAL CHARACTERISTICSThe ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25°C. VIN = 12V, SHDN = 12V, BIAS = 5V, FB = 1.25V, CSS/SYNC = 0V unless otherwise noted. θJA = 45°C/W, θJC(PAD) = 10°C/W EXPOSED PAD IS GND (PIN 11) MUST BE SOLDERED TO GND (PIN 4) TOP VIEW DD PACKAGE 10-LEAD (3mm × 3mm) PLASTIC DFN
1 SHDN
V C BIAS SW VIN BST GND CSS Operating Junction Temperature Range FE PACKAGE 16-LEAD PLASTIC TSSOP TOP VIEW NC SW NC V IN NC BOOST NC GND NC SHDN SYNC NC FB V C BIAS C SS θJA = 45°C/W, θJC(PAD) = 10°C/W EXPOSED PAD IS GND (PIN 17) MUST BE SOLDERED TO GND (PIN 8) 3437EFE 3437IFE LBDJ LBDK SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VSHDN SHDN Threshold ● 1.15 1.3 1.45 V ISHDN SHDN Input Current SHDN = 12V ● 53 0 µA Minimum Input Voltage (Note 3) ● 2.5 3 V IVINS Supply Shutdown Current SHDN = 0V, BOOST = 0V, FB/PGFB = 0V 0.1 2 µA Supply Sleep Current (Note 4) BIAS = 0V, FB = 1.35V ● 300 500 µA FB = 1.35V ● 25 50 µA IVIN Supply Quiescent Current BIAS = 0V, FB = 1.15V, V C = 0.8V, SYNC = 2V 1.35 2 mA BIAS = 5V, FB = 1.15V, VC = 0.8V, SYNC = 2V 0.475 1 mA Minimum BIAS Voltage (Note 5) 2.7 3.15 V
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT3437EDD/LT3437EFE are guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40 °C to 125 °C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3437IDD/LT3437IFE are guaranteed and tested over the full –40 °C to 125°C operating junction temperature range. Note 3: Minimum input voltage is defined as the voltage where switching starts. Actual minimum input voltage to maintain a regulated output will depend upon output voltage and load current. See Applications Information. Note 4: Supply input current is the quiescent current drawn by the input pin. Its typical value depends on the voltage on the BIAS pin and operating state of the LT3437. With the BIAS pin at 0V, all of the quiescent current required to operate the LT3437 will be provided by the VIN pin. With the BIAS voltage above its minimum input voltage, a portion of the total quiescent current will be supplied by the BIAS pin. Supply sleep current is defined as the quiescent current during the “sleep” portion of Burst Mode operation. See Applications Information for determining application supply currents. Note 5: Minimum BIAS voltage is the voltage on the BIAS pin when I BIAS is sourced into the pin. Note 6: This is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch. Note 7: Boost current is the current flowing into the BOOST pin with the pin held 3.3V above input voltage. It flows only during switch on time. Note 8: Gain is measured with a V C swing from 1.15V to 750mV. Note 9: Switch saturation voltage guaranteed by correlation to wafer level measurements for DD package parts. Note 10: The CSS threshold is defined as the value of current sourced into the CSS pin which results in an increase in sink current from the VC pin. See the Soft-Start section in Applications Information. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IBIASS BIAS Sleep Current (Note 4) ● 150 250 µA IBIAS BIAS Quiescent Current SYNC = 2V 0.75 1 mA Minimum Boost Voltage (Note 6) I SW = 250mA 1.8 2.5 V Input Boost Current (Note 7) I SW = 0.5A 11 16 mA ISW = 0.25A 8 13 mA VREF Reference Voltage (VREF) 3.3V < V VIN < 80V ● 1.225 1.25 1.275 V IFB FB Input Bias Current 50 200 nA EA Voltage Gain (Note 8) 900 V/V EA Voltage gm dI(VC)= ±10µA 650 µMho EA Source Current FB = 1.15V 15 35 55 µA EA Sink Current FB = 1.35V 15 30 55 µA VC to SW gm 1A / V VC Switching Threshold V SYNC = 2V 500 mV VC High Clamp 1.5 1.75 2.1 V IPK SW Current Limit ● 500 650 900 mA SW VCESAT Switch Saturation Voltage I SW = 250mA ● 200 400 mV (Note 9) I SW = 500mA ● 400 800 mV Switching Frequency ● 170 200 240 kHz Maximum Duty Cycle 95 % Minimum SYNC Amplitude 1.5 2 V SYNC Frequency Range 240 700 kHz SYNC Input Impedance 50 k Ω ICSS CSS Current Threshold (Note 10) FB = 0V 4 10 16 µA The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25°C. VIN = 12V, SHDN = 12V, BIAS = 5V, FB = 1.25V, CSS/SYNC = 0V unless otherwise noted.
ELECTRICAL CHARACTERISTICS
IBIAS (µA)
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TEMPERATURE (°C) –50 0 50 75–25 25 100 125 RUN MODE SLEEP MODE
1.20 FB VOLTAGE (V)
1.24 1.30 1.22 1.28 1.26 TEMPERATURE (°C) –50 0 50 75
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–25 25 100 125 TEMPERATURE (°C) –50
150 FREQUENCY (kHz)
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–25 25 100 125 VOLTAGE (V) 1.35
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1.20 1.10 1.40 1.45 1.50 1.30 1.25 1.15 TEMPERATURE (°C) –50 0 50 75–25 25 100 125 VSHDN (V) ISHDN (µA) 10 20 30 40
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CURRENT (µA)
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5 TEMPERATURE (°C)
–50 0 50 75–25 25 100 125 VVIN = 12V VVIN = 60V VVIN = 80V IVIN (µA)
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TEMPERATURE (°C) –50 0 50 75–25 25 100 125 RUN MODE SLEEP MODE VBIAS = 0V SLEEP MODE VBIAS = 5V TEMPERATURE (°C) –50 PEAK SWITCH CURRENT (mA) 200 100 300 400 500 600 700 800 –25 –0 25 50
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TYPICAL PERFOR A CE CHARACTERISTICS UW FB Voltage vs Temperature Oscillator Frequency vs Temperature SHDN Threshold SHDN Pin Current Shutdown Supply Current vs Temperature Input Current vs Temperature Bias Current vs Temperature Switch Peak Current Limit vs Temperature Efficiency and Power Loss vs Load Current LOAD CURRENT (mA) 0.1 EFFICIENCY (%) 100 100
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POWER LOSS (mW)EFFICIENCY POWER LOSS VIN = 12V VOUT = 3.3V TA = 25°C
ON-TIME (ns)
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TEMPERATURE (°C) –50 0 50 75–25 25 100 125 Supply Current vs Input Voltage Burst Mode Threshold vs Input Voltage Oscillator Frequency vs FB Voltage Switch On Voltage (V CESAT) LOAD CURRENT (mA) VOLTAGE (mV)200 600 500 200 400 500
3437 G12
TJ = 125°C TJ = –40°C TJ = 25°C TYPICAL PERFOR A CE CHARACTERISTICS UW Minimum Input Voltage FB VOLTAGE (V) FREQUENCY (kHz) 100 150 0.25 0.50 0.75
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1.00 200 250 1.25 INPUT VOLTAGE (V) SUPPLY CURRENT (µA) 100 10 20 30 40
3437 F13
VOUT = 3.3V LOAD CURRENT (mA) 3.0 INPUT VOLTAGE (V) 3.5 4.5 5.0 5.5 400 7.5
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4.0 200100 300 500 6.0 6.5 7.0 5V TO RUN 5V TO START 3.3V TO RUN 3.3V TO START INPUT VOLTAGE (V) LOAD CURRENT (mA) 200 20 40 50
3437 G15
VOUT = 3.3V Minimum On-Time Boost Current vs Load Current LOAD CURRENT (mA) 100 BOOST CURRENT (mA) 200 400
3437 G17
INPUT VOLTAGE (V) 2.0 3.0 OUTPUT VOLTAGE (V) 0.5 1.5 2.0 2.5 4.0 4.0
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1.0 3.02.5 3.5 4.5 3.5 VOUT = 3.3V ILOAD = 250mA BOOST DIODE = DIODES INC B1100 FB VOLTAGE (V) ICSS (µA) 0.2 0.4 0.6 0.8
3437 G10
1.0 1.2 SOFT-START DEFEATED Soft-Start Current Threshold vs FB Voltage
TYPICAL PERFOR A CE CHARACTERISTICS UW Burst Mode Operation Burst Mode Defeated VOUT 20mV/DIV AC COUPLED ISW 100mA/DIV VIN = 12V 10 µs/DIV 3437 G23 VOUT = 3.3V IQ = 100µA VOUT 20mV/DIV AC COUPLED ISW 100mA/DIV 10µs/DIV 3437 G24 Step Response Step Response VOUT 50mV/DIV IOUT 100mA/DIV 1ms/DIV 3437 G25 LOAD STEP 0mA TO 200mA VOUT 50mV/DIV IOUT 100mA/DIV 1ms/DIV 3437 G26 LOAD STEP 100mA TO 300mA Maximum Duty Cycle vs Temperature MAXIMUM DUTY CYCLE (%)
3437 G20
94.0 91.5 94.5 93.0 93.5 92.0 92.5 TEMPERATURE (°C) –50 0 50 75–25 25 100 125 ILOAD = 250mA VC Switching Threshold vs Temperature Maximum Sync Frequency vs Temperature VC VOLTAGE (V)
3437 G21
0.5 0.6 0.3 0.4 0.1 0.2 TEMPERATURE (°C) –50 0 50 75–25 25 100 125 MAXIMUM SYNC FREQUENCY (kHz)
3437 G22
TEMPERATURE (°C) –50 0 50 75–25 25 100 125 VIN = 12V VOUT = 3.3V IOUT = 100mA Dropout Operation INPUT VOLTAGE (V) 2.0 OUTPUT VOLTAGE (V) 4.0
3437 G19
VOUT = 5V ILOAD = 250mA BOOST DIODE = DIODES INC B1100 VIN = 12V VOUT = 3.3V IQ = 1.7mA VSYNC = 3.3V
BIAS (Pin 6/Pin 10): The BIAS pin is used to improve efficiency when operating at higher input voltages and light load current. Connecting this pin to the regulated output voltage forces most of the internal circuitry to draw its operating current from the output voltage rather than the input supply. This architecture increases efficiency especially when the input voltage is much higher than the output. Minimum output voltage setting for this mode of operation is typically 3V. VC (Pin 7/Pin 11): The VC pin is the output of the error amplifier and the input of the peak switch current com- parator. It is normally used for frequency compensation, but can also serve as a current clamp or control loop override. VC sits at about 0.45V for light loads and 1.5V at maximum load. During the sleep portion of Burst Mode operation, the V C pin is held at a voltage slightly below the burst threshold for better transient response. Driving the V C pin to ground will disable switching and place the IC into sleep mode. FB (Pin 8/Pin 12): The feedback pin is used to determine the output voltage using an external voltage divider from the output that generates 1.25V at the FB pin. When the FB pin drops below 0.9V, switching frequency is reduced, the SYNC function is disabled and output ramp rate control is enabled via the C SS pin. See the Feedback section in Applications Information for details. SYNC (Pin 9/Pin 14): The SYNC pin is used to synchronize the internal oscillator to an external signal. It is directly logic compatible and can be driven with any signal be- tween 25% and 75% duty cycle. The synchronizing range is equal to maximum initial operating frequency up to 700kHz. When the voltage on the FB pin is below 0.9V the SYNC function is disabled. When a synchronization signal or logic-level high is present at the SYNC pin, Burst Mode operation is disabled. See the synchronizing section in Applications Information for details. SHDN (Pin 10/Pin 15): The SHDN pin is used to turn off the regulator and to reduce input current to less than 1µA. The SHDN pin requires a voltage above 1.3V with a typical source current of 5µA to take the IC out of the shutdown state. Exposed Pad (Pin 11/Pin 17): Ground. Must be soldered to the PCB. UUUPI FU CTIO S SW (Pin 1/Pin 2): The SW pin is the emitter of the on-chip power NPN switch. This pin is driven up to the input pin voltage during switch on time. Inductor current drives the SW pin negative during switch off time. Negative voltage is clamped with the external catch diode. Maximum nega- tive switch voltage allowed is –0.8V. NC (Pins 1, 3, 5, 7, 13, 16)(FE Package ONLY): No Connection. V IN (Pin 2/Pin 4): This is the collector of the on-chip power NPN switch. VIN powers the internal control circuitry when a voltage on the BIAS pin is not present. High di/dt edges occur on this pin during switch turn on and off. Keep the path short from the V IN pin through the input bypass capacitor, through the catch diode back to SW. All trace inductance on this path will create a voltage spike at switch off, adding to the V CE voltage across the internal NPN. BOOST (Pin 3/Pin 6): The BOOST pin is used to provide a drive voltage, higher than the input voltage, to the internal bipolar NPN power switch. Without this added voltage, the typical switch voltage loss would be about 1.5V. The additional BOOST voltage allows the switch to saturate and its voltage loss approximates that of a 0.8 Ω FET structure. GND (Pins 4, 11/ Pins 8, 17): The GND pin connection acts as the reference for the regulated output, so load regulation will suffer if the “ground” end of the load is not at the same voltage as the GND pin of the IC. This condition will occur when load current or other currents flow through metal paths between the GND pin and the load ground. Keep the path between the GND pin and the load ground short and use a ground plane when possible. The GND pin also acts as a heat sink and should be soldered (along with the exposed leadframe) to the cop- per ground plane to reduce thermal resistance (see Appli- cations Information). CSS (Pin 5/Pin 9): A capacitor from the C SS pin to the regulated output voltage determines the output voltage ramp rate during start-up. When the current through the CSS capacitor exceeds the CSS threshold (ICSS), the volt- age ramp of the output is limited. The C SS threshold is proportional to the FB voltage (see Typical Performance Characteristics) and is defeated for FB voltage greater than 0.9V (typical). See Soft-Start section in Applications Infor- mation for details. (DD/FE)
response and line rejection. output voltage). This improves efficiency. than the input voltage, allowing the switch to be saturated. supply current to 25µA and bias input current to 150µA. by driving the SYNC pin with logic-level inputs. Figure 1. LT3437 Block Diagram
voltage and provide several overload protection features. both parts before committing to a final design.
- –. SOFT-START FOLDBACK DETECT 200kHz OSCILLATOR ERROR AMP 1.25V VC FB 8 CSS VOUT SW LT3437
3437 F02
Figure 2. Feedback Network operation during normal load conditions.
cause the input voltage to swing above the DC level of input power source and it may exceed the maximum voltage rating of the input capacitor and LT3437. All input voltage transient sequences should be observed at the V IN pin of the LT3437 to ensure that absolute maximum voltage ratings are not violated. The easiest way to suppress input voltage transients is to add a small aluminum electrolytic capacitor in parallel with the low ESR input capacitor. The selected capacitor needs to have the right amount of ESR to critically damp the resonant circuit formed by the input lead inductance and the input capacitor. The typical values of ESR will fall in the range of 0.5Ω to 2Ω and capacitance will fall in the range of 5µF to 50µF. If tantalum capacitors are used, values in the 22 µF to 470µF range are generally needed to minimize ESR and meet ripple current and surge ratings. Care should be taken to ensure the ripple and surge ratings are not exceeded. The AVX TPS and Kemet T495 series are surge rated. AVX recommends derating capacitor operating voltage by 2:1 for high surge applications. OUTPUT CAPACITOR The output capacitor is normally chosen by its effective series resistance (ESR) because this is what determines output ripple voltage. To get low ESR takes volume, so physically smaller capacitors have higher ESR. The ESR range for typical LT3437 applications is 0.05Ω to 0.2Ω. A typical output capacitor is an AVX type TPS, 100µF at 10V, with a guaranteed ESR less than 0.1Ω. This is a “D” size surface mount solid tantalum capacitor. TPS capacitors are specially constructed and tested for low ESR, so they give the lowest ESR for a given volume. The value in microfarads is not particularly critical, and values from 22µF to greater than 500 µF work well, but you cannot cheat Mother Nature on ESR. If you find a tiny 22µF solid tantalum capacitor, it will have high ESR and output ripple voltage could be unacceptable. Table 2 shows some typical solid tantalum surface mount capacitors. function reduces input current surge by regulating switch current via the V C pin to maintain a constant voltage ramp rate (dV/dt) at the output. A capacitor (C1 in Figure 2) from the C SS pin to the output determines the maximum output dV/dt. When the feedback voltage is below 0.4V, the VC pin will rise, resulting in an increase in switch current and output voltage. If the dV/dt of the output causes the current through the C SS capacitor to exceed ICSS, the VC voltage is reduced resulting in a constant dV/dt at the output. As the feedback voltage increases, I CSS increases, resulting in an increased dV/dt until the soft-start function is defeated with 0.9V present at the FB pin. The soft-start function does not affect operation during normal load conditions. However, if a momentary short (brown out condition) is present at the output which causes the FB voltage to drop below 0.9V, the soft-start circuitry will become active. INPUT CAPACITOR Step-down regulators draw current from the input supply in pulses. The rise and fall times of these pulses are very fast. The input capacitor is required to reduce the voltage ripple this causes at the input of LT3437 and force the switching current into a tight local loop, thereby minimiz- ing EMI. The RMS ripple current can be calculated from: I I V VV VRIPPLE RMS OUT IN OUT IN OUT() –= () Ceramic capacitors are ideal for input bypassing. At 200kHz switching frequency input capacitor values in the range of 2.2µF to 10µF are suitable for most applications. If opera- tion is required close to the minimum input required by the LT3437, a larger value may be required. This is to prevent excessive ripple causing dips below the minimum operat- ing voltage resulting in erratic operation. Input voltage transients caused by input voltage steps, or by hot plugging the LT3437 to a pre-powered source such as a wall adapter, can exceed maximum V IN ratings. The sudden application of input voltage will cause a large surge of current in the input leads that will store energy in the parasitic inductance of the leads. This energy will APPLICATIO S I FOR ATIOWU UU
to be small compared to ESR or ESL. Table 2. Surface Mount Solid Tantalum Capacitor ESR are prone to failure if they undergo high surge currents. dead shorted, do not harm the capacitors.
Figure 3. LT3437 Ripple Voltage Waveform
current in the inductor, saturation and of course cost.
- Choose a value in microhenries such that the maximum
designed to work well in either mode. switch current overload condition.
- Calculate peak inductor current at full load current to
saturate softly, whereas ferrite cores saturate abruptly. tinuous mode, so it can be used for all conditions.
- Decide if the design can tolerate an “open” core geom-
when the magnetic field radiation will be a problem.
- After making an initial choice, consider the secondary
things like output voltage ripple, second sourcing, etc. department if you feel uncertain about the final choice. low profile, surface mounting, etc. Table 3. Inductor Selection Criteria then determined by the switch current limit.
voltage drop, the potential exists for a loss of control.
- •≤ + where: f = switching frequency tON = switch on time VF = diode forward voltage VIN = Input voltage I • R = inductor I • R voltage drop If this condition is not observed, the current will not be limited at IPK but will cycle-by-cycle ratchet up to some higher value. Using the nominal LT3437 clock frequency of 200kHz, a VIN of 40V and a (VF + I • R) of say 0.7V, the maximum tON to maintain control would be approximately 90ns, an unacceptably short time. The solution to this dilemma is to slow down the oscillator to allow the current in the inductor to drop to a sufficiently low value such that the current does not continue to ratchet higher. When the FB pin voltage is abnormally low, thereby indicating some sort of short-circuit condition, the oscillator frequency will be reduced. Oscillator fre- quency is reduced by a factor of 10 when the FB pin voltage is below 0.4V and increases linearly to its typical value of 200kHz at a FB voltage of 0.95V (see Typical Performance Characteristics). These oscillator frequency reductions during short-circuit conditions allow the LT3437 to main- tain current control SOFT-START For applications where [V IN/(VOUT + VF)] >10 or large input surge currents cannot be tolerated, the LT3437 soft-start feature should be used to control the output capacitor charge rate during start-up, or during recovery from an output short circuit, thereby adding additional control over peak inductor current. The soft-start function limits the switch current via the V C pin to maintain a constant voltage ramp rate (dV/dt) at the output capacitor. A capaci- tor (C1 in Figure 2) from the CSS pin to the regulated output voltage determines the output voltage ramp rate. When the current through the C SS capacitor exceeds the C SS threshold (ICSS), the voltage ramp of the output capacitor is limited by reducing the VC pin voltage. The CSS threshold is proportional to the FB voltage (see Typical Performance Characteristics) and is defeated for FB voltages greater than 0.9V (typical). The output dV/dt can be approximated by: dV dt I C CSS SS but actual values will vary due to start-up load conditions, compensation values and output capacitor selection. VOUT 1V/DIV VIN = 12V 1ms/DIV 3437 F04 COUT = 100µF ILOAD = 200mA
Figure 4. VOUT dV/dt
be reduced at the expense of light load efficiency. and even 100V, and are price competitive with other types. Figure 5. IQ vs VIN
3435 F05
series with the BOOST diode (Figure 6a option). discharge ripple and improve start-up operation. pin has an internal sink current with a typical value of 5µA.
3437 F06
Figure 6. BOOST Pin Configurations
graphs of SHDN and VIN currents verses input voltage. short-circuit conditions), the sync function is disabled. hazardous conditions for the SW pin. present at the SYNC pin, Burst Mode operation is disabled. this pin should be connected to ground. is implemented in the suggested layouts of Figure 9.
3437 F07
Figure 7. Undervoltage Lockout
reduce any additional heating effects. not be used for calculating efficiency at light load currents. Figure 9. Suggested Layouts Figure 8. High Speed Switching Path
3437 F08
3437 F09b
3437 F09a
APPLICATIO S I FOR ATIOWU UU (tr + tf + tIR + tIF) tr = (VIN/0.6)ns tf = (VIN/2)ns tIR = tIF = (IOUT/0.05)ns f = switch frequency Example: with VIN = 40V, VOUT = 5V and IOUT = 250mA: Pe W PW PW SW BOOST Q = () () = = () + () = 1 0 25 5 40 92 12 0 25 40 200 3 0 008 0 092 0 1 50 2 5 3 0 40 0 005 40 0 0005 5 0 0008 0 024 . /. ... ./ . .. . Total power dissipation is: PTOT = 0.1 + 0.065 + 0.024 = 0.13W Thermal resistance for the LT3437 package is influenced by the presence of internal or backside planes. With a full plane under the package, thermal resistance will be about 45°C for the FE and DD packages. No plane will increase resistance to about 150°C/W. To calculate die temperature, use the proper thermal resistance number for the desired package and add in worst-case ambient temperature: T J = TA + QJA (PTOT) With the DD package (Q JA = 45 °C/W) at an ambient temperature of 70°C: Input Voltage vs Operating Frequency Considerations The absolute maximum input supply voltage for the LT3437 is specified at 80V. This is based solely on internal semi- conductor junction breakdown effects. Due to internal power dissipation, the actual maximum V IN achievable in a particular application may be less than this. A detailed theoretical basis for estimating internal power loss is given in the section Thermal Considerations. Note that AC switching loss is proportional to both operating frequency and output current. The majority of AC switch- ing loss is also proportional to the square of input voltage. For example, while the combination of V IN = 40V, VOUT = 5V at 700mA and fOSC = 200kHz may be easily achievable, simultaneously raising VIN to 80V and fOSC to 700kHz is not possible. Nevertheless, input voltage transients up to 80V can usually be accommodated, assuming the resulting increase in internal dissipation is of insufficient time dura- tion to raise die temperature significantly. A second consideration is controllability. A potential limi- tation occurs with a high step-down ratio of V IN to VOUT, as this requires a correspondingly narrow minimum switch on time. An approximate expression for this (assuming continuous mode operation) is given as follows: tON(MIN) = (VOUT + VF)/VIN(fOSC) where: VIN = input voltage VOUT = output voltage VF = Schottky diode forward drop fOSC = switching frequency A potential controllability problem arises if the LT3437 is called upon to produce an on time shorter than it is able to produce. Feedback loop action will lower, then reduce, the V C control voltage to the point where some sort of cycle- skipping or Burst Mode behavior is exhibited. In summary: 1. Be aware that the simultaneous requirements of high V IN, high IOUT and high fOSC may not be achievable in practice due to internal dissipation. The Thermal Con- siderations section offers a basis to estimate internal power. In questionable cases, a prototype supply should be built and exercised to verify acceptable operation. 2. The simultaneous requirements of high VIN, low VOUT and high fOSC can result in an unacceptably short mini- mum switch on time. Cycle skipping and/or Burst Mode behavior will result causing an increase in output volt- age ripple while maintaining the correct output voltage.
APPLICATIO S I FOR ATIOWU UU FREQUENCY COMPENSATION Before starting on the theoretical analysis of frequency response, the following should be remembered—the worse the board layout, the more difficult the circuit will be to stabilize. This is true of almost all high frequency analog circuits. Read the Layout Considerations section first. Common layout errors that appear as stability problems are distant placement of input decoupling capacitor and/or catch diode, and connecting the V C compensation to a ground track carrying significant switch current. In addi- tion, the theoretical analysis considers only first order non-ideal component behavior. For these reasons, it is important that a final stability check is made with produc- tion layout and components. The LT3437 uses current mode control. This alleviates many of the phase shift problems associated with the inductor. The basic regulator loop is shown in Figure 10. The LT3437 can be considered as two g m blocks, the error amplifier and the power stage. Figure 11 shows the overall loop response. At the VC pin, the frequency compensation components used are: R C = 25k, C C = 1500pF and C F = 330pF. The output capacitor used is a 100µF, 10V tantalum capacitor with typical ESR of 100mΩ. The ESR of the tantalum output capacitor provides a useful zero in the loop frequency response for maintaining stabil- ity. This ESR, however, contributes significantly to the ripple voltage at the output (see Output Ripple Voltage in the Applications Information section). It is possible to reduce capacitor size and output ripple voltage by replac- ing the tantalum output capacitor with a ceramic output capacitor because of its very low ESR. The zero provided by the tantalum output capacitor must now be reinserted back into the loop. Alternatively, there may be cases where, even with the tantalum output capacitor, an addi- tional zero is required in the loop to increase phase margin for improved transient response. A zero can be added into the loop by placing a resistor (R at the VC pin in series with the compensation capacitor, CC, or by placing a capacitor (CFB) between the output and the FB pin. When using RC, the maximum value has two limitations. First, the combination of output capacitor ESR and RC may stop the loop rolling off altogether. Second, if the loop gain is not rolled off sufficiently at the switching frequency, output ripple will perturb the V C pin enough to cause unstable duty cycle switching, similar to subharmonic oscillations. If needed, an additional capacitor (CF) can be added across the RC/CC network from the VC pin to ground to further suppress VC ripple voltage. With a tantalum output capacitor, the LT3437 already includes a resistor (RC) and filter capacitor (CF) at the VC pin (see Figures 10 and 11) to compensate the loop over the entire VIN range (to allow for stable pulse skipping for high VIN-to-VOUT ratios ≥ 10). A ceramic output capacitor can still be used with a simple adjustment to the resistor RC for stable operation (see Ceramic Capacitors section for stabilizing LT3430). If additional phase margin is required, a capacitor (C FB) can be inserted between the output and FB pin, but care must be taken for high output voltage applications. Sudden shorts to the output can create unacceptably large negative transients on the FB pin. For V IN-to-VOUT ratios < 10, higher loop bandwidths are possible by readjusting the frequency compensation com- ponents at the VC pin. When checking loop stability, the circuit should be oper- ated over the application’s full voltage, current and tem- perature range. Proper loop compensation may be obtained by empirical methods, as described in Application Notes 19 and 76.
Figure 10. Model for Loop Response Figure 11. Overall Loop Response
3437 F12
10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699) 3.00 ±0.10 (4 SIDES) NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.38 ± 0.10 BOTTOM VIEW—EXPOSED PAD 1.65 ± 0.10 (2 SIDES) 0.75 ±0.05 R = 0.115 TYP 2.38 ±0.10 (2 SIDES) 106 PIN 1 TOP MARK (SEE NOTE 6)
0.200 REF
0.00 – 0.05 (DD10) DFN 1103 0.25 ± 0.05 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 1.65 ±0.05 (2 SIDES)2.15 ±0.05 0.50 BSC 0.675 ±0.05 3.50 ±0.05 PACKAGE OUTLINE 0.25 ± 0.05
0.50 BSC
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. FE16 (BC) TSSOP 0204 0.09 – 0.20 (.0035 – .0079) 0° – 8° 0.25 REF 0.50 – 0.75 (.020 – .030) 4.30 – 4.50* (.169 – .177) 13 4 5 6 7 8 10 9 4.90 – 5.10* (.193 – .201) 16 1514 13 12 11 1.10 (.0433) MAX 0.05 – 0.15 (.002 – .006) 0.65 (.0256) BSC 2.94 (.116) 0.195 – 0.30 (.0077 – .0118) TYP 2RECOMMENDED SOLDER PAD LAYOUT 0.45 ±0.05
0.65 BSC
4.50 ±0.10 6.60 ±0.10 1.05 ±0.10 2.94 (.116) 3.58 (.141) 3.58 (.141) MILLIMETERS (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE SEE NOTE 4 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT 6.40 (.252) BSC 16-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation BC
Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORA TION 2005 LT/TP 0605 500 PRINTED IN USA RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1765 25V, 3A (I OUT), 1.25MHz, High Efficiency Step-Down DC/DC V IN: 3V to 25V, VOUT(MIN) = 1.20V, IQ = 1mA, ISD < 15µA, Converter SO-8, TSSOP16E LT1766 60V, 1.2A (I OUT), 200kHz, High Efficiency Step-Down DC/DC V IN: 5.5V to 60V, VOUT(MIN) = 1.20V, IQ = 2.5mA, Converter I SD < 25µA, TSSOP16/E LT1767 25V, 1.5A (I OUT), 1.25MHz, High Efficiency Step-Down DC/DC V IN: 3V to 25V, VOUT(MIN) = 1.20V, IQ = 1mA, ISD < 6µA, Converter MS8/E LT1776 40V, 550mA (I OUT), 200kHz, High Efficiency Step-Down DC/DC V IN: 7.4V to 40V, VOUT(MIN) = 1.24V, IQ = 3.2mA, Converter I SD < 30µA, N8, S8 LT1936 36V, 1.4A, 500kHz, High Efficiency Step-Down DC/DC Converter V IN: 3.6V to 36V, VOUT(MIN) = 1.2V, IQ = 1.8mA, ISD 4mA MS8/E LT1940 Dual 1.2A (I OUT), 1.1MHz, High Efficiency Step-Down DC/DC V IN: 3V to 25V, VOUT(MIN) = 1.2V, IQ = 3.8mA, TSSOP-16E Converter LT1956 60V, 1.2A (I OUT), 500kHz, High Efficiency Step-Down DC/DC V IN: 5.5V to 60V, VOUT(MIN) = 1.20V, IQ = 2.5mA, Converter I SD < 25µA, TSSOP16/E LT1976 60V, 1.5A (I OUT), 200kHz, High Efficiency Step-Down DC/DC V IN: 3.3V to 60V, IQ = 100µA, ISD < 1µA, TSSOP-16E Converter LT1977 60V, 1.5A (I OUT), 500kHz, High Efficiency Step-Down DC/DC V IN: 3.3V to 60V, IQ = 100µA, ISD < 1µA, TSSOP-16E Converter LT3010 80V, 50mA, Low Noise Linear Regulator V IN: 1.5V to 80V, VOUT(MIN) = 1.28V, IQ = 30µA, ISD < 1µA, MS8E LT3430 60V, 2.5A (I OUT), 200kHz, High Efficiency Step-Down DC/DC V IN: 5.5V to 60V, VOUT(MIN) = 1.20V, IQ = 2.5mA, Converter I SD < 30µA, TSSOP-16E LT3431 60V, 2.5A (I OUT), 500kHz, High Efficiency Step-Down DC/DC V IN: 5.5V to 60V, VOUT(MIN) = 1.20V, IQ = 2.5mA, Converter I SD < 30µA, TSSOP-16E LT3433 60V, 400mA (I OUT), 200kHz/500kHz, Buck-Boost DC/DC Converter V IN: 5V to 60V, VOUT: 3.3V to 20V, IQ = 100µA, TSSOP-16E LT3434/LT3435 60V, 3A (I OUT), 200kHz, High Efficiency Step-Down DC/DC Converter V IN: 3.3V to 60V, IQ = 100µA, ISD < 1µA, TSSOP-16E LT3470 40V, 300mA, MicroPower Buck Regulator with Integrated Boost and V IN: 4V to 40V, VOUT(MIN) = 1.25V, IQ = 26µA, ThinSOT Catch Diodes LTC3727/LTC3727-1 36V, 500kHz, High Efficiency Step-Down DC/DC Controllers V IN: 4V to 36V, VOUT(MIN) = 0.8V, IQ = 670µA, ISD < 20µA, QFN-32, SSOP-28 14V to 3.3V Step-Down Converter with 100µA No Load Quiescent Current Supply Current vs Input Voltage INPUT VOLTAGE (V) SUPPLY CURRENT (µA) 100 10 20 30 40
3435 TA05
8060 70TYPICAL APPLICATIO U LOAD CURRENT (mA) 0.1 EFFICIENCY (%) 100 100 POWER LOSS (mW)EFFICIENCY POWER LOSS VIN = 12V VOUT = 3.3V TA = 25°C Efficiency and Power Loss vs Load Current VIN SHDN BOOST LT3437 2.2µF 100V CER 330pF 0.1µF 0.1µF 100µH BAS21 SYNC GND 100µF 6.3V TANT VOUT 3.3V 400mAVIN 4.5V TO 80V* 10MQ100N 1500pF 25k 165k 100k
3437 TA04
*FOR INPUT VOLTAGES ABOVE 60V SOME RESTRICTIONS MAY APPLY VBIAS