LT3430

LT3430-1 LINER | Alldatasheet

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FEATURES

APPLICATIONS

DESCRIPTION

High Voltage, 3A, 200kHz/100kHz Step-Down Switching Regulators The LT®3430/LT3430-1 are monolithic buck switching regulators that accept input voltages up to 60V. A high ef- fi ciency 3A, 0.1Ω switch is included on the die along with all the necessary oscillator, control and logic circuitry. A current mode architecture provides fast transient response and excellent loop stability. Special design techniques and a new high voltage process achieve high effi ciency over a wide input range. Effi ciency is maintained over a wide output current range by using the output to bias the circuitry and by utilizing a supply boost capacitor to saturate the power switch. Patented circuitry* maintains peak switch current over the full duty cycle range. A shutdown pin reduces supply current to 30µA and a SYNC pin can be externally synchronized with a logic level input from 228kHz to 700kHz for the LT3430 or from 125kHz to 250kHz for the LT3430-1. The LT3430/LT3430-1 are available in a thermally enhanced 16-pin TSSOP package. 5V, 2A Buck Converter ■ Wide Input Range: 5.5V to 60V ■ 3A Peak Switch Current over All Duty Cycles ■ Constant Switching Frequency: 200kHz (LT3430) 100kHz (LT3430-1) ■ 0.1 Ω Switch Resistance ■ Current Mode ■ Effective Supply Current: 2.5mA ■ Shutdown Current: 30µA ■ 1.2V Feedback Reference Voltage ■ Easily Synchronizable ■ Cycle-by-Cycle Current Limiting ■ Small, 16-Pin Thermally Enhanced TSSOP Package ■ Industrial and Automotive Power Supplies ■ Portable Computers ■ Battery Chargers ■ Distributed Power Systems , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. *US Patent # 6498466 Effi ciency vs Load Current BOOST VIN 30BQ060 15.4k VOUT 220pF 0.022µF *FOR INPUT VOLTAGES BELOW 7.5V, SOME RESTRICTIONS MAY APPLY SEE LT3430-1 CIRCUIT IN APPLICATIONS INFORMATION SECTION LT3430 SHDN SYNC SW BIAS FB VCGND 0.68µF 100µF 10V SOLID TANTALUM 22µH MMSD914TI 4.99k

3430 TA01

4.7µF 100V ONOFF VIN 5.5V* TO 60V 3.3k LOAD CURRENT (A) EFFICIENCY (%) 100 2.0

3430 TA02

0.5 1.0 1.5 2.5 VIN = 12V VIN = 42V VOUT = 5V LT3430-1 L = 68µH LT3430 L =27µH

ELECTRICAL CHARACTERISTICS

Operating Junction Temperature Range (Note 1) PARAMETER CONDITIONS MIN TYP MAX UNITS Reference Voltage (VREF)V OL + 0.2 ≤ VC ≤ VOH – 0.2 5.5V ≤ VIN ≤ 60V ● 1.204 1.195 1.219 1.234 1.243 V FB Input Bias Current ● –0.2 –1.5 µA Error Amp Voltage Gain (Note 2) 200 400 V/V Error Amp gm dl (VC) = ±10µA 1650 1000 2200 3300 4200 µMho µMho V C to Switch gm 3.4 A/V EA Source Current FB = 1V ● 125 225 450 µA EA Sink Current FB = 1.4V ● 100 225 500 µA VC Switching Threshold Duty Cycle = 0 0.9 V VC High Clamp ⎯S⎯H⎯D⎯N = 1V 2.1 V Switch Current Limit V C Open, Boost = VIN + 5V, FB = 1V –40°C ≤ TJ ≤ 25°C TJ = 125°C (Note 9) 2.5 6.5 5.5 A A Switch On Resistance I SW = 2.5A, Boost = VIN + 5V (Note 7) 0.1 0.14 0.18 Ω Ω Maximum Switch Duty Cycle (LT3430) FB = 1V 96 % FE PACKAGE 16-LEAD PLASTIC TSSOP TOP VIEW GND SW V IN VIN SW BOOST NC GND GND SHDN SYNC NC FB V C BIAS GND TJMAX = 125°C, θJA = 45°C/W, θJC = 10°C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB ORDER PART NUMBER FE PART MARKING LT3430EFE LT3430IFE LT3430EFE-1 LT3430IFE-1 3430EFE 3430IFE 3430EFE-1 3430IFE-1 Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TJ = 25°C. VIN = 15V, VC = 1.5V, ⎯S⎯H⎯D⎯N = 1V, BOOST = Open Circuit, SW = Open Circuit, unless otherwise noted.

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Gain is measured with a V C swing equal to 200mV above the low clamp level to 200mV below the upper clamp level. Note 3: Minimum input voltage is not measured directly, but is guaranteed by other tests. It is defi ned as the voltage where internal bias lines are still regulated so that the reference voltage and oscillator remain constant. Actual minimum input voltage to maintain a regulated output will depend upon output voltage and load current. See Applications Information. Note 4: This is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch. Note 5: Boost current is the current fl owing into the BOOST pin with the pin held 5V above input voltage. It fl ows only during switch on time. Note 6: Input supply current is the quiescent current drawn by the input pin when the BIAS pin is held at 5V with switching disabled. Bias supply current is the current drawn by the BIAS pin when the BIAS pin is held at 5V. Total input referred supply current is calculated by summing input supply current (I VIN) with a fraction of bias supply current (IBIAS): I TOTAL = IVIN + (IBIAS)(VOUT/VIN) With VIN = 15V, VOUT = 5V, IVIN = 1.4mA, IBIAS = 2.9mA, ITOTAL = 2.4mA. ELECTRICAL CHARACTERISTICS The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TJ = 25°C. VIN = 15V, VC = 1.5V, ⎯S⎯H⎯D⎯N = 1V, BOOST = Open Circuit, SW = Open Circuit, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS Maximum Switch Duty Cycle (LT3430-1) 98 % Switch Frequency (LT3430) V C Set to Give DC = 50% 184 172 200 200 216 228 kHz kHz Switch Frequency (LT3430-1) 100 100 115 120 kHz kHz f SW Line Regulation 5.5V ≤ V IN ≤ 60V ● 0.05 0.15 %/V fSW Shifting Threshold Df = 10kHz 0.8 V Minimum Input Voltage (Note 3) ● 4.6 5.5 V Minimum Boost Voltage (Note 4) I SW ≤ 2.5A ● 1.8 3 V Boost Current (Note 5) Boost = V IN + 5V, ISW = 0.75A Boost = VIN + 5V, ISW = 2.5A 120 mA mA Input Supply Current (I VIN) (Note 6) V BIAS = 5V 1.5 2.2 mA Bias Supply Current (IBIAS) (Note 6) V BIAS = 5V 3.1 4.2 mA Shutdown Supply Current ⎯S⎯H⎯D⎯N = 0V, VIN ≤ 60V, SW = 0V, VC Open 30 100 200 µA µA Lockout Threshold V C Open ● 2.3 2.42 2.53 V Shutdown Threshold V C Open, Shutting Down VC Open, Starting Up 0.15 0.25 0.37 0.42 0.58 0.60 V V Minimum SYNC Amplitude 1.5 V SYNC Frequency Range (LT3430) 228 700 kHz SYNC Frequency Range (LT3430-1) 125 250 kHz SYNC Input Resistance 20 k Ω Note 7: Switch on resistance is calculated by dividing V IN to SW voltage by the forced current (3A). See Typical Performance Characteristics for the graph of switch voltage at other currents. Note 8: The LT3430EFE/LT3430EFE-1 are guaranteed to meet performance specifi cations from 0°C to 125°C junction temperature. Specifi cations over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3430IFE/LT3430IFE-1 are guaranteed over the full –40°C to 125°C operating junction temperature range. Note 9: See Peak Switch Current Limit vs Junction Temperature graph in the Typical Performance Characteristics section. Note 10: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specifi ed maximum operating junction temperature may impair device reliability. Note 11: The maximum operational Boost-SW voltage is limited by thermal and load current constraints. See ‘Boost Pin’ and ‘Thermal Calculations’ in the Applications Information section.

DUTY CYCLE (%) SWITCH PEAK CURRENT (A) 20 40 60 80

3430 G01

TJ = 25°C TYPICAL JUNCTION TEMPERATURE (°C) –50 FEEDBACK VOLTAGE (V) CURRENT (µA) 1.224 1.229 1.234 25 75

3430 G02

1.219 1.214 –25 0 50 100 125 1.209 1.204 1.5 2.0 1.0 0.5 VOLTAGE CURRENT JUNCTION TEMPERATURE (°C) –50 250 200 150 100 25 75

3430 G03

–25 0 50 100 125 CURRENT (µA) CURRENT REQUIRED TO FORCE SHUTDOWN (FLOWS OUT OF PIN). AFTER SHUTDOWN, CURRENT DROPS TO A FEW µA AT 2.38V STANDBY THRESHOLD (CURRENT FLOWS OUT OF PIN) JUNCTION TEMPERATURE (°C) –50 SHDN PIN VOLTAGE (V) 50 100

3430 G04

2.4 2.0 1.6 1.2 0.8 0.4 –25 125 LOCKOUT START-UP SHUTDOWN INPUT VOLTAGE (V) INPUT SUPPLY CURRENT (µA)

3430 G05

VSHDN = 0V TA = 25°C SHUTDOWN VOLTAGE (V) INPUT SUPPLY CURRENT (µA) 100 150 200 250 300 0.1 0.2 0.3 0.4

3430 G06

0.5 VIN = 60V VIN = 15V TA = 25°C JUNCTION TEMPERATURE (°C) TRANSCONDUCTANCE (µmho)

3430 G07

–50 50 100 0 25 75–25 125 FREQUENCY (Hz) GAIN (µMho) PHASE (DEG) 3000 2500 2000 1500 1000 500 200 150 100 –50 100 10k 100k 10M

3430 G08

ERROR AMPLIFIER EQUIVALENT CIRCUIT ROUT 200k COUT 12pF VC RLOAD = 50Ω TA = 25°C VFB 2 • 10–3 )( VFB (V) SWITICHING FREQUENCY (kHz) OR FB CURRENT (µA) 300 400

600 TA = 25°C

3430 G09

0.5 1.0 1.5 SWITCHING FREQUENCY FB PIN CURRENT 3430 3430-1 TYPICAL PERFORMANCE CHARACTERISTICS Switch Peak Current Limit FB Pin Voltage and Current ⎯S⎯H⎯D⎯N Pin Bias Current Lockout and Shutdown Threshold Shutdown Supply Current Shutdown Supply Current Error Amplifi er Transconductance Error Amplifi er Transconductance Frequency Foldback

JUNCTION TEMPERATURE (°C) –50 FREQUENCY (kHz) 50 100

3430 G10

–25 125 (LT3430) LOAD CURRENT (A) INPUT VOLTAGE (V)

3430 G11

7.5 7.0 6.5 6.0 5.5 5.0 MINIMUM INPUT VOLTAGE TO START MINIMUM INPUT VOLTAGE TO RUN TA = 25°C SWITCH CURRENT (A) 0123 BOOST PIN CURRENT (mA)

3430 G12

TA = 25°C JUNCTION TEMPERATURE (°C) –50 1.5 1.7 2.1 25 75

3430 G13

1.3 1.1 –25 0 50 100 125 0.9 0.7 1.9 THRESHOLD VOLTAGE (V) SWITCH CURRENT (A) 0123 SWITCH VOLTAGE (mV)

3430 G14

TJ = 125°C TJ = 25°C TJ = –40°C JUNCTION TEMPERATURE (°C) –50 SWITCH MINIMUM ON TIME (ns) 400 500 600 25 75

3430 G15

–25 0 50 100 125 100 JUNCTION TEMPERATURE (°C) –50 SWITCH PEAK CURRENT LIMIT (A) 50 100

3430 G16

6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 –25 125 TYPICAL PERFORMANCE CHARACTERISTICS Switching Frequency Minimum Input Voltage with 5V Output BOOST Pin Current VC Pin Shutdown Threshold Switch Voltage Drop Switch Peak Current Limit Switch Minimum ON Time vs Temperature

GND (Pins 1, 8, 9, 16, 17): The GND pin connections act as the reference for the regulated output, so load regulation will suffer if the “ground” end of the load is not at the same voltage as the GND pins of the IC. This condition will occur when load current or other currents fl ow through metal paths between the GND pins and the load ground. Keep the paths between the GND pins and the load ground short and use a ground plane when possible. The FE package has an exposed pad that is fused to the GND pins. The pad (Pin 17) should be soldered to the copper ground plane under the device to reduce thermal resistance. (See Applications Information—Layout Considerations.) SW (Pins 2, 5): The switch pin is the emitter of the on-chip power NPN switch. This pin is driven up to the input pin voltage during switch on time. Inductor current drives the switch pin voltage negative during switch off time. Negative voltage is clamped with the external catch diode. Maximum negative switch voltage allowed is –0.8V. V IN (Pins 3, 4): This is the collector of the on-chip power NPN switch. VIN powers the internal control circuitry when a voltage on the BIAS pin is not present. High dI/dt edges occur on this pin during switch turn on and off. Keep the path short from the V IN pin through the input bypass capacitor, through the catch diode back to SW. All trace inductance in this path creates voltage spikes at switch off, adding to the V CE voltage across the internal NPN. BOOST (Pin 6): The BOOST pin is used to provide a drive voltage, higher than the input voltage, to the internal bipolar NPN power switch. Without this added voltage, the typical switch voltage loss would be about 1.5V. The additional BOOST voltage allows the switch to saturate and voltage loss approximates that of a 0.1Ω FET structure. NC (Pins 7, 13): No Connection. BIAS (Pin 10): The BIAS pin is used to improve effi ciency when operating at higher input voltages and light load cur- rent. Connecting this pin to the regulated output voltage forces most of the internal circuitry to draw its operating current from the output voltage rather than the input supply. This architecture increases effi ciency especially when the input voltage is much higher than the output. Minimum output voltage setting for this mode of operation is 3V. V C (Pin 11): The VC pin is the output of the error amplifi er and the input of the peak switch current comparator. It is normally used for frequency compensation, but can also serve as a current clamp or control loop override. V C sits at about 0.9V for light loads and 2.1V at maximum load. It can be driven to ground to shut off the regulator, but if driven high, current must be limited to 4mA. FB (Pin 12): The feedback pin is used to set the output voltage using an external voltage divider that generates 1.22V at the pin for the desired output voltage. Three additional functions are performed by the FB pin. When the pin voltage drops below 0.6V, switch current limit is reduced and the external SYNC function is disabled. Below 0.8V, switching frequency is also reduced. See Feedback Pin Functions in Applications Information for details. SYNC (Pin 14): The SYNC pin is used to synchronize the internal oscillator to an external signal. It is directly logic compatible and can be driven with any signal between 10% and 90% duty cycle. The synchronizing range is 125kHz to 250kHz for the LT3430-1 and 228kHz to 700kHz for the LT3430. See Synchronizing in Applications Information for details. ⎯S⎯H⎯D⎯N (Pin 15): The ⎯S⎯H⎯D⎯N pin is used to turn off the regulator and to reduce input drain current to a few mi- croamperes. This pin has two thresholds: one at 2.38V to disable switching and a second at 0.4V to force complete micropower shutdown. The 2.38V threshold functions as an accurate undervoltage lockout (UVLO); sometimes used to prevent the regulator from delivering power until the input voltage has reached a predetermined level. If the ⎯S⎯H⎯D⎯N pin functions are not required, the pin can either be left open (to allow an internal bias current to lift the pin to a default high state) or be forced high to a level not to exceed 6V.

and output capacitor, then an abrupt 180° shift will occur. and also gives much quicker transient response. than the input voltage, allowing switch to be saturated.

3430 F01

Figure 1. LT3430/LT3430-1 Block Diagram

values is shown in Table 1 for common output voltages. **Table 1. *LT3430, LT3430-1 Foldback graph in Typical Performance Characteristics).

the range of 5µH to 47µH (10µH to 100µH for LT3430-1). inductor value (to reduce the ripple current in the inductor).

3430 F02

Figure 2. Frequency and Current Limit Foldback Figure 3. LT3430 Output Ripple Voltage Waveforms.

3430 F032µs/DIV

inductor value to achieve a desirable output ripple volt- age level. If output ripple voltage is of less importance, the subsequent suggestions in Peak Inductor and Fault Current and EMI will additionally help in the selection of the inductor value. Peak-to-peak output ripple voltage is the sum of a triwave (created by peak-to-peak ripple current (I LP-P) times ESR) and a square wave (created by parasitic inductance (ESL) and ripple current slew rate). Capacitive reactance is as- sumed to be small compared to ESR or ESL. V I ESR ESL dI dtRIPPLE LP P= () ( ) + ()- where: ESR = equivalent series resistance of the output capaci- tor ESL = equivalent series inductance of the output capaci- tor dI/dt = slew rate of inductor ripple current = VIN/L Peak-to-peak ripple current (I LP-P) through the inductor and into the output capacitor is typically chosen to be between 20% and 40% of the maximum load current. It is approximated by: I VV V Vf LLP P OUT IN OUT IN - = () ( ) () ( ) ( ) Example: with V IN = 40V, V OUT = 5V, L = 22µH, ESR = 0.080Ω and ESL = 10nH, output ripple voltage can be approximated as follows: IA dI dt VA mV RIPPLE P-P P-P = () −() () () () =+= 54 0 5 40 22 10 200 10 09 9 22 10 10 1 8 0 99 0 08 10 10 10 1 8 0 079 0 018 97 .. • . To reduce output ripple voltage further requires an increase in the inductor value with the trade-off being a physically larger inductor with the possibility of increased component height and cost. Ceramic Output Capacitor An alternative way to further reduce output ripple voltage is to reduce the ESR of the output capacitor by using a ceramic capacitor. Although this reduction of ESR removes a useful zero in the overall loop response, this zero can be replaced by inserting a resistor (R C) in series with the VC pin and the compensation capacitor CC. (See Ceramic Capacitors in Applications Information.) Peak Inductor Current and Fault Current To ensure that the inductor will not saturate, the peak inductor current should be calculated knowing the maximum load current. An appropriate inductor should then be chosen. In addition, a decision should be made whether or not the inductor must withstand continuous fault conditions. If maximum load current is 1A, for instance, a 1A induc- tor may not survive a continuous 4A overload condition. Dead shorts will actually be more gentle on the inductor because the LT3430/LT3430-1 have frequency and current limit foldback. APPLICATIONS INFORMATION Table 2 VENDOR/ PART NO. VALUE (µH) IDC (Amps) DCR (Ohms) HEIGHT (mm) Sumida CDRH104R-150 15 3.6 0.050 4 CDRH104R-220 22 2.9 0.073 4 CDRH104R-330 33 2.3 0.093 4 CDRH124-220 22 2.9 0.066 4.5 CDRH124-330 33 2.7 0.097 4.5 CDRH127-330 33 3.0 0.065 8 CDRH127-470 47 2.5 0.100 8 CEI122-220 22 2.3 0.085 8 Coiltronics UP3B-330 33 3 0.069 6.8 UP3B-470 47 2.4 0.108 6.8 UP4B-680 68 4.3 0.120 7.9 Coilcraft DO3316P-153 15 3 0.046 5.2 DO5022p-683 68 3.5 0.130 7.1

Peak switch and inductor current can be signifi cantly higher than output current, especially with smaller inductors and lighter loads, so don’t omit this step. Powdered iron cores are forgiving because they saturate softly, whereas ferrite cores saturate abruptly. Other core materials fall somewhere in between. The following formula assumes continuous mode of operation, but errs only slightly on the high side for discontinuous mode, so it can be used for all conditions. II I I VV V Vf LPEAK OUT LP P OUT OUT IN OUT IN =+ =+ () ( ) () ( ) ( ) () EMI Decide if the design can tolerate an “open” core geometry like a rod or barrel, which have high magnetic fi eld radiation, or whether it needs a closed core like a toroid to prevent EMI problems. This is a tough decision because the rods or barrels are temptingly cheap and small and there are no helpful guidelines to calculate when the magnetic fi eld radiation will be a problem. Additional Considerations After making an initial choice, consider additional factors such as core losses and second sourcing, etc. Use the experts in Linear Technology’s Applications department if you feel uncertain about the fi nal choice. They have ex- perience with a wide range of inductor types and can tell you about the latest developments in low profi le, surface mounting, etc. Maximum Output Load Current Maximum load current for a buck converter is limited by the maximum switch current rating (I P). The current rating for the LT3430/LT3430-1 is 3A. Unlike most current mode converters, the LT3430/LT3430-1 maximum switch current limit does not fall off at high duty cycles. Most current mode converters suffer a drop off of peak switch current for duty cycles above 50%. This is due to the effects of slope compensation required to prevent subharmonic oscillations in current mode converters. (For detailed analysis, see Application Note 19.) The LT3430/LT3430-1 are able to maintain peak switch current limit over the full duty cycle range by using patented circuitry* to cancel the effects of slope compensation on peak switch current without affecting the frequency compensation it provides. Maximum load current would be equal to maximum switch current for an infi nitely large inductor , but with fi nite inductor size, maximum load current is reduced by one- half peak-to-peak inductor current (I LP-P). The following formula assumes continuous mode operation, implying that the term on the right is less than one-half of IP . I OUT(MAX) = Continuous Mode I– I 2 =IP LP-P P − +() −() () ( ) VV V VV LfV OUT F IN OUT F –

2 IIN()

For VOUT = 5V, VIN = 12V, VF(D1) = 0.52V, f = 200kHz and L = 15µH: I A OUT MAX() −=− +() −() () () () =− = 3 5 0 52 12 5 0 52 2 15 10 200 10 12 30 52 5 .– . Note that there is less load current available at the higher input voltage because inductor ripple current increases. At V IN = 24V, duty cycle is 23% and for the same set of conditions: I A OUT MAX() .– . =− +() −() () () () =− = −3 5 0 52 24 5 0 52 2 15 10 200 10 24 3 0 71 2 29 To calculate actual peak switch current with a given set of conditions, use: II I VV V VV LfV SW PEAK OUT P OUT OUT F IN OUT F IN () =+ =+ +− () () ( ) ( ) I L- P () – APPLICATIONS INFORMATION *US Patent # 6,498,466

Reduced Inductor Value and Discontinuous Mode If the smallest inductor value is of most importance to a converter design, in order to reduce inductor size/cost, discontinuous mode may yield the smallest inductor solu- tion. The maximum output load current in discontinuous mode, however, must be calculated and is defi ned later in this section. Discontinuous mode is entered when the output load current is less than one-half of the inductor ripple current LP-P). In this mode, inductor current falls to zero before the next switch turn on (see Figure 8). Buck converters will be in discontinuous mode for output load current given by: I OUT Discontinuous Mode < +() ( – – ) () ( ) ( ) () VV V VV Vf L OUT F IN OUT F IN2 The inductor value in a buck converter is usually chosen large enough to keep inductor ripple current (ILP-P) low; this is done to minimize output ripple voltage and maximize output load current. In the case of large inductor values, as seen in the equation above, discontinuous mode will be associated with “light loads.” When choosing small inductor values, however, discontinu- ous mode will occur at much higher output load currents. The limit to the smallest inductor value that can be chosen is set by the LT3430/LT3430-1 peak switch current (I P) and the maximum output load current required, given by: I OUT(MAX) Discontinuous Mode =< ILP-P = () I If L V VV V VV P PI N OUT F IN OUT F () ( ) () ( – – ) ILP-P Example: For VIN = 15V, VOUT = 5V, VF = 0.52V, f = 200kHz and L = 4.7µH. I OUT(MAX) Discontinuous Mode = + −3 200 10 4 7 10 15 2 50 5 2 1 550 5 2 (. ) ( – – . ) I OUT(MAX) = 1.21A Discontinuous Mode What has been shown here is that if high inductor ripple current and discontinuous mode operation can be tolerated, small inductor values can be used. If a higher output load current is required, the inductor value must be increased. If I OUT(MAX) no longer meets the discontinuous mode criteria, use the IOUT(MAX) equation for continuous mode; the LT3430/LT3430-1 are designed to operate well in both modes of operation, allowing a large range of inductor values to be used. Short-Circuit Considerations The LT3430/LT3430-1 are current mode controllers. They use the V C node voltage as an input to a current compara- tor which turns off the output switch on a cycle-by-cycle basis as this peak current is reached. The internal clamp on the V C node, nominally 2V, then acts as an output switch peak current limit. This action becomes the switch current limit specifi cation. The maximum available output power is then determined by the switch current limit. A potential controllability problem could occur under short-circuit conditions. If the power supply output is short circuited, the feedback amplifi er responds to the low output voltage by raising the control voltage, V C, to its peak current limit value. Ideally, the output switch would be turned on, and then turned off as its current exceeded the value indicated by V C. However, there is fi nite response time involved in both the current comparator and turnoff of the output switch. These result in a minimum on time t ON(MIN). When combined with the large ratio of VIN to (VF + I • R), the diode forward voltage plus inductor I • R voltage drop, the potential exists for a loss of control. Expressed mathematically the requirement to maintain control is: ft VI R VON F IN

• •≤ + APPLICATIONS INFORMATION

for the LT3430-1, unacceptably short times. control with the effective minimum on time. range for typical LT3430 applications is 0.05 Ω to 0.2Ω. tantalum surface mount capacitors. Table 3. Surface Mount Solid Tantalum Capacitor ESR

frequency gain of the error amplifi er, including the gain at the switching frequency. If the gain of the error amplifi er is high enough at the switching frequency, output ripple voltage (although smaller for a ceramic output capacitor) may still affect the proper operation of the regulator. A fi lter capacitor C F in parallel with the R C/CC network is suggested to control possible ripple at the VC pin. An “All Ceramic” solution is possible for the LT3430/LT3430-1 by choosing the correct compensation components for the given application. Example: For V IN = 8V to 40V, VOUT = 5V at 2A, the LT3430 can be stabilized, provide good transient response and maintain very low output ripple voltage using the follow- ing component values: (refer to the fi rst page of this data sheet for component references) C IN = 4.7µF, RC = 3.3k, CC = 22nF, CF = 220pF and COUT = 100µF. See Application Note 19 for further detail on techniques for proper loop compensation. INPUT CAPACITOR Step-down regulators draw current from the input supply in pulses. The rise and fall times of these pulses are very fast. The input capacitor is required to reduce the volt- age ripple this causes at the input of LT3430/LT3430-1 and force the switching current into a tight local loop, thereby minimizing EMI. The RMS ripple current can be calculated from: II V V V VRIPPLE RMS OUT OUT IN OUT IN() = () –/ 2 Ceramic capacitors are ideal for input bypassing. At 200kHz (100kHz) switching frequency, the energy storage requirement of the input capacitor suggests that values in the range of 4.7µF to 20µF (10µF to 47µF) are suitable for most applications. If operation is required close to the minimum input required by the output of the LT3430, a larger value may be required. This is to prevent excessive ripple causing dips below the minimum operating voltage resulting in erratic operation. Depending on how the LT3430/LT3430-1 circuit is powered up you may need to check for input voltage transients. The input voltage transients may be caused by input voltage steps or by connecting the LT3430/LT3430-1 converter to an already powered up source such as a wall adapter. The sudden application of input voltage will cause a large surge of current in the input leads that will store energy in the parasitic inductance of the leads. This energy will cause the input voltage to swing above the DC level of input power source and it may exceed the maximum voltage rating of input capacitor and LT3430/LT3430-1. The easiest way to suppress input voltage transients is to add a small aluminum electrolytic capacitor in parallel with the low ESR input capacitor. The selected capacitor needs to have the right amount of ESR in order to criti- cally dampen the resonant circuit formed by the input lead inductance and the input capacitor. The typical values of ESR will fall in the range of 0.5Ω to 2Ω and capacitance will fall in the range of 5µF to 50µF. If tantalum capacitors are used, values in the 22µF to 470µF range are generally needed to minimize ESR and meet ripple current and surge ratings. Care should be taken to ensure the ripple and surge ratings are not exceeded. The AVX TPS and Kemet T495 series are surge rated. AVX recommends derating capacitor operating voltage by 2:1 for high surge applications. CATCH DIODE Highest effi ciency operation requires the use of a Schottky type diode. DC switching losses are minimized due to its low forward voltage drop, and AC behavior is benign due to its lack of a signifi cant reverse recovery time. The use of so-called “ultrafast” recovery diodes is generally not recommended. When operating in continuous mode, the reverse recovery time exhibited by “ultrafast” diodes will result in a slingshot type effect. The power internal switch will ramp up V IN current into the diode in an at- tempt to get it to recover. Then, when the diode has fi nally turned off, some tens of nanoseconds later, the VSW node voltage ramps up at an extremely high dV/dt, perhaps 5 to even 10V/ns ! With real world lead inductances, the V SW node can easily overshoot the VIN rail. This can result in APPLICATIONS INFORMATION

poor RFI behavior and if the overshoot is severe enough, damage the IC itself. The suggested catch diode (D1) is an International Recti- fi er 30BQ060 Schottky. It is rated at 3A average forward current and 60V reverse voltage. Typical forward voltage is 0.52V at 3A. The diode conducts current only during switch off time. Peak reverse voltage is equal to regulator input voltage. Average forward current in normal operation can be calculated from: I IV V VD AVG OUT IN OUT IN –= () This formula will not yield values higher than 3A with maximum load current of 3A. BOOST PIN For most LT 3430 applications, the boost components are a 0.68µF capacitor and a MMSD914TI diode. The anode is typically connected to the regulated output voltage to generate a voltage approximately V OUT above VIN to drive the output stage. However, the output stage discharges the boost capacitor during the on time of the switch. The output driver requires at least 3V of headroom throughout this period to keep the switch fully saturated. If the output voltage is less than 3.3V, it is recommended that an alternate boost supply is used. For output voltages greater than 6V, it is recommended to place a zener diode (D4; page 20) in series with the Boost diode to set Boost-to-SW voltage between 4V to 6V. This minimizes power loss within the IC, improving maximum ambient temperature operation. In addition, D4 minimizes Boost current overshoot during power switch turn on to reduce noise within the regula- tor loop. For output voltages greater than the standard demoboard 5V output, a location for D4 is provided. A 0.68µF boost capacitor is recommended for most LT3430 applications. Almost any type of fi lm or ceramic capaci- tor is suitable, but the ESR should be <1 Ω to ensure it can be fully recharged during the off time of the switch. The LT3430 capacitor value is derived from conditions of 4800ns on time, 75mA boost current and 0.7V discharge ripple. The boost capacitor value could be reduced under less demanding conditions, but this will not improve cir- cuit operation or effi ciency. Under low input voltage and low load conditions, a higher value capacitor will reduce discharge ripple and improve start-up operation. For the LT3430-1 a 1.5µF boost capacitor is recommended. SHUTDOWN FUNCTION AND UNDERVOLTAGE LOCKOUT Figure 4 shows how to add undervoltage lockout (UVLO) to the LT3430/LT3430-1. Typically, UVLO is used in situ- ations where the input supply is current limited, or has a relatively high source resistance. A switching regulator draws constant power from the source, so source cur- rent increases as source voltage drops. This looks like a negative resistance load to the source and can cause the source to current limit or latch low under low source voltage conditions. UVLO prevents the regulator from operating at source voltages where these problems might occur. Threshold voltage for lockout is about 2.38V. A 5.5µA bias current fl ows out of the pin at this threshold. The internally generated current is used to force a default high state on the shutdown pin if the pin is left open. When low shutdown current is not an issue, the error due to this current can be minimized by making R LO 10k or less. If shutdown current is an issue, RLO can be raised to 100k, but the error due to initial bias current and changes with temperature should be considered. Rk R RV V VR A LO HI LO IN LO = () = −() − () 23 8 23 8 55 to 100k 25k suggested .. µ V IN = Minimum input voltage Keep the connections from the resistors to the shutdown pin short and make sure that interplane or surface capaci- tance to the switching nodes are minimized. If high resistor values are used, the shutdown pin should be bypassed with a 1000pF capacitor to prevent coupling problems from the switch node. If hysteresis is desired in the undervoltage lockout point, a resistor R FB can be added to the output node. Resistor values can be calculated from: APPLICATIONS INFORMATION

3430 F04

Figure 4. Undervoltage Lockout

3430 F05

3430 F06

6 BOOST

Figure 5. High Speed Switching Path Figure 6. Suggested Layout

stability or subharmonic like oscillation. the four corner pins to the ground plane will also help. will reduce any additional heating effects. path is 1 inch, the inductance will be approximately 25nH. details of the falling edge overshoot in Figure 7.

3430 F081µs/DIV

Figure 7. Switch Node Resonance Figure 8. Discontinuous Mode Ringing

Power dissipation in the LT3430/LT3430-1 chip comes from four sources: switch DC loss, switch AC loss, boost circuit current, and input quiescent current. The follow- ing formulas show how to calculate each of these losses. These formulas assume continuous mode operation, so they should not be used for calculating effi ciency at light load currents. Switch loss: P RI V V tI V fSW SW OUT OUT IN EFF OUT IN= () ( ) + () ( ) ( ) 12(/ ) (Note: Switching losses are less for the LT3430-1 oper- ating at only 100kHz) Boost current loss: P VI VBOOST OUT OUT IN = ()2 36/ Quiescent current loss: PV VQ IN OUT= () + ()0 0015 0 003.. R SW = Switch resistance (≈ 0.15) hot t EFF = Effective switch current/voltage overlap time = (t r + tf + tIr + tIf) t r = (VIN/1.2)ns t f = (VIN/1.1)ns t Ir = tIf = (IOUT/0.2)ns f = Switch frequency Example: with VIN = 40V, VOUT = 5V and IOUT = 2A: P W PW PW SW BOOST Q =+= = () () = =+ = −01 5 2 5 40 90 10 1 2 2 40 200 10 00 8 07 2 08 52 3 6 40 00 4 40 0 0015 5 0 003 0 08 . •/ • ... / . (. ) (. ) . Total power dissipation in the IC is given by: P TOT = PSW + PBOOST + PQ Thermal resistance for the LT3430/LT3430-1 package is in- fl uenced by the presence of internal or backside planes. TSSOP (Exposed Pad) Package: With a full plane under the TSSOP package, thermal resistance will be about 45°C/W. To calculate die temperature, use the proper thermal resistance number for the desired package and add in worst-case ambient temperature: T J = TA + (θJA • PTOT) When estimating ambient, remember the nearby catch diode and inductor will also be dissipating power: P VV V I VDIODE F IN OUT LOAD IN = ( )( – )( ) V F = Forward voltage of diode (assume 0.52V at 2A) 40 09 1 P INDUCTOR = (ILOAD)2(RIND) R IND = Inductor DC resistance (assume 0.1Ω) P INDUCTOR (2)2(0.1) = 0.4W Only a portion of the temperature rise in the external inductor and diode is coupled to the junction of the LT3430. Based on empirical measurements, the thermal effect on the LT3430 junction temperature due to power dissipation in the external inductor and catch diode can be calculated as: J(LT3430) ≈ (PDIODE + PINDUCTOR)(5°C/W) Using the example calculations for LT3430 dissipation, the LT3430 die temperature will be estimated as: T J = TA + (θJA • PTOT) + [5 • (PDIODE + PINDUCTOR)] With the TSSOP package (θJA = 45°C/W), at an ambient temperature of 50°C: T Die temperature can peak for certain combinations of VIN, VOUT and load current. While higher V IN gives greater switch AC losses, quiescent and catch diode losses, a APPLICATIONS INFORMATION

ment of the SYNC pin resistance (to GND) can be used.

• / •= () 36 Here it can be seen that boost power dissipation increases as the square of VOUT. It is possible, however, to reduce VC2 below VOUT to save power dissipation by increasing the voltage drop in the path of D2. Care should be taken that V C2 does not fall below the minimum 3.3V boost voltage required for full saturation of the internal power switch. For output voltages of 5V, V C2 is approximately 5V. During switch turn on, VC2 will fall as the boost capacitor C2 is dicharged by the BOOST pin. In the previous BOOST Pin section, the value of C2 was designed for a 0.7V droop in V C2 = VDROOP. Hence, an output voltage as low as 4V would still allow the minimum 3.3V for the boost function using the C2 capacitor calculated. If a target output voltage of 12V is required, however, an excess of 8V is placed across the boost capacitor which is not required for the boost function but still dissipates additional power. What is required is a voltage drop in the path of D2 to achieve minimal power dissipation while still maintaining minimum boost voltage across C2. A zener, D4, placed in series with D2 (see Figure 9), drops voltage to C2. Example : the BOOST pin power dissipation for a 20V input to 12V output conversion at 2A is given by: PWBOOST = () =12 2 36 12 20 04•/ • . If a 7V zener D4 is placed in series with D2, then power dissipation becomes : PWBOOST = () =12 2 36 5 20 0 167•/ • . For an FE package with thermal resistance of 45°C/W, ambient temperature savings would be, T(ambient) sav- APPLICATIONS INFORMATION BOOST VIN VOUT CF CC LT3430/ LT3430-1 SHDN SYNC SW BIAS FB VCGND

3430 F09

Figure 9. BOOST Pin, Diode Selection

ings = 0.233W • 45°C/W = 11°C. The 7V zener should be sized for excess of 0.233W operaton. The tolerances of the zener should be considered to ensure minimum V exceeds 3.3V + VDROOP. Input Voltage vs Operating Frequency Considerations The absolute maximum input supply voltage for the LT3430/ LT3430-1 is specifi ed at 60V. This is based solely on internal semiconductor junction breakdown effects. Due to internal power dissipation, the actual maximum V IN achievable in a particular application may be less than this. A detailed theoretical basis for estimating internal power loss is given in the section, Thermal Considerations. Note that AC switching loss is proportional to both operating frequency and output current. The majority of AC switching loss is also proportional to the square of input voltage. For example, while the combination of V IN = 40V, V OUT = 5V at 2A and f OSC = 200kHz may be easily achievable, simultaneously raising VIN to 60V and fOSC to 700kHz is not possible. Nevertheless, input voltage transients up to 60V can usually be accommodated, assuming the result- ing increase in internal dissipation is of insuffi cient time duration to raise die temperature signifi cantly. A second consideration is controllability. A potential limita- tion occurs with a high step-down ratio of V IN to VOUT, as this requires a correspondingly narrow minimum switch on time. An approximate expression for this (assuming continuous mode operation) is given as follows: min t VV Vf ON OUT F IN OSC = + where: V IN = input voltage V OUT = output voltage V F = Schottky diode forward drop f OSC = switching frequency A potential controllability problem arises if the LT3430/ LT3430-1 are called upon to produce an on time shorter than it is able to produce. Feedback loop action will lower then reduce the V C control voltage to the point where some sort of cycle-skipping or odd/even cycle behavior is exhibited. In summary: 1. Be aware that the simultaneous requirements of high V IN, high IOUT and high fOSC may not be achievable in practice due to internal dissipation. The Thermal Con- siderations section offers a basis to estimate internal power. In questionable cases a prototype supply should be built and exercised to verify acceptable operation. 2. The simultaneous requirements of high V IN, low VOUT and high fOSC can result in an unacceptably short minimum switch on time. Cycle skipping and/or odd/even cycle behavior will result although correct output voltage is usually maintained. The LT3430-1 100kHz switching frequency will allow higher V IN/VOUT ratios without pulse skipping. FREQUENCY COMPENSATION Before starting on the theoretical analysis of frequency response, the following should be remembered—the worse the board layout, the more diffi cult the circuit will be to stabilize. This is true of almost all high frequency analog circuits, read the Layout Considerations section fi rst. Common layout errors that appear as stability prob- lems are distant placement of input decoupling capacitor and/or catch diode, and connecting the V C compensation to a ground track carrying signifi cant switch current. In addition, the theoretical analysis considers only fi rst order non-ideal component behavior. For these reasons, it is important that a fi nal stability check is made with production layout and components. The LT3430/LT3430-1 use current mode control. This al- leviates many of the phase shift problems associated with the inductor. The basic regulator loop is shown in Figure 10. The LT3430/LT3430-1 can be considered as two g m blocks, the error amplifi er and the power stage. Figure 11 shows the overall loop response. At the V C pin, the frequency compensation components used are: R C = 3.3k, C C = 0.022µF and C F = 220pF. The output capacitor used is a 100µF, 10V tantalum capacitor with typical ESR of 100m Ω. LT3430-1 uses two of these capacitors in parallel. The ESR of the tantalum output capacitor provides a use- ful zero in the loop frequency response for maintaining APPLICATIONS INFORMATION

improved transient response. C, the maximum value has two limitations. to further suppress VC ripple voltage. unacceptably large negative transients on the FB pin.

3430 F10

3430 F11

Figure 10. Model for Loop Response Figure 11. Overall Loop Response

regulation, Q1 turns off and the circuit operates normally. R3 is transient protection for the base of Q1. be used for sequencing multiple regulator outputs.

3430 F12

3430 F13

Figure 12. Dual Source Supply with 25µA Reverse Leakage Figure 13. Buck Converter with Adjustable Soft-Start

changes L1B current waveform from square to triangular. then provides the proper feedback voltage for the chip.

3430 F14

Figure 14. Dual Output SEPIC Converter

ensuring that peak switch current rating is not exceeded. current is higher, use the continuous mode formula. 2.0 for smaller inductors at lower load currents.

3430 F15

• INCREASE L1 FOR HIGHER CURRENT APPLICATIONS.

Figure 15. Positive-to-Negative Converter

value equal to the peak-to-peak triangular waveform of the inductor. The low output ripple design in Figure 15 places the input capacitor between V IN and the regulated negative output. This placement of the input capacitor signifi cantly reduces the size required for the output capacitor (versus placing the input capacitor between V IN and ground). The peak-to-peak ripple current in both the inductor and output capacitor (assuming continuous mode) is: IP-P P-P == + DC V fL DC Duty Cycle VV VV V I RMS I IN OUT F OUT IN F COUT The output ripple voltage for this confi guration is as low as the typical buck regulator based predominantly on the inductor’s triangular peak-to-peak ripple current and the ESR of the chosen capacitor (see Output Ripple Voltage in Applications Information). Diode Current Average diode current is equal to load current. Peak diode current will be considerably higher. Peak diode current: Continuous Mode I VV V VV LfV V Discontinuous Mode IV Lf OUT IN OUT IN IN OUT IN OUT OUT OUT + + + () ( ) ( ) () ( ) ( ) () ( ) () ( ) Keep in mind that during start-up and output overloads, average diode current may be much higher than with nor- mal loads. Care should be used if diodes rated less than 1A are used, especially if continuous overload conditions must be tolerated. BOOST VIN 2, 5 30BQ060 20.5k VOUT 3.3V 3, 4 220pF 0.022µF *FOR INPUT VOLTAGES BELOW 7.5V, SOME RESTRICTIONS MAY APPLY 1, 8, 9, 16 LT3430-1 SHDN SYNC SW BIAS FB VCGND 1.5µF 100µF 10V SOLID TANTALUM

2 IN PARALLEL

68µH MMSD914TI 12.1k

3430 F16

4.7µF 100V ONOFF VIN 5.5V* TO 60V 3.3k 3.3V, 2A Buck Converter TYPICAL APPLICATION

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION 16-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation BB FE16 (BB) TSSOP 0204 0.09 – 0.20 (.0035 – .0079) 0° – 8° 0.25 REF 0.50 – 0.75 (.020 – .030) 4.30 – 4.50* (.169 – .177) 13 4 5 6 7 8 10 9 4.90 – 5.10* (.193 – .201) 16 1514 13 12 11 1.10 (.0433) MAX 0.05 – 0.15 (.002 – .006) 0.65 (.0256) BSC 2.94 (.116) 0.195 – 0.30 (.0077 – .0118) TYP 2RECOMMENDED SOLDER PAD LAYOUT 0.45 ±0.05

0.65 BSC

4.50 ±0.10 6.60 ±0.10 1.05 ±0.10 2.94 (.116) 3.58 (.141) 3.58 (.141) MILLIMETERS (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE SEE NOTE 4 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT 6.40 (.252) BSC

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006 LT 0107 REV A • PRINTED IN USA RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1074/LT1074HV 4.4A (I OUT), 100kHz, High Effi ciency Step-Down DC/DC Converters VIN: 7.3V to 45V/64V, VOUT(MIN): 2.21V, IQ: 8.5mA, ISD: 10µA DD-5/7, TO220-5/7 LT1076/LT1076HV 1.6A (I OUT), 100kHz, High Effi ciency Step-Down DC/DC Converters VIN: 7.3V to 45V/64V, VOUT(MIN): 2.21V, IQ: 8.5mA, ISD: 10µA DD-5/7, TO220-5/7 LT1676 60V, 440mA (I OUT), 100kHz, High Effi ciency Step-Down DC/DC Converter VIN: 7.4V to 60V, VOUT(MIN): 1.24V, IQ: 3.2mA, ISD: 2.5µA, S8 LT1765 25V, 2.75A (I OUT), 1.25MHz, High Effi ciency Step-Down DC/DC Converter VIN: 3V to 25V, VOUT(MIN): 1.20V, IQ: 1mA, ISD: 15µA, S8, TSSOP16E LT1766 60V, 1.2A (I OUT), 200kHz, High Effi ciency Step-Down DC/DC Converter VIN: 5.5V to 60V, VOUT(MIN): 1.20V, IQ: 2.5mA, ISD: 25µA, TSSOP16/E LT1767 25V, 1.2A (I OUT), 1.25MHz, High Effi ciency Step-Down DC/DC Converter VIN: 3V to 25V, VOUT(MIN): 1.20V, IQ: 1mA, ISD: 6µA, MS8/E LT1776 40V, 550mA (I OUT), 200kHz, High Effi ciency Step-Down DC/DC Converter VIN: 7.4V to 40V, VOUT(MIN): 1.24V, IQ: 3.2mA, ISD: 30µA, N8, S8 LT1940 25V, Dual 1.2A (I OUT), 1.1MHz, High Effi ciency Step-Down DC/DC Converter VIN: 3V to 25V, VOUT(MIN): 1.2V, IQ: 3.8mA, ISD: <1µA, TSSOP16E LT1956 60V, 1.2A (I OUT), 500kHz, High Effi ciency Step-Down DC/DC Converter VIN: 5.5V to 60V, VOUT(MIN): 1.20V, IQ: 2.5mA, ISD: 25µA, TSSOP16/E LT1976 60V, 1.2A (I OUT), 200kHz, High Effi ciency Step-Down DC/DC Converter with Burst Mode Operation VIN: 3.3V to 60V, VOUT(MIN): 1.20V, IQ: 100µA, ISD: <1µA, TSSOP16/E LT3010 80V, 50mA Low Noise Linear Regulator V IN: 1.5V to 80V, VOUT(MIN): 1.28V, IQ: 30µA, ISD: <1µA, MSE8 LTC3407 Dual 600mA (I OUT), 1.5MHz, Synchronous Step-Down DC/DC Converter VIN: 2.5V to 5.5V, VOUT(MIN): 0.6V, IQ: 40µA, ISD: <1µA, MS10E LTC3412 2.5A (I OUT), 4MHz, Synchronous Step-Down DC/DC Converter VIN: 2.5V to 5.5V, VOUT(MIN): 0.8V, IQ: 60µA, ISD: <1µA, TSSOP16E LTC3414 4A (I OUT), 4MHz, Synchronous Step-Down DC/DC Converter VIN: 2.3V to 5.5V, VOUT(MIN): 0.8V, IQ: 64µA, ISD: <1µA, TSSOP20E LT3430/LT3431 60V, 2.75A (I OUT), 200kHz/500kHz, High Effi ciency Step-Down DC/DC Converters VIN: 5.5V to 60V, VOUT(MIN): 1.20V, IQ: 2.5mA, ISD: 30µA, TSSOP16E LT3433 60V, 400mA (I OUT), 200kHz, High Effi ciency Step-Up Step-Down DC/DC Converter with Burst Mode Operation VIN: 4V to 60V, VOUT(MIN): 3.3V to 20V, IQ: 100µA, ISD: <1µA, TSSOP16E LTC3727/LTC3727-1 36V, 500kHz, High Effi ciency Step-Down DC/DC Controllers VIN: 4V to 36V, VOUT(MIN): 0.8V, IQ: 670µA, ISD: 20µA, QFN-32, SSOP-28 Burst Mode is a registered trademark of Linear Technology Corporation.