LT3420

LT3420/LT3420-1 - Photoflash Capacitor Chargers with Automatic Refresh

Document overview

• Manufacturer or author: Linear Technology Corporation
• PDF pages: 20

Technical content

Figure 1. High Charge Rate LT3420 Photoflash Circuit

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Figure 2. Small Size LT3420-1 Photoflash Circuit

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R REF VBAT RFB VCC GND C T CHARGE DONE SEC SW TOP VIEW MS PACKAGE 10-LEAD PLASTIC MSOP PARAMETER CONDITIONS MIN TYP MAX UNITS Minimum Operating Voltage, VCC ● 2.2 2.5 V Maximum Operating Voltage, VCC 16 V VCC UVLO Hysteresis 40 mV Minimum VBAT Voltage 1.6 1.8 V Maximum VBAT Voltage 16 V VBAT UVLO Hysteresis 275 mV RREF Threshold Voltage 0.98 1.00 1.02 V

• 0.975 1.025 V RREF Pin Bias Current V RREF = 0V, Switching 2 4 µA VRFB = VBAT – 0.2V (Note 4) Quiescent Current V RREF = 1.1V, Not Switching 90 130 µA Quiescent Current in Shutdown V CHARGE = 0V, VIN = 3.3V 0.01 1 µA Consult LTC Marketing for parts specified with wider operating temperature ranges. SW Voltage (Note 2) ABSOLUTE AXI U RATI GSW WW U (Note 1) ELECTRICAL CHARACTERISTICSThe ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = VBAT = 3.3V, VCHARGE = VCC unless otherwise noted. (Note 3) TJMAX = 125°C, θJA = 100°C/W, θJC = 45°C/W (4-LAYER BOARD) TOP VIEW DD PACKAGE 10-LEAD (3mm × 3mm) PLASTIC DFN 1 CT CHARGE DONE SEC SW R REF VBAT RFB VCC GND ORDER PART NUMBER LT3420EDD LT3420EDD-1 TJMAX = 125°C, θJA = 43°C/W, θJC = 3°C/W EXPOSED PAD IS GND (PIN 11) AND MUST BE SOLDERED TO PCB PACKAGE/ORDER INFORMATIONW UU DD PART MARKING LBJW LBJX ORDER PART NUMBER MS PART MARKING LTYH LTAJG LT3420EMS LT3420EMS-1 Operating Ambient Temperature Range Lead Temperature (Soldering, 10 sec)

VBAT (V) TIME (s)

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T A = 25°C FIGURE 1 CIRCUIT UNLESS OTHERWISE NOTED. COUT = 220µF COUT = 100µF Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Rated breakdown with LT3420 in power delivery mode and power switch off. Note 3: The LT3420/LT3420-1 are guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the –40°C to 85°C PARAMETER CONDITIONS MIN TYP MAX UNITS Primary Side Current Limit LT3420 (Note 5) 1.20 1.4 1.60 A LT3420-1 (Note 5) 0.75 0.9 1.05 A Secondary Side Current Limit LT3420 (Note 5) 20 40 50 mA LT3420-1 (Note 5) 5 15 25 mA Leakage Blanking Pulse Width LT3420 200 ns LT3420-1 0 ns Refresh Timer Charge/Discharge Current V CT = 0.75V 1.5 2.5 3.5 µA Refresh Timer Upper Threshold 0.9 1.0 1.1 V Refresh Timer Lower Threshold 0.45 0.5 0.55 V Switch VCESAT LT3420, SW = 1A (Note 5) 220 340 mV LT3420-1, SW = 0.5A (Note 5) 130 230 mV Switch Leakage Current V SW = 38V (LT3420), VSW = 50V (LT3420-1) 0.01 1 µA CHARGE Input Voltage High 1.5 V CHARGE Input Voltage Low 0.2 V CHARGE Pin Bias Current V CHARGE = 3V 4.5 15 µA VCHARGE = 0V 0.01 0.1 µA DONE Output Signal High 100k from V CC to DONE 3.3 V DONE Output Signal Low 33 µA into DONE Pin 100 200 mV ELECTRICAL CHARACTERISTICSThe ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = VBAT = 3.3V, VCHARGE = VCC unless otherwise noted. (Note 3) operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 4: Bias current flows out of RFB pin. Note 5: Current limit and VCESAT guaranteed by design and/or correlation to static test for DD package. TYPICAL PERFOR A CE CHARACTERISTICSUW Output Voltage in Refresh Mode, LT3420 Output Voltage in Refresh Mode, LT3420 Charge Time, LT3420 TEMPERATURE (°C) –50 VOUT (V) 100

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–25 25 75 125 FIGURE 1 CIRCUIT VCC = 3.3V VBAT = 3.3V VIN (V) 2.5 VOUT (V)

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VCC = VIN VBAT = VIN TA = 25°C 335 330 325 320 315 310 305 300 295 Graphs apply to both the LT3420 and LT3420-1 unless otherwise noted.

Output Voltage in Refresh Mode, LT3420-1 TEMPERATURE (°C) –50 VOUT (V) 100

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–25 25 75 125 FIGURE 2 CIRCUIT VCC = 3.3V VBAT = 3.3V VIN (V) 2.5 VOUT (V) 5.5

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VCC = VIN VBAT = VIN TA = 25°C 335 330 325 320 315 310 305 300 295 VBAT (V) TIME (s)

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T A = 25°C COUT = 100µF COUT = 40µF Output Voltage in Refresh Mode, LT3420-1 Charge Pin Input Current Primary Current Limit, LT3420 Secondary Current Limit, LT3420 Charge Time, LT3420-1 CHARGE PIN VOLTAGE (V) CURRENT (µA) 57 1 0

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TA = 25°C TEMPERATURE (°C) –50 CURRENT (A)

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1.7 1.5 1.3 1.1 0.9 –25 25 75 125 TEMPERATURE (°C) –50 CURRENT (mA) 100

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–25 25 75 125 Efficiency of Figure 1 Circuit, LT3420 Primary Current Limit, LT3420-1 Secondary Current Limit, LT3420-1 EFFICIENCY (%)

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V OUT (V) 100 200 30050 150 350 250 VCC = VBAT = VIN VIN = 3.3V VIN = 5V TA = 25°C TEMPERATURE (°C) –50 CURRENT (A)

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1.2 1.1 1.0 0.9 0.8 –25 25 75 125 TEMPERATURE (°C) –50 CURRENT (mA) 100

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–25 25 75 125 Graphs apply to both the LT3420 and LT3420-1 unless otherwise noted. TYPICAL PERFOR A CE CHARACTERISTICS UW

TYPICAL PERFOR A CE CHARACTERISTICSUW Efficiency for Figure 2 Circuit, LT3420-1 Input Current, LT3420 VCC Minimum Operating VoltageQuiescent Current in Refresh Mode V BAT Minimum Operating Voltage Input Current, LT3420-1 EFFICIENCY (%)

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V OUT (V) 100 200 30050 150 350 250 VCC = VBAT = VIN VIN = 3.3V VIN = 5V TA = 25°C AVERAGE INPUT CURRENT (mA)

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V OUT (V) 100 200 30050 150 350 250 FIGURE 1 CIRCUIT VCC = VBAT = 3.3V TA = 25°C VOUT (V)

300 AVERAGE INPUT CURRENT (mA)350

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VCC = VBAT = 3.3V TA = 25°C VCC (V) 2.5 QUIESCENT CURRENT (µA)

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5.5 8.5 140 120 100 4.0 7.0 TA = 25°C TEMPERATURE (°C) –50 VCC PIN VOLTAGE (V) 100

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2.6 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 –25 25 75 125 V ENABLE VOLTAGE IS HYSTERETIC TEMPERATURE (°C) –50 VBAT PIN VOLTAGE (V) 100

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05 0–25 25 75 125 2.0 1.8 1.6 1.4 1.2 1.0 ENABLE VOLTAGE IS HYSTERETIC Graphs apply to both the LT3420 and LT3420-1 unless otherwise noted.

RREF (Pin 1): Reference Resistor Pin. Place a resistor (R2) from the RREF pin to GND. 2k is recommended. VBAT (Pin 2): Battery Voltage Input. This pin should be connected to the power supply or battery, which supplies power to transformer T1. Must be locally bypassed. R FB (Pin 3): Feedback Resistor Pin. Place a resistor (R1) from the SW pin to the RFB pin. Set R1 according to the following formula: R R N RN V VSEC OUT D1 2 14 2 R R N RN V VSEC OUT D1 2 22=+ +[]() ( ) (LT3420-1) VOUT : Desired Output Voltage N: Transformer Turns Ratio R SEC: Transformer Secondary Resistance VD: Diode Forward Voltage Drop R2: Resistor from the RREF Pin to GND. 2k is a Typical Choice VCC (Pin 4): Input Supply Pin. Must be locally bypassed with a 4.7µF or larger ceramic capacitor. GND (Pin 5): Ground. Tie directly to local ground plane. SW (Pin 6): Switch Pin. This is the collector of the internal NPN power switch. Minimize the metal trace area con- nected to this pin to minimize EMI. SEC (Pin 7): Transformer Secondary Pin. Tie one end of the transformer secondary to this pin. Take care to use the correct phasing of the transformer (Refer to Figures 1 and 2). DONE (Pin 8): Done Output Pin. Open collector NPN output. DONE is pulled low whenever the chip is delivering power to the output and goes high when power delivery stops. CHARGE (Pin 9): Charge Pin. Drive CHARGE high (1.5V or more) to commence charging of the output capacitor. Drive to 0.2V or less to put the part in shutdown mode. C T (Pin 10): Refresh Timer Capacitor Pin. Place a capacitor from the CT pin to GND to set the refresh timer sample rate according to the following formula: CT = 2.5 • 10–6 • tREFRESH tREFRESH: Desired Refresh Period in Seconds. EXPOSED PAD (Pin 11) (DD Package only): GND. Must be soldered to local ground plane on PCB.

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Figure 3. Block Diagram, LT3420

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Figure 4. Block Diagram, LT3420-1

The following text focuses on the operation of the LT3420. differences discussed at the end of this section. the part is indicated below the photo. the charging mode by toggling the CHARGE pin. reset the latch is approximately 1.4A (~20mV/14mΩ). ample, the peak secondary current is 116mA (1.4A/12). Diode D1 now conducts, providing power to the output. and the output voltage (neglecting the diode voltage drop). Figure 5. Demonstrating 3 Operating Modes of LT3420:

of Q1 so that the peak current of Q1 is 1.4A and the mini- mum secondary current is 40mA (typical values). The previously described charging cycle must be halted when the output voltage reaches the desired value. The LT3420 monitors the output voltage via the flyback pulse on the SW pin. When Q1 turns off, the secondary side conducts current turning on diode D1. Since the diode is conducting and the SEC pin is at nearly ground, the voltage across the secondary is nearly equal to V OUT. The voltage across the primary is therefore close to VOUT/N. A current proportional to VOUT/N flows through R1 and into the RFB pin. The current flows out of the RREF pin through a resis- tor creating a ground referred voltage. When this voltage exceeds an internal 1V reference voltage, the output of comparator A3 goes high which resets the master latch. The Q output of the master latch goes low, disabling the entire power delivery block and enabling the refresh timer. Leakage Spike Blanking Another function of the LT3420 is leakage spike blanking when the power switch, Q1, turns off. Right after Q1 turns off, a one-shot turns on Q2 for 200ns (typ). With Q2 on, comparator A3 is disabled. This function may prevent A3 from false tripping on the leakage inductance spike on the SW pin. In practice, the PNP transistor Q3 filters out the leakage spike. Refresh Timer When the refresh timer is enabled, a 2.5µA current source is switched on, charging up the external timing capacitor, Figure 6b. Switching Waveforms with VOUT = 300V, VCC = VBAT = 3.3V Figure 6a. Switching Waveforms with VOUT = 100V, VCC = VBAT = 3.3V OPERATIOU C3, from its initial voltage towards 1V. When the voltage on C3 reaches 1V, the polarity of the current source changes and 2.5µA discharges C3. When the voltage on C3 reaches 0.5V, the refresh timer sends a set pulse to the master latch, which puts the LT3420 into the charging mode. Interface/Control The CHARGE pin serves two functions. The first is to enable or shutdown the part depending on the level of the pin (high = enable, low = shutdown). The second is to force the part into the charging mode (low→high transi- tion). The LT3420 also has a DONE pin, which signals whether or not the part is done charging the photoflash capacitor. The DONE pin is an open collector NPN switch (Q5) so an external pull-up resistor is needed. Whenever the part is in charging mode, DONE will be low. DONE will go high when the charging mode is complete. Both the CHARGE and DONE pins can be easily interfaced to a microprocessor in a digital or film camera. LT3420-1 Differences The LT3420-1 has different primary and secondary cur- rent limit levels. The primary current limit level of the LT3420-1 is 1A (typ) and the secondary current limit is 15mA (typ). The LT3420-1 has no leakage spike blanking which causes no problems since the PNP transistor, Q3, provides adequate filtering. Finally, the breakdown voltage of the SW pin of the LT3420-1 is higher at 50V. ISW 1A/DIV VSW 20V/DIV ISEC 200mA/DIV 2µs/DIV

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2µs/DIV

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Choosing the Right Transformer The flyback transformer plays a key role in any LT3420/ LT3420-1 application. A poorly designed transformer can result in inefficient operation. Linear Technology Corpora- tion has worked with a number of transformer manufactur- ers to develop specific transformers for use with the LT3420/LT3420-1. These predesigned transformers are sufficient for a large majority of the applications that may be encountered. In some cases, the reader may choose to design his own transformer or may simply be curious about the issues involved in designing the transformer. The fol- lowing is a brief discussion of the issues relating to trans- former design. Transformer Turns Ratio The turns ratio for the transformer, N, should be high enough so that the absolute maximum voltage rating for the NPN power switch is not exceeded. When the power switch turns off, the voltage on the collector of the switch (SW Pin) will “fly” up to the output voltage divided by N plus the battery voltage (neglecting the voltage drop across the rectifying diodes). This voltage should not exceed the 38V (LT3420) or 50V (LT3420-1) breakdown rating of the power switch. Choose the minimum N by the following formula. N V V LT N V V LT MIN OUT BAT MIN OUT BAT 38 3420 50 3420 1 – () – () For an LT3420 design, a 5V battery voltage and a 330V output results in a NMIN of 10 so a turns ratio of 10 or greater should be used. Transformer Primary Inductance A flyback transformer needs to store substantial amounts of energy in the core during each switching cycle. The transformer, therefore, will generally require an air gap. The use of an air gap in the core makes the energy storage ability, or inductance, much more stable with temperature and variations in the core material. Most core manufactur- ers will supply standard sizes of air gaps with a given type of core, resulting in different A L values. AL is the induc- tance of a particular core per square turns of winding. To get a certain inductance, simply divide the desired induc- tance by the A L value and take the square root of the result to find the number of turns needed on the primary of the transformer. The LT3420/LT3420-1 detect the output voltage via the flyback pulse on the SW pin. Since this can only occur while the power switch is off, an important criteria is that the value of the primary inductance of the transformer be larger than a certain minimum value. The switch off time should be 500ns or larger for the LT3420 and 350ns or larger for the LT3420-1. The minimum inductance can be calculated with the following formula: L V NN LT L V NN LT PRI OUT PRI OUT 500 10 14 00 4 3420 350 10 10 00 1 5 3420 1

• ( . – . ) ()
• ( .–. ) () VOUT: Target Output Voltage N: Transformer Turns Ratio Transformer Leakage Inductance The leakage inductance of the transformer must be care- fully minimized for both proper and efficient operation of the part. The DC voltage rating of the SW pin on the LT3420 is 38V while on the LT3420-1 it is 50V. These ratings are for DC blocking voltages only and additional precautions APPLICATIO S I FOR ATIOWU UU

blocking voltage capability of both parts is 38V. Table 1. SW Pin Voltage Ratings labeled “B” must not exceed the DC rating of the SW pin. current stress on the SW pin.

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Figure 7. New Transformer Design Check (Not to Scale)

APPLICATIO S I FOR ATIOWU UU efficiency of the circuit. In addition, the effective capaci- tance on the primary is largely dominated by the actual secondary capacitance. This is simply a result of any secondary capacitance being multiplied by N 2 when re- flected to the primary. Since N is generally 10 or higher, a small capacitance of 10pF on the secondary is 100 times larger, or 1.0nF, on the primary. This capacitance forms a resonant circuit with the primary leakage inductance of the transformer. As such, both the primary leakage induc- tance and secondary side capacitance should be mini- mized. Table 2 shows various predesigned transformers along with relevant parameters. Contact the individual trans- former manufacturer for additional information or customization. Table 2a. Predesigned Transformers, LT3420 TURNS L SIZE PART RATIO ( µH) LxWxH (mm) VENDOR SRW10EPC 1:12 24 10.9x10.8x5.2 TDK -U01H003 (847) 803-6100 www.components.tdk.com 6375-T108 1:12 15 10.8x9.5x3.6 Sumida (847) 956-0666 www.sumida.com 852-2489-8266 kijimahk@netvigator.com Table 2b. Predesigned Transformers, LT3420-1 TURNS L SIZE PART RATIO ( µH) LxWxH (mm) VENDOR SBL-5.6S-2 1:10 15 5.6x8.5x3.0 Kijima Musen 852-2489-8266 kijimahk@netvigator.com -002 (847) 803-6100 www.components.tdk.com DIODE SELECTION The rectifying diode(s) should be low capacitance type with sufficient reverse voltage and forward current rat- ings. The peak reverse voltage that the diode(s) will see is approximately: VPK-R ≈ +()VN VOUT BAT(• ) •. 16 5 The peak current of the diode is simply: I I PK-SEC PK-SEC = − 14 3420 10 3420 1 . () . () A N LT A N LT For the circuit of Figure 1 with VBAT of 3.3V, VPK-R is 590V and IPK-SEC is 116mA. Table 3 shows various diodes that can work with the LT3420/LT3420-1. These are chosen for low capacitance and high reverse blocking voltage. Use the appropriate number of diodes to achieve the necessary reverse breakdown voltage. Table 3 MAX REVERSE CAPACITANCE PART VOLTAGE (V) (pF) VENDOR GSD2004S 2x300 5 Vishay (Dual diode) (402) 563-6866 www.vishay.com BAS21 250 1.5 Philips Semiconductor (Single diode) (800) 234-7381 www.philips.com MMBD3004S 2x300 5 Diodes Inc. (805) 446-4800 www.diodes.com

the CHARGE pin is brought low, which disables the part. pin is brought high and the charging operation continues. errors associated with the non-ideal photoflash capacitor. Figure 8. Halting the Charge Cycle at Any Time

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overrides the refresh timer. cycle of the PWM signal is varied. Figure 9. Simple Logic for Adjustable Input Current Figure 10. Input Current as Duty Cycle is Varied

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close to the part. This insures adequate bypassing. this circuit. Use caution when working with the circuit. Figure 11. Suggested Layout (MS10 Package)

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Figure 12. Suggested Layout (DD Package)

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4.7µF 0.1µF 4.7µF VBAT 1.8V TO 6V VCC 2.5V TO 10V 52.3k 10 5 10 5 1:12 320V 3, 4 5, 6 8 C1, C2, C4, C5, C6, C7: 4.7µF, X5R or X7R, 10V T1-T3: TDK SRW10EPC-U01H003 FLYBACK TRANSFORMER D1-D3: VISHAY GSD2004S SOT-23 DUAL DIODE. DIODES CONNECTED IN SERIES Q1: 2N3904 OR EQUIVALENT * CAN CHARGE ANY SIZE PHOTOFLASH CAPACITOR ** USE AS MANY SLAVE CHARGERS AS NEEDED. DANGER HIGH VOLTAGE OPERATION BY HIGH VOLTAGE TRAINED PERSONEL ONLY 650µF* 350V PHOTOFLASH CAPACITOR VCC CHARGE DONE SEC RREF LT3420 VBAT RFB SW CT GND 4.7µF 4.7µF VBAT 1:123, 4 5, 6 3, 4 5, 6 10 5 SLAVE CHARGER MASTER CHARGER SLAVE CHARGER VCC CHARGE DONE SEC RREF LT3420 VBAT RFB SW CT GND 4.7µF 4.7µF VBAT 1:12 100k 100k VCC VCC 2N3904 CHARGE TYPICAL APPLICATIO SU Professional Charger uses Multiple LT3420 Circuits in Parallel to Charge Large Photoflash Capacitors Quickly

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4.7µF 0.1µF 4.7µF VBAT 1.8V TO 5V VCC 2.5V TO 10V CHARGE DONE 47.5k T1* 1:12 300V 1 3 C1: 4.7µF, X5R or X7R, 6.3V C2: 4.7µF, X5R or X7R, 10V C4: RUBYCON 220µF PHOTOFLASH CAPACITOR D1: VISHAY GSD2004S SOT-23 DUAL DIODE. DIODES CONNECTED IN SERIES T1: KIJIMA MUSEN SBL-6.4 * MAXIMUM AMBIENT TEMPERATURE OF 60°C DICTATED BY TRANSFORMER DANGER HIGH VOLTAGE OPERATION BY HIGH VOLTAGE TRAINED PERSONEL ONLY 220µF 330V PHOTOFLASH CAPACITOR 10 5 632 VOUT (V) EFFICIENCY (%) 100 150 200 250

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VIN = 3.3V VCC = VBAT = VIN VIN = 5V Efficiency LT3420 Photoflash Charging Circuit Uses Small Transformer

(Reference LTC DWG # 05-08-1661) MSOP (MS) 0603 0.53 ± 0.152 (.021 ± .006) SEATING PLANE 0.18 (.007) 1.10 (.043) MAX 0.17 – 0.27 (.007 – .011) TYP 0.127 ± 0.076 (.005 ± .003) 0.86 (.034) REF 0.50 (.0197) BSC 12 3 45 4.90 ± 0.152 (.193 ± .006) 0.497 ± 0.076 (.0196 ± .003) REF8910 7 6 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.254 (.010) 0° – 6° TYP DETAIL “A” DETAIL “A” GAUGE PLANE 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 0.889 ± 0.127 (.035 ± .005) RECOMMENDED SOLDER PAD LAYOUT 0.305 ± 0.038 (.0120 ± .0015) TYP 0.50 (.0197) BSC

10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTIO U 3.00 ±0.10 (4 SIDES) NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.38 ± 0.10 BOTTOM VIEW—EXPOSED PAD 1.65 ± 0.10 (2 SIDES) 0.75 ±0.05 R = 0.115 TYP 2.38 ±0.10 (2 SIDES) 106 PIN 1 TOP MARK (SEE NOTE 6)

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0.00 – 0.05 (DD10) DFN 1103 0.25 ± 0.05 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 1.65 ±0.05 (2 SIDES)2.15 ±0.05 0.50 BSC 0.675 ±0.05 3.50 ±0.05 PACKAGE OUTLINE 0.25 ± 0.05

0.50 BSC

PART NUMBER DESCRIPTION COMMENTS LTC 3400/LTC3400B 600mA (I SW), 1.2MHz, Synchronous Step-Up V IN = 0.85V to 5V, VOUT(MAX) = 5V, IQ = 19µA/300µA, DC/DC Converters I SD = <1µA, ThinSOT TM Package LTC3401/LTC3402 1A/2A (I SW), 3MHz, Synchronous Step-Up V IN = 0.5V to 5V, VOUT(MAX) = 6V, IQ = 38µA, ISD = <1µA, DC/DC Converters MS Package LTC3405/LTC3405A 300mA (I OUT), 1.5MHz, Synchronous Step-Down 95% Efficiency, V IN = 2.7V to 6V, VOUT(MIN) = 0.8V , IQ = 20µA, DC/DC Converters I SD = <1µA, ThinSOT Package LTC3406/LTC3406B 600mA (I OUT), 1.5MHz, Synchronous Step-Down 95% Efficiency, V IN = 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 20µA, DC/DC Converters I SD = <1µA, ThinSOT Package LTC3407 Dual 600mA (I OUT), 1.5MHz, Synchronous Step-Down 95% Efficiency, V IN = 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40µA, DC/DC Converter I SD = <1µA, ThinSOT Package LTC3411 1.25A (I OUT), 4MHz, Synchronous Step-Down 95% Efficiency, V IN = 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60µA, DC/DC Converter I SD = <1µA, MS Package LTC3425 5A (I SW), 8MHz, Multiphase Synchronous Step-Up 95% Efficiency, V IN = 0.5V to 4.5V, VOUT(MIN) = 5.25V, IQ = 12µA, DC/DC Converter I SD = <1µA, QFN Package LTC3440/LTC3441 600mA/1A (I OUT), 2MHz/1MHz, Synchronous Buck-Boost 95% Efficiency, V IN = 2.5V to 5.5V, VOUT(MIN) = 2.5V, IQ = 25µA, DC/DC Converters I SD = <1µA, MS Package LT3464 85mA (I SW), Constant Off-Time, High Efficiency V IN = 2.3V to 10V, VOUT(MAX) = 34V, IQ = 25µA, ISD = <0.5µA, Step-Up DC/DC Converter with Integrated Schottky ThinSOT Package and Output Disconnect LTC3467 1.1A (I SW), 1.3MHz, High Efficiency Step-Up V IN = 2.4V to 16V, VOUT(MAX) = 40V, IQ = 1.2mA, ISD = <1µA, DC/DC Converter ThinSOT Package LTC3468/LTC3468-1/ Photoflash Capacitor Charger in ThinSOT Fast Photoflash Charge Times; 4.6sec for LT3468, 5.5sec for LTC3468-2 LT3468-1, 5.7sec for LT3468-2 ThinsSOT is a trademark of Linear Technology Corporation. Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2002 LT/LT 0305 REV B • PRINTED IN USA RELATED PARTS LT3420-1 Photoflash Circuit Uses Tiny (3mm Tall) Transformer

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4.7µF 0.1µF 4.7µF VBAT 1.8V TO 6V VCC 2.5V TO 6V CHARGE DONE 60.4k 1:10.2 320V 5 4 C1, C2: 4.7µF, X5R or X7R, 6.3V C3: RUBYCON 100µF PHOTOFLASH CAPACITOR T1: TDK LDT565630T-002 FLYBACK TRANSFORMER D1: VISHAY GSD2004S SOT-23 DUAL DIODE. DIODES CONNECTED IN SERIES DANGER HIGH VOLTAGE OPERATION BY HIGH VOLTAGE TRAINED PERSONEL ONLY 100µF 330V PHOTOFLASH CAPACITOR 10 5 632 VBAT (V) TIME (s)

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COUT = 100µF COUT = 40µF Charge Time UTYPICAL APPLICATIO