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Rev. AFor more information www.analog.comDocument Feedback TYPICAL APPLICATION FEATURES DESCRIPTION Multioutput Power Management Solution with Four Buck Switching and Thr ee LDO Linear Regulators with I2C The LT®3380 is a complete power management solution for advanced portable application processor-based sys - tems. The device contains four synchronous step-down DC/DC converters for core, memory, I/O, and system on- chip (SoC) rails and three 300mA LDO regulators for low noise analog supplies. An I 2C serial port may be used to control regulator enables, power-down sequencing, output voltage levels, dynamic voltage scaling, operating modes, and status reporting. Regulator start-up is sequenced by connecting outputs to enable pins in the desired order or via the I 2C port. The LT3380 outputs may be sequenced off in one of four time slots selected using I2C command registers. The device is available in a 40-lead 6mm × 6mm QFN with wettable flanks for optical inspection. Start-Up Sequence
APPLICATIONS
n Quad I2C Adjustable High Efficiency Step-Down DC/DC Converters: 2.5A, 2.5A, 1.5A, 1.5A n Three 300mA LDO Regulators (T wo Adjustable) n Independent Enable Pin-Strap or I2C Sequencing n Programmable Autonomous Power-Down Control n Warnings and Faults n IRQ Pin and IRQ Status Register n Power Good Pin and Status Register n 150°C TJ Operation (LT3380H) n Dynamic Voltage Scaling n Selectable 2.25MHz or 1.12MHz Switching Frequency n 12µA Standby Current n Side Wettable 40-Lead 6mm × 6mm QFN Package n Automotive n Industrial n Communications n General Purpose Multichannel Power Supplies 1µF 1.8V 300mA 1.8V TO VIN 1.6V TO 5.5V 1µF 300mA 1.7V TO VIN 1.7V TO VIN 1µF 47µF300mA 2.5A LDO1 LDO2 LDO3 DVDD FB_L1 FB_B1 FB_L2 SW1 L T3380 2.7V TO 5.5V VIN VIN_L1 VIN_L2 VIN_L3 1µH
3380 TA01a
PWR_ON PGOOD IRQ I2C7 47µF 2.5A FB_B2 SW2 1µH 47µF 1.5A FB_B3 SW3 1µH 47µF 1.5A FB_B4 SW4 1µH All registered trademarks and trademarks are the property of their respective owners. PWR_ON 1ms/DIV LDO1 BUCK1 AND BUCK2 BUCK4 LDO2 BUCK3
3380 TA01b
Rev. A For more information www.analog.com PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS LDO1, FB_L1, LDO2, FB_L2, LDO3, FB_B1, FB_B2, FB_B3, FB_B 4, PGOOD, EN_B1, EN_B2, EN_B3, EN_B4, 3V to 6V 3V to DVDD + 0.3V Operating Junction Temperature Range C to 150°C C to 150°C (Note 1) LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3380EUJM#PBF LT3380EUJM#TRPBF LT3380UJM 40-Lead Plastic Side Wettable QFN (6mm 6mm) –40°C to 125°C LT3380IUJM#PBF LT3380IUJM#TRPBF LT3380UJM 40-Lead Plastic Side Wettable QFN (6mm 6mm) –40°C to 125°C LT3380HUJM#PBF LT3380HUJM#TRPBF LT3380UJM 40-Lead Plastic Side Wettable QFN (6mm 6mm) –40°C to 150°C AUTOMOTIVE PRODUCTS** LT3380IUJM#WPBF LT3380IUJM#WTRPBF LT3380UJM 40-Lead Plastic Side Wettable QFN (6mm 6mm) –40°C to 125°C LT3380HUJM#WPBF LT3380HUJM#WTRPBF LT3380UJM 40-Lead Plastic Side Wettable QFN (6mm 6mm) –40°C to 150°C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. **Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. ORDER INFORMATION 3940 38 37 36 35 34 33 32 31 11 2012 13 14 15 TOP VIEW GND UJM PACKAGE 40-LEAD (6mm × 6mm) PLASTIC QFN TJMAX = 150°C, θJA = 33°C/W, θJC = 2°C/W EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB 16 17 18 19 FB_L2 VIN_L2 LDO2 LDO3 VIN_L3 LDO1 VIN_L1 FB_L1 EN_L1 EN_L3 EN_L2 GND GND V IN GND FB_B3 FB_B4 FB_B1 FB_B2 PWR_ON SW4 PGOOD GND EN_B4 PV IN4 PVIN3 EN_B3 GND IRQ SW3 SW1 DV DD SDA SCL PVIN1 PVIN2 EN_B1 EN_B2 GND SW2
Rev. AFor more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = PVIN1 = PVIN2 = PVIN3 = PVIN4 = VIN_L1 = VIN_L2 = VIN_L3 = DVDD = 3.8V. All regulators disabled unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS Operating Input Supply Voltage, VIN l 2.7 5.5 V VIN Standby Current PWR_ON = 0V l 12 21 µA VIN Undervoltage Fault Rising (Note 7) VIN Undervoltage Fault Falling l l 2.35 2.55 2.45 2.65 V V VIN Undervoltage Warning Falling CNTRL[4:2] = 000 (POR Default) CNTRL[4:2] = 001 CNTRL[4:2] = 010 CNTRL[4:2] = 011 CNTRL[4:2] = 100 CNTRL[4:2] = 101 CNTRL[4:2] = 110 CNTRL[4:2] = 111 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 V V V V V V V V Step-Down Switching Regulators 1, 2, 3 and 4 Output Voltage Range l VFB PVIN V Burst Mode VIN Quiescent Current Pulse-Skipping Mode VIN Quiescent Current Forced Continuous VIN Quiescent Current VFB_Bx = 850mV (Note 5) VFB_Bx = 850mV (Note 5) VFB_Bx = 0V (Note 5) l l l 120 170 200 300 µA µA µA Feedback Pin Input Current V FB_Bx = 850mV –0.05 0.05 µA Maximum Duty Cycle VFB_Bx = 0V l 100 % Minimum Duty Cycle l 18 24 % SW Pull-Down Resistance Regulator Disabled 625 Ω Feedback Reference Soft-Start Rate (Note 6) 0.8 V/ms High Feedback Regulation Voltage (VFB) DVBxA[4:0] = DVBxB[4:0] = 11111, VIN = 2.7V to 5.5V l 788 800 812 mV Default Feedback Regulation Voltage (VFB) DVBxA[4:0] = DVBxB[4:0] = 11001, VIN = 2.7V to 5.5V l 714 725 736 mV Low Feedback Regulation Voltage (VFB) DVBxA[4:0] = DVBxB[4:0] = 00000, VIN = 2.7V to 5.5V l 404 412.5 421 mV Feedback LSB Step Size 12.5 mV Switching Frequency BUCKx[2] = 0 BUCKx[2] = 1 l l 1.7 0.85 2.25 1.125 2.7 1.35 MHz MHz 1.5A Step-Down Switching Regulators 3 and 4 PMOS Current Limit l 2.0 A PMOS On-Resistance 160 mΩ NMOS On-Resistance 80 mΩ 2.5A Step-Down Switching Regulators 1 and 2 PMOS Current Limit l 3.0 A PMOS On-Resistance 120 mΩ NMOS On-Resistance 70 mΩ LDO Regulators 1, 2 and 3 Feedback Reference Soft-Start Rate 10 V/ms Output Pull-Down Resistance Regulator Disabled 625 Ω LDO Regulators 1 and 2 V IN_Lx Input Voltage l 1.7 VIN V Output Voltage Range ILDO = 0mA VFB VIN_Lx V
Rev. A For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = PVIN1 = PVIN2 = PVIN3 = PVIN4 = VIN_L1 = VIN_L2 = VIN_L3 = DVDD = 3.8V. All regulators disabled unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS Available Output Current l 300 mA VIN_Lx Quiescent Current VIN_Lx Shutdown Current Regulator Enabled, ILDO = 0A Regulator Disabled l l µA µA VIN Quiescent Current Regulator Enabled l 50 85 µA Feedback Regulation Voltage l 0.707 0.725 0.743 V Line Regulation ILDO =1mA, VIN = 2.7V to 5.5V 0.01 %/V Load Regulation ILDO = 1mA to 300mA 0.01 % Short-Circuit Current Limit 770 mA Dropout Voltage (Note 4) ILDO = 300mA, VLDO = 2.5V ILDO = 300mA, VLDO = 1.2V 210 450 260 615 mV mV Feedback Pin Input Current V FB_Lx = 725mV –0.05 0.05 µA LDO Regulator 3 VIN_L3 Input Voltage l 2.35 VIN V Output Voltage ILDO = 1mA l 1.746 1.8 1.854 V Available Output Current l 300 mA VIN_L3 Quiescent Current VIN_L3 Shutdown Current Regulator Enabled, ILDO = 0A Regulator Disabled l l µA µA VIN Quiescent Current Regulator Enabled l 50 85 µA Line Regulation ILDO =1mA, VIN = 2.7V to 5.5V 0.01 %/V Load Regulation ILDO = 1mA to 300mA 0.05 % Short-Circuit Current Limit 770 mA Dropout Voltage (Note 4) ILDO = 300mA, VLDO = 1.8V 280 350 mV Enable Inputs Threshold Rising All Enables Low l 0.75 1.2 V Threshold Falling One Enable High l 0.4 0.7 V Precision Threshold One or More Regulators Previously Enabled l 0.370 0.400 0.430 V Input Pull-Down Resistance 4.5 MΩ PWR_ON Threshold l 0.370 0.400 0.430 V Pull-Down Resistance 4.5 MΩ PWR_ON High to Allow Enables Delay 3 ms PWR_ON High to Inhibit Enables Delay 3 ms Inhibit Enable Time from PWR_ON Low 1 s Status Output Pins (PGOOD, IRQ) IRQ Output Low Voltage I IRQ = 3mA 0.1 0.4 V IRQ Output High Leakage Current IIRQ = 3.8mA –0.1 0.1 µA PGOOD Output Low Voltage IPGOOD = 3mA 0.1 0.4 V PGOOD Output High Leakage Current VPGOOD = 3.8V –0.1 0.1 µA PGOOD Threshold Rising PGOOD Threshold Falling
Rev. AFor more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = PVIN1 = PVIN2 = PVIN3 = PVIN4 = VIN_L1 = VIN_L2 = VIN_L3 = DVDD = 3.8V. All regulators disabled unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I2C Port DVVDD DVDD Input Supply Voltage l 1.6 5.5 V IDVDD DVDD Quiescent Current SCL/SDA = 0kHz 0.3 1 µA DVVDD_UVLO DVDD UVLO Level 1 V ADDRESS LT3380 Device Address 0111100[R/W] VIH SDA/SCL Input Threshold Rising 70 %DVDD VIL SDA/SCL Input Threshold Falling 30 %DVDD IIH SDA/SCL High Input Current SDA = SCL = 5.5V –1 0 1 µA IIL SDA/SCL Low Input Current SDA = SCL = 0V –1 0 1 µA VOL_SDA SDA Output Low Voltage ISDA = 3mA 0.4 V fSCL Clock Operating Frequency 400 kHz tBUF Bus Free Time Between Stop and Start Condition 1.3 µs tHD, STA Hold Time After Repeated Start Condition 0.6 µs tSU, STA Repeated Start Condition Setup Time 0.6 µs tSU, STO Stop Condition Setup Time 0.6 µs tHD, DAT(O) Data Hold Time Output 0 900 ns tSU, DAT Data Setup Time 100 ns tLOW SCL Clock Low Period 1.3 µs tHIGH SCL Clock High Period 0.6 µs tf Clock/Data Fall Time CB = Capacitance of BUS Line (pF) 20 + 0.1C B 300 ns tr Clock/Data Rise Time CB = Capacitance of BUS Line (pF) 20 + 0.1C B 300 ns tSP Input Spike Suppression Pulse Width 50 ns Note 1: Stresses beyond those listed Under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3380 is tested under pulsed load conditions such that T J ≈ TA. The LT3380E is guaranteed to meet specifications from 0°C to 85°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3380I is guaranteed over the –40°C to 125°C operating junction temperature range and the LT3380H is guaranteed over the full –40°C to 150°C operating junction temperature range. High junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125°C. The junction temperature (T J in °C) is calculated from the ambient temperature (TA in °C) and power dissipation (PD, in Watts), and package to junction ambient thermal impedance (JA in Watts/°C ) according to the formula: TJ = TA + (PD • JA). Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Note 3: The LT3380 includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 150°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 4: Dropout voltage is defined as (V IN_Lx – VLDOx) when VLDOx is 3% lower than VLDOx measured with VIN = VIN_Lx = 4.3V. Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. Note 6: Soft-Start measured in test mode with regulator error amplifier in unity-gain mode. Note 7: The LT3380 will operate before VIN has risen higher than VIN undervoltage fault rising (2.65V max) but will shutdown if VIN does not cross the rising threshold in less than 5 seconds. Please refer to the Operation section.
Rev. A For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Standby IVIN vs VIN LDO1 to LDO3 IVIN vs VIN Step-Down Switching Regulator IVIN vs VIN Step-Down Switching Regulator I VIN vs VIN Input Supply Current vs Temperature Oscillator Frequency vs Temperature V IN = 3.8V, TA = 25°C unless otherwise noted VIN (V) 2.5 IVIN (µA)8
3380 G01
5.5 VIN (V) 2.50 IVIN (µA) 100 150
3380 G02
3.50 4.50 5.50 250 200 ENABLE 3 LDOs ENABLE 2 LDOs ENABLE 1 LDO VIN (V) 2.5 IVIN (µA) 100 300 400 500 4.5 900
3380 G03
VIN (V) 2.5 IVIN (µA) 100 4.5 180
3380 G04
TEMPERATURE (°C) –50 IVIN (µA) 200 400 600 800 1000 1200 0 50 PULSE-SKIPPING STANDBY Burst Mode OPERATION 100 150
3380 G05
TEMPERATURE (°C) –50
2.00 FREQUENCY (MHz)
2.05 2.10 2.15 2.20 2.25 2.30 0 50 100 150
3380 G06
VIN (V) 2.5 PERCENT CHANGE (%)
3380 G07
–0.4 –0.8 0.4 0.8 –0.2 –0.6 0.2 0.6 5.5 IOUT (mA) EFFICIENCY (%) 10 100
3380 G08
VIN = 3.3V VOUT = 1.2V IOUT (mA) EFFICIENCY (%) 10 100
3380 G09
VIN = 5V VOUT = 1.2V Oscillator Frequency Change vs VIN Step-Down Switching Regulators 3 and 4 Efficiency vs I OUT Step-Down Switching Regulators 3 and 4 Efficiency vs I OUT
Rev. AFor more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Step-Down Switching Regulators 1 and 2 Efficiency vs IOUT Buck RDS(ON) vs Temperature Buck RDS(ON) vs VIN Step-Down Switching Regulator Load Step Step-Down Switching Regulator Current Limit vs Temperature IOUT (mA) EFFICIENCY (%) VOUT = 2.5V 10 100
3380 G10
VIN = 3.3V PULSE-SKIPPING MODE VOUT = 1.2V TEMPERATURE (°C) –50 RDS(ON) (m/uni03A9) 100 150 150
3380 G11
BUCK 3, 4 PMOS BUCK 3, 4 NMOS BUCK 1, 2 NMOS BUCK 1, 2 PMOS VIN (V) 2.5 RDS(ON) (m/uni03A9) 100 200 140 3.5 4.5
3380 G12
5.5 BUCK 3, 4 PMOS BUCK 1, 2 PMOS BUCK 1, 2 NMOS BUCK 3, 4 NMOS TEMPERATURE (°C) –50 1.5 CURRENT (A) 2.0 2.5 3.0 3.5 4.0 4.5 0 50 100 150
3380 G13
BUCK 1, 2 BUCK 3, 4 100mV/DIV 500mA/DIV 10µs/DIVCOUT = 47µF 3380 G14 VOUT = 1.2V ILOAD = 0.5A TO 1.5A Buck Minimum Duty Cycle vs VIN Buck Minimum Duty Cycle vs Temperature TEMPERATURE (°C) –50 100 150 DUTY CYCLE (%)
3380 G15
V = 3.8V IN V = 5.0V IN VIN (V) 2.5 3.5 4.5 5.5 DUTY CYCLE (%)
3380 G16
LDO1 to LDO3 Dropout Voltage vs Temperature TEMPERATURE (°C) –50 DROPOUT VOLTAGE (mV) 250 300 350 150
3380 G17
VLDO = 1.2V VLDO = 1.8V VLDO = 3.3V 400 ILDO = 200mA
Rev. A For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Buck Minimum Duty Cycle vs VIN VIN (V) 2.5 3.5 4.5 5.5 DUTY CYCLE (%) LDO1 to LDO3 Dropout Voltage vs Temperature TEMPERATURE (°C) –50 DROPOUT VOLTAGE (mV) 250 300 350 150 VLDO = 1.2V VLDO = 1.8V VLDO = 3.3V 400 ILDO = 200mA LDO1 to LDO3 Short-Circuit Current vs Temperature TEMPERATURE (°C) –50
300 LDO SHORT-CIRCUIT CURRENT (mA)350
3380 G18
LDO1 to LDO3 Load Step Response 50mV/DIV VLDO = 1.8V ILOAD = 220mA 10mA 100mA/DIV 10µs/DIV 3380 G19CLDO = 1µF
Rev. AFor more information www.analog.com PIN FUNCTIONS FB_L2 (Pin 1): Feedback Input for LDO2. Set output volt- age using a resistor divider connected from LDO2 to this pin to ground. VIN_L2 (Pin 2): Power Input for LDO2. This pin should be bypassed to ground with a 1μF or greater ceramic capacitor . Voltage on VIN_L2 should not exceed voltage on VIN pin. LDO2 (Pin 3): Output Voltage of LDO2. Nominal output voltage is set with a resistor feedback divider that servos to a fixed 725mV reference. This pin must be bypassed to ground with a 1µF or greater ceramic capacitor . LDO3 (Pin 4): Output Voltage of LDO3. Nominal output voltage is a fixed 1.8V. This pin must be bypassed to ground with a 1µF or greater ceramic capacitor . VIN_L3 (Pin 5): Power Input for LDO3. This pin should be bypassed to ground with a 1µF or greater ceramic capacitor . Voltage on VIN_L3 should not exceed voltage on VIN pin. LDO1 (Pin 6): Output Voltage of LDO1. Nominal output voltage is set with a resistor feedback divider that servos to a fixed 725mV reference. This pin must be bypassed to ground with a 1µF or greater ceramic capacitor . VIN_L1 (Pin 7): Power Input for LDO1. This pin should be bypassed to ground with a 1μF or greater ceramic capacitor . Voltage on VIN_L1 should not exceed voltage on VIN pin. FB_L1 (Pin 8): Feedback Input for LT3380 LDO1. Set output voltage using a resistor divider connected from LDO1 to this pin to ground. EN_L1 (Pin 9): Enable LDO1 Input for LT3380. Active high enables LDO1. A weak pull-down pulls EN_L1 low when left floating. EN_L3 (Pin 10): Enable LDO3 Input. Active high enables LDO3. A weak pull-down pulls EN_L3 low when left floating. SW1 (Pin 11): Switch Pin for Step-Down Switching Regulator 1. Connect one side of step-down switching regulator 1 inductor to this pin. DVDD (Pin 12): Supply Voltage for I 2C Serial Port. This pin sets the logic reference level of SCL and SDA I 2C pins. DVDD resets I 2C registers to power-on state when driven to < 1V. SCL and SDA logic levels are scaled to DVDD. Connect a 0.1µF decoupling capacitor from this pin to ground. SDA (Pin 13): Data Pin for the I 2C Serial Port. The I 2C logic levels are scaled with respect to DVDD. SCL (Pin 14): Clock Pin for the I 2C Serial Port. The I 2C logic levels are scaled with respect to DVDD. PVIN1 (Pin 15): Power Input for Step-Down Switching Regulator 1. Tie this pin to V IN supply. This pin should be bypassed to ground with a 10μF or greater ceramic capacitor . PVIN2 (Pin 16): Power Input for Step-Down Switching Regulator 2. Tie this pin to the VIN supply. This pin should be bypassed to ground with a 10μF or greater ceramic capacitor . EN_B1 (Pin 17): Enable Step-Down Switching Regulator 1. Active high input enables step-down switching regulator 1. A weak pull-down pulls EN_B1 low when left floating. EN_B2 (Pin 18): Enable Step-Down Switching Regulator 2. Active high input enables step-down switching regulator 2. A weak pull-down pulls EN_B2 low when left floating. GND (Pins 19/26/28/29/33/38): Ground. SW2 (Pin 20): Switch Pin for Step-Down Switching Regulator 2. Connect one side of step-down switching regulator 2 inductor to this pin. PWR_ON (Pin 21): Power On. PWR_ON is a master enable and disable input. When low, PWR_ON inhibits the regulator enable pins. When high, PWR_ON allows enable pin operation. FB_B2 (Pin 22): Feedback Input for Step-Down Switching Regulator 2. Set output voltage using resistor divider con- nected from the output of step-down switching regulator 2 to this pin to ground.
Rev. A For more information www.analog.com PIN FUNCTIONS FB_B1 (Pin 23): Feedback Input for Step-Down Switching Regulator 1. Set output voltage using resistor divider connected from the output of step-down switching regu- lator 1 to this pin to ground. FB_B4 (Pin 24): Feedback Input for Step-Down Switching Regulator 4. Set output voltage using resistor divider con- nected from the output of step-down switching regulator 4 to this pin to ground. FB_B3 (Pin 25): Feedback Input for Step-Down Switching Regulator 3. Set output voltage using resistor divider con- nected from the output of step-down switching regulator 3 to this pin to ground. VIN (Pin 27): Supply Voltage Input. This pin should be bypassed to ground with a 1μF or greater ceramic capaci- tor . All switching regulator PVIN supplies should be tied to VIN. EN_L2 (Pin 30): Enable LDO2 Input. Active high enables LDO2. A weak pull-down pulls EN_L2 low when left floating. SW3 (Pin 31): Switch Pin for Step-Down Switching Regulator 3. Connect one side of step-down switching regulator 3 inductor to this pin. IRQ (Pin 32): Interrupt Request Output. Open-drain driver is pulled low for power good, undervoltage, and over - temperature warning and fault conditions. Clear IRQ by writing to the I2C CLIRQ command register . EN_B3 (Pin 34): Enable Step-Down Switching Regulator 3. Active high input enables step-down switching regulator 3. A weak pull-down pulls EN_B3 low when left floating. PVIN3 (Pin 35): Power Input for Step-Down Switching Regulator 3. Tie this pin to VIN supply. This pin should be bypassed to ground with a 10μF or greater ceramic capacitor . PVIN4 (Pin 36): Power Input for Step-Down Switching Regulator 4. Tie this pin to VIN supply. This pin should be bypassed to ground with a 10μF or greater ceramic capacitor . EN_B4 (Pin 37): Enable Step-Down Switching Regulator 4. Active high enables step-down switching regulator 4. A week pull-down pulls EN_B4 low when left floating. PGOOD (Pin 39): Power Good Output. Open-drain output pulls low when any enabled regulator falls below power good threshold or during dynamic voltage slew unless disabled in command register . Pulls low when all regula- tors are disabled. SW4 (Pin 40): Switch Pin for Step-Down Switching Regulator 4. Connect one side of step-down switching regulator 4 inductor to this pin. GND (Exposed Pad Pin 41): Ground. The exposed pad must be connected to a continuous ground plane of the printed circuit board by multiple interconnect vias directly under the LT3380 to maximize electrical and thermal conduction.
Rev. AFor more information www.analog.com BLOCK DIAGRAM BUCK1 VREF EN OK DEFAUL T = 725mV RANGE = 800mV TO 412.5mV PVIN1 SW1 FB_B1 DAC VIN BUCK2 VREF EN OK DEFAUL T = 725mV RANGE = 800mV TO 412.5mV PV IN2 SW2 FB_B2 DAC BUCK3 VREF EN OK DEFAUL T = 725mV RANGE = 800mV TO 412.5mV PV IN3 SW3 FB_B3 DAC BUCK4 LDO1 VREF EN OK DEFAUL T = 725mV RANGE = 800mV TO 412.5mV PRECISION ENABLE THRESHOLD AND SEQUENCE DELAY PV IN4 SW4 VIN_L1 LDO1 FB_B4 VREF 725mV EN OK FB_L1 DAC LDO2 VIN_L2 LDO2 VREF EN OKGND (EXPOSED PAD) FB_L2 3380 BD LDO3 VIN_L3 LDO3 VREF EN OK EN_B1 PWR_ON EN_B2 EN_B3 I2C COMMAND REGISTERS DVDD DYNAMIC VOL TAGE SCALING FAUL T DETECTION UNDER VOL TAGE OVER TEMPERATURE SDA SCL EN_B4 EN_L2 EN_L3 EN_L1 IRQ PGOOD VSEL VA 4x5 VB 4x5
age regulator . It generates a total of seven voltage rails. and extensive status and interrupt outputs. VIN_L2, and VIN_L3 must be at a potential of VIN or less. Figure 1. LDO1 and LDO2 Application Circuit
3380 F01
Table 1. LDO Control Command Register Settings start, and switch slew rate control for lower radiated EMI. controlled using the I2C port. shown in Table 2, Table 3, Table 4, and Table 5.
Table 2. Buck1 Control Command Register Table 3. Buck2 Control Command Register Table 4. Buck3 Control Command Register Table 5. Buck4 Control Command Register
3380 F02
Figure 2. Step-Down Switching Regulator Application Circuit load but operates at constant frequency at higher loads. the buck regulator has the ability to sink output current. output voltage ripple at light load. FB pin and helps to improve load step transient response. A value of 10pF is recommended. counters the efficiency advantage of reduced peak current. gives ripple equal to 30% of the maximum output current. switching losses at the expense of a larger inductor .
halved to accommodate a high VIN to VOUT ratio. I2C command register settings (see Figure 3). of the DAC is slewed at 3.5mV/µs to the new value. Table 6. Buck1, Buck2, Buck3, and Buck4 Slewing DAC Control Figure 3. Phase Settings Full- and Half-Speed Buck Clock
3380 F03
of command register mode settings.
Figure 4. Dynamic Voltage Scaling and the PGSTAT register is not affected. ship between PWR_ON and inhibition of the enable pins. Figure 5. LT3380 Operating Mode State Diagram
1 SEC OFF
3380 F05
3380 F06
Figure 6. Power Up and Down with PWR_ON state. In the POR/HRST state VIN draws typically 12µA. 0.75V (typical) input voltage threshold. start-up timing of the example shown in Figure 7.
3380 F07
Figure 7. Pin-Strapped Power-On Sequence Application
and respond only to I 2C command register bit settings. sequence begins at the next LT3380 power on. fault shutdown resets the keep alive bits.
3380 F08
Figure 8. Pin-Strapped Power-On Sequence Table 7. Sequence Down Control Command Register Settings PWR_ON and Buck1 shuts off 300ms after PWR_ON. and PGSTAT status registers.
to the ON state and the LT3380 will start-up immediately. voltage at which VIN rising undervoltage fault is detected. may be used to ensure VIN is above 2.7V. Table 8. Undervoltage Warning Threshold Command Register *denotes default power-on value. programmable as shown in Table 9. Table 9. Overtemperature Warning Threshold Command enable and low output voltage events. Figure 9. Power-Down Sequence
3380 F09
of the low voltage condition. Table 10. Power Good Status Registers Each regulator has a corresponding bit in the MSKPG register . not masked by the MSKPG bits. Table 11. Power Good Status Masking Command Register Table 12. Interrupt Request Status Register
3380 F10
Figure 10. Output Low Voltage PGOOD and IRQ Timing
IRQSTAT status register and releases the IRQ pin. Table 13. Interrupt Request Mask Command Register bits to their default power-on state. SDA and SCL, are scaled internally to the DV DD supply. commands the LT3380 to act upon its new command set.
significant bit (MSB) first. data returned from the LT3380. know that the latest byte of information was received. releases the SDA line during the acknowledge clock cycle. the HIGH period of this clock pulse. Table 14. LT3380 I2C Read and Write Addresses pointed to by the sub-address. by the LT3380 until a STOP signal is issued.
3380 F11
Figure 11. LT3380 I2C Serial Port Timing
3380 F12
3380 F13
Figure 12. LT3380 I2C Serial Port Multiple Write Pattern Figure 13. LT3380 I2C Serial Port Read Pattern
Table 15. LT3380 Command Registers tus register without the need to re-write its sub-address. address and clocking out the data.
0x1E HRST Hard Reset Command. No Data. Table 16. LT3380 Status Registers
100 W( )
temperature of 118°C at an ambient temperature of 55°C. the switching regulators at three quarters rated current. Table 17. LT3380 Power Loss Example
- Connect the exposed pad of the package (Pin 41)
- The switching regulator input supply traces to their
decoupling capacitors should be as short as possible. from the capacitors to the LT3380 pins.
- Minimize the switching power traces connecting SW1,
the large voltage swings on the switching nodes.
- Minimize the length of the connection between the
Rev. AFor more information www.analog.com TYPICAL APPLICATIONS LT3380 Seven Power Rails VIN 3.5V TO 5V 10pF 22µF 22µF 22µF 22µF 1M 47µF 1.5µH 1µF BUCK3 2.48V 1.5A 412k 4.7k4.7k 68k68k 10pF 1.07M 47µF 0.82µH 10pF 649k 47µF 0.82µH BUCK2 1.5V 2.5A BUCK4 1.81V 1.5A 10pF 1µF 1µF 1M 47µF 1.5µH BUCK1 1.2V 2.5A 665k SW3VIN EN_B1 EN_B2 EN_B3 EN_B4 EN_L2 EN_L3 EN_L1 FB_B3 SW2 FB_B2 SW1 FB_B1 SW4 FB_B4 649k LDO1 FB_L1 1µF LDO3 1µF LDO2 0.8V 300mA LDO3 1.8V 300mA 102k
3380 TA02
FB_L2 GND L T3380 VIN_L1 1µF VIN_L3 1µF VIN_L2 PVIN4PVIN3PVIN2PVIN1 IRQIRQ PGOODPGOOD SCL SCL SDA SDA VCC_MCU PWR_ON DVDD PWR_ON SEQUENCE: BUCK2 BUCK3 LDO2 LDO1 LDO3 BUCK1 BUCK4 BUCK1 VIN BUCK2 LDO2 PWR_ON LDO1 1.2V 300mA
Rev. A For more information www.analog.com PACKAGE DESCRIPTION 6.00 ±0.10 (4 SIDES) NOTE: 1. DRAWING NOT TO SCALE 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 4. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (SEE NOTE 4) PIN 1 NOTCH R = 0.45 OR 0.35 × 45° CHAMFER 0.40 ±0.10 40 39 BOTTOM VIEW—EXPOSED PAD
4.50 REF
(4-SIDES) 4.10 ±0.10 4.10 ±0.10 4.10 ±0.05 4.10 ±0.05 0.75 ±0.05 R = 0.115 TYP 0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05 (UJM40) QFN REV Ø 1218 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 4.50 ±0.05 (4 SIDES) 5.10 ±0.05 6.50 ±0.05 0.25 ±0.05 R = 0.10 TYP 40-Lead Plastic Side Wettable QFN (6mm × 6mm) (Reference LTC DWG # 05-08-1681 Rev Ø)
0.203 REF
0.40 ± 0.10
0.05 REF
0.10 REF
Rev. AFor more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER A 09/21 Add Ordering Information for Automotive Products 2
Rev. A For more information www.analog.com ANALOG DEVICES, INC. 2021 www.analog.com TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS LTC3676/ LTC3676-1 PMIC for Application Processors Quad I 2C Adjustable High Efficiency Step-Down DC/DC Converters: 2.5A, 2.5A, 15A, 1.5A, Three 300mA LDO Regulators (T wo Adjustable), DDR Power Solutions with VTT and VTTR Reference, Pushbutton ON/ OFF Control, LTC3676-1 Supports DDR, 40-Lead 6mm × 6mm × 0.75mm QFN Package. LTC3375 8-Channel Programmable, Parallelable 1A Buck DC/DCs 8-Channel Independent Step-Down DC/DCs. Master Slave Configurable for Up to 4A per Output Channel with a Single Inductor , Die Temperature Monitor Output, 48-Lead 7mm × 7mm QFN Package LTC3589/ LTC3589-1/ LTC3589-2 8-Output Regulator with Sequencing and I T riple I2C Adjustable High Efficiency Step-Down DC/DC Converters: 1.6A, 1A, 1A. High Efficiency 1.2A Buck-Boost DC/DC Converter . T riple 250mA LDO Regulators. Pushbutton ON/OFF Control with System Reset. Flexible Pin-Strap Sequencing Operation. I 2C and Independent Enable Control Pins, DVS and Slew Rate Control, 40-Lead 6mm × 6mm × 0.75mm QFN Package LTC3586/ LTC3586-1 Switching USB Power Manager PMIC with Li-Ion/Polymer Charger Complete Multifunction PMIC: Switching Power Manager , 1A Buck-Boost + 2 Bucks + Boost + LDO, 4mm 6mm QFN-38 Package, LTC3586-1 Version Has 4.1V V FLOAT. Seven Sequenced Power Rails From 40V Input Using LT8609-5 RELATED PARTS BUCK2 10pF 22µF 22µF 22µF 22µF 294k 47µF 1µH 1µF BUCK4 1.8V 1.5A 200k 4.7k4.7k 10pF 130k 47µF 1µH 200k 10pF 178k 47µF 1µH BUCK2 1.2V 2.5A BUCK3 3.3V 1.5A 200k 10pF 1µF 1µF 715k 47µF 1µH BUCK1 1.37V 2.5A200k SW4VIN EN_B1 EN_B2 EN_B3 EN_B4 EN_L2 EN_L3 EN_L1 FB_B4 SW2 FB_B2 SW1 FB_B1 SW3 FB_B3 130k 200k LDO3 1µF LDO1 1µF LDO2 3.3V 300mA LDO1 1.2V 300mA 715k 200k
3380 TA03
FB_L2 GND L T3380 VIN_L3 1µF VIN_L1 1µF VIN_L2 PVIN4PVIN3PVIN2PVIN1 IRQIRQ PGOODPGOOD SCL SCL SDA SDA LD02 PWR_ON DVDD BUCK1 BUCK1 BUCK4 PMIC_OFFPMIC_ON LDO3 1.8V 300mA 0.1µF 4.7µF 1µF 2.2µH 18.2k 10nF VIN EN/UV SYNC L T8609-5 INTVCC TR/SS RT GND PG VOUT SW BST VIN TO 40V ON OFF 47µF V5P0 100k PMIC_ON SEQUENCE: BUCK2 LDO2 BUCK1 BUCK3BUCK4 LDO1 FB_L1