LT3154 (Rev. A)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 32
Technical content
Rev. AFor more information www.analog.com Document Feedback TYPICAL APPLICATION FEATURES DESCRIPTION 5.5V 6A Low-IQ Monolithic Buck-Boost DC/DC Converter The LT®3154 is a highly efficient, high current, buck‑boost DC/DC converter that operates from input voltages above, below or equal to the regulated output voltage. The LT3154’s advanced topology provides a continu ‑ ous transfer through all operating modes. V IN operation from 1.8V to 5.5V provides flexibility for a wide variety of power sources. The output voltage is adjustable between 1.8V to 5.5V. To minimize external components the LT3154 can be configured to operate from a 2.2MHz internal oscillator . To optimize applications for highest efficiency or small ‑ est footprint the oscillator can be programmed between 500kHz to 4MHz, or synchronized to an external clock for noise sensitive circuits. Selectable Burst Mode operation reduces quiescent cur‑ rent to 17μA, ensuring high efficiency across the entire load range. The V IN start‑up threshold (UVLO) can be adjusted for various input sources. An internal or exter ‑ nally programmable soft ‑start limits inrush current during start‑up. Other features include <1μA shutdown current, short circuit, and thermal overload protection. The LT3154 is housed in the thermally enhanced 16‑lead (3mm × 3mm × 0.74mm) LQFN package. Efficiency vs VIN PWM Mode
APPLICATIONS
n Single Inductor Buck-Boost Architecture n Low Noise Buck-Boost Architecture n Wide VIN Range 1.8V to 5.5V n Adjustable VOUT Range 1.8V to 5.5V n 5A of Continuous Output Current with VIN > VOUT n Up to 97% Efficiency n Selectable Internal 2.2MHz Fixed Frequency Adjustable and Synchronizable: Up to 4MHz n Burst Mode® IQ 17µA for High Efficiency at Light Loads n Programmable Soft‑Start and VIN UVLO n Simple Solution with Minimal External Components n Small 3mm × 3mm × 0.74mm LQFN package n Portable Inventory Terminals n Handheld Computers n Medical and Industrial Instruments n Wireless RF T ransmitter n Backup Power Applications n Battery Powered Systems All registered trademarks and trademarks are the property of their respective owners. 0.5A INPUT VOL TAGE (V) 1.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0 5.4 5.8 EFFICIENCY (%)
3154 TA01b
2.2MHz OPERATION VOUT 3.3VVIN 1.8V TO 5.5V BURST
3154 TA01a
22µF COUT 100µF 1nF 40.2k 43.2k 1MΩ 0.68µH EN/UVLO L T3154 RT SS FB VC GND SW1 SW2 PGND SYNC/MODE PVOUT VOUTPVIN VIN
Rev. A For more information www.analog.com PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS Supply Voltages SW1, SW2 Voltage (Notes 4, 6) Operating Junction Temperature Range (Notes 2, 3, 5) (Note 1) ORDER INFORMATION PVIN PVIN VIN EN/UVLO PVOUT VOUT VC FB SYNC/MODE RT GND SS SW1 PGND PGND SW2 16 15 14 13 5 6 7 8 TOP VIEW LQFN PACKAGE 16-LEAD (3mm × 3mm × 0.75mm) TJMAX = 150°C, DEMOBOARD θJA = 22°C/W θJC = 6°C/W , JEDEC θJA = 30°C/W (NOTE 5) EXPOSED PAD (PIN 17) IS PGND, MUST BE SOLDERED TO PCB PGND PART NUMBER TAPE AND REEL PAD OR BALL FINISH PART MARKING* PACKAGE TYPE MSL RATING TEMPERATURE RANGE (SEE NOTE 2)DEVICE FINISH CODE LT3154AV#PBF LT3154AV#TRPBF Au (RoHS) LHGJ e4 LQFN (Laminate Package with QFN Footprint) 3 –40°C to 125°C
- Contact the factory for parts specified with wider operating temperature ranges. *Pad or ball finish code is per IPC/JEDEC J‑STD‑609.
- Parts ending with PBF are RoHS and WEEE compliant.
- The LT3154 package has the same footprint as a standard 3mm × 3mm
- For more information on tape and reel specifications, go to: Tape and reel specifications.
- Recommended LGA and BGA PCB Assembly and Manufacturing Procedures
- LGA and BGA Package and Tray Drawings
Rev. AFor more information www.analog.com
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Operating Voltage EN/UVLO > 1.245V l 1.8 5.5 V VOUT Operating Voltage Adjustable Version with External Divider l 1.8 5.5 V Feedback Voltage l 0.97 0.99 1.01 V VIN/VOUT Currents PWM Mode No‑Load Current – VIN 20 mA Sleep Quiescent Current – VIN SYNC/MODE = 0V, VOUT in Regulation, Non‑Switching 17 30 µA Sleep Quiescent Current – VOUT SYNC/MODE = 0V 1 2 µA Shutdown Current – VIN EN/UVLO = 0V 0.5 2 µA Current in UVLO – VIN EN/UVLO = 1.05V 8 25 µA EN/UVLO Operation EN/UVLO Pin Rising Threshold l 1.155 1.2 1.245 V EN/UVLO Pin Falling Threshold l 1.055 1.1 1.145 V EN/UVLO Pin Input Leakage Current EN/UVLO = 5.5V 1 50 nA EN/UVLO Pin Shutdown Threshold EN/UVLO Pin Voltage l 0.2 0.75 1.05 V Switch Operation Average Inductor Current Limit l 5.4 6.8 8.7 A Peak Inductor Current Limit 8 9.7 12 A IZERO Current SYNC/MODE = 0V –0.3 0 0.3 A Reverse Inductor Current Limit SYNC/MODE = 3.6V –1.8 –1.2 –0.9 A Lowside (B & C) MOSFET RDS(ON) VIN = 3.6V, VOUT = 3.0V 18 mΩ Highside (A & D) MOSFET RDS(ON) VIN = VOUT = 3.6V 25 mΩ Lowside MOSFETs Leakage Currents VSW = 5.5V, EN/UVLO = 0 0.05 2 µA Highside MOSFETs Leakage Current VIN = VOUT = 5.5V, VSW1 = VSW2 = 0V, EN/UVLO = 0 0.1 10 µA Oscillator Operation Switching Frequency RT to VIN or RT = 49.9kΩ l 1.8 2.2 2.6 MHz Switching Frequency Range RT Programmable l 0.5 4 MHz Max Boost Duty Cycle (SW2 Low) RT = VIN, FB = 0.94V l 83 88 95 % Min Duty Cycle (SW1 High) RT = VIN, FB = 1.04V l 0 % SYNC/MODE Applied Clock Frequency RT Chosen to Program a 25% Lower Frequency l 0.5 4 MHz SYNC/MODE High or Low Pulse Width 75 ns SYNC/MODE Input High Logic Level l 1.5 V SYNC/MODE Input Low Logic Level l 0.5 V SYNC/MODE Input Leakage Current SYNC/MODE = 5.5V 1 50 nA Soft-Start Soft‑Start Period (CSS Charge Time to 0.8V) SS = VIN or CSS = 2.7nF 2.2 ms External SS Regulation Voltage Capacitor to GND Sets SS Time 1.0 V Voltage GM Amp Feedback Pin Input Current FB = 1V 0 50 nA VC Source/Sink Current FB = 0.9V Source, FB = 1.1V Sink ±12 µA Error Amplifier T ransconductance VC Current = ±4µA 110 µS The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2), PVIN = VIN = 3.6V, PVOUT = VOUT = 3.3V unless otherwise noted.
Rev. A For more information www.analog.com Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3154 is tested under pulsed load conditions such that TJ ≈TA. The LT3154A is specified over the –40°C to 125°C operating junction temperature. High junction temperatures degrade operating lifetimes; operating lifetime is derated for temperatures greater than 125°C.The maximum ambient temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. The junction temperature (TJ in °C) is calculated from the ambient temperature (TA in °C) and power dissipation (PD in Watts) according to the following formula: TJ = TA + (PD) • (θJA °C/W) Where θJA is the package thermal impedance. Note the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. The maximum rated junction temperature will be exceeded when this protection is active. Continuous operation above the maximum operating junction temperature may impair device reliability or permanently damage the device. Note 4: Specification is guaranteed by design and not 100% tested in production. Note 5: Failure to solder exposed backside of the package to the PC Board will result in a higher thermal resistance Note 6: Voltage transients on the switch pins beyond the DC limits specified in Absolute Maximum Ratings are non‑disruptive to normal operation when using good layout practices as described elsewhere in the data sheet and as seen on the demo board.
Rev. AFor more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Efficiency/Power Loss at 2.2MHz 3.3VOUT, L = 0.68µH Efficiency/Power Loss at 2.2MHz 5.0VOUT, L = 0.68µH Efficiency/Power Loss at 1.2MHz Li-Ion (3.0V, 3.6V, 4.2V) to 3.3VOUT, L = 1µH Efficiency/Power Loss at 2.2MHz 1.8V, 3.6V, 5.0V to 2.5VOUT, L = 0.68µH Burst Mode Operation No-Load Input Current vs VIN PWM Mode Efficiency vs fSW VIN Current in Shutdown Current vs Temperature (TA = 25°C, VIN = 3.6, VOUT = 3.3V unless otherwise specified) PWM Mode No-Load Input Current vs VIN Shutdown vs VIN LOAD CURRENT (A) 0.0001 EFFICIENCY (%)40
3154 G01
0.001 0.01 0.1 1 100 PWM POWER LOSS (W) PWM BURST LOSS 1.8VIN 2.5VIN 3.6VIN 5.0VIN LOAD CURRENT (A) 0.0001 EFFICIENCY (%)40
3154 G02
0.001 0.01 0.1 1 100 PWM POWER LOSS (W) PWM BURST LOSS 1.8VIN 2.5VIN 3.6VIN 5.0VIN LOAD CURRENT (A) 0.0001 EFFICIENCY (%)40
3154 G03
0.001 0.01 0.1 1 100 PWM POWER LOSS (W) PWM BURST LOSS 3.0VIN 3.6VIN 4.2VIN VIN (V) 1.8 2.2 2.6 3.4 3.8 4.2 4.6 5.4 5.0 5.8 VIN CURRENT (µA)
3154 G05
1.8VOUT 3.3VOUT 5.0VOUT SWITCHING FREQUENCY (kHz) 400 800 1200 1600 2000 2400 2800 3200 3600 4000 EFFICIENCY (%)
3154 G06
4.2VIN, 3.3VOUT, 1uH, 1A LOAD LOAD CURRENT (A) 0.0001 EFFICIENCY (%)40
3154 G04
0.001 0.01 0.1 1 100 PWM POWER LOSS (W) PWM BURST LOSS 1.8VIN 3.6VIN 5.0VIN VIN (V) 1.8 2.2 2.6 3.4 3.8 4.2 4.6 5.4 5.0 5.8 VIN CURRENT (mA)
3154 G07
1.8VOUT 3.3VOUT 5.0VOUT FSW = 1MHz VIN (V) 1.8 2.2 2.6 3.4 3.8 4.2 4.6 5.4 5.0 5.8 0.1 0.2 0.3 0.4 0.5 0.6 VIN CURRENT (µA)
3154 G08
TEMPERATURE (°C) –50 CURRENT (µA)1 150
3154 G09
0.5 –10 70 90 110 130–30 10 5030 2.5 1.5 VIN = 3.6V
Rev. A For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Feedback Voltage vs Temperature Maximum Load Current in PWM Mode vs VIN Output Voltage vs ILOAD (TA = 25°C, VIN = 3.6, VOUT = 3.3V unless otherwise specified) Normalized N-/P-Channel Switch Resistance vs Temperature Normalized N-/P-Channel Switch Resistance vs VGATE Peak, Average, Zero and Reverse Limits vs Temperature Burst to PWM Mode Thresholds vs VIN and VOUT VGATE (V) 1.5 2.5 3.5 4.5 5.5 RESISTANCE (m/uni03A9)
3154 G10
TEMPERATURE (°C) –50 –25 100 125 150 RESISTANCE (m/uni03A9)
3154 G11
(VGATE = 5V) VIN (V) 1.8 2.2 2.6 3.4 3.8 4.2 4.6 5.4 5.0 5.8 LOAD CURRENT (A)
3154 G14
1.8VOUT 3.3VOUT 5.0VOUT TEMPERATURE (°C) –50 –25 100 125 150 INDUCTOR CURRENT (A)
3154 G16
V IN (V) 1.8 2.2 2.6 3.4 3.8 4.2 4.6 5.0 5.4 5.8 200 300 400 500 600 700 LOAD CURRENT (mA)
3154 G13
1.8V OUT 3.3V OUT 5.0V OUT LOAD CURRENT (A) 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 OUTPUT VOL TAGE (V)
3681 G15
VIN = 5V TEMPETATURE (°C) -75 -50 -25 100 125 150 175 0.980 0.990 0.985 0.995 1.005 1.015 1.000 1.010 1.020 FB (V)
3154 G12
Rev. AFor more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS 3.3VOUT Load Step, 0.2A to 2A, VIN = 3.3V, SYNC/MODE = 0V Soft-Start Waveforms 3.3Ω Load 3.3VOUT Load Step, 0.15A to 1.5A, VIN = 2.5V, SYNC/MODE = VIN 3.3VOUT Load Step, 0.2A to 2A, VIN = 3.3V, SYNC/MODE = VIN 3.3VOUT Load Step, 0.2A to 2A, VIN = 5.0V, SYNC/MODE = VIN (TA = 25°C, VIN = 3.6, VOUT = 3.3V unless otherwise specified) Frequency vs RT RT (k/uni03A9) 100 125 150 175 200 225 250 275 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 FREQUENCY (MHz)
3154 G22
0.5V/DIV FRONT PAGE APPLICATION 200/uni03BCs/DIV 3154 G18 INDUCTOR CURRENT 2A/DIV LOAD CURRENT 2A/DIV VOUT 0.5V/DIV FRONT PAGE APPLICATION 200/uni03BCs/DIV 3154 G19 INDUCTOR CURRENT 2A/DIV LOAD CURRENT 2A/DIV VOUT 0.5V/DIV FRONT PAGE APPLICATION 200/uni03BCs/DIV 3154 G20 INDUCTOR CURRENT 2A/DIV LOAD CURRENT 2A/DIV VOUT 0.5V/DIV FRONT PAGE APPLICATION 1ms/DIV 3154 G21 INDUCTOR CURRENT 1A/DIV EN/UVLO 2V/DIV SS 0.5V/DIV VOUT 2V/DIV CSS = 10nF
Rev. A For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS (TA = 25°C, VIN = 3.6, VOUT = 3.3V unless otherwise specified) Die Temperature vs Load and VIN at 3.3VOUT, 2.2MHz, L = 0.68µH Die Temperature vs Load and VIN at 5VOUT, 2.2MHz, L = 0.68µH SYNC/MODE Pin Clock Release, 2.5MHz to 1.5MHz Die Temperature vs Load and VIN at 2.5VOUT, 2.2MHz, L = 0.68µH LOAD CURRENT (A) L T3154 DEMO BOARD TEMPERATURE RISE (°C)
3154 G25
(VOUT = 2.5V) 1.8VIN 2.5VIN 3.6VIN 5.0VIN LOAD CURRENT (A) TEMPERATURE RISE (°C)
3154 G26
(VOUT = 3.3V) 1.8VIN 2.5VIN 3.6VIN 5.0VIN L T3154 DEMO BOARD LOAD CURRENT (A) TEMPERATURE RISE (°C)
3154 G27
1.8VIN 2.5VIN 3.6VIN 5.0VIN (VOUT = 5.0V) L T3154 DEMO BOARD SYNC/MODE Pin Clock Acquisition 1.5MHz to 2.5MHz RT = 74.9k 20/uni03BCs/DIV 3154 G23 INDUCTOR CURRENT 1A/DIV SYNC/MODE 2V/DIV VOUT 0.5V/DIV SW1 5V/DIV 20/uni03BCs/DIV RT = 74.9k
3154 G24
0.5V/DIV SW1 5V/DIV
Rev. AFor more information www.analog.com PIN FUNCTIONS PVIN (Pins 1, 2): Power Input for Buck‑Boost Converter . Connect a minimum 22μF low ESR capacitor to PGND as close to the device as possible. This pin must be con‑ nected to VIN in application. VIN (Pin 3): Signal Input Voltage. Decouple with minimum 1µF capacitor . Low noise input for control circuitry. EN/UVLO (Pin 4) : Input to Enable the IC. Connect EN/ UVLO to VIN to enable the LT3154 at the 1.8V minimum operating voltage. Connect to an external divider from VIN to provide a programmable accurate V IN undervolt‑ age threshold: V(TURNON) =1.2V 1+ R1 ⎝⎜ ⎞ The accurate EN/UVLO pin threshold has 100mV of hys‑ teresis provided internally: V(TURNOFF) =1.1V 1+ R1 ⎝⎜ ⎞ SYNC/MODE (Pin 5) : Burst Mode operation Select and Oscillator Synchronization. Do not leave this pin floating. SYNC/MODE = High (V IN). Disable Burst Mode Operation and maintain low noise, constant frequency PWM operation. SYNC/MODE = Low (GND). The converter operates in Automatic Burst Mode operation. SYNC/MODE = External CLK. The internal oscillator is syn‑ chronized to the external CLK signal, Burst Mode opera‑ tion is disabled. A clock pulse width between 75ns and T period –75ns is required to synchronize the oscillator . An external resistor must be connected between RT and GND to program the oscillator 25% to 50% below the desired synchronization frequency. RT (Pin 6) : Oscillator Frequency Programming Input. Connect to V IN for 2.2MHz fixed frequency operation. Connect an external resistor from RT to GND to program the switching frequency according to the formula: RT (kΩ)= 110 fSW (MHz) GND (Pin 7) : Signal Ground. Low noise ground for control circuits. SS (Pin 8): External Soft Start. Connect to VIN for 2.2ms default soft‑start period. Connect an external capacitor to set soft start period according to the formula: t SS (ms) = 0.8 × CSS (nF) FB (Pin 9): Feedback Input to Error Amplifier . The resistor divider connected to this pin sets the converter output voltage. VOUT =1.0V 1+R3 ⎝⎜ ⎞ VC (Pin 10): Voltage error amplifier output VC is used to program average inductor current. An R‑C from this pin to ground sets the voltage loop compensation. VOUT (Pin 11): Signal Output Voltage. Decouple with mini‑ mum 1µF capacitor . Low noise input for VOUT control cir‑ cuitry. VOUT must be connected to PVOUT at the IC. PVOUT (Pin 12): Power Output for Buck‑Boost Converter . Connect a minimum 68μF (see Table 3 low ESR capaci‑ tor to PGND as close to the device as possible. Capacitor value may change depending on V OUT voltage and load current requirements. This pin must be connected to VOUT in application. SW2 (Pin 13): Buck‑Boost Converter Switch Pin. Connect inductor between SW1 and SW2 pins. PGND (Pins 14, 15, 17-Exposed Pad): Power Ground Connection. These pins and exposed thermal pad must make full connection to PCB ground plane to meet speci‑ fied thermal requirements. PGND must be connected to the GND pin in the application. SW1 (Pin 16): Buck‑Boost Converter Switch Pin. Connect inductor between SW1 and SW2 pins.
Rev. A For more information www.analog.com BLOCK DIAGRAM – + CDRV DDRV BDRV ADRV PGND PGND VBEST VBEST VBESTISWB ISWA ISWD D C A B PVIN PVOUT VOUT VOUT 1.8V TO 5.5VVIN 1.8V TO 5.5V VOL TAGE AMPLIFIER CURRENT AMPLIFIER PGND EN/UVLO 1.65V ISWA UVLO ADRV BDRV CDRV PWM/BURST DRIVE LOGIC DDRV SW2 SW1 PWMs PWM RAMPS SYNC 2.2MHz IPEAK IREVERSE /IZERO RUN ISWD 9.5A –1.2A/0A 1.2V GND SYNC/MODE VIN PGND BUCK BOOST RT VIN RCS INT/EXT RT SS CC RC ISWA INT/EXT SS ISWB RAMP VC FB R3 gm 1.0V SW1 SW2 BURSTPWM SYNC OSCILLATOR NOTE: PVIN AND VIN MUST BE CONNECTED TOGETHER IN THE APPLICATION PVOUT AND VOUT MUST BE CONNECTED TOGETHER IN THE APPLICATION PGND AND GND MUST BE CONNECTED TOGETHER IN THE APPLICATION 3154 BD
component selection for the LT3154 where applicable.
3154 QR01
3154 QR02
setting is 1.8V, the maximum is 5.5V. RT pin and ground according to the following equation.
3154 QR04
Table 1. RT Value for Common Switching Frequencies
the internal oscillator at 1.9MHz or lower .
3154 QR05
Table 2. Approximate Time for VOUT to Achieve Regulation vs crossover frequency to avoid the RHPZ. Table 3. Minimum Output Capacitor vs VOUT
- SYNC/MODE and EN/UVLO are low voltage input pins
and cannot be forced above 6V.
- The RT and SS pins should be connected to V IN to
external resistor or capacitor when programmed.
verter optimized for demanding high current applications. to be regulated above, below or equal to the input voltage. selected via the SYNC/MODE pin for low noise operation. reducing external component count. A remains on for a larger portion of the switching cycle. Figure 1. Buck-Boost Switch Topology
3154 F01PGND
loop transfer function throughout all modes of operation. cycle to maintain regulation of the output voltage.
to power saving Burst mode operation below this level. to load transients and inherent line voltage rejection.
3154 F02
Figure 2. Average Current Mode Control Loop
Rev. AFor more information www.analog.com OPERATION generates an output, VC, used by the current mode con‑ trol loop to command the appropriate inductor current level. To ensure stability, external frequency compensa ‑ tion components (RC, CC and CHF) must be installed between VC and GND. The procedure for determining these components is provided in the Applications Section of this data sheet. VC is internally connected to the non‑inverting input of a second amplifier , referred to in Figure 2 as I_AMP. The inverting input of the average current amplifier is con ‑ nected to the inductor current sense resistor R CS with a 200mV offset. I_AMP contains an internal averaging filter and frequency compensation network to stabilize operation of the internal current loop. The average cur ‑ rent amplifier’s output (ICOMP) provides the cycle‑by‑cycle duty cycle command into the buck‑boost PWM circuitry. The non‑inverting reference level input to the average current amplifier is VC and the feedback or inverting input is driven from the inductor current sensing circuitry. The inductor current sensing circuitry alternately measures the current through switches A and B. The output of the sensing circuitry produces a voltage across resistor RCS that resembles the inductor current waveform transformed to a voltage. If there is an increase in the power converter load on V OUT, the instantaneous level of V OUT will drop slightly, which will increase the voltage level on VC by the inverting action of the voltage error amplifier . When the increase on VC first occurs, the output of the current averaging amplifier , ICOMP, will increase momentarily to command a larger duty cycle. This duty cycle increase will result in a higher inductor current level, ultimately raising the average voltage across RCS. Once the average value of the voltage on RCS is equivalent to the VC level, the voltage on ICOMP will revert very closely to its previous level into the PWM and force the correct duty cycle to maintain voltage regulation at this new higher inductor current level. The average current amplifier is configured, so in steady state, the average value of the voltage applied to its inverting input (voltage across RCS) will be equivalent to the voltage on its non‑inverting input VC. As a result, the average value of the inductor current is controlled in order to maintain voltage regulation. The entire current amplifier and PWM can be simplified as a voltage controlled current source, with the driving voltage coming from VC. The voltage error amplifier monitors VOUT through a voltage divider and makes adjustments to the current command as necessary to maintain regulation. The voltage error amplifier therefore controls the outer voltage regulation loop. The average current amplifier makes adjustments to the inductor current as directed by the voltage Error Amplifier output via VC and is commonly referred to as the inner current loop amplifier . The average current mode control technique is similar to peak current mode control except that the average current amplifier controls aver ‑ age current instead of the peak current. This difference eliminates the peak to average current error inherent to peak current mode control, while maintaining most of the advantages inherent to peak current mode control. Control loop compensation techniques are detailed in the Applications section of this data sheet. Inductor Current Sense and Maximum Output Current As part of the current control loop, the LT3154 has cur‑ rent sense circuitry that measures the inductor current of the buck‑boost converter as shown in Figure 2. This circuitry measures the current through switches A and B separately and produces proportional output currents that are summed at the current sense resistor RCS. Sensed A and B switch currents form a voltage replica of the induc‑ tor current at RCS, which is used by the average current amplifier as described in the Quick Reference section. The voltage amplifier output, VC, is internally clamped to a nominal value of 0.9V. Since the average inductor current is proportional to VC, the 0.9V clamp sets the maximum average inductor current that can be programmed by the inner current loop. Taking into account the current sense amplifier’s gain and the value of RCS, the maximum aver‑ age inductor current is 6.8A typical.
Rev. A For more information www.analog.com OPERATION In buck mode, the output current is approximately equal to the inductor current IL: I OUT(BUCK)≈ IL In boost mode, the output current is related to average inductor current and duty cycle by: I OUT(BOOST)≈ IL • (1‑D) where D is the converter duty cycle Since the output current in boost mode is reduced by the duty cycle (D), the output current rating in buck mode is always greater than in boost mode. Also, because boost mode operation requires a higher inductor current for a given output current compared to buck mode, the efficiency in boost mode will be lower due to higher con‑ duction (IL² × RDS(ON)) losses in the power switches. This will further reduce the output current capability in boost mode. In either operating mode, however , the inductor peak‑to‑peak ripple current does not play a major role in determining the output current capability, unlike peak current mode control. The maximum output current capability in PWM mode curves in the Typical Performance Characteristics section show the relationship of input voltage and the ability to deliver load current at VOUT = 3.3V. If VOUT drops below approximately 1V, the inductor current will be reduced by approximately 50% to limit power dissipation during a short circuit. Peak, Reverse and Zero Current Comparators The internal current sense waveforms are used by the Peak (IPEAK), Reverse (IREVERSE) and Zero current (IZERO) com‑ parators. The IPEAK current comparator monitors I SENSE and interrupts normal PWM operation if the inductor current level exceeds its maximum internal threshold. This threshold is approximately 33% above the maxi ‑ mum average current level of the current control loop or 9.5 Amps. If the internal current sense waveform rises above this level, the LT3154 will disconnect the inductor from VIN by shutting off switch A to prevent higher current in the inductor . The IPEAK circuitry is reset by the oscillator clock at the end of each switching cycle. In the event that the IPEAK comparator is tripped as the result of an output short circuit condition, where V OUT is discharged below approximately 1V, the LT3154 will initiate a soft‑start event keeping the on‑chip power dissipation to low levels. Once the short circuit is removed, the LT3154 will restart in the normal fashion. If the average current loop is able to prevent inductor current from reaching IPEAK during a short circuit event, soft‑start will not be initiated, but the maximum current capability of the current loop will be reduced by 50% to reduce power dissipation. In addition to controlling the maximum inductor current, the LT3154 contains sense circuitry on the D switch to limit the reverse current as well. The amount of reverse current allowed depends on the mode of operation. In PWM mode (SYNC/MODE = 1), the typical reverse cur ‑ rent limit is –1.2A, providing clean, fixed frequency switch operation at light loads and during load step transients. In BURST mode (SYNC/MODE = 0), the LT3154 operates with a traditional zero current comparator , maintaining high efficiency at light loads and during burst packet intervals. Once IREVERSE or IZERO is detected, the D switch is shut off for the remainder of the switching cycle and reset by the oscillator clock at the end of the cycle. Oscillator The frequency of operation is programmed by an external resistor from the RT pin to ground, according to the fol‑ lowing equation: RT(kΩ)= 110 fSW MHz( ) The recommended frequency range is between 500kHz and 4MHz, allowing efficiency and external component sizes to be optimized for each application. An internal 2.2MHz oscillator frequency can be selected by connecting RT to VIN, eliminating the need for an external R T resistor . The LT3154 can also be synchronized to an external clock source using the SYNC/MODE pin and an internal phase lock loop (PLL). If synchronization to an external source is desired, the value of the RT resistor should be chosen at a frequency 25% to 50% below the applied clock signal for proper operation.
worst case low logic threshold of 0.3V. values are 1.7V rising/1.6V falling).
3154 F03
Figure 3. Accurate and Logic Level EN/UVLO sients and output voltage overshoot on initial power‑up. in power‑up times at a fraction of the soft‑start period. asserting, Thermal Shutdown, or a VOUT short circuit.
Rev. A For more information www.analog.com OPERATION Thermal Considerations The power switches of the LT3154 are designed to oper‑ ate continuously with currents up to the internal current limit thresholds. However , when operating at high current levels, there may be significant heat generated within the IC. Careful consideration must be given to the thermal environment of the IC in order to provide a means to remove heat from the IC and ensure that the LT3154 is able to provide its full rated output current. Specifically, the exposed die attach pad of both the LQFN package must be soldered to a copper layer on the PCB to maxi ‑ mize the conduction of heat out of the IC package. This can be accomplished by utilizing multiple vias from the die attach pad connection underneath the IC package to other PCB layer(s) containing large copper planes. A recommended board layout incorporating these concepts is show in Figure 4. Typical temperature rise versus load current curves using Figure 4 PCB are given in the Typical Performance Characteristics section. If the IC die temperature exceeds approximately 170°C, thermal shutdown will be invoked and all switching will be inhibited. The part will remain disabled until the die temperature cools by approximately 10°C. The soft‑start circuit is re‑initialized in thermal shutdown to provide a smooth recovery when the die temperature cools enough to resume operation. out the data sheet with varied use of pin‑strapped/default or programmable operation as described in the Quick Reference section. The selection of external components is dependent upon the required performance of each par‑ ticular application given considerations and trade ‑offs such as PCB area, input and output voltage range, output voltage ripple, required efficiency, thermal considerations and cost. This section of the data sheet provides some basic guidelines and considerations to aid in the selection of external components and the design of the applications circuit. Inductor Selection The choice of inductor used in LT3154 applications influ‑ ences the maximum deliverable output current, the con‑ verter bandwidth, the magnitude of the inductor current ripple and the overall converter efficiency. The inductor must have a low DC series resistance or output current capability and efficiency will be compromised. Larger inductor values reduce inductor current ripple but will not increase output current capability as is the case with peak current mode control as described in the “Inductor Current Sense and Maximum Output Current” section of APPLICATIONS INFORMATION this data sheet. Larger value inductors also tend to have a higher DC series resistance for a given case size, which will have a negative impact on efficiency. Larger values of inductance will also lower the Right Half Plane (RHP) zero frequency when operating in boost mode, which requires the converter bandwidth to be set lower in frequency, slowing the converter’s response to load transients. f RHPZ(Hz)= VIN 2 •RL VOUT 2 •2π•L Regardless of inductor value, the saturation current rating should be selected such that it is greater than the worst case average inductor current plus half of the ripple cur‑ rent. The peak ‑to‑peak inductor current ripple for each operational mode can be calculated from the following formula, where f SW is the switching frequency in MHz and L is the inductance in µH. ΔIL(P−P)(BUCK) = VOUT fSW •L VIN – VOUT VIN ⎟Amps ΔIL(P−P)(BOOST) = VIN fSW •L VOUT – VIN VOUT ⎟Amps It should be noted that the worst case inductor peak‑to‑ peak inductor ripple current occurs when the duty cycle in
when the duty cycle is 50% (VOUT = 2VIN). Table 4. Recommended Values minimizes the chances of interference with other circuitry. Table 5. Representative Surface Mount Inductors ing ∆IL, in buck mode is given in the Operation section.
voltage ripple is dominated by the inductor current ripple. terms as previously defined. noise to the control circuitry. GND to reduce switching noise to the control circuitry. capacitor vendor’s curve of capacitance vs DC bias voltage. Table 6. Representative Multilayer Ceramic Capacitors
The LT3154 switches large currents at high frequencies. sure a stable, noise‑free and efficient application circuit.
- All circulating high current paths should be kept as
as wide as possible to reduce the series resistance. current capability of the buck‑boost converter .
- The exposed pad is the power ground connection for
power handling capabilities of the IC.
- The components shown in bold boxes and their con ‑
minimizes EMI and reduces inductive drops.
- Keep the connection from the resistor dividers ( R3,
bandwidth over a wide operating range. Figure 4. Example PCB Layout, Top Layer is Shown, Bottom Layer is Mostly PGND Plane
3154 F05
Figure 5. Simplified Representation of and COUT, as shown in Figure 5. enough frequency to be ignored. using the external compensation network.
compensation components for a typical LT3154 application. on the application requirements.
3154 F07
3154 F08
Figure 6. Buck Bode Plots (VIN > VOUT, Figure 7. Boost Bode Plots (VIN = 1.8V, example Bode plots are shown in Figure 6 and Figure 7.
Rev. A For more information www.analog.com APPLICATIONS INFORMATION In boost mode the power stage gain is reduced by VIN/2 • VOUT: Boost DC Gain at 1.8VIN
20 Log
V •2Ω•1.8V 2•3.3V =15dB The output load pole will move depending on the output load resistance. The power stage gains and pole locations at full load are shown in Figure 6 and Figure 7. Output LoadPole (Buck) 2π•RLOAD •COUT = 1 2π•2Ω•100µF =800Hz Output LoadPole (Boost) 2π•RLOAD •COUT = 2 2π•2Ω•100µF =1600Hz The resulting power stage crossover frequencies are around 16kHz in buck mode (VIN > 3.3V), 8.5kHz in boost mode at 1.8VIN. The uncompensated power stage crossover frequency is lower than the goal of 20kHz. More importantly, the uncom‑ pensated power stage DC gain is low especially in boost mode. A pole‑zero‑pole network is now added to the voltage amplifier to increase the DC gain, increase the crossover frequency, and reduce the overall gain at high frequencies. VEA Pole 1 = 1 2πRVEA •CC; this pole is close to DC, This pole is close to DC, R VEA = Voltage Error Amp out‑ put resistance, which is approximately 5M. This pole is mentioned for completeness, but has no effect on the overall loop design. VEA Zero 1 = 1 2πRC•CC; this zero is placed below the This zero is placed below the crossover frequency to flat‑ ten the VA gain at the crossover to improve phase margin VEA Pole 2 = 1 2πRC•CHF ; This pole is placed above the This pole is placed above the crossover frequency to reduce the gain to suppress noise and mitigate any RHPZ effects. Referring to the buck power stage gain curves in Figure 6, the loop gain needs to be increased by 3dB to achieve a total loop crossover frequency of 20kHz. Assuming Zero 1 is placed well below the crossover frequency and Pole 2 is placed well above the crossover frequency, the voltage amplifiers gain at crossover is given by: VEA gain at crossover: 20Log VFB •gm •RC VOUT ⎠⎟= 20Log 1V •110µA/V •RC 3.3V ⎝⎜ ⎞ ⎠⎟= 3dB Where gm is the VEA transconductance, V FB/VOUT is the feedback divider gain, and RC is the external zero resistor: RC= 3.3V 1V •110µA/V •103dB/20dB = 40.2kΩ A 60k value for RC will provide 3dB of gain at crossover . With RC selected, CC’s value is determined by setting the Zero 1 frequency at 1/5 the crossover frequency or 4kHz: CC= 1 2π•RC•fZERO1 = 1 2π•40.2kΩ•4kHz =1nF Optionally, a high frequency Pole 2 is set at 20 times the crossover frequency to provide a high frequency pole at 400kHz: CHF = 1 2π•RC•fPOLE2 = 1 2π•40.2kΩ•400kHz =10pF VEA Gain in Figure 6 or Figure 7 shows the resulting voltage error amplifier (VEA) response to the selected values. Combining the power stage and VEA frequency responses, the measured total loop gains are illustrated in Figure 6 and Figure 7. As shown, the crossover frequency was in‑ creased to 20kHz in buck mode, 10kHz in boost mode. The phase margin at crossover is around 70°C in both cases. The VEA loop design provided the additional benefits of high gain (>60dB) at DC and gain attenuation above the crossover frequency to prevent RHPZ issues.
Rev. AFor more information www.analog.com TYPICAL APPLICATIONS Efficiency vs VIN and Load at 2.2MHz VIN Step 2V to 5V at 0.5A PWM Mode Load Transient Burst Mode 3.6VIN, 200mA to 2A Wide VIN to 3.3V with Minimal External Components LOAD CURRENT (A) 0.0001 EFFICIENCY (%)40
3154 TA02b
0.001 0.01 0.1 1 100 PWM BURST 1.8VIN 2.5VIN 3.6VIN 5.0VIN VOUT 3.3VVIN 1.8V TO 5.5V BURST
3154 TA02a
22µF COUT 100µF 1nF 40.2k 100k 232k 10pF 0.68µH RT L T3154 SS EN/UVLO GND SW1 SW2 PGND SYNC/MODE PVOUT VOUT VC FB PVIN VIN 200/uni03BCs/DIV 3154 TA02c INDUCTOR CURRENT 1A/DIV VIN 2V/DIV VOUT 0.5V/DIV 200/uni03BCs/DIV 3154 TA02d INDUCTOR CURRENT 2A/DIV LOAD CURRENT 2V/DIV VOUT 0.5V/DIV
Rev. A For more information www.analog.com TYPICAL APPLICATIONS Efficiency vs VIN and Load at 2.2MHz VIN Step 2V to 5V at 0.5A PWM Mode Load Transient Burst Mode 3.6VIN, 150mA to 1.5A Wide VIN to 5.0V with Minimal External Components LOAD CURRENT (A) 0.0001 EFFICIENCY (%)40
3154 TA03b
0.001 0.01 0.1 1 100 PWM BURST 1.8VIN 2.5VIN 3.6VIN 5.0VIN VOUT 5.0VVIN 1.8V TO 5.5V BURST
3154 TA03a
22µF COUT 100µF 1nF 60.4k 100k 402k 10pF 0.68µH RT L T3154 SS EN/UVLO GND SW1 SW2 PGND SYNC/MODE PVOUT VOUT VC FB PVIN VIN 200/uni03BCs/DIV 3154 TA03c INDUCTOR CURRENT 2A/DIV VIN 2V/DIV VOUT 0.5V/DIV 200/uni03BCs/DIV 3154 TA03d INDUCTOR CURRENT 2A/DIV LOAD CURRENT 2A/DIV VOUT 0.5V/DIV
Rev. AFor more information www.analog.com TYPICAL APPLICATIONS Efficiency vs VIN and Load at 1.2MHz VIN Step 2V to 5V at 1A Load Transient PWM Mode 3.3VIN, 300mA to 3A Wide VIN to 1.8V-4A Buck Converter LOAD CURRENT (A) 0.0001 EFFICIENCY (%)40
3154 TA04b
0.001 0.01 0.1 1 100 PWM BURST 2.2VIN 3.6VIN 5.0VIN VOUT 1.8VVIN 1.8V TO 5.5V
3154 TA04a
22µF COUT 220µF 100k60.4k 80.6k 1nF90.9k 0.1µF 1µH EN/UVLO L T3154 GNDRT SS SW1BURSTPWM SW2 PGND SYNC/MODE PVOUT VOUT FB VC PVIN VIN 200/uni03BCs/DIV 3154 TA04c VIN 2V/DIV VOUT 200mV/DIV INDUCTOR CURRENT 1A/DIV 200/uni03BCs/DIV 3154 TA04d INDUCTOR CURRENT 2A/DIV LOAD CURRENT 2A/DIV VOUT 0.5V/DIV
Rev. A For more information www.analog.com TYPICAL APPLICATIONS IL current and VOUT Voltage from 0V to 4.8V Charging Stacked Supercapacitor Charging Application VOUT VIN
3154 TA05a
22µF 22F* 2.4V 22F* 2.4V 100k 382k 60.4k 1nF90.9k 0.1µF 1µH EN/UVLO L T3154 GNDRT SS SW1BURSTPWM SW2 PGND SYNC/MODE *COOPER BUSSMAN POWERSTOR AEROGEL B SERIES 1.2MHz PVOUT VOUT FB VC PVIN VIN 2s/DIV 3154 TA05b RUN 5V/DIV VOUT 0.5V/DIV INDUCTOR CURRENT 2A/DIV
Rev. AFor more information www.analog.com TYPICAL APPLICATIONS Stacked Supercapacitor Powering PA Application Waveforms of VIN, VOUT, IL During Discharge VOUT 3.6V
3154 TA06a
22F* 2.4V 22F* 2.4V *COOPER BUSSMAN POWERSTOR AEROGEL B SERIES 3.6/uni03A9 RTRANSMIT COUT 100µF 100k 261k 49.9k 1nF0.1µF 0.68µH 2.2MHz RT L T3154 GND EN/UVLO SS SW1 BURSTPWM SW2 PGND SYNC/MODE 100k 100k 700k+ PVOUT VOUT FB VC PVIN VIN VOUT VIN = 5V 2s/DIV 3154 TA06b VIN CAPACITOR CURRENT 1A/DIV VIN CAPACITOR VOL TAGE 2V/DIV VOUT 2V/DIV RUN 2V/DIV
Rev. A For more information www.analog.com TYPICAL APPLICATIONS 3.3V to 5.0V − 3A Boost Converter , 2.4V UVLO with Output Disconnect Efficiency vs Load at 1.2MHz Power-Up/Down Waveforms 0.5A Load Load Transient PWM Mode 3.6VIN, 150mA to 1.5A LOAD CURRENT (A) 0.0001 EFFICIENCY (%)40
3154 TA07b
0.001 0.01 0.1 1 100 PWM BURST 2.5VIN 3.3VIN 5.0VIN VOUT 5.0VVIN 3.3V
3154 TA07a
22µF COUT 100µF 90.9k 1MΩ 1MΩ 0.1µF 1µH EN/UVLO L T3154 GNDRT SS SW1 BURSTPWM SW2 PGND SYNC/MODE PVOUT VOUTPVIN VIN 249k 1M/uni03A9 60.4k 1nF FB VC 200/uni03BCs/DIV 3154 TA07d INDUCTOR CURRENT 2A/DIV VOUT 0.5V/DIV LOAD CURRENT 2A/DIV 2ms/DIV 3154 TA07c INDUCTOR CURRENT 1A/DIV VIN 5V/DIV VOUT 5V/DIV
Rev. AFor more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. PACKAGE DESCRIPTION 16-Lead (3mm × 3mm × 0.74mm) (Reference L TC DWG # 05-08-1595 Rev Ø) DETAIL B A PACKAGE TOP VIEW PAD “A1” CORNER Y X aaa Z2× 16b PACKAGE BOTTOM VIEW SEE NOTES E D b e e b DETAIL B SUBSTRATE MOLD CAP // bbb Z Z DETAIL C SUGGESTED PCB LAYOUT TOP VIEW 0.0000 0.0000 0.7500 0.2500 0.2500 0.7500 0.7500 0.2500 0.2500 0.7500 DETAIL A PIN 1 NOTCH 0.25 × 45° 13 16 8 5 aaa Z 2× M X YZccc MXY Z ccc M X YZeee M Zfff PACKAGE OUTLINE 0.25 ±0.05 0.70 ±0.05 3.50 ±0.05 3.50 ±0.05 LGA 16 0817 REV Ø TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” L TXXXXX 0.25 0.25 DETAIL A ddd Z 16× SYMBOL A L b D E e aaa bbb ccc ddd eee fff MIN 0.65 0.01 0.30 0.22 NOM 0.74 0.02 0.40 0.25 3.00 3.00 1.70 1.70 0.50 0.24 0.50 MAX 0.83 0.03 0.50 0.28 0.10 0.10 0.10 0.10 0.15 0.08 NOTES DIMENSIONS Z DETAIL C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. PRIMARY DATUM -Z- IS SEATING PLANE METAL FEATURES UNDER THE SOLDER MASK OPENING NOT SHOWN SO AS NOT TO OBSCURE THESE TERMINALS AND HEAT FEATURES DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE
6 THE EXPOSED HEAT FEATURE MAY HAVE OPTIONAL CORNER RADII
e L e/2 1.70 1.70
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER A 08/23 Added tape and reel version to the Order Information. 2
Rev. A For more information www.analog.com ANALOG DEVICES, INC. 2023 www.analog.com RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS LTC3533 5V, 2A Wide VIN, Buck‑Boost DC/DC Converter VIN: 1.8V to 5.5V, VOUT: 1.8V to 5.25V, IQ = 40µA, ISD <1µA, DFN Package LTC3113 5V, 3A Wide VIN, Low Noise, Buck‑Boost DC/DC Converter VIN: 1.8V to 5.5V, VOUT: 1.8V to 5.5V, IQ = 40µA, ISD <1µA, DFN and TSSOP Packages LTC3112 15V, 2.5A Synchronous Buck‑Boost DC/DC Converter VIN: 2.7V to 15V, VOUT: 2.5V to 14V, IQ = 50µA, ISD <1µA, DFN Package LT3120 26V, 9A Low IQ CC/CV Monolithic Buck‑Boost Converter VIN: 2.5V to 26V, VOUT: 0.8V to 24V, IQ = 30µA, ISD <1µA, LQFN Package ADP2503/ ADP2504 Li-Chemistry to 3.3V at 3.4MHz Efficiency vs Load at 3.4MHz Load T ransient PWM Mode VIN = 3.6V, 200mA to 2A LOAD CURRENT (A) 0.0001 EFFICIENCY (%)40
3154 TA08b
0.001 0.01 0.1 1 100 PWM BURST 3.0VIN 3.6VIN 4.2VIN VOUT 3.3V
3154 TA08a
22µF COUT 100µF 32.2k 121k 100k 10pF 0.47µH EN/UVLO L T3154 GNDRT SW1 BURSTPWM SW2 PGND SYNC/MODE Li ION 2.7 TO 4.3V PVOUT VOUTPVIN VIN SS 100k 232k 40.2k 1nF FB VC 200/uni03BCs/DIV 3154 TA08c INDUCTOR CURRENT 2A/DIV VOUT 0.5V/DIV LOAD CURRENT 2A/DIV