LT3150

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Fast Transient Response, Low Input Voltage, Very Low Dropout Linear Regulator Controller 1.8V to 1.5V, 4A Very Low Dropout Linear Regulator (Typical Dropout Voltage = 65mV at IOUT = 4A) 50mV/DIV 2A/DIV 20ms/DIV

3150 TA02

0.1A to 4A Output Load Step n Microprocessor, ASIC and I/O Supplies n Very Low Dropout Input-to-Output Conversion n Logic Termination Supplies n Fast Transient Response Optimized with Ceramic Output Capacitors n FET RDS(ON) Defines Dropout Voltage n –1% Reference Tolerance Over Temperature n Multifunction LDO Shutdown Pin with Latchoff n Fixed Frequency 1.4MHz Boost Converter Generates MOSFET Gate Drive n Internally Compensated Boost Converter Uses Tiny Capacitors and Inductor n Independent Boost Converter Shutdown Control Permits LDO Output Voltage Supply Sequencing n 16-Lead SSOP Package The LT 3150 drives a low cost external N-channel MOSFET as a source follower to produce a fast transient response, very low dropout voltage linear regulator. Selection of the N-channel MOSFET R DS(ON) allows dropout voltages below 300mV for low VIN to low VOUT applications. The LT3150 includes a fixed frequency boost regulator that generates gate drive for the N-channel MOSFET. The internally compensated current mode PWM architecture combined with the 1.4MHz switching frequency permits the use of tiny, low cost capacitors and inductors. The LT3150’s transient load performance is optimized with ceramic output capacitors. A precision 1.21V refer- ence accommodates low voltage supplies. Protection includes a high side current limit amplifier that activates a fault timer circuit. A multifunction shutdown pin provides either current limit time-out with latchoff, overvoltage protection or thermal shutdown. Independent shutdown control of the boost converter provides on/off and sequencing control of the LDO output voltage. VIN2 FB1 SHDN2 SWGND GND GND SW V IN1 SHDN1 IPOS INEG GATE FB2 COMP LT3150 MBR0520L 10µH 1.5k CIN: PANASONIC SP SERIES EEFUE0E221R 20% C1: AVX TAJA475M020R 20V 20% L1: MURATA LQH32CN100K11 OR SUMIDA CDRH3D16100 243Ω 1020Ω 4.7µF + CIN 220µF 2.5V V IN 1.8V VOUT 1.5V 6.19k 1.37k Si4410

3150 TA01

2.2µF ·10 X5R CERAMIC

0805 CASE

5.1Ω 6800pF 50pF DESCRIPTIO UFEATURES APPLICATIO SU TYPICAL APPLICATIO U , LTC and LT are registered trademarks of Linear Technology Corporation.

(Note 1) ABSOLUTE AXI U RATI GSW WW U PACKAGE/ORDER I FOR ATIOUU W GN PACKAGE 16-LEAD PLASTIC SSOP TOP VIEW SW SWGND V IN1 SHDN2 VIN2 GND NC FB2 FB1 GND SHDN1 I POS INEG GATE NC COMP ORDER PART NUMBER LT3150CGN GN PART MARKING 3150 TJMAX = 125°C, qJA = 130°C/W, qJC = 40°C/W Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN1 = 1.5V, VSHDN1 = VIN1, VIN2 = 12V, GATE = 6V, IPOS = INEG = 5V, VSHDN2 = 0.75V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Boost Switching Regulator VIN1 Minimum Operating Voltage 0.9 1.1 V VIN1 Maximum Operating Voltage 10 V VFB1 FB1 Reference Voltage l 1.20 1.23 1.255 V FB1 Input Bias Current Current Flows into Pin l 27 80 nA IQ1 VIN1 Quiescent Current V SHDN1 = 1.5V 3 4.5 mA VIN1 Quiescent Current in Shutdown V SHDN1 = 0V, VIN1 = 2V 0.01 0.5 mA VSHDN1 = 0V, VIN1 = 5V 0.01 1.0 mA FB1 Reference Line Regulation 1.5V £ VIN1 £ 10V 0.02 0.2 %/V Switching Frequency l 1 1.4 1.9 MHz Maximum Duty Cycle l 82 86 % Switch Current Limit (Note 3) 550 800 mA Switch VCESAT ISW = 300mA 300 350 mV Switch Leakage Current V SW = 5V 0.01 1 mA SHDN1 Input Voltage High 1 V SHDN1 Input Voltage Low 0.3 V SHDN1 Input Bias Current V SHDN1 = 3V, Current Flows into Pin 25 50 mA VSHDN1 = 0V, Current Flows into Pin 0.01 0.1 mA Linear Regulator Controller IQ2 VIN2 Quiescent Current l 51 2 1 9 m A VFB2 FB2 Reference Voltage 1.203 1.210 1.217 V l 1.198 1.210 1.222 V FB2 Line Regulation 10V £ VIN2 £ 20V l 0.01 0.03 %/V FB2 Input Bias Current FB2 = V FB2, Current Flows out of Pin l –0.6 –4 mA

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS AVOL Large-Signal Voltage Gain V GATE = 3V to 10V l 69 84 dB VOL GATE Output Swing Low (Note 4) I GATE = 0mA l 2.5 3 V VOH GATE Output Swing High I GATE = 0mA l VIN2 – 1.6 V IN2 – 1 V IPOS + INEG Supply Current 3V £ IPOS £ 20V l 0.3 0.625 1 mA Current Limit Threshold Voltage 42 50 58 mV l 37 50 63 mV Current Limit Threshold Voltage 3V £ IPOS £ 20V l – 0.20 – 0.50 %/V Line Regulation SHDN2 Sink Current Current Flows Into Pin l 2.5 5.0 8.0 mA SHDN2 Source Current Current Flows Out of Pin l –8 –15 –23 mA SHDN2 Low Clamp Voltage l 0.1 0.25 V SHDN2 High Clamp Voltage l 1.50 1.85 2.20 V SHDN2 Threshold Voltage l 1.18 1.21 1.240 V SHDN2 Threshold Hysteresis l 50 100 150 mV Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD • 130°C/W) The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN1 = 1.5V, VSHDN1 = VIN1, VIN2 = 12V, GATE = 6V, IPOS = INEG = 5V, VSHDN2 = 0.75V unless otherwise noted. Note 3: Switch current limit is guaranteed by design and/or correlation to static test. Note 4: The VGS(th) of the external MOSFET must be greater than 3V – VOUT.

Switch VCESAT vs Switch Current SHDN1 Input Bias Current vs VSHDN1 Oscillator Frequency vs Temperature FB2 Reference Voltage vs Temperature Switch Current Limit vs Duty Cycle FB1 Reference Voltage vs Temperature FB2 Input Bias Current vs Temperature TYPICAL PERFOR A CE CHARACTERISTICS UW SWITCH CURRENT (mA) 0 100 200 300 400 500 600 700 VCESAT (mV)

3150 G01

TA = 25°C TEMPERATURE (°C) –50 –25 0 25 50 75 100 SWITCHING FREQUENCY (MHz)

3150 G02

2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 VIN = 5V VIN = 1.5V SHDN1 PIN VOLTAGE (V) 012345 SHDN1 INPUT BIAS CURRENT (µA)

3150 G03

TA = 25°C DUTY CYCLE (%) 10 20 30 40 50 60 70 80 SWITCH CURRENT LIMIT (mA)

3150 G04

70°C 25°C –40°C TEMPERATURE (°C) –50 FB1 REFERENCE VOLTAGE (V)

3150 G05

1.25 1.24 1.23 1.22 1.21 1.20 VOLTAGE –25 0 25 50 75 100 TEMPERATURE (°C) –75 FB2 REFERENCE VOLTAGE (V) 1.210 1.214 1.218 1.222 125

3150 G07

1.206 1.202 1.208 1.212 1.216 1.220 1.204 1.200 1.198 –25 25 75–50 150 0 50 100 175 TEMPERATURE (°C) –75 FB2 INPUT BIAS CURRENT (mA) 3.0 4.0 125

3150 G08

2.0 1.0 2.5 3.5 1.5 0.5 –25 25 75–50 150 0 50 100 175 VIN = 20V VIN = 12V VIN = 8V Boost Switching Regulator VIN2 Quiescent Current vs Temperature TEMPERATURE (°C) –75 VIN2 QUIESCENT CURRENT (mA) –25 25 50 150 –50 0 75 100 125 175

3150 G06

VIN = 8V VIN = 12V VIN = 20V Linear Regulator Controller

Gain and Phase vs Frequency Error Amplifier Large-Signal Voltage Gain vs Temperature Gate Output Swing High (VIN2 – VGATE) vs Temperature IPOS + INEG Supply Current vs Temperature Gate Output Swing Low vs Temperature Current Limit Threshold Voltage vs Temperature Current Limit Threshold Voltage Line Regulation vs Temperature TEMPERATURE (°C) –75 LARGE-SIGNAL VOLTAGE GAIN (dB) 105 115 125

3150 G10

–25 25 75–50 150 0 50 100 175 FREQUENCY (Hz) 100ERROR AMPLIFIER GAIN (dB) AND PHASE (DEG) 150 200 1k 100k 1M 100M

3150 G11

TEMPERATURE (°C) –75 GATE OUTPUT SWING LOW (V) 2.50 3.00 125

3150 G12

2.00 1.50 2.25 2.75 1.75 1.25 1.00 –25 25 75–50 150 0 50 100 175 ILOAD = 50mA NO LOAD TEMPERATURE (°C) GATE OUTPUT SWING HIGH (V) 1.0 2.0 3.0 0.5 1.5 2.5 –25 25 75 125

3150 G13

175–50–75 0 50 100 150 NO LOAD ILOAD = 50mA TEMPERATURE (°C) –75

300 IPOS + INEG SUPPLY CURRENT (mA)

–50 50 100

3150 G14

25 150 175–25 0 75 125 IPOS = INEG = 3V IPOS = INEG = 5V IPOS = INEG = 12V IPOS = INEG = 20V TEMPERATURE (°C) CURRENT LIMIT THRESHOLD VOLTAGE (mV) –25 25 75 125

3150 G15

175–50–75 0 50 100 150 IPOS = 5V IPOS = 3V IPOS = 20V TEMPERATURE (°C) –75 CURRENT LIMIT THRESHOLD VOLTAGE LINE REGULATION (%/V) –0.2 –0.1 125

3150 G16

–0.3 –0.4 –0.5 –25 25 75–50 150 0 50 100 175 SHDN2 Sink Current vs Temperature TEMPERATURE (°C) –75 SHDN2 SINK CURRENT (mA) 5.5 6.5 7.5 125

3150 G17

4.5 3.5 5.0 6.0 7.0 4.0 3.0 2.5 –25 25 75–50 150 0 50 100 175 TYPICAL PERFOR A CE CHARACTERISTICS UW FB2 Line Regulation vs Temperature TEMPERATURE (°C) FB2 LINE REGULATION (%/V) 0.010 0.020 0.030 0.005 0.015 0.025 –25 25 75 125

3150 G09

175–50–75 0 50 100 150 Linear Regulator Controller

SHDN2 Hysteresis vs Temperature SHDN2 High Clamp Voltage vs Temperature TYPICAL PERFOR A CE CHARACTERISTICS UW TEMPERATURE (°C) –75 SHDN2 LOW CLAMP VOLTAGE (V) 0.15 0.20 0.25 125

3150 G19

0.10 0.05 –25 25 75–50 150 0 50 100 175 TEMPERATURE (°C)

1.5 SHDN2 HIGH CLAMP VOLTAGE (V)

1.7 1.9 2.1 1.6 1.8 2.0 –25 25 75 125

3150 G20

175–50–75 0 50 100 150 TEMPERATURE (°C) –75 SHDN2 HYSTERESIS (mV) 110 130 150 125

3150 G21

–25 25 75–50 150 0 50 100 175 UUUPI FU CTIO S SW (Pin 1): Boost Converter Switch Pin. Connect induc- tor/diode here. Minimize trace area at this pin to keep EMI down. SWGND (Pin 2): Switch Ground. Tie directly to the local ground plane and the GNDs at Pins 6 and 15. VIN1 (Pin 3): Boost Converter Input Supply Pin. Must be locally bypassed. SHDN2 (Pin 4): This is a multifunction shutdown pin that provides GATE drive latchoff capability. A 15 mA current source, that turns on when current limit is activated, charges a capacitor placed in series with SHDN2 to GND and performs a current limit time-out function. The pin is also the input to a comparator referenced to VREF (1.21V). When the pin pulls above VREF, the comparator latches the gate drive to the external MOSFET off. The comparator typically has 100mV of hysteresis and the SHDN2 pin can be pulled low to reset the latchoff function. This pin provides overvoltage protection or thermal shutdown protection when driven from various resistor divider schemes. TEMPERATURE (°C) –75 SHDN2 SOURCE CURRENT (mA) –15 –13 –11 125

3150 G18

–17 –19 –16 –14 –12 –18 –20 –10 –25 25 75–50 150 0 50 100 175SHDN2 Source Current vs Temperature Linear Regulator Controller

VIN2 (Pin 5): This is the input supply for the linear regulator control circuitry and provides sufficient gate drive compli- ance for the external N-channel MOSFET. The maximum operating V IN2 is 20V and the minimum operating VIN2 is set by VOUT + (VGS of the MOSFET at max I OUT) + 1.6V (worst-case VIN2 to GATE output swing). GND (Pin 6): Analog Ground. This pin is also the negative sense terminal for the internal 1.21V reference. Connect the LDO regulator external feedback divider network and fre- quency compensation components that terminate to GND directly to this pin for best regulation and performance. Also, tie this pin directly to SWGND (Pin 2) and GND (Pin 15). NC (Pins 7, 10): No Connect. FB2 (Pin 8): This is the inverting input of the error amplifier for the linear regulator. The noninverting input is tied to the internal 1.21V reference. Input bias current for this pin is typically 0.6mA flowing out of the pin. Tie this pin to a resistor divider network to set output voltage. Tie the top of the external resistor divider directly to the output load for best regulation performance. COMP (Pin 9): This is the high impedance gain node of the error amplifier and is used for external frequency compen- sation. The transconductance of the error amplifier is 15 millimhos and open-loop voltage gain is typically 84dB. Frequency compensation is generally performed with a series RC + C network to ground. GATE (Pin 11): This is the output of the error amplifier that drives N-channel MOSFETs with up to 5000pF of “effective” gate capacitance. The typical open-loop out- put impedance is 2W . When using low input capacitance MOSFETs (< 1500pF), a small gate resistor of 2W to 10W dampens high frequency ringing created by an LC reso- nance due to the MOSFET gate’s lead inductance and input capacitance. The GATE pin delivers up to 50mA for a few hundred nanoseconds when slewing the gate of the N-channel MOSFET in response to output load current transients. INEG (Pin 12): This is the negative sense terminal of the current limit amplifier. A small sense resistor is connected in series with the drain of the external MOSFET and is connected between the I POS and I NEG pins. A 50mV threshold voltage in conjunction with the sense resistor value sets the current limit level. The current sense resis- tor can be a low value shunt or can be made from a piece of PC board trace. If the current limit amplifier is not used, tie the I NEG pin to IPOS to defeat current limit. An alternative is to ground the INEG pin. This action disables the current limit amplifier and additional internal circuitry activates the timer circuit on the SHDN2 pin if the GATE pin swings to the V IN rail. This option provides the user with a No RSENSE TM current limit function. IPOS (Pin 13): This is the positive sense terminal of the current limit amplifier. Tie this pin directly to the main input voltage from which the output voltage is regulated. SHDN1 (Pin 14): Boost Regulator Shutdown Pin. Tie to 1V or more to enable device. Ground to shut down. This pin must not float for proper operation. Connect SHDN1 externally as it does not incorporate an internal pull-up or pull-down. GND (Pin 15): Boost Converter Analog Ground. This pin is also the negative sense terminal for the FB1 1.23V reference. Connect the external feedback divider net- work, which sets the V IN2 supply voltage and terminates to GND, directly to this pin for best regulation and performance. Also, tie this pin directly to SWGND (Pin 2) and GND (Pin 6). FB1 (Pin 16): Boost Regulator Feedback Pin. Reference voltage is 1.23V. Connect resistive divider tap here. Minimize trace area at FB1. Set VOUT = VIN2 according to VOUT = 1.23V(1 + R1/R2). UUUPI FU CTIO S No RSENSE is a trademark of Linear Technology Corporation.

3150 BD02

1V+– IPOS INEG GATE D2 – COMP2 COMP3 OR2 START-UP VREF 1.21V 50k OR1 Q6Q5Q4 (EXTERNAL) (EXTERNAL) VOUT FB2 + – FF RQ S 0.15W SW DRIVER COMPARATOR 2SHUTDOWN SHDN1 SRAMP GENERATOR RC 100k CC 40pF 1.4MHz OSCILLATOR SWGND

3150 BD1

(EXTERNAL) (EXTERNAL) 40k VIN2 VIN1VIN1 3 FB1 FB1 16 GND ILIM1 gm = 77µmhos Boost Switching Regulator Linear Regulator Controller

APPLICATIO S I FOR ATIOWU UU INTRODUCTION With each new generation of computing systems, total power increases while system voltages fall. CPU core, logic and termination supplies below 1.8V are now com- mon. Power supplies must not only regulate low output voltages, but must also operate from low input voltages. A low voltage, very low dropout linear regulator is an attractive conversion option for applications with output current in the range of several amperes. Component count and cost are low in comparison with switching regulator solutions and with low input-to-output differential volt- ages, efficiencies are comparable. In addition to low input-to-output voltage conversion, these systems require stringent output voltage regulation. The output voltage specification includes input voltage change, output load current change, temperature change and output load current transient response. Total toler- ances as low as –2% are now required. For a 1.5V output voltage, this amounts to a mere –30mV. Transient load current response is the most critical component as output current can cycle from zero to amps in tens of nanosec- onds. These requirements mandate the need for a very accurate, very high speed regulator. Historically employed solutions include monolithic 3-terminal linear regulators, PNP transistors driven by low cost control circuits and simple buck converter switching regulators. The 3-terminal regulator provides high integration, the PNP driven regulator provides low dropout performance and the switching regulator pro- vides high electrical efficiency. However, these solutions manifest a common trait of transient response measured in many microseconds. This fact translates to a regulator output decoupling capacitor scheme requiring several hundred microfarads of very low ESR bulk capacitance using multiple capacitors in parallel. This required bulk capacitance is in addition to the ceramic decoupling capacitor network that handles the transient load response during the first few hundred nanoseconds as well as providing high frequency noise immunity. The combined cost of all capacitors is a significant percentage of the total power supply cost. The LT3150 controller IC is a unique, easy-to-use device that drives an external N-channel MOSFET as a source follower and realizes an extremely low dropout, ultrafast transient response regulator. The circuit achieves supe- rior regulator bandwidth and transient load performance by eliminating expensive special polymer, tantalum or bulk electrolytic capacitors in the most demanding appli- cations. Performance is optimized around the latest gen- eration of low cost, low ESR, readily available ceramic capacitors. Users benefit directly by saving significant cost as all bulk capacitance is removed. Additional savings include insertion cost, purchasing/inventory cost and board space. The precision-trimmed adjustable voltage LT3150 ac- commodates most power supply voltages. Proper selec- tion of the N-channel MOSFET R DS(ON) allows user-settable dropout voltage performance. Transient load step perfor- mance is optimized for ceramic output capacitor networks allowing the regulator to respond to transient load changes in a few hundred nanoseconds. The output capacitor network typically consists of multiple 1mF to 10mF ceramic capacitors in parallel depending on the power supply requirements. The LT3150 also incorporates current lim- iting, on/off control for power supply sequencing and overvoltage protection or thermal shutdown with simple external components. The LT3150 combines the benefits of low input voltage operation, very low dropout voltage performance, preci- sion regulation and fast transient response. With low input/output differential voltage applications becoming the norm, an LT3150-based solution is a practical alterna- tive to switching regulators providing comparable effi- ciency performance at an appreciable cost savings. BLOCK DIAGRAM OPERATION Gate drive for the external N-channel MOSFET in the linear regulator loop is provided by a current mode, internally compensated, fixed frequency step-up switching regula- tor. Referring to the Block Diagram, Q1 and Q2 form a bandgap reference core whose loop is closed around the output of the regulator. The voltage drop across R5 and R6

APPLICATIO S I FOR ATIOWU UU is low enough such that Q1 and Q2 do not saturate, even when VIN1 is 1V. When there is no load, FB1 rises slightly above 1.23V, causing VC (the error amplifier’s output) to decrease. Comparator A2’s output stays high, keeping switch Q3 in the off state. As increased output loading causes the FB1 voltage to decrease, A1’s output increases. Switch current is regulated directly on a cycle-by-cycle basis by the V C node. The flip flop is set at the beginning of each switch cycle, turning on the switch. When the summation of a signal representing switch current and a ramp generator (introduced to avoid subharmonic oscilla- tions at duty factors greater than 50%) exceeds the V C signal, comparator A2 changes state, resetting the flip flop and turning off the switch. More power is delivered to the output as switch current is increased. The output voltage, attenuated by external resistor divider R1 and R2, appears at the FB1 pin, closing the overall loop. Frequency com- pensation is provided internally by R C and CC. Transient response can be optimized by the addition of a phase lead capacitor CPL in parallel with R1 in applications where large value or low ESR output capacitors are used. As the load current is decreased, the switch turns on for a shorter period each cycle. If the load current is further decreased, the converter will skip cycles to maintain output voltage regulation. The linear regulator controller section of the LT3150 Block Diagram consists of a simple feedback control loop and multiple protection functions. Examining the Block Dia- gram for the LT3150, a start-up circuit provides controlled start-up, including the precision-trimmed bandgap refer- ence, and establishes all internal current and voltage biasing. Reference voltage accuracy at the FB2 pin is specified as –0.6% at room temperature and as –1% over the full operating temperature range. This places the LT3150 among a select group of regulators with a very tightly specified reference voltage tolerance. The 1.21V reference is tied to the noninverting input of the main error amplifier in the feedback control loop. The error amplifier consists of a single high gain gm stage with a transconductance equal to 15 millimhos. The inverting terminal is brought out as the FB2 pin. The gm stage provides differential-to-single ended conversion at the COMP pin. The output impedance of the gm stage is about 1MW and thus, 84dB of typical DC error amplifier open-loop gain is realized along with a typical 75MHz uncompensated unity-gain crossover frequency. Note that the overall feedback loop’s DC gain decreases from the gain provided by the error amplifier by the attenuation factor in the resistor divider network which sets the DC output voltage. External access to the high impedance gain node of the error amplifier permits typical loop compensation to be accomplished with a series RC + C network to ground. A high speed, high current output stage buffers the COMP node and drives up to 5000pF of “effective” MOSFET gate capacitance with almost no change in load transient per- formance. The output stage delivers up to 50mA peak when slewing the MOSFET gate in response to load current transients. The typical output impedance of the GATE pin is typically 2W . This pushes the pole due to the error amplifier output impedance and the MOSFET input capacitance well beyond the loop crossover frequency. If the capacitance of the MOSFET used is less than 1500pF, it may be necessary to add a small value series gate resistor of 2W to 10W . This gate resistor helps damp the LC resonance created by the MOSFET gate’s lead induc- tance and input capacitance. In addition, the pole formed by this resistance and the MOSFET input capacitance can be fine tuned. Because the MOSFET pass transistor is connected as a source follower, the power path gain is much more predict- able than designs that employ a discrete PNP transistor as the pass device. This is due to the significant production variations encountered with PNP Beta. MOSFETs are also very high speed devices which enhance the ability to pro- duce a stable wide bandwidth control loop. An additional advantage of the follower topology is inherently good line rejection. Input supply disturbances do not propagate through to the output. The feedback loop for a regulator circuit is completed by providing an error signal to the FB2 pin. A resistor divider network senses the output voltage and sets the regulated DC bias point. In general, the LT3150 regulator feedback loop permits a loop crossover frequency on the order of 1MHz while maintaining good phase and gain margins. This unity-gain frequency is a factor of 20 to 30 times the bandwidth of currently implemented regulator

APPLICATIO S I FOR ATIOWU UU solutions for microprocessor power supplies. This signifi- cant performance benefit is what permits the elimination of all bulk output capacitance. Several other unique features are included in the design that increase its functionality and robustness. These func- tions comprise the remainder of the Block Diagram. A high side sense, current limit amplifier provides active current limiting for the regulator. The current limit ampli- fier uses an external low value shunt resistor connected in series with the external MOSFET’s drain. This resistor can be a discrete shunt resistor or can be manufactured from a Kelvin-sensed section of “free” PC board trace. All load current flows through the MOSFET drain and thus, through the sense resistor. The advantage of using high side current sensing in this topology is that the MOSFET’s gain and the main feedback loop’s gain remain unaffected. The sense resistor develops a voltage equal to I OUT(RSENSE). The current limit amplifier’s 50mV threshold voltage is a good compromise between power dissipation in the sense resistor, dropout voltage impact and noise immunity. Current limit activates when the sense resistor voltage equals the 50mV threshold. Two events occur when current limit activates: the first is that the current limit amplifier drives Q5 in the Block Diagram and clamps the positive swing of the COMP node in the main error amplifier to a voltage that provides an output load current of 50mV/R SENSE. This action contin- ues as long as the output current overload persists. The second event is that a timer circuit activates at the SHDN2 pin. This pin is normally held low by a 5mA active pull-down that limits to » 100mV above ground. When current limit activates, the 5mA pull-down turns off and a 15mA pull-up current source turns on. Placing a capacitor in series with the SHDN2 pin to ground generates a programmable time ramp voltage. The SHDN2 pin is also the positive input of COMP1. The negative input is tied to the internal 1.21V reference. When the SHDN2 pin ramps above VREF, the comparator drives Q7 and Q8. This action pulls the COMP and GATE pins low and latches the external MOSFET drive off. This condition reduces the MOSFET power dissipation to zero. The time period until the latched-off condition occurs is typically equal to C SHDN2(1.11V)/15mA. For example, a 1mF capacitor on the SHDN2 pin yields a 74ms ramp time. In short, this unique circuit block performs a current limit time-out function that latches off the regulator drive after a predefined time period. The time-out period selected is a function of system requirements including start-up and safe operating area. The SHDN2 pin is internally clamped to typically 1.85V by Q9 and R10. The comparator tied to the SHDN2 pin has 100mV of typical hysteresis to provide noise immunity. The hysteresis is especially useful when using the SHDN2 pin for thermal shutdown. Restoring normal operation after the load current fault is cleared is accomplished in two ways. One option is to recycle the V IN2 LT3150 supply voltage as long as an external bleed path for the SHDN2 pin capacitor is pro- vided. The second option is to provide an active reset circuit that pulls the SHDN2 pin below V REF. Pulling the SHDN2 pin below VREF turns off the 15mA pull-up current source and reactivates the 5mA pull-down. If the SHDN2 pin is held below VREF during a fault condition, the regu- lator continues to operate in current limit into a short. This action requires being able to sink 15mA from the SHDN2 pin at less than 1V. The 5mA pull-down current source and the 15mA pull-up current source are designed low enough in value so that an external resistor divider network can drive the SHDN2 pin to provide overvoltage protection or to provide thermal shutdown with the use of a thermistor in the divider network. Diode-ORing these functions to- gether is simple to accomplish and provides multiple functionality for one pin. If the current limit amplifier is not used, two choices present themselves. The simplest choice is to tie the I NEG pin directly to the IPOS pin. This action defeats current limit and provides the simplest, no frills circuit. Applications in which the current limit amplifier is not used are where extremely low dropout voltages must be achieved and the 50mV threshold voltage cannot be tolerated. However, a second available choice permits a user to pro- vide short-circuit protection with no external sensing. This technique is activated by grounding the I NEG pin. This action disables the current limit amplifier because Schottky diode D1 clamps the amplifier’s output and prevents Q5 from pulling down the COMP node. In addition, Schottky diode D2 turns off pull-down transistor Q4. Q4 is normally on and

APPLICATIO S I FOR ATIOWU UU holds internal comparator COMP3’s output low. This comparator circuit, now enabled, monitors the GATE pin and detects saturation at the positive rail. When a saturated condition is detected, COMP3 activates the shutdown timer. Once the time-out period occurs, the output is shut down and latched off. The operation of resetting the latch remains the same. Note that this technique does not limit the FET current during the time-out period. The output current is only limited by the input power supply and the input/out- put impedance. Setting the timer to a short period in this mode of operation keeps the external MOSFET within its SOA (safe operating area) boundary and keeps the MOSFET’s temperature rise under control. Unique circuit design incorporated into the LT3150 allevi- ates all concerns about power supply sequencing. The issue of power supply sequencing is an important topic as the typical LT3150 application has two separate power supply inputs, V IN1 and VIN2. If the VIN2 supply voltage is slow in ramping up or is held off by SHDN1, insufficient MOSFET gate drive exists and therefore, the output voltage does not come up. This statement is true as long as the V IN1 input voltage is lower than the threshold of the external MOSFET. Prior to the boost converter powering up, VIN2 equals V IN1 – V F due to the DC path present through the boost inductor. If V IN1 is high enough, the MOSFET turns on and pulls the output voltage up. If this situation exists and the output must be held off, then pulling the SHDN2 pin high actively holds the output off. Pull the SHDN2 pin low to allow start-up, as the SHDN2 high logic state is a latched condition. If V IN2 is present, but the VIN1 supply voltage tied to the IPOS pin is slow in ramping, then the feedback loop wants to drive the GATE pin to the positive VIN2 rail. This results in a large current as the VIN1 supply ramps up. However, undervoltage lockout circuit COMP2, which monitors the IPOS supply voltage, holds Q6 on and pulls the COMP pin low until the IPOS voltage increases to greater than the internal 1.21 reference voltage. The undervoltage lockout circuit then smoothly releases the COMP pin and allows the output voltage to come up in dropout from the input supply voltage. An additional benefit derived from the speed of the LT3150 feedback loop is that turn-on overshoot is virtually nonexistent in a properly compen- sated system. BOOST REGULATOR COMPONENT SELECTION Diode Linear Technology recommends the use of a Schottky diode with the LT3150. For input supply voltages less than 2V, the Motorola MBR0520 or equivalent is a good choice due to its small size, low cost and low forward voltage. The average diode current equals the V IN2 supply current of 12mA typically. The peak diode current equals the peak switch current, which in these low input-to-output voltage applications ranges from 100mA to 200mA. The diode’s forward voltage during its conduction period directly affects the duty cycle of the boost converter. These low input-to-output voltage applications require the boost converter to operate at duty cycles close to the maximum and the difference of a few hundred millivolts in the diode forward voltage results in a duty cycle difference of several percent. For supply voltages greater than 2V, a 1N4148 is suitable and lowers cost. Inductor Use inductors with a saturation current rating (where inductance is approximately 70% of zero current induc- tance) of 0.2A or greater. Also, choose an inductor with a DCR of 2.5W or less. The inductor’s DCR also affects the boost converter’s duty cycle. A larger DCR value increases the required duty cycle. An inductance value between 4.7mH and 10mH works well in most applications. Table 1 lists several 10 mH inductors that work with the LT3150, although this is by no means an exhaustive list. Many magnetic vendors have components suitable for use in this boost application. Input Capacitor The input bypass capacitors serve as the reservoir capaci- tor for the boost regulator, the linear regulator and what- ever other system circuitry the input supply powers. Therefore, the input capacitor network is most likely distributed along the input supply PCB plane. However, the switching of current at high speed by the boost regulator mandates a local bypass capacitor at the V IN1 pin. Place this input capacitor physically close to the

Table 1. Inductor Vendors capacitor’s characteristics determines output voltage ripple. capacitor the simpler and preferred choice. loop that determines the unity-gain crossover frequency. X5R is less expensive and is available in higher values.

Figure 1. Ceramic Capacitor DC Bias Characteristics Figure 2. Ceramic Capacitor Temperature Characteristics

3150 F01

1210 CASE SIZE, 10µF

3150 F02

coefficient comparisons between Y5V and X5R material. ceramic capacitors with X5R or X7R dielectric material. package thermal resistance RTH(JA). voltage must exceed the maximum input voltage.

.09 5 18 09 5 15 34 23 8VV A m A Siliconix Si4410 MOSFET with an RDS(ON) of 20mW is a close match. Although the Si4410’s 30V maximum V DS and 8A maximum I D ratings exceed the application’s requirements, the Si4410’s low cost makes it an excellent choice. As the final criteria, consider the thermal resistance R TH(JA) of the MOSFET’s package. The temperature rise in the MOSFET must be kept under control and within the manufacturer’s maximum junction temperature specifica- tion. The power dissipated in the MOSFET is calculated by: PMOSFET = (VIN – VOUT) • IOUT In the design example, P MOSFET = (1.8V – 1.5V) • 4A = 1.2W. The Si4410’s RTH(JA) is 50°C/W for its S0-8 pack- age, which translates to a 60 °C temperature rise above ambient. MOSFET manufacturers have significantly low- ered the thermal resistance of modern devices with im- proved packages. These packages provide exposed backsides that directly transfer heat to the PCB board. These packages enable LT3150 applications with much higher output currents while keeping the MOSFET tem- perature in control.

Figure 3. Simplified Block Diagram for Frequency Compensation

3150 F03

capacitor type (ceramic, tantalum, electrolytic). therefore the COMP pin network sets the “zero” location. the correct spot in the frequency response. change and thus, results in output voltage perturbation.

Figure 4. Typical Bode Plot for

3150 F04

3150 F05

Figure 5. Typical Bode Plot for Tantalum increase output capacitance. at a low enough frequency to provide adequate phase boost. stability or it makes the small signal settling time very long. Z1 provides phase boost prior to crossing unity gain. exist just beyond the unity-gain crossover frequency. provide the desired response. decoupling capacitors and run wide planes if possible. the preceding paragraph to be eliminated or fine tuned.

Setting the Linear Regulator Output Voltage Using No RSENSE Current Limit Shutdown Time-Out with Reset Overvoltage Protection Shutdown Time-Out with Reset Basic Thermal Shutdown Setting Current Limit Current Limit with Foldback Limiting Example TYPICAL APPLICATIO SU FB2

3150 TA03

VOUT = 1.21V(1 + R2/R1) VOUT 10mF MBR0520L CT IPOSSHDN2 V IN1

3150 TA04VOUT

RSENSE* *ILIM = 50mV/RSENSE RSENSE = DISCRETE SHUNT RESISTOR OR RSENSE = KELVIN-SENSED PC BOARD TRACE ACTIVATING CURRENT LIMIT ALSO ACTIVATES THE SHDN2 PIN TIMER 3150 TA05 VOUT INEG GATE IPOS VIN1 IOUT 1N4148 1N4148

3150 TA06

SET R5 << R6 IOUT = – R6 R5 + R6() R5 + R6() (VIN1 – VOUT – 2VF) 100k C1*

3150 TA07

*C1 = 15mA(t)/1.11V t = SHUTDOWN LATCHOFF TIME SHDN2 VN2222L RESET 0V TO 5V SHDN2

3150 TA08

V IN1 R4* RT1 = DALE NTHS-1206N02 THERMALLY MOUNT RT1 IN CLOSE PROXIMITY TO THE EXTERNAL N-CHANNEL MOSFET *CHOOSE R4 BASED ON V IN1 AND REQUIRED THERMAL SHUTDOWN TEMPERATURE 100k 100k C2*

3150 TA09

*C2 = 15mA(t)/1.11V t = SHUTDOWN LATCH-OFF TIME SHDN2 2N3904 RESET 0V TO 5V SHDN2

3150 TA10

VOUT(uth) = 1.21(R6/R5) + 5mA(R6) VOUT(lth) = 1.11(R6/R5) – 15mA(R6)

1.5V to 1.2V, 4A Very Low Dropout Linear Regulator VIN2 FB1 SHDN2 SWGND GND GND SW V IN1 SHDN1 IPOS INEG GATE FB2 COMP LT3150 MBR0520L 10µH 1.5k 4.7µF + CIN 220µF 2.5V V IN 1.5V VOUT 1.2V 5.9k 1.37k Si4410

3150 TA11

2.2µF ·10 X5R CERAMIC 5.1Ω 6800pF 50pF CIN: PANASONIC SP SERIES EEFUE0E221R 20% C1: AVX TAJA475M020R 20V 20% L1: MURATA LQH32CN100K11 OR SUMIDA CDRH3D16100 VIN2 FB1 SHDN2 SWGND GND GND SW V IN1 SHDN1 IPOS INEG GATE FB2 COMP LT3150 MBR0520L 10µH 1.5k 499Ω 1020Ω 4.7µF + CIN 220µF V IN 2.5V VOUT 1.8V 1.7A 6.65k 1.37k Si4410

3150 TA11a

2.2µF ·6 X5R CERAMIC 5.1Ω 6800pF 50pF CIN: PANASONIC SP SERIES EEFUE0G221R 20% C1: AVX TAJA475M020R 20V 20% L1: MURATA LQH32CN100K11 OR SUMIDA CDRH3D16100 2.5V to 1.8V, 1.7A Low Dropout Linear Regulator

16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) GN16 (SSOP) 0502 12 3 4 5 6 7 8 .229 – .244 (5.817 – 6.198) .150 – .157** (3.810 – 3.988) 16 15 14 13 .189 – .196* (4.801 – 4.978) 12 11 10 9 .016 – .050 (0.406 – 1.270) .015 – .004 (0.178 – 0.249) .053 – .068 (1.351 – 1.727) .008 – .012 (0.203 – 0.305) .004 – .0098 (0.102 – 0.249) .0250 (0.635) BSC .009 (0.229) REF .254 MIN RECOMMENDED SOLDER PAD LAYOUT .150 – .165 .0250 TYP.0165 – .0015 .045 –.005 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE INCHES (MILLIMETERS) NOTE: 1. CONTROLLING DIMENSION: INCHES 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

ª LINEAR TECHNOLOGY CORPORATION 2002 LT/TP 1003 1K • PRINTED IN THE USA Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 l FAX: (408) 434-0507 l www.linear.com RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1573 UltraFast Transient Response Low Dropout V IN: 2.8V to 10V, VOUT: 1.265V, Dropout Voltage: 0.35V, IQ: 1.7mA, Regulator PNP Driver, Up to 5A I SD: 200mA, Requires External PNP Transistor, S8 Package LT1575/LT1577 UltraFast Transient Response Low Dropout V IN: 1.5V to 22V, VOUT: 1.21V, Dropout Voltage: 0.15V, IQ: 12mA, Regulator MOSFET Driver, Up to 10A LT1577 is Dual Version, N8, S8 Packages LT1761 100mA, Low Noise Micropower, LDO V IN: 1.8V to 20V, VOUT: 1.22V, Dropout Voltage: 0.30V, IQ: 20mA, ISD: <1mA, Low Noise <20mVRMS P-P, Stable with 1mF Ceramic Capacitors, ThinSOT Package LT1762 150mA, Low Noise Micropower, LDO V IN: 1.8V to 20V, VOUT: 1.22V, Dropout Voltage: 0.30V, IQ: 25mA, ISD: <1mA, Low Noise <20mVRMS P-P, MS8 Package LT1763 500mA, Low Noise Micropower, LDO V IN: 1.8V to 20V, VOUT: 1.22V, Dropout Voltage: 0.30V, IQ: 30mA, ISD: <1mA, Low Noise <20mVRMS P-P, S8 Package LT1764/LT1764A 3A, Low Noise, Fast Transient Response, LDO V IN: 2.7V to 20V, VOUT: 1.21V, Dropout Voltage: 0.34V, IQ: 1mA, ISD: <1mA,Low Noise <40mVRMS P-P, “A” Version Stable with Ceramic Capacitors, DD, TO220-5 Packages LT1962 300mA, Low Noise Micropower, LDO V IN: 1.8V to 20V, VOUT: 1.22V, Dropout Voltage: 0.27V, IQ: 30mA, ISD: <1mA, Low Noise <20mVRMS P-P, MS8 Package LT1963/LT1963A 1.5A, Low Noise, Fast Transient Response, LDO V IN: 2.1V to 20V, VOUT: 1.21V, Dropout Voltage: 0.34V, IQ: 1mA, ISD: <1mA, Low Noise <40mVRMS P-P, “A” Version Stable with Ceramic Capacitors, DD, T0220-5, SOT-223, S8 Packages DC/DC Converter I SD: <1mA, MS and DFN Packages DC/DC Converter I SD: <1mA, TSSOP16E Package UTYPICAL APPLICATIO 1.8V to 1.5V, 4A Very Low Dropout Linear Regulator with No RSENSE Current Limiting and Shutdown VIN2 FB1 SHDN2 SWGND GND GND SW V IN1 SHDN1 IPOS INEG GATE FB2 COMP LT3150 MBR0520L 10µH 10kSHDN1 1.5k 243Ω 1020Ω 4.7µF 0.01µF SHDN2 + CIN 220µF 2.5V V IN 1.8V VOUT 1.5V 6.19k 1.37k Si4410 2.2µF ·10 X5R CERAMIC 5.1Ω BAT54 6800pF 50pF 10µF CIN: PANASONIC SP SERIES EEFUE0E221R 20% C1: AVX TAJA475M020R 20V 20% L1: MURATA LQH32CN100K11 OR SUMIDA CDRH3D16100

Summary

Fast Transient Response, Low Input Voltage, Very Low Dropout Linear Regulator Controller

Description