LT1725 LINER | Alldatasheet
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t ON ENDLY MENAB R OCMP RCMPC VCC UVLO GATE ISENSE SGND PGND 1nF 0.1µF 47pF 51k 51k 51k 2.7k 35.7k 3.01k 1% + 15µF 150µF 1µF 1.5µF 47k 820k 100pF 33k 68Ω 150pF 22Ω BAS16 VIN 36V TO 72V IRF620 18Ω 51Ω 470pF 12CWQ06 VOUT = 5V IOUT = 0 to 2A CTX02-14989
1725 TA01a
0.18Ω FEATURES DESCRIPTIO U TYPICAL APPLICATIO U APPLICATIO SU General Purpose Isolated Flyback Controller The LT 1725 is a monolithic switching regulator control- ler specifically designed for the isolated flyback topology. It drives the gate of an external MOSFET and is generally powered from a third transformer winding. These features allow for an application input voltage limited only by external power path components. The third transformer winding also provides output voltage feedback informa- tion, such that an optoisolator is not required. Its gate drive capability coupled with a suitable external MOSFET can deliver load power up to tens of watts. The LT1725 has a number of features not found on most other switching regulator ICs. By utilizing current mode switching techniques, it provides excellent AC and DC line regulation. Its unique control circuitry can maintain regu- lation well into discontinuous mode in most applications. Optional load compensation circuitry allows for improved load regulation. An optional undervoltage lockout pin halts operation when the application input voltage is too low. An optional external capacitor implements a soft- start function. A 3V output is available at up to several mA for powering primary side application circuitry. n Drives External Power MOSFET with External ISENSE Resistor n Application Input Voltage Limited Only by External Power Components n Senses Output Voltage Directly from Primary Side Winding—No Optoisolator Required n Accurate Regulation Without User Trims n Regulation Maintained Well into Discontinuous Mode n Switching Frequency from 50kHz to 250kHz with External Capacitor n Optional Load Compensation n Optional Undervoltage Lockout n Available in 16-Pin SO and SSOP Packages , LTC and LT are registered trademarks of Linear Technology Corporation. n Telecom Isolated Converters n Offline Isolated Power Supplies n Instrumentation Power Supplies Output Load Regulation 48V to Isolated 5V Converter ILOAD (A) VOUT (V)5.00
1725 F10b
4.75 0.5 1.0 1.5 2.0 5.25 VIN = 36V VIN = 72V VIN = 48V
(Note 1) Operating Junction Temperature Range ORDER PART NUMBER LT1725CGN LT1725CS LT1725IGN LT1725IS TJMAX = 125°C, qJA = 110°C/W (GN) TJMAX = 125°C, qJA = 100°C/W (SO) PACKAGE/ORDER I FOR ATIOUU WABSOLUTE AXI U RATI GSW WW U TOP VIEW S PACKAGE 16-LEAD PLASTIC SO GN PACKAGE 16-LEAD PLASTIC SSOP PGND ISENSE SFST ROCMP RCMPC OSCAP VC FB GATE VCC tON ENDLY MINENAB SGND UVLO OUT The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 14V, GATE open, VC = 1.4V unless otherwise noted.
ELECTRICAL CHARACTERISTICS
Consult LTC Marketing for parts specified with wider operating temperature ranges. GN PART MARKING 1725 1725I SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Supply VCC VCC Turn-On Voltage l 14.0 15.1 16.0 V VCC Turn-Off Voltage l 8 9.7 11 V VCC Hysteresis (Note 3) (V TURN-ON – VTURN-OFF) l 4.0 5.4 6.5 V ICC Supply Current V C = Open l 61 0 1 5 m A Start-Up Current l 120 280 mA Feedback Amplifier VFB Feedback Voltage 1.230 1.245 1.260 V l 1.220 1.270 V IFB Feedback Pin Input Current 500 nA gm Feedback Amplifier Transconductance DlC = –10mA l 400 1000 1800 mmho ISRC, ISNK Feedback Amplifier Source or Sink Current l 30 50 80 mA VCL Feedback Amplifier Clamp Voltage 2.5 V Reference Voltage/Current Line Regulation 12V £ VIN £ 18V l 0.01 0.05 %/V Voltage Gain V C = 1V to 2V 2000 V/V Soft-Start Charging Current V SFST = 0V 25 40 50 mA Soft-Start Discharge Current V SFST = 1.5V, VUVLO = 0V 0.8 1.5 mA Gate Output VGATE Output High Level I GATE = 100mA l 11.5 12.1 V IGATE = 500mA l 11.0 11.8 V Output Low Level I GATE = 100mA l 0.3 0.45 V IGATE = 500mA l 0.6 1.0 V IGATE Output Sink Current in Shutdown, VUVLO = 0V V GATE = 2V l 1.2 2.5 mA tr Rise Time C L = 1000pF 30 ns tf Fall Time C L = 1000pF 30 ns
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Component value range guaranteed by design. Note 3: The VCC turn-on/turn-off voltages and hysteresis voltage are proportional in magnitude to each other-guaranteed by design. The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 14V, GATE open, VC = 1.4V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Current Amplifier VC Control Pin Threshold Duty Cycle = Min 0.90 1.12 1.25 V l 0.80 1.35 V VISENSE Switch Current Limit Duty Cycle £ 30% 220 250 270 mV Duty Cycle £ 30% l 200 280 mV Duty Cycle = 80% 220 mV DVISENSE/DVC 0.30 mV Timing f Switching Frequency C OSCAP = 100pF 90 100 115 kHz l 80 125 kHz COSCAP Oscillator Capacitor Value (Note 2) 33 200 pF tON Minimum Switch On Time R tON = 50k 200 ns tED Flyback Enable Delay Time R ENDLY = 50k 200 ns tEN Minimum Flyback Enable Time R MENAB = 50k 200 ns Rt Timing Resistor Value (Note 2) 24 200 k W Maximum Switch Duty Cycle l 85 90 % Load Compensation Sense Offset Voltage 25 m V Current Gain Factor 0.80 0.95 1.05 mV UVLO Function VUVLO UVLO Pin Threshold l 1.21 1.25 1.29 V IUVLO UVLO Pin Bias Current V UVLO = 1.2V –0.25 +0.1 +0.25 mA VUVLO = 1.3V –4.50 –3.5 –2.50 mA 3V Output Function VREF Reference Output Voltage I LOAD = 1mA l 2.8 3.0 3.2 V Output Impedance 10 W Current Limit l 81 5 m A
TYPICAL PERFOR A CE CHARACTERISTICS UW TEMPERATURE (°C) –50 16.00 15.75 15.50 15.25 15.00 14.75 14.50 14.25 25 75
1725 G01
–25 0 50 100 125 VCC TURN-ON VOLTAGE (V) TEMPERATURE (°C) –50 6.50 6.25 6.00 5.75 5.50 5.25 5.00 4.75 25 75
1725 G02
–25 0 50 100 125 VCC HYSTERESIS VOLTAGE (V) TEMPERATURE (°C) –50 START-UP CURRENT (µA) 250 200 150 100 0 50 75
1725 G03
–25 25 100 125 VCC Turn-On Voltage vs Temperature VCC Hysteresis Voltage vs Temperature Start-Up Current vs Temperature TEMPERATURE (°C) –50 SUPPLY CURRENT (mA) 0 50 75
1725 G04
–25 25 100 125 TEMPERATURE (°C) –50 25 75
1725 G05
–25 0 50 100 125 UVLO PIN INPUT CURRENT (µA) VUVLO = 1.3V VUVLO = 1.2V TEMPERATURE (°C) –50 OSCILLATOR FREQUENCY (kHz) 115 110 105 100 25 75
1725 G06
–25 0 50 100 125 ISINK (mA) VGATE (V) 1.0 0.8 0.6 0.4 0.2 10 100 1000
1725 G07
TA = 125°C TA = –55°C TA = 25°C ISOURCE (mA) VCC-VGATE (V) –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 10 100 1000
1725 G08
TA = 125°C TA = –55°C TA = 25°C TEMPERATURE (°C) –50 VC CLAMP VOLTAGE, SWITCHING THRESHOLD (V) 3.0 2.5 2.0 1.5 1.0 0.5 25 75
1725 G09
–25 0 50 100 125 CLAMP VOLTAGE SWITCHING THRESHOLD Supply Current vs Temperature UVLO Pin Input Current vs Temperature Oscillator Frequency vs Temperature VGATE vs ISINK VCC-VGATE vs ISOURCE VC Clamp Voltage, Switching Threshold vs Temperature
TYPICAL PERFOR A CE CHARACTERISTICS UW TEMPERATURE (°C) –50 MINIMUM SWITCH-ON TIME (ns) 275 250 225 200 175 150 125 25 75
1725 G10
–25 0 50 100 125 RTON = 50k TEMPERATURE (°C) –50 MINIMUM ENABLE TIME (ns) 275 250 225 200 175 150 125 25 75
1725 G11
–25 0 50 100 125 RMINENAB = 50k TEMPERATURE (°C) –50 ENABLE DELAY TIME (ns) 275 250 225 200 175 150 125 25 75
1725 G12
–25 0 50 100 125 FB PIN VOLTAGE (V) 1.05 FEEDBACK AMPLIFIER OUTPUT CURRENT (µA) 1.35
1725 G13
1.15 1.25 –20 –40 –60 –80 1.10 1.20 1.30 1.40 TA = 125°C TA = –55 °CTA = 25°C TEMPERATURE (°C) –50 1600 1400 1200 1000 800 600 400 200 25 75
1725 G14
–25 0 50 100 125 FEEDBACK AMPLIFIER TRANSCONDUCTANCE (µmho) TEMPERATURE (°C) –50 SOFT-START CHARGING CURRENT (µA) 25 75
1725 G15
–25 0 50 100 125 V(SFST) = 0V TEMPERATURE (°C) –50 SOFT-START SINK CURRENT (mA) 2.5 2.0 1.5 1.0 0.5 0 50 75
1725 G16
–25 25 100 125 V(SFST) = 1.5V Minimum Switch-On Time vs Temperature Minimum Enable Time vs Temperature Enable Delay Time vs Temperature Feedback Amplifier Output Current vs FB Pin Voltage Feedback Amplifier Transconductance vs Temperature Soft-Start Charging Current vs Temperature Soft-Start Sink Current vs Temperature
PGND (Pin 1): The power ground pin carries the GATE node discharge current. This is typically a current spike of several hundred mA with a duration of tens of nanosec- onds. It should be connected directly to a good quality ground plane. ISENSE (Pin 2): Pin to measure switch current with exter- nal sense resistor. The sense resistor should be of a noninductive construction as high speed performance is essential. Proper grounding technique is also required to avoid distortion of the high speed current waveform. A preset internal limit of nominally 250mV at this pin effects a switch current limit. SFST (Pin 3): Pin for optional external capacitor to effect soft-start function. See Applications Information for details. ROCMP (Pin 4): Input pin for optional external load compen- sation resistor. Use of this pin allows nominal compensa- tion for nonzero output impedance in the power transformer secondary circuit, including secondary winding impedance, output Schottky diode impedance and output capacitor ESR. In less demanding applications, this resistor is not needed. See Applications Information for more details. R CMPC (Pin 5): Pin for external filter capacitor for optional load compensation function. A common 0.1 mF ceramic capacitor will suffice for most applications. See Applica- tions Information for further details. OSCAP (Pin 6): Pin for external timing capacitor to set oscillator switching frequency. See Applications Informa- tion for details. VC (pin 7): This is the control voltage pin which is the output of the feedback amplifier and the input of the current comparator. Frequency compensation of the overall loop is effected in most cases by placing a capaci- tor between this node and ground. FB (Pin 8): Input pin for external “feedback” resistor divider. The ratio of this divider, times the internal bandgap (VBG) reference, times the effective output-to- third winding transformer turns ratio is the primary deter- minant of the output voltage. The Thevenin equivalent resistance of the feedback divider should be roughly 3k. See Applications Information for more details. OUT (Pin 9): Output pin for nominal 3V reference. This facilitates various user applications. This node is internally current limited for protection and is intended to drive either moderate capacitive loads of several hundred pF or less, or, very large capacitive loads of 0.1mF or more. See Applications Information for more details. UVLO (Pin 10): This pin allows the use of an optional external resistor divider to set an undervoltage lockout based upon V IN (not VCC) level. (Note: If the VCC voltage is sufficient to allow the part to start up, but the UVLO pin is held below its threshold, output switching action will be disabled, but the part will draw its normal quiescent current from V CC. This typically causes a benign relaxation oscillation action on the V CC pin in the conventional “trickle-charge” bootstrapped configuration.) The bias current on this pin is a function of the state of the UVLO comparator; as the threshold is exceeded, the bias current increases. This creates a hysteresis band equal to the change in bias current times the Thevenin impedance of the user’s resistive divider. The user may thereby adjust the impedance of the UVLO divider to achieve a desired degree of hysteresis. A 100pF capacitor to ground is recommended on this pin. See Applications Information for details. SGND (Pin 11): The signal ground pin is a clean ground. The internal reference, oscillator and feedback amplifier are referred to it. Keep the ground path connection to the FB pin, OSCAP capacitor and the V C compensation capaci- tor free of large ground currents. MINENAB (Pin 12): Pin for external programming resistor to set minimum enable time. See Applications Information for details.
(INTERNAL) BIAS VC SOFT-START LOAD COMPENSATION ISENSE GATE PGND ROCMPSFST RCMPC SGND 1725 BD LOGIC UUUPI FU CTIO S ENDLY (Pin 13): Pin for external programming resistor to set enable delay time. See Applications Information for details. tON (Pin 14): Pin for external programming resistor to set switch minimum on time. See Applications Information for details. VCC (Pin 15): Supply voltage for the LT1725. Bypass this pin to ground with 1mF or more. GATE (Pin 16): This is the gate drive to the external power MOSFET switch and has large dynamic currents flowing through it. Keep the trace to the MOSFET as short as possible to minimize electromagnetic radiation and volt- age spikes. A series resistance of 5W or more may help to dampen ringing in less than ideal layouts.
MINIMUM ENABLE TIME 1725 TD OFF ONSWITCH STATE FLYBACK AMP STATE 0.80· VFLBK VFLBK COLLAPSE DETECT ENABLEDDISABLED DISABLED FLYBACK ERROR A PLIFIERW ISOLATED VOUTC1 VIN VC R1 FB VBGQ1 Q2 I IM IM IFXD ENAB 1725 EA
The LT1725 is a current mode switcher controller IC designed specifically for the isolated flyback topology. The Block Diagram shows an overall view of the system. Many of the blocks are similar to those found in traditional designs, including: Internal Bias Regulator, Oscillator, Logic, Current Amplifier and Comparator, Driver and Out- put Switch. The novel sections include a special Flyback Error Amplifier and a Load Compensation mechanism. Also, due to the special dynamic requirements of flyback control, the Logic system contains additional functionality not found in conventional designs. The LT1725 operates much the same as traditional current mode switchers, the major difference being a different type of error amplifier that derives its feedback informa- tion from the flyback pulse. Due to space constraints, this discussion will not reiterate the basics of current mode switcher/controllers and isolated flyback converters. A good source of information on these topics is Application Note AN19. ERROR AMPLIFIER—PSEUDO DC THEORY Please refer to the simplified diagram of the Flyback Error Amplifier. Operation is as follows: when MOSFET output switch M1 turns off, its drain voltage rises above the V IN rail. The amplitude of this flyback pulse as seen on the third winding is given as: V V V I ESR NFLBK OUT F SEC ST = ++() · VF = D1 forward voltage ISEC = transformer secondary current ESR = total impedance of secondary circuit N ST = transformer effective secondary-to-third winding turns ratio The flyback voltage is then scaled by external resistor divider R1/R2 and presented at the FB pin. This is then compared to the internal bandgap reference by the differ- ential transistor pair Q1/Q2. The collector current from Q1 is mirrored around and subtracted from fixed current source I FXD at the VC pin. An external capacitor integrates this net current to provide the control voltage to set the current mode trip point. OPERATIOU The relatively high gain in the overall loop will then cause the voltage at the FB pin to be nearly equal to the bandgap reference V BG. The relationship between V FLBK and V BG may then be expressed as: V RR R VFLBK BG= +()12 Combination with the previous VFLBK expression yields an expression for V OUT in terms of the internal reference, programming resistors, transformer turns ratio and diode forward voltage drop: VV RR RN V I ESROUT BG ST FS E C= +() æ Łç ö 1 ±± · Additionally, it includes the effect of nonzero secondary output impedance, which is discussed below in further detail, see Load Compensation Theory. The practical as- pects of applying this equation for VOUT are found in the Applications Information section. So far, this has been a pseudo-DC treatment of flyback error amplifier operation. But the flyback signal is a pulse, not a DC level. Provision must be made to enable the flyback amplifier only when the flyback pulse is present. This is accomplished by the dotted line connections to the block labeled “ENAB”. Timing signals are then required to enable and disable the flyback amplifier. ERROR AMPLIFIER—DYNAMIC THEORY There are several timing signals which are required for proper LT1725 operation. Please refer to the Timing Diagram. Minimum Output Switch On Time The LT1725 effects output voltage regulation via flyback pulse action. If the output switch is not turned on at all, there will be no flyback pulse and output voltage informa- tion is no longer available. This would cause irregular loop response and start-up/latchup problems. The solution cho- sen is to require the output switch to be on for an absolute minimum time per each oscillator cycle. This in turn estab- lishes a minimum load requirement to maintain regula- tion. See Applications Information for further details.
Applications Information for further details. the low load level at which output voltage regulation is lost. See Applications Information for details.
1725 F01
Figure 1. Load Compensation Diagram
transformer secondary and output capacitor. This has been represented previously by the expression “I SEC • ESR.” However, it is generally more useful to convert this expression to an effective output impedance. Because the secondary current only flows during the off portion of the duty cycle, the effective output impedance equals the lumped secondary impedance times the inverse of the OFF duty cycle. That is: R ESR DC OUT OFF = æ Łç ö where ROUT = effective supply output impedance ESR = lumped secondary impedance DC OFF = OFF duty cycle Expressing this in terms of the ON duty cycle, remember- ing DCOFF = 1 – DC, R ESR DC OUT = æ Łç ö DC = ON duty cycle In less critical applications, or if output load current remains relatively constant, this output impedance error may be judged acceptable and the external FB resistor divider adjusted to compensate for nominal expected error. In more demanding applications, output impedance error may be minimized by the use of the load compensa- tion function. To implement the load compensation function, a voltage is developed that is proportional to average output switch current. This voltage is then impressed across the external R OCMP resistor, and the resulting current acts to increase the VBG reference used by the flyback error amplifier. As output loading increases, average switch current increases to maintain rough output voltage regulation. This causes an increase in R OCMP resistor current which effects a corresponding increase in target output voltage. Assuming a relatively fixed power supply efficiency, Eff, Power Out = Eff • Power In VOUT • IOUT = Eff • VIN • IIN Average primary side current may be expressed in terms of output current as follows: OPERATIOU I V V EFF IIN OUT IN OUT= æ Łç ö ł÷· · combining the efficiency and voltage terms in a single variable: IIN = K1 • IOUT, where K V V EFF OUT IN 1= æ Łç ö ł÷· Switch current is converted to voltage by the external sense resistor and averaged/lowpass filtered by R3 and the external capacitor on R CMPC. This voltage is then impressed across the external ROCMP resistor by op amp A1 and transistor Q3. This produces a current at the collector of Q3 which is then mirrored around and then subtracted from the FB node. This action effectively in- creases the voltage required at the top of the R1/R2 feedback divider to achieve equilibrium. So the effective change in V OUT target is: D=D () æ Łç ö D D = æ Łç ö VK I R R RRo r V I K R R RR OUT OUT SENSE OCMP OUT OUT SENSE OCMP 11 2 11 2
- · ( | | )
- ( || ) Nominal output impedance cancellation is obtained by equating this expression with ROUT: RK R R R R and RK R R R R where OUT SENSE OCMP OCMP SENSE OUT = æ Łç ö = æ Łç ö 11 2 11 2
- ( || )
- ( || ) K1 = dimensionless variable related to VIN, VOUT and efficiency as above RSENSE = external sense resistor ROUT = uncompensated output impedance (R1||R2) = impedance of R1 and R2 in parallel The practical aspects of applying this equation to deter- mine an appropriate value for the ROCMP resistor are found in the Applications Information section.
APPLICATIO S I FOR ATIOWU UU TRANSFORMER DESIGN CONSIDERATIONS Transformer specification and design is perhaps the most critical part of applying the LT1725 successfully. In addi- tion to the usual list of caveats dealing with high frequency isolated power supply transformer design, the following information should prove useful. Turns Ratios Note that due to the use of the external feedback resistor divider ratio to set output voltage, the user has relative freedom in selecting transformer turns ratio to suit a given application. In other words, “screwball” turns ratios like “1.736:1.0” can scrupulously be avoided! In contrast, simpler ratios of small integers, e.g., 1:1, 2:1, 3:2, etc. can be employed which yield more freedom in setting total turns and mutual inductance. Turns ratio can then be chosen on the basis of desired duty cycle. However, remember that the input supply voltage plus the second- ary-to-primary referred version of the flyback pulse (in- cluding leakage spike) must not exceed the allowed external MOSFET breakdown rating. Leakage Inductance Transformer leakage inductance (on either the primary or secondary) causes a spike after output switch turnoff. This is increasingly prominent at higher load currents, where more stored energy must be dissipated. In many cases a “snubber” circuit will be required to avoid overvoltage breakdown at the output switch node. Application Note AN19 is a good reference on snubber design. In situations where the flyback pulse extends beyond the enable delay time, the output voltage regulation will be affected to some degree. It is important to realize that the feedback system has a deliberately limited input range, roughly –50mV referred to the FB node, and this works to the user’s advantage in rejecting large, i.e., higher voltage, leakage spikes. In other words, once a leakage spike is several volts in amplitude, a further increase in amplitude has little effect on the feedback system. So the user is generally advised to arrange the snubber circuit to clamp at as high a voltage as comfortably possible, observing MOSFET breakdown, such that leakage spike duration is as short as possible. As a rough guide, total leakage inductances of several percent (of mutual inductance) or less may require a snubber, but exhibit little to no regulation error due to leakage spike behavior. Inductances from several percent up to perhaps ten percent cause increasing regulation error. Severe leakage inductances in the double digit percentage range should be avoided if at all possible as there is a potential for abrupt loss of control at high load current. This curious condition potentially occurs when the leak- age spike becomes such a large portion of the flyback waveform that the processing circuitry is fooled into thinking that the leakage spike itself is the real flyback signal! It then reverts to a potentially stable state whereby the top of the leakage spike is the control point, and the trailing edge of the leakage spike triggers the collapse detect circuitry. This will typically reduce the output volt- age abruptly to a fraction, perhaps between one-third to two-thirds of its correct value. If load current is reduced sufficiently, the system will snap back to normal opera- tion. When using transformers with considerable leakage inductance, it is important to exercise this worst-case check for potential bistability: 1. Operate the prototype supply at maximum expected load current. 2. Temporarily short circuit the output. 3. Observe that normal operation is restored. If the output voltage is found to hang up at a abnormally low value, the system has a problem. This will usually be evident by simultaneously monitoring the V SW waveform on an oscilloscope to observe leakage spike behavior firsthand. A final note—the susceptibility of the system to bistable behavior is somewhat a function of the load I/V characteristics. A load with resistive, i.e., I = V/R behavior is the most susceptible to bistability. Loads which exhibit “CMOSsy”, i.e., I = V 2/R behavior are less susceptible. Secondary Leakage Inductance In addition to the previously described effects of leakage inductance in general, leakage inductance on the second- ary in particular exhibits an additional phenomenon. It forms an inductive divider on the transformer secondary,
APPLICATIO S I FOR ATIOWU UU which reduces the size of the primary-referred flyback pulse used for feedback. This will increase the output voltage target by a similar percentage. Note that unlike leakage spike behavior, this phenomena is load indepen- dent. To the extent that the secondary leakage inductance is a constant percentage of mutual inductance (over manufacturing variations), this can be accommodated by adjusting the feedback resistor divider ratio. Winding Resistance Effects Resistance in either the primary or secondary will act to reduce overall efficiency (P OUT/PIN). Resistance in the secondary increases effective output impedance which degrades load regulation, (at least before load compensa- tion is employed). Bifilar Winding A bifilar or similar winding technique is a good way to minimize troublesome leakage inductances. However re- member that this will increase primary-to-secondary ca- pacitance and limit the primary-to-secondary breakdown voltage, so bifilar winding is not always practical. Finally, the LTC Applications group is available to assist in the choice and/or design of the transformer. Happy Winding! SELECTING FEEDBACK RESISTOR DIVIDER VALUES The expression for VOUT developed in the Operation sec- tion can be rearranged to yield the following expression for the R1/R2 ratio: RR R V V I ESR V NOUT F SEC BG ST +() = ++() · where: VOUT = desired output voltage VF = switching diode forward voltage ISEC • ESR = secondary resistive losses VBG = data sheet reference voltage value NST = effective secondary-to-third winding turns ratio The above equation defines only the ratio of R1 to R2, not their individual values. However, a “second equation for two unknowns” is obtained from noting that the Thevenin impedance of the resistor divider should be roughly 3k for bias current cancellation and other reasons. SELECTING R OCMP RESISTOR VALUE The Operation section previously derived the following expressions for ROUT, i.e., effective output impedance and ROCMP, the external resistor value required for its nominal compensation: R ESR DC RK R R RR OUT OCMP SENSE OUT = æ Łç ö = æ Łç ö ł÷() 11 2 While the value for ROCMP may therefore be theoretically determined, it is usually better in practice to employ empirical methods. This is because several of the required input variables are difficult to estimate precisely. For instance, the ESR term above includes that of the trans- former secondary, but its effective ESR value depends on high frequency behavior, not simply DC winding resis- tance. Similarly, K1 appears to be a simple ratio of V IN to VOUT times (differential) efficiency, but theoretically esti- mating efficiency is not a simple calculation. The sug- gested empirical method is as follows: Build a prototype of the desired supply using the eventual secondary components. Temporarily ground the R CMPC pin to disable the load compensation function. Operate the supply over the expected range of output current loading while measuring the output voltage deviation. Approxi- mate this variation as a single value of ROUT (straight line approximation). Calculate a value for the K1 constant based on VIN, VOUT and the measured (differential) effi- ciency. These are then combined with RSENSE as indicated to yield a value for ROCMP. Verify this result by connecting a resistor of roughly this value from the R OCMP pin to ground. (Disconnect the ground short to R CMPC and connect the requisite 0.1 mF filter capacitor to ground.) Measure the output impedance
and the OSCAP node length/area minimized. action, especially at light load. havior (see Maximum Load/Short-Circuit Considerations). to be short to minimize these load related consequences. switching current spike considerations.
1725 F02
Figure 2. fOSC vs OSCAP Value time versus external resistor value for these functions. optimizing these timing values.
1725 F03
Figure 3. “One Shot” Times vs Programming Resistor
to transformer leakage inductance. This spike is not in- dicative of actual output voltage (see Figure 4B). Delaying the enabling of the feedback amplifier allows this system to effectively ignore most or all of the voltage spike and maintain proper output voltage regulation. The enable delay time should therefore be set to the maximum ex- pected duration of the leakage spike. This may have implications regarding output voltage regulation at mini- mum load (see Minimum Load Considerations). A second benefit of the enable delay time function occurs at light load. Under such conditions the amount of energy stored in the transformer is small. The flyback waveform becomes “lazy” and some time elapses before it indicates the actual secondary output voltage (see Figure 4C). So the enable delay time should also be set long enough to ignore the “irrelevant” portion of the flyback waveform at light load. Additionally, there are cases wherein the gate output is called upon to drive a large geometry MOSFET such that the turnoff transition is slowed significantly. Under such circumstances, the enable delay time may be increased to accommodate for the lengthy transition. Minimum Enable Time This function sets a minimum duration for the expected flyback pulse. Its primary purpose is to provide a mini- mum source current at the V C node to avoid start-up problems. Average “start-up” VC current = MinimumEnable Time SwitchingFrequency ISRC· Minimum enable time can also have implications at light load (see Minimum Load Considerations). The temptation is to set the minimum enable time to be fairly short, as this is the least restrictive in terms of minimum load behavior. However, to provide a “reliable” minimum start-up current of say, nominally 1mA, the user should set the minimum enable time at no less that 2% of the switching period (= 1/switching frequency). CURRENT SENSE RESISTOR CONSIDERATIONS The external current sense resistor allows the user to optimize the current limit behavior for the particular appli- cation under consideration. As the current sense resistor is varied from several ohms down to tens of milliohms, peak switch current goes from a fraction of an ampere to tens of amperes. Care must be taken to ensure proper circuit operation, especially with small current sense resistor values. For example, a peak switch current of 10A requires a sense resistor of 0.025W . Note that the instantaneous peak power in the sense resistor is 2.5W, and it must be rated accord- ingly. The LT1725 has only a single sense line to this re- sistor. Therefore, any parasitic resistance in the ground side connection of the sense resistor will increase its apparent value. In the case of a 0.025W sense resistor, one milliohm of parasitic resistance will cause a 4% reduction in peak switch current. So resistance of printed circuit copper traces and vias cannot necessarily be ignored. An additional consideration is parasitic inductance. Induc- tance in series with the current sense resistor will accen- tuate the high frequency components of the current waveform. In particular, the gate switching spike and multimegahertz ringing at the MOSFET can be considerably APPLICATIO S I FOR ATIOWU UU ENABLE DELAY TIME NEEDED 1725 F04 DISCONTINUOUS MODE RINGING IDEALIZED FLYBACK WAVEFORM MOSFET GATE DRIVE FLYBACK WAVEFORM WITH LARGE LEAKAGE SPIKE AT HEAVY LOAD “SLOW” FLYBACK WAVEFORM AT LIGHT LOAD B A C ENABLE DELAY TIME NEEDED Figure 4
amplified. If severe enough, this can cause erratic opera- tion. For example, assume 3nH of parasitic inductance (equivalent to about 0.1 inch of wire in free space) is in series with an ideal 0.025W sense resistor. A “zero” will be formed at f = R/(2pL), or 1.3MHz. Above this frequency the sense resistor will behave like an inductor. Several techniques can be used to tame this potential parasitic inductance problem. First, any resistor used for current sensing purposes must be of an inherently non- inductive construction. Mounting this resistor directly above an unbroken ground plane and minimizing its ground side connection will serve to absolutely minimize parasitic inductance. In the case of low valued sense resistors, these may be implemented as a parallel combi- nation of several resistors for the thermal considerations cited above. The parallel combination will help to lower the parasitic inductance. Finally, it may be necessary to place a “pole” between the current sense resistor and the LT1725 I SENSE pin to undo the action of the inductive zero (see Figure 5). A value of 51W is suggested for the resistor, while the capacitor is selected empirically for the particular application and layout. Using good high frequency mea- surement techniques, the I SENSE pin waveform may be observed directly with an oscilloscope while the capacitor value is varied. APPLICATIO S I FOR ATIOWU UU GATE PARASITIC INDUCTANCE CCOMP RSENSE LP
1725 F05
51Ω PGNDSGND ISENSE f = RSENSE 2πLP SENSE RESISTOR ZERO AT: f = 1 2π(51Ω )CCOMP COMPENSATING POLE AT: CCOMP = LP RSENSE(51Ω ) FOR CANCELLATION: Figure 5 SOFT-START FUNCTION The LT1725 contains an optional soft-start function that is enabled by connecting an explicit external capacitor be- tween the SFST pin and ground. Internal circuitry prevents the control voltage at the V C pin from exceeding that on the SFST pin. The soft-start function is enagaged whenever VCC power is removed, or as a result of either undervoltage lockout or thermal (overtemperature) shutdown. The SFST node is then discharged to roughly a V BE above ground. (Remember that the VC pin control node switching thresh- old is deliberately set at a V BE plus several hundred millivolts.) When this condition is removed, a nominal 40mA current acts to charge up the SFST node towards roughly 3V. So, for example, a 0.1mF soft-start capacitor will place a 0.4V/ms limit on the ramp rate at the V C node. UVLO PIN FUNCTION The UVLO pin effects an undervoltage lockout function with at threshold of roughly 1.25V. An external resistor divider between the input supply and ground can then be used to achieve a user-programmable undervoltage lock- out (see Figure 6a). An additional feature of this pin is that there is a change in the input bias current at this pin as a function of the state of the internal UVLO comparator. As the pin is brought above the UVLO threshold, the bias current sourced by the part increases. This positive feedback effects a hysteresis band for reliable switching action. Note that the size of the hysteresis is proportional to the Thevenin impedance of the external UVLO resistor divider network, which makes it user programmable. As a rough rule of thumb, each 4k or so of impedance generates about 1% of hysteresis. (This is based on roughly 1.25V for the threshold and 3mA for the bias current shift.) Even in good quality ground plane layouts, it is common for the switching node (MOSFET drain) to couple to the UVLO pin with a stray capacitance of several thousandths of a pF. To ensure proper UVLO action, a 100pF capacitor is recommended from this pin to ground as shown in Figure 6b. This will typically reduce the coupled noise to a few millivolts. The UVLO filter capacitor should not be made much larger than a few hundred pF, however, as the hysteresis action will become too slow. In cases where further filtering is required, e.g., to attenuate high speed supply ripple, the topology in Figure 6c is recommended. Resistor R1 has been split into two equal parts. This provides a node for effecting capacitor filtering of high
(6a) “Standard” UVLO Divider Topology UVLO VIN (6b) Filter Capacitor Directly On UVLO Node UVLO R2C1 100pF VIN (6c) Recommended Topology to Filter High Frequency Ripple UVLO R1/2 R1/2
1725 F06
APPLICATIO S I FOR ATIOWU UU Figure 6 speed supply ripple, while leaving the UVLO pin node impedance relatively unchanged at high frequency. INTERNAL WIDE HYSTERESIS UNDERVOLTAGE LOCKOUT The LT1725 is designed to implement isolated DC/DC converters operating from input voltages of typically 48V or more. The standard operating topology utilizes a third transformer winding on the primary side that provides both feedback information and local power for the LT1725 via its V CC pin. However, this arrangement is not inherently self-starting. Start-up is effected by the use of an external “trickle-charge” resistor and the presence of an internal wide hysteresis undervoltage lockout circuit that monitors V CC pin voltage (see Figure 7). Operation is as follows: “Trickle charge” resistor R1 is connected to V IN and supplies a small current, typically on the order of a single mA, to charge C1. At first, the LT1725 is off and draws only its start-up current. After some time, the voltage on C1 CC) reaches the VCC turn-on threshold. The LT1725 then turns on abruptly and draws its normal supply current. Switching action commences at the GATE pin and the MOSFET begins to deliver power. The voltage on C1 begins to decline as the LT1725 draws its normal supply current, which greatly exceeds that delivered by R1. After some time, typically tens of milliseconds, the output voltage approaches its desired value. By this time, the third transformer winding is providing virtually all the supply current required by the LT1725. One potential design pitfall is undersizing the value of capacitor C1. In this case, the normal supply current + IVCC
1725 F07
drawn by the LT1725 will discharge C1 too rapidly; before the third winding drive becomes effective, the VCC turn-off threshold will be reached. The LT1725 turns off, and the V CC node begins to charge via R1 back up to the turn-on threshold. Depending upon the particular situation, this may result in either several on-off cycles before proper operation is reached, or, permanent relaxation oscillation at the V CC node. Component selection is as follows: Resistor R1 should be selected to yield a worst-case minimum charging current greater than the maximum rated LT1725 start-up current, and a worst-case maxi- mum charging current less than the minimum rated LT1725 supply current.
Capacitor C1 should then be made large enough to avoid the relaxation oscillatory behavior described above. This is complicated to determine theoretically as it depends on the particulars of the secondary circuit and load behavior. Empirical testing is recommended. (Use of the optional soft-start function will lengthen the power-up timing and require a correspondingly larger value for C1.) A further note—certain users may wish to utilize the general functionality of the LT1725, but may have an available input voltage significantly lower than, say, 48V. If this input voltage is within the allowable V CC range, i.e., perhaps 20V maximum, the internal wide hysteresis range UVLO function becomes counterproductive. In such cases it is simply better to operate the LT1725 directly from the available DC input supply. The LT1737 is identical to the LT1725, with the exception that it lacks the internal wide hysteresis UVLO function. It is therefore designed to operate directly from DC input supplies in the range of 4.5V to 20V. See the LT1737 data sheet for further information. FREQUENCY COMPENSATION Loop frequency compensation is performed by connect- ing a capacitor from the output of the error amplifier (V C pin) to ground. An additional series resistor, often re- quired in traditional current mode switcher controllers, is usually not required and can even prove detrimental. The phase margin improvement traditionally offered by this extra resistor will usually be already accomplished by the nonzero secondary circuit impedance, which adds a “zero” to the loop response. In further contrast to traditional current mode switchers, V C pin ripple is generally not an issue with the LT1725. The dynamic nature of the clamped feedback amplifier forms an effective track/hold type response, whereby the V C voltage changes during the flyback pulse, but is then “held” during the subsequent “switch on” portion of the next cycle. This action naturally holds the V C voltage stable during the current comparator sense action (current mode switching). OUTPUT VOLTAGE ERROR SOURCES Conventional nonisolated switching power supply ICs typically have only two substantial sources of output voltage error: the internal or external resistor divider network that connects to V OUT and the internal IC refer- ence. The LT1725, which senses the output voltage in both a dynamic and an isolated manner, exhibits additional potential error sources to contend with. Some of these errors are proportional to output voltage, others are fixed in an absolute millivolt sense. Here is a list of possible error sources and their effective contribution. Internal Voltage Reference The internal bandgap voltage reference is, of course, imperfect. Its error, both at 25°C and over temperature is already included in the specifications. User Programming Resistors Output voltage is controlled by the user-supplied feedback resistor divider ratio. To the extent that the resistor ratio differs from the ideal value, the output voltage will be proportionally affected. Highest accuracy systems will demand 1% components. Schottky Diode Drop The LT1725 senses the output voltage from the trans- former primary side during the flyback portion of the cycle. This sensed voltage therefore includes the forward drop, V F, of the rectifier (usually a Schottky diode). The nominal VF of this diode should therefore be included in feedback resistor divider calculations. Lot to lot and ambient tem- perature variations will show up as output voltage shift/ drift. Secondary Leakage Inductance Leakage inductance on the transformer secondary re- duces the effective secondary-to-third winding turns ratio S/NT) from its ideal value. This will increase the output voltage target by a similar percentage. To the extent that secondary leakage inductance is constant from part to part, this can be accommodated by adjusting the feedback resistor ratio. APPLICATIO S I FOR ATIOWU UU
An additional error source is caused by transformer sec- ondary current flow through the real life nonzero imped- ances of the output rectifier, transformer secondary and output capacitor. Because the secondary current only flows during the off portion of the duty cycle, the effective output impedance equals the “DC” lumped secondary impedance times the inverse of the off duty cycle. If the output load current remains relatively constant, or, in less critical applications, the error may be judged acceptable and the feedback resistor divider ratio adjusted for nomi- nal expected error. In more demanding applications, out- put impedance error may be minimized by the use of the load compensation function (see Load Compensation). MINIMUM LOAD CONSIDERATIONS The LT1725 generally provides better low load perfor- mance than previous generation switcher/controllers uti- lizing indirect output voltage sensing techniques. Specifically, it contains circuitry to detect flyback pulse “collapse,” thereby supporting operation well into discon- tinuous mode. Nevertheless, there still remain constraints to ultimate low load operation. These relate to the mini- mum switch on time and the minimum enable time. Discontinuous mode operation will be assumed in the following theoretical derivations. As outlined in the Operation section, the LT1725 utilizes a minimum output switch on time, t ON. This value can be combined with expected VIN and switching frequency to yield an expression for minimum delivered power. Minimum Power f L Vt VI PRI IN ON OUT OUT = æ Łç ö ł÷() This expression then yields a minimum output current constraint: I f LV VtOUT MIN PRI OUT IN ON()
- = æ Łç ö ł÷() where f = switching frequency LPRI = transformer primary side inductance VIN = input voltage VOUT = output voltage tON = output switch minimum on time An additional constraint has to do with the minimum enable time. The LT1725 derives its output voltage infor- mation from the flyback pulse. If the internal minimum enable time pulse extends beyond the flyback pulse, loss of regulation will occur. The onset of this condition can be determined by setting the width of the flyback pulse equal to the sum of the flyback enable delay, t ED, plus the minimum enable time, tEN. Minimum power delivered to the load is then: Minimum Power f L Vt t VI SEC OUT EN ED OUT OUT = æ Łç ö ł÷ +()[] Which yields a minimum output constraint: I fV L ttOUT MIN OUT SEC ED EN()
- = æ Łç ö ł÷ +() where f = switching frequency LSEC = transformer secondary side inductance VOUT = output voltage tED = enable delay time tEN = minimum enable time Note that generally, depending on the particulars of input and output voltages and transformer inductance, one of the above constraints will prove more restrictive. In other words, the minimum load current in a particular applica- tion will be either “output switch minimum on time” constrained, or “minimum flyback pulse time” constrained. (A final note—L PRI and LSEC refer to transformer induc- tance as seen from the primary or secondary side respec- tively. This general treatment allows these expressions to be used when the transformer turns ratio is nonunity.) APPLICATIO S I FOR ATIOWU UU
APPLICATIO S I FOR ATIOWU UU MAXIMUM LOAD/SHORT-CIRCUIT CONSIDERATIONS The LT1725 is a current mode controller. It uses the V C node voltage as an input to a current comparator which turns off the output switch on a cycle-by-cycle basis as this peak current is reached. The internal clamp on the VC node, nominally 2.5V, then acts as an output switch peak current limit. This 2.5V at the VC pin corresponds to a value of 250mV at the ISENSE pin, when the (ON) switch duty cycle is less than 40%. For a duty cycle above 40%, the internal slope compensation mechanism lowers the effective I SENSE voltage limit. For example, at a duty cycle of 80%, the nominal ISENSE voltage limit is 220mV. This action be- comes the switch current limit specification. Maximum available output power is then determined by the switch current limit, which is somewhat duty cycle dependent due to internal slope compensation action. Overcurrent conditions are handled by the same mecha- nism. The output switch turns on, the peak current is quickly reached and the switch is turned off. Because the output switch is only on for a small fraction of the available period, power dissipation is controlled. Loss of current limit is possible under certain conditions. Remember that the LT1725 normally exhibits a minimum switch on time, irrespective of current trip point. If the duty cycle exhibited by this minimum on time is greater than the ratio of secondary winding voltage (referred-to-primary) divided by input voltage, then peak current will not be controlled at the nominal value, and will cycle-by-cycle ratchet up to some higher level. Expressed mathemati- cally, the requirement to maintain short-circuit control is: tf VI R VN ON F SC SEC IN SP +() where tON = output switch minimum on time f = switching frequency I SC = short-circuit output current VF = output diode forward voltage at ISC RSEC = resistance of transformer secondary VIN = input voltage NSP = secondary-to-primary turns ratio ( NSEC/NPRI) Trouble is typically only encountered in applications with a relatively high product of input voltage times secondary- to-primary turns ratio and/or a relatively long minimum switch on time. (Additionally, several real world effects such as transformer leakage inductance, AC winding losses, and output switch voltage drop combine to make this simple theoretical calculation a conservative estimate.) THERMAL CONSIDERATIONS Care should be taken to ensure that the worst-case input voltage condition does not cause excessive die tempera- tures. The 16-lead SO package is rated at 100 °C/W, and the 16-lead GN at 110°C/W. Average supply current is simply the sum of quiescent current given in the specifications section plus gate drive current. Gate drive current can be computed as: I G = f • QG where QG = total gate charge f = switching frequency (Note: Total gate charge is more complicated than CGS • VG as it is frequently dominated by Miller effect of the C GD. Furthermore, both capacitances are nonlinear in practice. Fortunately, most MOSFET data sheets provide figures and graphs which yield the total gate charge directly per operating conditions.) Nearly all gate drive power is dissi- pated in the IC, except for a small amount in the external gate series resistor, so total IC dissipation may be com- puted as: P D(TOTAL) = VCC (IQ + • f • QG ), where IQ = quiescent current (from specifications) QG = total gate charge f = switching frequency V CC = LT1725 supply voltage
prevent interplane coupling. are essential to ensure clean switching and minimal EMI. tice used to minimize the parasitic inductance. will suffer due to the sluggish switching action. Figure 8. High Speed Current Switching Paths
1725 F08
Figure 9. 48V to Isolated 15V Converter
1725 F09a
threshold at about 32V, with a hysteresis band of about 2V. OUT features are unused as shown.
ILOAD (A) VOUT (V)15.0 2.0
1725 F09b
14.5 0.5 1.0 1.5 2.5 15.5 VIN = 36V VIN = 72V VIN = 48V Application Regulation Application Efficiency ILOAD (A) 0.01 EFFICIENCY (%) 0.1 1 10
1725 F09c
VIN = 48V VOUT = 15V 48V to Isolated 15V Application Parts List T1: Coiltronics VP5-0155 VERSA-PAK M1: International Rectifier IRF620. 200V, 0.8W N-channel MOSFET D1: Motorola MBRD660. 6A, 60V Schottky diode D2: Motorola MBRS1100. 1A, 100V Schottky diode D3, D4: 1N5257. 33V, 500mW Zener diode D5: BAS16. 75V rectifier diode C1: AVX TPSD226M025R0200. 22 mF, 25V tantalum capacitor C2a, C2b, C2c: Vishay/Vitramon VJ1825Y155MXB. 1.5mF, 100V X7R ceramic capacitor C3: 100pF, 100V, X7R ceramic capacitor C4: Sanyo 20SV150M. 150mF, 20V, OS-CON electrolytic capacitor C5: 1mF, 25V, Z5U ceramic capacitor C6: 1nF, 25V, X7R ceramic capacitor C7: 47pF, 25V NPO/COG ceramic capacitor C8: 0.1mF, 25V, Z5U ceramic capacitor C9: 470pF, 25V, X7R ceramic capacitor C10: 100pF, 25V, X7R ceramic capacitor R1: 24k, 1/4W, 5% resistor R2: IRC LR2010. 0.1W , 1/2W current sense resistor R3: 34.0k, 1% resistor R4: 3.01k, 1% resistor R5, R6, R7: 51k, 5% resistor R8: 6.2k, 5% resistor R9: 51W , 5% resistor R10: 18W , 5% resistor R11: 150W , 1/4W, 5% resistor R12: 5.1W , 5% resistor R13a, R13b: 1.5k, 1/2W, 5% resistor R14: 820k, 5% resistor R15: 33k, 5% resistor
range of 36V to 72V and outputs an isolated 5V at up to 2A. Transformer T1 is available as a Coiltronics CTX02-14989. threshold at about 32V, with a hysteresis band of about 2V. OUT features are unused as shown.
1725 F10a
Figure 10. 48V to Isolated 5V Converter
1725 F10c
48V to Isolated 5V Application Parts List T1: Coiltronics CTX02-14989 M1: International Rectifier IRF620. 200V, 0.8W N-channel MOSFET D1: International Rectifier 12CWQ06FN. 12A, 60V Schottky diode D2: BAS16. 75V switching diode C1: AVX TPSD156M035R0300. 15 mF, 35V tantalum capacitor C2: Vishay/Vitramon VJ1825Y155MXB. 1.5mF, 100V, X7R ceramic capacitor C3: Sanyo 6SA150M. 150 mF, 6.3V, OS-CON electrolytic capacitor C4: 150pF, 100V, X7R ceramic capacitor C5: 470pF, 50V, X7R ceramic capacitor C6: 1nF, 25V X7R ceramic capacitor C7: 47pF, 25V, NPO ceramic capacitor C8: 0.1mF, 25V, Z5U ceramic capacitor C9: 100pF, 25V, X7R ceramic capacitor C10: 1mF, 25V, Z5U ceramic capacitor R1: 47k, 1/4W, 5% resistor R2: Panasonic type ERJ-14RSJ. 0.18 W , 1/4W, 5% resistor R3: 35.7k, 1% resistor R4: 3.01k, 1% resistor R5, R6, R7: 51k, 5% resistor R8: 2.7k, 5% resistor R9: 18W , 5% resistor R10: 22W , 5% resistor R11: 51W , 1W, 5% resistor R12: 68W , 5% resistor R13: 820k, 5% resistor R14: 33k, 5% resistor
GN16 (SSOP) 1098 * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 12 3 4 5 6 7 8 0.229 – 0.244 (5.817 – 6.198) 0.150 – 0.157 (3.810 – 3.988) 16 15 14 13 0.189 – 0.196* (4.801 – 4.978) 12 11 10 9 0.016 – 0.050 (0.406 – 1.270) 0.015 – 0.004 0° – 8° TYP0.007 – 0.0098 (0.178 – 0.249) 0.053 – 0.068 (1.351 – 1.727) 0.008 – 0.012 (0.203 – 0.305) 0.004 – 0.0098 (0.102 – 0.249) 0.0250 (0.635) BSC 0.009 (0.229) REF 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. UPACKAGE DESCRIPTIO 0.016 – 0.050 (0.406 – 1.270) 0.010 – 0.020 0° – 8° TYP 0.008 – 0.010 (0.203 – 0.254) 1 2 3 4 5 6 7 8 0.150 – 0.157** (3.810 – 3.988) 16 15 14 13 0.386 – 0.394* (9.804 – 10.008) 0.228 – 0.244 (5.791 – 6.197) 12 11 10 9 S16 1098 0.053 – 0.069 (1.346 – 1.752) 0.014 – 0.019 (0.355 – 0.483) TYP 0.004 – 0.010 (0.101 – 0.254) 0.050 (1.270) BSC DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE S Package 16-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610)
ª LINEAR TECHNOLOGY CORPORATION 2000 LT/TP 1201 2K • PRINTED IN THE USA Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 l FAX: (408) 434-0507 l www.linear.com PART NUMBER DESCRIPTION COMMENTS LT1424-5 Isolated Flyback Switching Regulator 5V Output Voltage, No Optoisolator Required LT1424-9 Isolated Flyback Switching Regulator 9V Output , Regulation Maintained Under Light Loads LT1425 Isolated Flyback Switching Regulator No Third Winding or Optoisolator Required LT1533 Ultralow Noise 1A Switching Regulator Low Switching Harmonics and Reduced EMI, V IN = 2.7V to 23V LT1681/LTC1698 Isolated DC/DC Controller Chip-Set in Ouarter 36V £ VIN £ 72V; VOUT: 3.3V, 5V; POUT £ 100W; and Half-Brick Footprint Half the cost of a DC/DC Module; Low Profile, High Efficiency LT1737 High Power Isolated Flyback Controller Powered from a DC Supply Voltage RELATED PARTS