LT1715

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 28

Technical content

DESCRIPTION

Dual/Quad, 4.5ns, Single Supply 3V/5V Comparators with Rail-to-Rail Outputs The L T®1720/L T1721 are UltraFastTM dual/quad compara- tors optimized for single supply operation, with a supply voltage range of 2.7V to 6V . The input voltage range extends from 100mV below ground to 1.2V below the supply volt- age. Internal hysteresis makes the L T1720/L T1721 easy to use even with slow moving input signals. The rail-to-rail outputs directly interface to TTL and CMOS. Alternatively, the symmetric output drive can be harnessed for analog applications or for easy translation to other single supply logic levels. The L T1720 is available in three 8-pin packages; three pins per comparator plus power and ground. In addition to SO and MSOP packages, a 3mm × 3mm low profi le (0.8mm) dual fi ne pitch leadless package (DFN) is available for space limited applications. The L T1721 is available in the 16-pin SSOP and S packages. The pinouts of the L T1720/L T1721 minimize parasitic effects by placing the most sensitive inputs (inverting) away from the outputs, shielded by the power rails. The L T1720/L T1721 are ideal for systems where small size and low power are paramount. 2.7V to 6V Crystal Oscillator with TTL/CMOS Output L, L T , L TC and L TM are registered trademarks of Linear Technology Corporation. UltaFast is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.

FEATURES

APPLICATIONS

n High Speed Differential Line Receiver n Crystal Oscillator Circuits n Window Comparators n Threshold Detectors/Discriminators n Pulse Stretchers n Zero-Crossing Detectors n High Speed Sampling Circuits n UltraFast: 4.5ns at 20mV Overdrive 7ns at 5mV Overdrive n Low Power: 4mA per Comparator n Optimized for 3V and 5V Operation n Pinout Optimized for High Speed Ease of Use n Input Voltage Range Extends 100mV Below Negative Rail n TTL/CMOS Compatible Rail-to-Rail Outputs n Internal Hysteresis with Specifi ed Limits n Low Dynamic Current Drain; 15μA/(V-MHz), Dominated by Load In Most Circuits n Tiny 3mm × 3mm × 0.75mm DFN Package (L T1720) Propagation Delay vs Overdrive 1/2 LT1720 2.7V TO 6V 620Ω 220Ω 1MHz TO 10MHz CRYSTAL (AT-CUT)

17201 TA01

0.1μF 1.8k OUTPUT GROUND CASE OVERDRIVE (mV) DELAY (ns) 30 50

17201 TA02

25°C VSTEP = 100mV VCC = 5V CLOAD = 10pFRISING EDGE (tPDLH) FALLING EDGE (tPDHL)

(Note 1) TOP VIEW DD PACKAGE 8-LEAD (3mm s 3mm) PLASTIC DFN 1+IN A –IN A –IN B +IN B V CC OUT A OUT B GND TJMAX = 125°C, θJA = 160°C/W UNDERSIDE METAL INTERNALL Y CONNECTED TO GND +IN A –IN A –IN B +IN B V CC OUT A OUT B GND TOP VIEW MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 150°C, θJA = 230°C/W TOP VIEW VCC OUT A OUT B GND +IN A –IN A –IN B +IN B S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150°C, θJA = 200°C/W TOP VIEW GN PACKAGE 16-LEAD NARROW PLASTIC SSOP S PACKAGE 16-LEAD PLASTIC SO –IN A +IN A GND OUT A OUT B GND +IN B –IN B –IN D +IN D V CC OUT D OUT C V CC +IN C –IN C TJMAX = 150°C, θJA = 135°C/W (GN) TJMAX = 150°C, θJA = 115°C/W (S) PIN CONFIGURATION Operating Temperature Range

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCC Supply Voltage l 2.7 6 V ICC Supply Current (Per Comparator) V CC = 5V VCC = 3V l l 3.5 mA mA V CMR Common Mode Voltage Range (Note 2) l –0.1 VCC – 1.2 V VTRIP+ Input T rip Points (Note 3) l –2.0 –3.0 5.5 6.5 mV mV V TRIP– Input T rip Points (Note 3) l –5.5 –6.5 2.0 3.0 mV mV V OS Input Offset Voltage (Note 3) l 1.0 3.0 4.5 mV mV V HYST Input Hysteresis Voltage (Note 3) l 2.0 3.5 7.0 mV ΔVOS/ΔT Input Offset Voltage Drift l 10 μV/°C IB Input Bias Current l –6 0 μA IOS Input Offset Current l 0.6 μA CMRR Common Mode Rejection Ratio (Note 4) l 55 70 dB PSRR Power Supply Rejection Ratio (Note 5) l 65 80 dB AV Voltage Gain (Note 6) ∞ VOH Output High Voltage ISOURCE = 4mA, VIN = VTRIP+ + 10mV l VCC – 0.4 V VOL Output Low Voltage ISINK = 10mA, VIN = VTRIP– – 10mV l 0.4 V tPD20 Propagation Delay VOVERDRIVE = 20mV (Note 7) l 4.5 6.5 8.0 ns ns t PD5 Propagation Delay VOVERDRIVE = 5mV (Notes 7, 8) l 71 0 ns ns The l denotes specifi cations that apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VCC = 5V, VCM = 1V, COUT = 10pF , VOVERDRIVE = 20mV, unless otherwise specifi ed. ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L T1720CDD#PBF L T1720CDD#TRPBF LAAV 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C L T1720IDD#PBF L T1720IDD#TRPBF LAAV 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C L T1720CMS8#PBF L T1720CMS8#TRPBF L TDS 8-Lead Plastic MSOP 0°C to 70°C L T1720IMS8#PBF L T1720IMS8#TRPBF L TACW 8-Lead Plastic MSOP –40°C to 85°C L T1720CS8#PBF L T1720CS8#TRPBF 1720 8-Lead Plastic SO 0°C to 70°C L T1720IS8#PBF L T1720IS8#TRPBF 1720I 8-Lead Plastic SO –40°C to 85°C L T1721CGN#PBF L T1721CGN#TRPBF 1721 16-Lead Narrow Plastic SSOP 0°C to 70°C L T1721IGN#PBF L T1721IGN#TRPBF 1721I 16-Lead Narrow Plastic SSOP –40°C to 85°C L T1721CS#PBF L T1721CS#TRPBF 1721 16-Lead Plastic SO 0°C to 70°C L T1721IS#PBF L T1721IS#TRPBF 1721I 16-Lead Plastic SO –40°C to 85°C Consult L TC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container . Consult L TC Marketing for information on non-standard lead based fi nish parts. For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear .com/tapeandreel/

TYPICAL PERFORMANCE CHARACTERISTICS SUPPL Y VOL TAGE (V) 2.5 VOS AND TRIP POINT VOLTAGE (mV) 4.0 5.0

17201 G01

VTRIP– 25°C VCM = 1V TEMPERATURE (°C) VOS AND TRIP POINT VOLTAGE (mV) –25 25 100

17201 G02

–50 0 50 75 125 VTRIP+ VOS VTRIP– TEMPERATURE (°C) –50 3.6 3.8 4.2 25 75

17201 G03

0.2 –25 0 50 100 125 –0.2 –0.4 4.0 COMMON MODE INPUT VOLTAGE (V) VCC = 5V Input Offset and T rip Voltages vs Supply Voltage Input Offset and T rip Voltages vs Temperature Input Common Mode Limits vs Temperature Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: If one input is within these common mode limits, the other input can go outside the common mode limits and the output will be valid. Note 3: The L T1720/L T1721 comparators include internal hysteresis. The trip points are the input voltage needed to change the output state in each direction. The offset voltage is defi ned as the average of V TRIP+ and VTRIP–, while the hysteresis voltage is the difference of these two. Note 4: The common mode rejection ratio is measured with VCC = 5V and is defi ned as the change in offset voltage measured from VCM = –0.1V to VCM = 3.8V , divided by 3.9V . Note 5: The power supply rejection ratio is measured with VCM = 1V and is defi ned as the change in offset voltage measured from VCC = 2.7V to VCC = 6V , divided by 3.3V . ELECTRICAL CHARACTERISTICS The l denotes specifi cations that apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VCC = 5V, VCM = 1V, COUT = 10pF , VOVERDRIVE = 20mV, unless otherwise specifi ed. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ΔtPD Differential Propagation Delay (Note 9) Between Channels 0.3 1.0 ns tSKEW Propagation Delay Skew (Note 10) Between t PDLH/tPDHL 0.5 1.5 ns tr Output Rise Time 10% to 90% 2.5 ns tf Output Fall Time 90% to 10% 2.2 ns tJITTER Output Timing Jitter V IN = 1.2VP-P (6dBm), ZIN = 50Ω tPDLH VCM = 2V , f = 20MHz tPDHL psRMS psRMS fMAX Maximum Toggle Frequency V OVERDRIVE = 50mV , VCC = 3V VOVERDRIVE = 50mV , VCC = 5V 70.0 62.5 MHz MHz Note 6: Because of internal hysteresis, there is no small-signal region in which to measure gain. Proper operation of internal circuity is ensured by measuring V OH and VOL with only 10mV of overdrive. Note 7: Propagation delay measurements made with 100mV steps. Overdrive is measured relative to VTRIP±. Note 8: tPD cannot be measured in automatic handling equipment with low values of overdrive. The L T1720/L T1721 are 100% tested with a 100mV step and 20mV overdrive. Correlation tests have shown that t PD limits can be guaranteed with this test, if additional DC tests are performed to guarantee that all internal bias conditions are correct. Note 9: Differential propagation delay is defi ned as the larger of the two: ΔtPDLH = tPDLH(MAX) – tPDLH(MIN) ΔtPDHL = tPDHL(MAX) – tPDHL(MIN) where (MAX) and (MIN) denote the maximum and minimum values of a given measurement across the different comparator channels. Note 10: Propagation Delay Skew is defi ned as: t SKEW = |tPDLH – tPDHL|

TYPICAL PERFORMANCE CHARACTERISTICS DIFFERENTIAL INPUT VOLTAGE (V) INPUT CURRENT (μA) 1234

17201 G04

–4 –3 –2 –1 0 5 25°C VCC = 5V TEMPERATURE (˚C) –50 QUIESCENT SUPPLY CURRENT PER COMPARATOR (mA) 5.5

17201 G05

4.0 3.0 –25 0 50 2.5 2.0 6.0 5.0 4.5 3.5 75 100 125 VCC = 5V VCC = 3V SUPPLY VOLTAGE (V) SUPPLY CURRENT PER COMPARATOR (mA) 2 4 5

17201 G06

25°C 125°C –55°C OUTPUT LOAD CAPACITANCE (pF) DELAY (ns) 30 50

17201 G07

25°C VSTEP = 100mV OVERDRIVE = 20mV V CC = 5V RISING EDGE (tPDLH) FALLING EDGE (tPDHL) TEMPERATURE (°C) –50 PROPAGATION DELAY (ns) 7.5

17201 G08

6.0 5.0 –25 0 50 4.5 4.0 8.0 7.0 6.5 5.5 75 100 125 VCC = 3V VCC = 3V VCC = 5V VCC = 5V tPDLH VCM = 1V VSTEP = 100mV CLOAD = 10pF OVERDRIVE = 5mV OVERDRIVE = 20mV SUPPLY VOLTAGE (V) 2.5 4.5 DELAY (ns) 5.0 4.0 4.0 5.0

17201 G09

(tPDLH) FALLING EDGE (tPDHL) 25°C V STEP = 100mV OVERDRIVE = 20mV C LOAD = 10pF OUTPUT SINK CURRENT (mA) OUTPUT VOLTAGE (V) 0.3 0.4

17201 G10

0.2 0.1 4 8 12 20 0.5 125°C 25°C 125°C VCC = 2.7V VCC = 5V VCM = 1V VIN = –15mV –55°C OUTPUT SOURCE CURRENT (mA) OUTPUT VOLTAGE RELATIVE TO VCC (V) –0.4 –0.2 0.0

17201 G11

–0.6 –0.8 –1.0 4 8 12 20 125°C –55°C 25°C 25°C VCC = 2.7V VCC = 5V VCM = 1V VIN = 15mV FREQUENCY (MHz) NO LOAD

17201 G12

SUPPLY CURRENT PER COMPARATOR (mA) 25°C VCC = 5V CLOAD = 20pF Propagation Delay vs Load Capacitance Propagation Delay vs Temperature Propagation Delay vs Supply Voltage Output Low Voltage vs Load Current Output High Voltage vs Load Current Supply Current vs Frequency Input Current vs Differential Input Voltage Quiescent Supply Current vs Temperature Quiescent Supply Current vs Supply Voltage

+IN A (Pin 1): Noninverting Input of Comparator A. –IN A (Pin 2): Inverting Input of Comparator A. –IN B (Pin 3): Inverting Input of Comparator B. +IN B (Pin 4): Noninverting Input of Comparator B. GND (Pin 5): Ground. OUT B (Pin 6): Output of Comparator B. OUT A (Pin 7): Output of Comparator A. VCC (Pin 8): Positive Supply Voltage. L T1721 –IN A (Pin 1): Inverting Input of Comparator A. +IN A (Pin 2): Noninverting Input of Comparator A. GND (Pins 3, 6): Ground. OUT A (Pin 4): Output of Comparator A. OUT B (Pin 5): Output of Comparator B. +IN B (Pin 7): Noninverting Input of Comparator B. –IN B (Pin 8): Inverting Input of Comparator B. –IN C (Pin 9): Inverting Input of Comparator C. +IN C (Pin 10): Noninverting Input of Comparator C. VCC (Pins 11, 14): Positive Supply Voltage. OUT C (Pin 12): Output of Comparator C. OUT D (Pin 13): Output of Comparator D. +IN D (Pin 15): Noninverting Input of Comparator D. –IN D (Pin 16): Inverting Input of Comparator D.

~1kHz LTC203 1/2 LT1112 50Ω 100k 100k 2.4k 10nF 1μF 0.15μF 1/2 LT1638 1/2 LT1638 100k 100k 200k 10k 10k 1000 s VHYST 1000 s VTRIP+ 1000 s VTRIP– 1000 s VOS 0.1μF 50Ω 50k VCM VCC 1/2 LT1112

17201 TC01

10nF 1μF NOTES: LT1638, LT1112, LTC203s ARE POWERED FROM p15V. 200kW PULL-DOWN PROTECTS LTC203 LOGIC INPUTS WHEN DUT IS NOT POWERED 15 3 214 10 6 711 LTC203 2 14 153 7 11 106 ±VTRIP Test Circuit Response Time Test Circuit –3V –100mV –5V PULSE IN0V 50Ω 1N5711 400Ω 130Ω 25Ω 50Ω +VCC – VCM –VCM 50k DUT 1/2 LT1720 OR 1/4 LT1721 25Ω 0.1μF

17201 TC02

(CIN ≈ 10pF) 0.01μF 0.01μF 750Ω 2N3866 V1* *V1 = –1000 • (OVERDRIVE VTRIP+) NOTE: RISING EDGE TEST SHOWN. FOR FALLING EDGE, REVERSE LT1720 INPUTS

Input Voltage Considerations The L T1720/L T1721 are specifi ed for a common mode range of –100mV to 3.8V when used with a single 5V supply. In general the common mode range is 100mV below ground to 1.2V below V CC. The criterion for this common mode limit is that the output still responds correctly to a small differential input signal. Also, if one input is within the common mode limit, the other input signal can go outside the common mode limits, up to the absolute maximum limits (a diode drop past either rail at 10mA input current) and the output will retain the correct polarity. When either input signal falls below the negative common mode limit, the internal PN diode formed with the substrate can turn on, resulting in signifi cant current fl ow through the die. An external Schottky clamp diode between the input and the negative rail can speed up recovery from negative overdrive by preventing the substrate diode from turning on. When both input signals are below the negative common mode limit, phase reversal protection circuitry prevents false output inversion to at least –400mV common mode. However , the offset and hysteresis in this mode will increase dramatically, to as much as 15mV each. The input bias currents will also increase. When both input signals are above the positive common mode limit, the input stage will become debiased and the output polarity will be random. However , the internal hysteresis will hold the output to a valid logic level, and because the biasing of each comparator is completely independent, there will be no impact on any other com- parator . When at least one of the inputs returns to within the common mode limits, recovery from this state will take as long as 1μs. The propagation delay does not increase signifi cantly when driven with large differential voltages. However , with low levels of overdrive, an apparent increase may be seen with large source resistances due to an RC delay caused by the 2pF typical input capacitance. APPLICATIONS INFORMATION Input Protection The input stage is protected against damage from large differential signals, up to and beyond a differential voltage equal to the supply voltage, limited only by the absolute maximum currents noted. External input protection cir- cuitry is only needed if currents would otherwise exceed these absolute maximums. The internal catch diodes can conduct current up to these rated maximums without latchup, even when the supply voltage is at the absolute maximum rating. The L T1720/L T1721 input stage has general purpose internal ESD protection for the human body model. For use as a line receiver , additional external protection may be required. As with most integrated circuits, the level of immunity to ESD is much greater when residing on a printed circuit board where the power supply decoupling capacitance will limit the voltage rise caused by an ESD pulse. Unused Inputs The inputs of any unused compartor should be tied off in a way that defi nes the output logic state. The easiest way to do this is to tie IN + to VCC and IN– to GND. Input Bias Current Input bias current is measured with both inputs held at 1V . As with any PNP differential input stage, the L T1720/L T1721 bias current fl ows out of the device. With a differential input voltage of even just 100mV or so, there will be zero bias current into the higher of the two inputs, while the current fl owing out of the lower input will be twice the measured bias current. With more than two diode drops of differential input voltage, the L T1720/L T1721’s input protection circuitry activates, and current out of the lower input will increase an additional 30% and there will be a small bias current into the higher of the two input pins, of 4μA or less. See the Typical Performance curve “Input Current vs Differential Input Voltage.”

parasitic output to input feedback is kept below 4mV . ing) away from the outputs, shielded by the power rails. or AC termination topologies. Figure 1. Typical Topside Metal for Multilayer PCB Layouts

17201 F01

or power distribution traces. Figure 2. Hysteresis I/O Characteristics

17201 F02

supply dependence of the hysteresis voltage. Figure 3. Resistor R3 adds a portion of the output to the the internal 3.5mV hysteresis. Figure 3. Additional External Hysteresis Figure 4. Model for Additional Hysteresis Calculations

17201 F04

5V180Ω 270Ω 820Ω 10KH/E VCC 10KH/E 100K/E VCC 5V OR 5.2V 4.5V 510Ω 620Ω 180Ω 180Ω 750Ω 510Ω (a) STANDARD TTL TO PECL TRANSLATOR (b) L T1720/L T1721 OUTPUT TO PECL TRANSLATOR LSTTL 1/2 L T1720 VCC R3R4 10KH/E 100K/E VCC 5V OR 5.2V 4.5V 300Ω 330Ω 180Ω 180Ω OMIT 1500Ω (c) 3V L T1720/L T1721 OUTPUT TO PECL TRANSLATOR 1/2 L T1720 R4 560Ω 1000Ω VEE VCC

17201 F05

–5.2V 560Ω 270Ω VCC 270Ω 510Ω 330Ω 300Ω (d) LT1720/LT1721 OUTPUT TO STANDARD ECL TRANSLATOR 1/2 LT1720 1200Ω 330Ω 100K/E –4.5V 680Ω 330Ω 270Ω 390Ω 300Ω 270Ω 1500Ω 430Ω DO NOT USE FOR LT1720/LT1721 LEVEL TRANSLATION. SEE TEXT

swings for high speed at low power . nected common emitter for rail-to-rail output operation. units that are equivalent to picoFarads. Figure 6. L T1720/L T1721 Block Diagram

17201 F06

The L T1720/L T1721 comparators are intended for high speed applications, where it is important to understand a few limitations. These limitations can roughly be divided into three categories: input speed limits, output speed limits, and internal speed limits. There are no significant input speed limits except the shunt capacitance of the input nodes. If the 2pF typical input nodes are driven, the L T1720/L T1721 will respond. The output speed is constrained by two mechanisms, the fi rst of which is the slew currents available from the output transistors. To maintain low power quiescent op- eration, the L T1720/L T1721 output transistors are sized to deliver 25mA to 45mA typical slew currents. This is sufficient to drive small capacitive loads and logic gate inputs at extremely high speeds. But the slew rate will slow dramatically with heavy capacitive loads. Because the propagation delay (t PD) definition ends at the time the output voltage is halfway between the supplies, the fixed slew current actually makes the L T1720/L T1721 faster at 3V than 5V with 20mV of input overdrive. Another manifestation of this output speed limit is skew, the difference between t PDLH and tPDHL. The slew currents of the L T1720/L T1721 vary with the process variations of the PNP and NPN transistors, for rising edges and falling edges respectively. The typical 0.5ns skew can have either polarity, rising edge or falling edge faster . Again, the skew will increase dramatically with heavy capacitive loads. The skews of comparators in a single package are corre- lated, but not identical. Besides some random variability, there is a small (100ps to 200ps) systematic skew due to physical parasitics of the packages. For the L T1720 SO-8, comparator A, whose output is adjacent to the V CC pin, will have a relatively faster rising edge than comparator B. Likewise, comparator B, by virtue of an output adjacent to the ground pin will have a relatively faster falling edge. Similar dependencies occur in the L T1721 S16, while the systemic skews in the smaller MSOP and SSOP packages are half again as small. Of course, if the capacitive loads on the two comparators of a single package are not identical, the differential timing will degrade further . APPLICATIONS INFORMATION The second output speed limit is the clamp turnaround. The L T1720/L T1721 output is optimized for fast initial response, with some loss of turnaround speed, limiting the toggle frequency. The output transistors are idled in a low power state once V OH or VOL is reached by detecting the Schottky clamp action. It is only when the output has slewed from the old voltage to the new voltage, and the clamp circuitry has settled, that the idle state is reached and the output is fully ready to transition again. This clamp turnaround time is typically 8ns for each direction, resulting in a maximum toggle frequency of 62.5MHz, or a 125MB data rate. With higher frequencies, dropout and runt pulses can occur . Increases in capacitive load will increase the time needed for slewing due to the limited slew currents and the maximum toggle frequency will decrease further . For higher toggle frequency applications, refer to the L T1715, whose output stage can toggle at 150MHz typical. The internal speed limits manifest themselves as disper- sion. All comparators have some degree of dispersion, defined as a change in propagation delay versus input overdrive. The propagation delay of the L T1720/L T1721 will vary with overdrive, from a typical of 4.5ns at 20mV overdrive to 7ns at 5mV overdrive (typical). The L T1720/ L T1721’s primary source of dispersion is the hysteresis stage. As a change of polarity arrives at the gain stage, the positive feedback of the hysteresis stage subtracts from the overdrive available. Only when enough time has elapsed for a signal to propagate forward through the gain stage, backwards through the hysteresis stage and forward through the gain stage again, will the output stage receive the same level of overdrive that it would have received in the absence of hysteresis. With 5mV of overdrive, the L T1720/L T1721 are faster with a 5V supply than with a 3V supply, the opposite of what is true with 20mV overdrive. This is due to the internal speed limit, because the gain stage is faster at 5V than 3V due primarily to the reduced junction capacitances with higher reverse voltage bias. In many applications, as shown in the following examples, there is plenty of input overdrive. Even in applications providing low levels of overdrive, the L T1720/L T1721 are fast enough that the absolute dispersion of 2.5ns (= 7 – 4.5) is often small enough to ignore.

resonant positive feedback and stable oscillation occurs. from 1MHz to 10MHz over a 2.7V to 6V supply range. input is a filtered analog version of the square wave output. ing the same two nodes with the opposite input polarity. and resistive loading should be used in critical applications. and rail-to-rail style outputs of the L T1720. Figure 7. Crystal Oscillator with Complementary

17201 F07

use of the two independent comparators of the L T1720. the degree of separation between the output’s high pulses. high pulses. Figure 10 shows the two outputs. input node driven by the crystal is not a pure sinusoid. Figure 8. Timing Skew of Figure 7’s Circuit Figure 10. Nonoverlapping Outputs of Figure 9’s Circuit Figure 9. Crystal-Based Nonoverlapping 10MHz Clock Generator

17201 F09

17201 F10

applications requiring accurate differential timing skew. hysteresis, as described in the Speed Limits section. through Δt = 0 with negligible interaction. function and produces an output pulse (see Figure 13). resistors equal to R5 and R6.

17201 F11

Figure 11. Building Blocks for Timing Skew Generation with the L T1720

Figure 12. 3ns Delay Detector with Logarithmic Pulse Stretcher

17201 F12

Figure 13. Output Pulse Due to Delay of Y Input Pulse

Optional Logarithmic Pulse Stretcher The fourth comparator of the quad L T1721 can be put to work as a logarithmic pulse stretcher . This simple circuit can help tremendously if you don’t have a fast enough oscilloscope (or control circuit) to easily capture 3ns pulse widths (or faster). When an input pulse occurs, C2 is charged up with a 180ns capture 2 time constant. The hysteresis and 10mV offset across R3 are overcome within the fi rst nanosecond 3, switching the comparator output high. When the input pulse subsides, C2 discharges with a 540ns time constant, keeping the comparator on until the decay overrides the 10mV offset across R3 minus hysteresis. Because of this exponential decay, the output pulse width will be proportional to the logarithm of the input pulse width. It is important to bypass the circuit’s V CC well to avoid coupling into the resistive divider . R4 keeps the quiescent input voltage in a range where forward leakage of the diode due to the 0.4V V OL of the driving comparator is not a problem. Neglecting some effects 4, the output pulse is related to the input pulse as: t OUT = τ2 • ln {VCH • [1 – exp (–tP/τ1)]/(VOFF – VH/2)} – τ1 • ln [VCH/(VCH – VOFF – VH/2)] + tP (1) where t P = input pulse width tOUT = output pulse width τ1 = R1 || R2 • C2 the capture time constant τ2 = R2 • C2 the decay time constant VOFF = 10mV the voltage drop across R1 VH = 3.5mV L T1721 hysteresis VC = VIN – VFDIODE the input pulse voltage after the diode drop VCH = VC • R2/(R1 + R2) the effective source voltage for the charge APPLICATIONS INFORMATION For simplicity, with tP < τ1, and neglecting the very slight delay in turn-on due to offset and hysteresis, the equation can be approximated by: t OUT = τ2 • ln [(VCH • tP/τ1)/(VOFF – VH/2)] (2) For example, an 8ns input pulse gives a 1.67μs output pulse. Doubling the input pulse to 16ns lengthens the output pulse by 0.37μs. Doubling the input pulse again to 32ns adds another 0.37μs to the output pulse, and so on. The rate of 0.37μs per octave falls out of the above equation as: Δt OUT/octave = τ2 • ln(2) (3) There is ±0.01μs jitter5 in the output pulse which gives an uncertainty referred to the input pulse of less than 2% (60ps resolution on a 3ns pulse with a 60MHz oscilloscope—not bad!). The beauty of this circuit is that it gives resolution precisely where it’s hardest to get. The jitter is due to a combination of the slow decay of the last few millivolts on C2 and the 4nV/√Hz noise and 400MHz bandwidth of the L T1721 input stage. Increasing the offset across R3 or decreasing τ 2 will decrease this jitter at the expense of dynamic range. The circuit topology itself is extremely fast, limited theo- retically only by the speed of the diode, the capture time constant τ 1 and the pulse source impedance. Figure 14 shows results achieved with the implementation shown, compared to a plot of Equation (1). The low end is limited by the delivery time of the upstream comparators. As the input pulse width is increased, the log function is con- strained by the asymptotic RC response but, rather than becoming clamped, becomes time linear . Thus, for very long input pulses the third term of Equation (1) dominates and the circuit becomes a 3μs pulse stretcher .

2 So called because the very fast input pulse is “captured,” for later examination, as a charge on

the capacitor . 3 Assuming the input pulse slew rate at the diode is infi nite. This effective delay constant, about 0.4% of τ1 or 0.8ns, is the second term of equation 1, below. Driven by the 2.5ns slew-limited L T1721, this effective delay will be 2ns. 4 VC is dependent on the L T1721 output voltage and nonlinear diode characteristics. Also, the Thevenin equivalent charge voltage seen by C2 is boosted slightly by R2 being terminated above ground. 5 Output jitter increases with inputs pulse widths below ~3ns.

variety of cable lengths and a 20MHz or 60MHz oscilloscope. it is not producing any output pulses. of the RC network’s voltage. edge separations stay constant. voltage span, which allows it to work down to 2.7V supply. provides equal loading in either state. full power response is 30ns. Figure 14. Log Pulse Stretcher Output Pulse vs Input Pulse

17201 F14

Figure 15. RG-58 Cable with Velocity of Propogation = 66%;

1 FOOT CABLE

17201 F15

Figure 16. 10ns T riple Overlap Generator

17201 F16

Figure 17. Fast Waveform Sampler Using the L T1720 for Timing-Skew Compensation

17201 F17

the output of which feeds the L T1227 wideband amplifier . trim ensures bridge-drive signal simultaneity within 1ns. balances. A DC balance adjustment trims bridge offset. the circuit is ready for use. Figure 18. Voltage-Controlled Clock Skew

17201 F18

components as a fast AND gate. while the other two Schottkys provide for fast turn-off. This circuit can detect coincident pulses as narrow as 3ns. but it can typically drive CMOS as well. circuit, see Application Note 75, pages 10 and 11. Figure 19. A 3ns Coincidence Detector

17201 F19

–IN +IN GND 17201 SS OUTPUT VCC 150Ω 150Ω

8-Lead Plastic DFN (3mm × 3mm) (Reference L TC DWG # 05-08-1698) 3.00 p0.10 (4 SIDES) NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE 0.38 p 0.10 BOTTOM VIEW—EXPOSED PAD 1.65 p 0.10 (2 SIDES) 0.75 p0.05 R = 0.115 TYP 2.38 p0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6)

0.200 REF

0.00 – 0.05 (DD) DFN 1203 0.25 p 0.05 2.38 p0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 1.65 p0.05 (2 SIDES)2.15 p0.05 0.50 BSC 0.675 p0.05 3.5 p0.05 PACKAGE OUTLINE 0.25 p 0.05

0.50 BSC

8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference L TC DWG # 05-08-1610) .016 – .050 (0.406 – 1.270) .010 – .020 (0.254 – 0.508)s 45o 0o– 8o TYP .008 – .010 (0.203 – 0.254) SO8 0303 .053 – .069 (1.346 – 1.752) .014 – .019 (0.355 – 0.483) TYP .004 – .010 (0.101 – 0.254) .050 (1.270) BSC 1 2 3 4 .150 – .157 (3.810 – 3.988) NOTE 3 8 7 6 5 .189 – .197 (4.801 – 5.004) NOTE 3 .228 – .244 (5.791 – 6.197) .245 MIN .160 p.005 RECOMMENDED SOLDER PAD LAYOUT .045 p.005 .050 BSC .030 p.005 TYP INCHES (MILLIMETERS) NOTE: 1. DIMENSIONS IN 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)

(Reference L TC DWG # 05-08-1660) MSOP (MS8) 0307 REV F 0.53 p 0.152 (.021 p .006) SEATING PLANE NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.18 (.007) 0.254 (.010) 1.10 (.043) MAX 0.22 – 0.38 (.009 – .015) TYP 0.1016 p 0.0508 (.004 p .002) 0.86 (.034) REF 0.65 (.0256) BSC 0o – 6o TYP DETAIL “A” DETAIL “A” GAUGE PLANE 12 3 4 4.90 p 0.152 (.193 p .006) 8 7 6 5 3.00 p 0.102 (.118 p .004) (NOTE 3) 3.00 p 0.102 (.118 p .004) (NOTE 4) 0.52 (.0205) REF 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 0.889 p 0.127 (.035 p .005) RECOMMENDED SOLDER PAD LAYOUT 0.42 p 0.038 (.0165 p .0015) TYP 0.65 (.0256) BSC S Package 16-Lead Plastic Small Outline (Narrow .150 Inch) (Reference L TC DWG # 05-08-1610) .016 – .050 (0.406 – 1.270) .010 – .020 (0.254 – 0.508)s 45o 0o – 8o TYP .008 – .010 (0.203 – 0.254) N 2 3 4 5 6 7 8 N/2 .150 – .157 (3.810 – 3.988) NOTE 3 16 15 14 13 .386 – .394 (9.804 – 10.008) NOTE 3 .228 – .244 (5.791 – 6.197) 12 11 10 9 S16 0502 .053 – .069 (1.346 – 1.752) .014 – .019 (0.355 – 0.483) TYP .004 – .010 (0.101 – 0.254) .050 (1.270) BSC .245 MIN N

123 N / 2

.160 p.005 RECOMMENDED SOLDER PAD LAYOUT .045 p.005 .050 BSC .030 p.005 TYP INCHES (MILLIMETERS) NOTE: 1. DIMENSIONS IN 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference L TC DWG # 05-08-1641) GN16 (SSOP) 0204 12 3 4 5 6 7 8 .229 – .244 (5.817 – 6.198) .150 – .157** (3.810 – 3.988) 16 15 14 13 .189 – .196* (4.801 – 4.978) 12 11 10 9 .016 – .050 (0.406 – 1.270) .015 p .004 (0.38 p 0.10) s 45o 0o – 8o TYP.007 – .0098 (0.178 – 0.249) .0532 – .0688 (1.35 – 1.75) .008 – .012 (0.203 – 0.305) TYP .004 – .0098 (0.102 – 0.249) .0250 (0.635) BSC .009 (0.229) REF .254 MIN RECOMMENDED SOLDER PAD LAYOUT .150 – .165 .0250 BSC.0165 p.0015 .045 p.005 * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE INCHES (MILLIMETERS) NOTE: 1. CONTROLLING DIMENSION: INCHES 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE

circuit requires only 100pV-s of stimulus to trigger . be increased without limit for longer output pulses. with sensitivity better than 100mV .

6 It can detect short

logic high, without the help of a regenerative one-shot. pulse generator described after 40dB attenuation.

17201 F20

Figure 20. A 1ns Pulse Stretcher