LT1713CMS8

LT1713 LINER | Alldatasheet

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Single/Dual, 7ns, Low Power, 3V/5V/–5V Rail-to-Rail Comparators The LT 1713/LT1714 are UltraFast TM 7ns, single/dual comparators featuring rail-to-rail inputs, rail-to-rail complementary outputs and an output latch. Optimized for 3V and 5V power supplies, they operate over a single supply voltage range from 2.4V to 12V or from –2.4V to –6V dual supplies. The LT1713/LT1714 are designed for ease of use in a variety of systems. In addition to wide supply voltage flexibility, rail-to-rail input common mode range extends 100mV beyond both supply rails and the outputs are protected against phase reversal for inputs extending further beyond the rails. Also, the rail-to-rail inputs may be taken to opposite rails with no significant increase in input current. The rail-to-rail matched complementary outputs interface directly to TTL or CMOS logic and can sink 10mA to within 0.5V of GND or source 10mA to within 0.7V of V The LT1713/LT1714 have internal TTL/CMOS compatible latches for retaining data at the outputs. Each latch holds data as long as its latch pin is held high. Latch pin hysteresis provides protection against slow moving or noisy latch signals. The LT1713 is available in the 8-lead MSOP package. The LT1714 is available in the 16-lead narrow SSOP package. n Ultrafast: 7ns at 20mV Overdrive 8.5ns at 5mV Overdrive n Rail-to-Rail Inputs n Rail-to-Rail Complementary Outputs (TTL/CMOS Compatible) n Specified at 2.7V, 5V and –5V Supplies n Low Power (Per Comparator): 5mA n Output Latch n Inputs Can Exceed Supplies Without Phase Reversal n LT1713: 8-Lead MSOP Package n LT1714: 16-Lead Narrow SSOP Package , LTC and LT are registered trademarks of Linear Technology Corporation. n High Speed Automatic Test Equipment n Current Sense for Switching Regulators n Crystal Oscillator Circuits n High Speed Sampling Circuits n High Speed A/D Converters n Pulse Width Modulators n Window Comparators n Extended Range V/F Converters n Fast Pulse Height/Width Discriminators n Line Receivers n High Speed Triggers UltraFast is a trademark of Linear Technology Corporation. LT1713/LT1714 Propagation Delay vs Input Overdrive FEATURES DESCRIPTIO U APPLICATIO SU TYPICAL APPLICATIO U A 4· NTSC Subcarrier Voltage-Tunable Crystal Oscillator

171314 TA01

200pF * 1% FILM RESISTOR ** NORTHERN ENGINEERING LABS C-2350N-14.31818MHz FREQUENCY OUTPUT 3.9k* VIN 0V TO 5V MV-209 VARACTOR DIODE 100pF 15pFY1** 100pF 0.047µF C SELECT (CHOOSE FOR CORRECT PLL LOOP RESPONSE) 1M 1M* 1N4148 LT1004-2.547k* 1k* INPUT OVERDRIVE (mV) PROPAGATION DELAY (ns) 6.5 7.0 7.5 tPD+ tPD– 30 50

171314 TA02

6.0 5.5 5.0 10 20 40 8.0 8.5 9.0 TA = 25°C V+ = 5V V– = 0V VSTEP = 100mV

TJMAX = 150°C, qJA = 120°C/ W PACKAGE/ORDER I FOR ATIOUU W GN PART MARKING 1714 1714I ABSOLUTE AXI U RATI GSW WW U (Note 1) Specified Temperature Range (Note 2) ... – 40°C to 85°C ORDER PART NUMBER LT1713CMS8 LT1713IMS8 MS8 PART MARKING LTRD LTUK Consult factory for parts specified with wider operating temperature ranges. TJMAX = 150°C, qJA = 250°C/ W V +IN –IN Q OUT Q OUT GND LATCH ENABLE TOP VIEW MS8 PACKAGE 8-LEAD PLASTIC MSOP GN PACKAGE 16-LEAD PLASTIC SSOP TOP VIEW –IN A +IN A V +IN B –IN B GND Q A Q A Q B Q B GND LATCH ENABLE B LATCH ENABLE A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V+ Positive Supply Voltage Range l 2.4 7 V VOS Input Offset Voltage (Note 4) R S = 50W , VCM = V+/2 0.5 4 mV RS = 50W , VCM = V+/2 (Note 11) l 5m V RS = 50W , VCM = 0V 0.7 mV RS = 50W , VCM = V+ 1m V DVOS/DT Input Offset Voltage Drift l 5 mV/°C IOS Input Offset Current 0.1 1 mA l 2 mA IB Input Bias Current (Note 5) –7 –1.5 2 mA l –1 5 5 mA VCM Input Voltage Range (Note 9) l –0.1 V + + 0.1 V CMRR Common Mode Rejection Ratio V + = 5V, 0V £ VCM £ 5V 60 70 dB V + = 5V, 0V £ VCM £ 5V l 58 dB V + = 2.7V, 0V £ VCM £ 2.7V 57 70 dB V + = 2.7V, 0V £ VCM £ 2.7V l 55 dB The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 2.7V or V+ = 5V, V– = 0V, VCM = V+/2, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified.

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS PSRR+ Positive Power Supply Rejection Ratio 2.4V £ V+ £ 7V, VCM = 0V 65 80 dB l 60 dB PSRR– Negative Power Supply Rejection Ratio –7V £ V– £ 0V, V+ = 5V, VCM = 5V 65 80 dB l 60 dB AV Small-Signal Voltage Gain (Note 10) 1.5 3 V/mV VOH Output Voltage Swing HIGH I OUT = 1mA, V+ = 5V, VOVERDRIVE = 50mV l V+ – 0.5 V + – 0.2 V IOUT = 10mA, V+ = 5V, VOVERDRIVE = 50mV l V+ – 0.7 V + – 0.4 V VOL Output Voltage Swing LOW I OUT = –1mA, V OVERDRIVE = 50mV l 0.20 0.4 V IOUT = –10mA, V OVERDRIVE = 50mV l 0.35 0.5 V I+ Positive Supply Current (Per Comparator) V + = 5V, VOVERDRIVE = 1V 5 6.5 mA l 8.0 mA I– Negative Supply Current (Per Comparator) V + = 5V, VOVERDRIVE = 1V 3 4.0 mA l 4.5 mA VIH Latch Pin High Input Voltage l 2.4 V VIL Latch Pin Low Input Voltage l 0.8 V IIL Latch Pin Current V LATCH = V+ l 10 mA tPD Propagation Delay (Note 6) DVIN = 100mV, VOVERDRIVE = 20mV 8.0 11.0 ns DVIN = 100mV, VOVERDRIVE = 20mV l 12.5 ns DVIN = 100mV, VOVERDRIVE = 5mV 9.0 ns DtPD Differential Propagation Delay (Note 6) DVIN = 100mV, VOVERDRIVE = 20mV 0.5 3 ns tr Output Rise Time 10% to 90% 4 ns tf Output Fall Time 90% to 10% 4 ns tLPD Latch Propagation Delay (Note 7) 8n s tSU Latch Setup Time (Note 7) 1.5 ns tH Latch Hold Time (Note 7) 0n s tDPW Minimum Latch Disable Pulse Width (Note 7) 8 ns fMAX Maximum Toggle Frequency V IN = 100mVP-P Sine Wave 65 MHz tJITTER Output Timing Jitter V IN = 630mVP-P (0dBm) Sine Wave, f = 30MHz 15 ps RMS The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 2.7V or V+ = 5V, V– = 0V, VCM = V+/2, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified. The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, V– = – 5V, VCM = 0V, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V+ Positive Supply Voltage Range l 2.4 7 V V– Negative Supply Voltage Range (Note 3) l –7 0 V VOS Input Offset Voltage (Note 4) R S = 50W , VCM = 0V 0.5 3 mV RS = 50W , VCM = 0V l 4m V RS = 50W , VCM = –5V 0.7 mV RS = 50W , VCM = 5V 1 mV DVOS/DT Input Offset Voltage Drift l 5 mV/°C IOS Input Offset Current 0.1 1 mA l 2 mA IB Input Bias Current (Note 5) –7 –1.5 2 mA l –1 5 5 mA

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCM Input Voltage Range l –5.1 5.1 V CMRR Common Mode Rejection Ratio –5V £ VCM £ 5V 62 70 dB l 60 dB PSRR+ Positive Power Supply Rejection Ratio 2.4V £ V+ £ 7V, VCM = –5V 68 80 dB l 65 dB PSRR– Negative Power Supply Rejection Ratio –7V £ V– £ 0V, VCM = 5V 65 80 dB l 60 dB AV Small-Signal Voltage Gain (Note 10) 1V £ VOUT £ 4V, RL = ¥ 1.5 3 V/mV VOH Output Voltage Swing HIGH (Note 8) I OUT = 1mA, VOVERDRIVE = 50mV l 4.5 4.8 V IOUT = 10mA, VOVERDRIVE = 50mV l 4.3 4.6 V VOL Output Voltage Swing LOW (Note 8) I OUT = –1mA, V OVERDRIVE = 50mV l 0.20 0.4 V IOUT = –10mA, V OVERDRIVE = 50mV l 0.35 0.5 V I+ Positive Supply Current (Per Comparator) V OVERDRIVE = 1V 5.5 7.5 mA l 9.0 mA I– Negative Supply Current (Per Comparator) V OVERDRIVE = 1V 3.5 4.5 mA l 5.0 mA VIH Latch Pin High Input Voltage l 2.4 V VIL Latch Pin Low Input Voltage l 0.8 V IIL Latch Pin Current V LATCH = V+ l 10 mA tPD Propagation Delay (Note 6) DVIN = 100mV, VOVERDRIVE = 20mV 7 10 ns DVIN = 100mV, VOVERDRIVE = 20mV l 12 ns DVIN = 100mV, VOVERDRIVE = 5mV 8.5 ns DtPD Differential Propagation Delay (Note 6) DVIN = 100mV, VOVERDRIVE = 20mV 0.5 3 ns tr Output Rise Time 10% to 90% 4 ns tf Output Fall Time 90% to 10% 4 ns tLPD Latch Propagation Delay (Note 7) 8n s tSU Latch Setup Time (Note 7) 1.5 ns tH Latch Hold Time (Note 7) 0n s tDPW Minimum Latch Disable Pulse Width (Note 7) 8 ns fMAX Maximum Toggle Frequency V IN = 100mVP-P Sine Wave 65 MHz tJITTER Output Timing Jitter V IN = 630mVP-P (0dBm) Sine Wave, f = 30MHz 15 ps RMS The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, V– = – 5V, VCM = 0V, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT1713C/LT1714C are guaranteed to meet specified performance from 0°C to 70°C. They are designed, characterized and expected to meet specified performance from –40 °C to 85°C but are not tested or QA sampled at these temperatures. The LT1713I/LT1714I are guaranteed to meet specified performance from –40 °C to 85°C. Note 3: The negative supply should not be greater than the ground pin voltages and the maximum voltage across the positive and negative supplies should not be greater than 12V. Note 4: Input offset voltage (V OS) is defined as the average of the two voltages measured by forcing first one output, then the other to V+/2. Note 5: Input bias current (IB) is defined as the average of the two input currents. Note 6: Propagation delay (tPD) is measured with the overdrive added to the actual VOS. Differential propagation delay is defined as: DtPD = tPD+ – tPD–. Load capacitance is 10pF. Due to test system requirements, the LT1713/LT1714 propagation delay is specified with a 1kW load to ground for –5V supplies, or to mid-supply for 2.7V or 5V single supplies. Note 7: Latch propagation delay (t LPD) is the delay time for the output to respond when the latch pin is deasserted. Latch setup time (tSU) is the interval in which the input signal must remain stable prior to asserting the latch signal. Latch hold time (t H) is the interval after the latch is asserted in which the input signal must remain stable. Latch disable pulse width DPW) is the width of the negative pulse on the latch enable pin that latches in new data on the data inputs.

Note 8: Output voltage swings are characterized and tested at V+ = 5V and V– = 0V. They are designed and expected to meet these same specifications at V– = –5V. Note 9: The input voltage range is tested under the more demanding conditions of V+ = 5V and V– = –5V. The LT1713/LT1714 are designed and expected to meet these specifications at V– = 0V. Note 10: The LT1713/LT1714 voltage gain is tested at V+ = 5V and V– = –5V only. Voltage gain at single supply V + = 5V and V+ = 2.7V is guaranteed by design and correlation. Note 11: Input offset voltage over temperature at V+ = 2.7V is guaranteed by design and characterization. TYPICAL PERFOR A CE CHARACTERISTICS UW Propagation Delay vs Load Capacitance Input Offset Voltage vs Temperature TEMPERATURE (°C) –50 INPUT OFFSET VOLTAGE (mV) 2.5 2.0 1.5 1.0 0.5 – 0.5 – 1.0 – 1.5 – 2.0 – 2.5 0 50 75

171314 G01

–25 25 100 125 V+ = 5V V– = 0V VCM = 2.5V LOAD CAPACITANCE (pF) 0 60 100

171314 G02

t PD+ 40 80 120 PROPAGATION DELAY (ns) tPD– TA = 25°C V+ = 5V V– = 0V VCM = 2.5V VOD = 20mV VSTEP = 100mV TEMPERATURE (°C) –50 PROPAGATION DELAY (ns) 100

171314 G03

–25 25 75 125 tPD+ tPD V+ = 5V V– = 0V VCM = 2.5V VOD = 20mV VSTEP = 100mV CLOAD = 10pF Propagation Delay vs Input Common Mode Voltage Propagation Delay vs Positive Supply Voltage Positive Supply Current vs Positive Supply Voltage Propagation Delay vs Temperature INPUT COMMON MODE (V) – 0.5 PROPAGATION DELAY (ns) 7.5 8.0 tPD+ tPD– 8.5 2.5 4.5

171314 G04

7.0 6.5 6.0 0.5 1.5 3.5 9.0 9.5 10.0 5.5 TA = 25°C V+ = 5V V– = 0V VOD = 20mV VSTEP = 100mV CLOAD = 10pF POSITIVE SUPPLY VOLTAGE (V) PROPAGATION DELAY (ns) 9.5

171314 G05

8.0 7.0 24 8 6.5 6.0 10.0 9.0 8.5 7.5 10 12 14 tPD– TA = 25°C V– = 0V VCM = 2.5V VOD = 20mV VSTEP = 100mV CLOAD = 10pF tPD+ POSITIVE SUPPLY VOLTAGE (V) 4.0 POSITIVE SUPPLY CURRENT (PER COMPARATOR) (mA) 4.5 5.0 5.5 6.0 7.0 4 68 1 0

171314 G06

6.5 V– = –5V V– = 0V TA = 25°C ∆VIN = 100mV IOUT = 0

TYPICAL PERFOR A CE CHARACTERISTICS UW Negative Supply Current vs Negative Supply Voltage Positive Supply Current vs Switching Frequency SWITCHING FREQUENCY (MHz) POSITIVE SUPPLY CURRENT (PER COMPARATOR) (mA)

171314 G07

TA = 25°C V+ = 5V V– = 0V CLOAD = 10pF NEGATIVE SUPPLY VOLTAGE (V) 2.0 NEGATIVE SUPPLY CURRENT (PER COMPARATOR) (mA) 2.2 2.6 2.8 3.0 4.0 3.4 –2 –4 –5

171314 G08

2.4 3.6 3.8 3.2 –1 –3 –6 –7 TA = 25°C ∆VIN = 100mV IOUT = 0 V+ = 5V V+ = 2.7V Input Bias Current vs Input Common Mode Voltage INPUT COMMON MODE VOLTAGE (V) INPUT BIAS CURRENT (µA) 345

171314 G09

TA = 25°C V+ = 5V V– = 0V ∆VIN = 0mV Output High Voltage vs Source Current Input Bias Current vs Temperature Output Low Voltage vs Sink Current TEMPERATURE (°C) –50 INPUT BIAS CURRENT (µA) 100

171314 G10

–25 25 75 125 V+ = 5V V– = 0V VCM = 2.5V LOADING SOURCE CURRENT (mA) 0.01 4.0 OUTPUT VOLTAGE (V) 4.1 4.3 4.4 4.5 5.0 4.7

171314 G11

4.2 4.8 4.9 4.6 0.1 10 TA = 25°C V+ = 5V V– = 0V ∆VIN = 100mV LOADING SINK CURRENT (mA) 0.01 OUTPUT VOLTAGE (V) 0.1 0.3 0.4 0.5 1.0 0.7

171314 G12

0.2 0.8 0.9 0.6 0.1 10 TA = 25°C V+ = 5V V– = 0V ∆VIN = 100mV Output Timing Jitter vs Switching Frequency Output Rising Edge, 5V Supply Output Falling Edge, 5V Supply VIN VOUT VIN VOUT FREQUENCY (MHz) OUTPUT TIMING JITTER (psRMS) 100 200 140

171314 G13

TA = 25°C V+ = 5V V– = 0V VCM = 2.5V VIN = 630mVP-P (0dBm) SINE WAVE

171314 G14 171314 G15

V+ (Pin 1): Positive Supply Voltage, Usually 5V. + IN (Pin 2): Noninverting Input. – IN (Pin 3): Inverting Input. V– (Pin 4): Negative Supply Voltage, Usually 0V or – 5V. LATCH ENABLE (Pin 5): Latch Enable Input. With a logic high the output is latched. GND (Pin 6): Ground Supply Voltage, Usually 0V. Q (Pin 7): Noninverting Output. Q (Pin 8): Inverting Output. LT1714 – IN A (Pin 1): Inverting Input of A Channel Comparator. + IN A (Pin 2): Noninverting Input of A Channel Comparator. V– (Pins 3, 6): Negative Supply Voltage, Usually – 5V. Pins 3 and 6 should be connected together externally. V+ (Pins 4, 5): Positive Supply Voltage, Usually 5V. Pins 4 and 5 should be connected together externally. + IN B (Pin 7): Noninverting Input of B Channel Comparator. –IN B (Pin 8): Inverting Input of B Channel Comparator. LATCH ENABLE B (Pin 9): Latch Enable Input of B Channel Comparator. With a logic high, the B output is latched. GND (Pin 10): Ground Supply Voltage of B Channel Comparator, Usually 0V. Q B (Pin 11): Noninverting Output of B Channel Comparator. Q B (Pin 12): Inverting Output of B Channel Comparator. Q A (Pin 13): Inverting Output of A Channel Comparator. Q A (Pin 14): Noninverting Output of A Channel Comparator. GND (Pin 15): Ground Supply Voltage of A Channel Comparator, Usually 0V LATCH ENABLE A (Pin 16): Latch Enable Input of A Chan- nel Comparator. With a logic high, the A output is latched.

APPLICATIO S I FOR ATIOWU UU Common Mode Considerations The LT1713/LT1714 are specified for a common mode range of – 5.1V to 5.1V on a –5V supply, or a common mode range of – 0.1V to 5.1V on a single 5V supply. A more general consideration is that the common mode range is from 100mV below the negative supply to 100mV above the positive supply, independent of the actual supply volt- age. The criteria for common mode limit is that the output still responds correctly to a small differential input signal. When either input signal falls outside the common mode limit, the internal PN diode formed with the substrate can turn on resulting in significant current flow through the die. Schottky clamp diodes between the inputs and the supply rails speed up recovery from excessive overdrive conditions by preventing these substrate diodes from turning on. Input Bias Current Input bias current is measured with the outputs held at 2.5V with a 5V supply voltage. As with any rail-to-rail differential input stage, the LT1713/LT1714 bias current flows into or out of the device depending upon the com- mon mode level. The input circuit consists of an NPN pair and a PNP pair. For inputs near the negative rail, the NPN pair is inactive, and the input bias current flows out of the device; for inputs near the positive rail, the PNP pair is inactive, and these currents flow into the device. For inputs far enough away from the supply rails, the input bias current will be some combination of the NPN and PNP bias currents. As the differential input voltage increases, the input current of each pair will increase for one of the inputs and decrease for the other input. Large differential input voltages result in different input currents as the input stage enters various regions of operation. To reduce the influence of these changing input currents on system operation, use a low source resistance. Latch Pin Dynamics The internal latches of the LT1713/LT1714 comparators retain the input data (output latched) when their respective latch pin goes high. The latch pin will float to a low state when disconnected, but it is better to ground the latch when a flow-through condition is desired. The latch pin is designed to be driven with either a TTL or CMOS output. It has built-in hysteresis of approximately 100mV, so that slow moving or noisy input signals do not impact latch performance. For the LT1714, if only one of the compara- tors is being used at a given time, it is best to latch the second comparator to avoid any possibility of interactions between the two comparators in the same package. High Speed Design Techniques A substantial amount of design effort has made the LT1713/LT1714 relatively easy to use. As with most high speed comparators, careful attention to PC board layout and design is important in order to prevent oscillations. The most common problem involves power supply by- passing which is necessary to maintain low supply im- pedance. Resistance and inductance in supply wires and PC traces can quickly build up to unacceptable levels, thereby allowing the supply voltages to move as the supply current changes. This movement of the supply voltages will often result in improper operation. In addi- tion, adjacent devices connected through an unbypassed supply can interact with each other through the finite supply impedances. Bypass capacitors furnish a simple solution to this prob- lem by providing a local reservoir of energy at the device, thus keeping supply impedance low. Bypass capacitors should be as close as possible to the LT1713/LT1714 supply pins. A good high frequency capacitor, such as a 0.1mF ceramic, is recommended in parallel with a larger capacitor, such as a 4.7mF tantalum.

they are both connected directly to the ground plane.

1714 F01

Figure 1. Typical LT1714 Topside Metal for Multilayer PCB Layout

Figure 2. Various Configurations for Introducing Hysteresis

171314 F02

considerations. Figure 2 shows several configurations.

O, of the twisted-pair cable.

• | | ( ) This comes out to 120 W for the values shown. The Thevenin equivalent source voltage is given by: VV RRR RRR R RR R R TH S O O = + ++ []
• (± )
• ·| | ( ) 231 231 2123 LT1714TxD RxD LE 549.9Ω 750k 750k 100k 100k 49.9Ω 31613 R2A 2.55k R3A 124Ω ROA 140Ω ROB 140Ω R1B 499Ω 6-FEET TWISTED PAIR ZO ≈ 120Ω R1D 499Ω R1C 499Ω R3B 124Ω R2C 2.55k 100k 12 6

171314 F03

Figure 3. 75Mbaud Full Duplex Interface on Two Wires

Figure 4. Performance of Figure 3’s Circuit When

171112 F04

Figure 5. Performance When Operated Simultaneous Bidirectionally (Full Duplex). Crosstalk Appears as Noise.

171112 F05

quency exceeds –240ppm for a 0V to 5V input.

171112 F06

Figure 6. Control Voltage vs Output Frequency for the First Page

Figure 7. LT1713 Comparator is Configured as a Series Resonant Xtal Oscillator. Figure 8. Oscillator Waveforms with VS = 3V. Top is Comparator Output. Middle is

171314 F07

dal oscillators are not necessary.

2 The sine wave is filtered

on the second and third harmonics, respectively.

2 Amplitude will be a linear function of comparator output swing, which is supply dependent

nonoscillation versus clipping.

Dimensions in inches (millimeters) unless otherwise noted. 8-Lead Plastic MSOP (LTC DWG # 05-08-1660) UPACKAGE DESCRIPTIO MSOP (MS8) 1100 * DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE 0.021 – 0.006 (0.53 – 0.015) 0° – 6° TYP SEATING PLANE 0.007 (0.18) 0.043 (1.10) MAX 0.009 – 0.015 (0.22 – 0.38) 0.005 – 0.002 (0.13 – 0.05) 0.034 (0.86) REF 0.0256 (0.65) BSC 12 3 4 0.193 – 0.006 (4.90 – 0.15) 8 7 6 5 0.118 – 0.004* (3.00 – 0.102) 0.118 – 0.004** (3.00 – 0.102)

16-Lead Plastic SSOP (Narrow 0.150) (LTC DWG # 05-08-1641) Dimensions in inches (millimeters) unless otherwise noted. UPACKAGE DESCRIPTIO GN16 (SSOP) 1098 * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 12 3 4 5 6 7 8 0.229 – 0.244 (5.817 – 6.198) 0.150 – 0.157 (3.810 – 3.988) 16 15 14 13 0.189 – 0.196* (4.801 – 4.978) 12 11 10 9 0.016 – 0.050 (0.406 – 1.270) 0.015 – 0.004 0° – 8° TYP0.007 – 0.0098 (0.178 – 0.249) 0.053 – 0.068 (1.351 – 1.727) 0.008 – 0.012 (0.203 – 0.305) 0.004 – 0.0098 (0.102 – 0.249) 0.0250 (0.635) BSC 0.009 (0.229) REF UTYPICAL APPLICATIO Rail-to-Rail Pulse Width Modulator Using the LT1714 Binary modulation schemes are used in order to improve efficiency and reduce physical circuit size. They do this by reducing the power dissipation in the output driver tran- sistors. In a normal Class A or Class AB amplifier, voltage drop and current flow exist simultaneously in the output transistors and power losses proportional to V • I occur. In a binary modulation scheme, the output transistors, whether bipolar or FET, are switched hard-on and hard-off so that voltage drops do not occur simultaneously with current flow. The circuit of Figure 9 shows an example of a binary modulation scheme, in this case pulse width modulation. The LT1809 is configured as an integrator in order to generate nice linear rail-to-rail voltage ramps. The polarity of the ramp is determined by the output of the LT1714’s comparator A into R4. The heavy hysteresis of R1 around the LT1714’s comparator A combined with the feedback of the LT1809 force the devices to perpetually reverse each other, resulting in a 1MHz triangle wave. This constitutes the usual first half of any pulse width modulator, but the Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

171314 F09

Figure 9. Rail-to-Rail 1MHz Pulse Width Modulator clips at 5VP-P on a single 5V supply.