LT1709

LTC3728L-1 LINER | Alldatasheet

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Dual, 550kHz, 2-Phase Synchronous Regulator The L TC®3728L-1 is a dual high performance step-down switching regulator controller that drives all N-channel synchronous power MOSFET stages. A constant frequency current mode architecture allows phase-lockable frequency of up to 550kHz. Power loss and noise due to the ESR of the input capacitors are minimized by operating the two controller output stages out of phase. The L TC3728L-1 is identical to the L TC3728L except that the L TC3728L-1 lacks the over current latchoff feature. OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The precision 0.8V reference and power good output indicator are compatible with future microproces- sor generations, and a wide 4.5V to 28V (30V maximum/ 35V for L TC3728LI-1) input supply range encompasses all battery chemistries. A RUN/SS pin for each controller provides soft-start. Current foldback limits MOSFET dissipation during short- circuit conditions. The FCB mode pin can select among Burst Mode operation, constant frequency mode and continuous inductor current mode or regulate a secondary winding. The L TC3728L-1 includes a power good output pin that indicates when both outputs are within 7.5% of their designed set point. Figure 1. High Effi ciency Dual 5V/3.3V Step-Down Converter L, L T , L TC and L TM are registered trademarks of Linear Technology Corporation. Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.

Switch Voltage (SW1, SW2) L TC3728LI-1 ...35V to –0.3V INTV CC, EXTVCC, RUN/SS1, RUN/SS2, (BOOST1-SW1), SENSE1+, SENSE2+, SENSE1–, (Note 1) TOP VIEW GN PACKAGE 28-LEAD NARROW PLASTIC SSOP RUN/SS1 SENSE1 SENSE– VOSENSE1 PLLFLTR PLLIN FCB ITH1 SGND 3.3VOUT ITH2 VOSENSE2 SENSE2– SENSE2+ PGOOD TG1 SW1 BOOST1 V IN BG1 EXTV CC INTVCC PGND BG2 BOOST2 SW2 TG2 RUN/SS2 TJMAX = 125°C, θJA = 95°C/W 32 31 30 29 28 27 26 25 9 10 11 12 13 TOP VIEW 14 15 16 1VOSENSE1 PLLFLTR PLLIN FCB ITH1 SGND 3.3VOUT ITH2 BOOST1 V IN BG1 EXTV CC INTVCC PGND BG2 BOOST2 NC SENSE1 SENSE1+ NC RUN/SS1 PGOOD TG1 SW1 V OSENSE2 NC SENSE2– SENSE2+ RUN/SS2 TG2 SW2 NC UH PACKAGE 32-LEAD (5mm s 5mm) PLASTIC QFN TJMAX = 125°C, θJA = 34°C/W EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB PIN CONFIGURATION ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE L TC3728LEGN-1#PBF L TC3728LEGN-1#TRPBF L TC3728LEGN-1 28-Lead Narrow Plastic SSOP –40°C to 85°C L TC3728LIGN-1#PBF L TC3728LIGN-1#TRPBF L TC3728LIGN-1 28-Lead Narrow Plastic SSOP –40°C to 85°C L TC3728LEUH-1#PBF L TC3728LEUH-1#TRPBF 728LE1 32-Lead (5mm × 5mm) Plastic DFN –40°C to 85°C L TC3728LIUH-1#PBF L TC3728LIUH-1#TRPBF 3728L1 32-Lead (5mm × 5mm) Plastic DFN –40°C to 85°C LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE L TC3728LEGN-1 L TC3728LEGN-1#TR L TC3728LEGN-1 28-Lead Narrow Plastic SSOP –40°C to 85°C L TC3728LIGN-1 L TC3728LIGN-1#TR L TC3728LIGN-1 28-Lead Narrow Plastic SSOP –40°C to 85°C L TC3728LEUH-1 L TC3728LEUH-1#TR 728LE1 32-Lead (5mm × 5mm) Plastic DFN –40°C to 85°C L TC3728LIUH-1 L TC3728LIUH-1#TR 3728L1 32-Lead (5mm × 5mm) Plastic DFN –40°C to 85°C Consult L TC Marketing for parts specifi ed with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear .com/tapeandreel/ INTV Operating Temperature Range (Note 7).... –40°C to 85°C Lead Temperature (Soldering, 10 sec)

ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VIN = 15V , VRUN/SS1, 2 = 5V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Main Control Loops V OSENSE1, 2 Regulated Feedback Voltage (Note 3); I TH1, 2 Voltage = 1.2V ● 0.788 0.800 0.812 V IVOSENSE1, 2 Feedback Current (Note 3) – 5 –50 nA VREFLNREG Reference Voltage Line Regulation V IN = 3.6V to 30V (Note 3) 0.002 0.02 %/V VLOADREG Output Voltage Load Regulation (Note 3) Measured in Servo Loop; ΔITH Voltage = 1.2V to 0.7V Measured in Servo Loop; ΔITH Voltage = 1.2V to 2.0V 0.1 – 0.1 0.5 –0.5 gm1, 2 T ransconductance Amplifi er gm ITH1, 2 = 1.2V; Sink/Source 5μA; (Note 3) 1.3 mmho gmGBW1, 2 T ransconductance Amplifi er GBW I TH1, 2 = 1.2V; (Note 3) 3 MHz IQ Input DC Supply Current Normal Mode Shutdown (Note 4) V IN = 15V; EXTVCC Tied to VOUT1; VOUT1 = 5V VRUN/SS1, 2 = 0V 450 20 35 μA μA VFCB Forced Continuous Threshold ● 0.76 0.800 0.84 V IFCB Forced Continuous Pin Current V FCB = 0.85V – 0.50 –0.18 –0.1 μA VBINHIBIT Burst Inhibit (Constant Frequency) Threshold Measured at FCB pin 4.3 4.8 V UVLO Undervoltage Lockout V IN Ramping Down ● 3.5 4 V VOVL Feedback Overvoltage Lockout Measured at V OSENSE1, 2 ● 0.84 0.86 0.88 V ISENSE Sense Pins Total Source Current (Each Channel); V SENSE1–, 2– = VSENSE1+, 2+ = 0V –90 –60 μA DFMAX Maximum Duty Factor In Dropout 98 99.4 % IRUN/SS1, 2 Soft-Start Charge Current V RUN/SS1, 2 = 1.9V 0.5 1.2 μA VRUN/SS1, 2 ON RUN/SS Pin ON Threshold V RUN/SS1, VRUN/SS2 Rising 1.0 1.5 2.0 V VSENSE(MAX) Maximum Current Sense Threshold V OSENSE1, 2 = 0.7V ,VSENSE1–, 2– = 5V VOSENSE1, 2 = 0.7V ,VSENSE1–, 2– = 5V ● mV mV TG1, 2 t r TG1, 2 tf TG T ransition Time: Rise Time Fall Time (Note 5) C LOAD = 3300pF CLOAD = 3300pF 100 100 ns ns BG1, 2 tr BG1, 2 tf BG T ransition Time: Rise Time Fall Time (Note 5) C LOAD = 3300pF CLOAD = 3300pF 100 ns ns TG/BG t1D Top Gate Off to Bottom Gate On Delay Synchronous Switch-On Delay Time C LOAD = 3300pF Each Driver 80 ns BG/TG t2D Bottom Gate Off to Top Gate On Delay Top Switch-On Delay Time C LOAD = 3300pF Each Driver 80 ns tON(MIN) Minimum On-Time Tested with a Square Wave (Note 6) 100 ns INTVCC Linear Regulator VINTVCC Internal VCC Voltage 6V < V IN < 30V , VEXTVCC = 4V 4.8 5.0 5.2 V VLDO INT INTV CC Load Regulation I CC = 0 to 20mA, VEXTVCC = 4V 0.2 2.0 % VLDO EXT EXTV CC Voltage Drop I CC = 20mA, VEXTVCC = 5V 100 200 mV VEXTVCC EXTVCC Switchover Voltage I CC = 20mA, EXTVCC Ramping Positive ● 4.5 4.7 V VLDOHYS EXTVCC Hysteresis 0.2 V Oscillator and Phase-Locked Loop f NOM Nominal Frequency V PLLFL TR = 1.2V 360 400 440 kHz fLOW Lowest Frequency V PLLFL TR = 0V 230 260 290 kHz fHIGH Highest Frequency V PLLFL TR ≥ 2.4V 480 550 590 kHz RPLLIN PLLIN Input Resistance 50 kΩ

ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VIN = 15V , VRUN/SS1, 2 = 5V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IPLLFL TR Phase Detector Output Current Sinking Capability Sourcing Capability f PLLIN < fOSC fPLLIN > fOSC –15 μA μA 3.3V Linear Regulator V V3.3IL 3.3V Regulator Load Regulation I 3.3 = 0 to 10mA 0.5 2 % V3.3VL 3.3V Regulator Line Regulation 6V < V IN < 30V 0.05 0.2 % I3.3LEAK Leakage Current in Shutdown V RUN/SS1 = 0V; VRUN/SS2 = 0V , VIN = 3V ● 10 50 μA PGOOD Output VPGL PGOOD Voltage Low I PGOOD = 2mA 0.1 0.3 V IPGOOD PGOOD Leakage Current V PGOOD = 5V ±1 μA VPG PGOOD T rip Level, Either Controller V OSENSE with Respect to Set Output Voltage VOSENSE Ramping Negative VOSENSE Ramping Positive –7.5 7.5 – 9.5 9.5 Effi ciency vs Output Current and Mode (Figure 13) Effi ciency vs Output Current (Figure 13) Effi ciency vs Input Voltage (Figure 13) TYPICAL PERFORMANCCE CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: T J is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: L TC3728LUH-1: T J = TA + (PD • 34°C/W) L TC3728LGN-1: T J = TA + (PD • 95°C/W) Note 3: The IC is tested in a feedback loop that servos VITH1, 2 to a specifi ed voltage and measures the resultant VOSENSE1, 2. Note 4: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 5: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Note 6: The minimum on-time condition is specifi ed for an inductor peak-to-peak ripple current ≥ 40% of IMAX (see minimum on-time considerations in the Applications Information section). Note 7: The L TC3728LE-1 are guaranteed to meet performance specifi cations from 0°C to 85°C. Specifi cations over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. The L TC3728LI-1 is guaranteed to meet performance specifi cations over the full –40°C to 85°C operating temperature range OUTPUT CURRENT (A) 0.001 EFFICIENCY (%) 100 0.01 0.1 1 3728L1 G01 FORCED CONTINUOUS MODE (PWM) CONSTANT FREQUENCY (BURST DISABLE) Burst Mode OPERATION VIN = 15V VOUT = 5V f = 250kHz OUTPUT CURRENT (A) 0.001 EFFICIENCY (%) 3728L1 G02 0.01 0.1 1 100 VIN = 10V VIN = 15V VIN = 7V VIN = 20V VOUT = 5V f = 250kHz INPUT VOL TAGE (V) EFFICIENCY (%) 3728L1 G03 15 25 35 100 VOUT = 5V IOUT = 3A f = 250kHz

TYPICAL PERFORMANCE CHARACTERISTICS Supply Current vs Input Voltage and Mode (Figure 13) EXTV CC Voltage Drop INTVCC and EXTVCC Switch Voltage vs Temperature Internal 5V LDO Line Regulation Maximum Current Sense Threshold vs Duty Factor Maximum Current Sense Threshold vs Percent of Nominal Output Voltage (Foldback) Maximum Current Sense Threshold vs V RUN/SS (Soft-Start) Maximum Current Sense Threshold vs Sense Common Mode Voltage Current Sense Threshold vs ITH Voltage INPUT VOL TAGE (V) SUPPL Y CURRENT (μA) 400 1000 10 20 25 3728L1 G04 200 800 600 15 30 SHUTDOWN BOTH CONTROLLERS ON CURRENT (mA) EXTVCC VOL TAGE DROP (mV) 150 200 3728L1 G05 100 10 20 30 TEMPERATURE (°C) –50 INTVCC AND EXTVCC SWITCH VOLTAGE (V) 4.95 5.00 5.05 25 75 3728L1 G06 4.90 4.85 –25 0 50 100 125 4.80 4.70 4.75 INTVCC VOLTAGE EXTVCC SWITCHOVER THRESHOLD INPUT VOLTAGE (V) 4.8 4.9 5.1 15 25 3728L1 G07 4.7 4.6 51 0 20 30 4.5 4.4 5.0 INTVCC VOLTAGE (V) ILOAD = 1mA DUTY FACTOR (%) VSENSE (mV) 20 40 60 80 3728L1 G08 100 PERCENT ON NOMINAL OUTPUT VOLTAGE (%) VSENSE (mV) 100 3728L1 G09 25 50 75 VRUN/SS (V) VSENSE (mV) 1234 3728L1 G10 VSENSE(CM) = 1.6V COMMON MODE VOLTAGE (V) VSENSE (mV) 3728L1 G11 1 2 3 5 VITH (V) VSENSE (mV)30 3728L1 G12 –10 –20 –30 0.5 1 1.5 2.5

TYPICAL PERFORMANCE CHARACTERISTICS Load Regulation V ITH vs VRUN/SS SENSE Pins Total Source Current Maximum Current Sense Threshold vs Temperature Dropout Voltage vs Output Current (Figure 14) RUN/SS Current vs Temperature Soft-Start Up (Figure 13) Load Step (Figure 13) Load Step (Figure 13) LOAD CURRENT (A) NORMALIZED VOUT (%) –0.2 –0.1 3728L1 G13 –0.3 –0.4 1 2 3 5 0.0 FCB = 0V VIN = 15V FIGURE 13 VRUN/SS (V) VITH (V) 0.5 1.0 1.5 2.0 2.5 1 234 3728L1 G14 VOSENSE = 0.7V VSENSE COMMON MODE VOLTAGE (V) ISENSE (μA)0 3728L1 G15 –50 –100 100 TEMPERATURE (°C) –50 –25 VSENSE (mV) 0 50 75 3728L1 G17 25 100 125 OUTPUT CURRENT (A) DROPOUT VOLTAGE (V)1 0.5 1.0 1.5 2.0 3728L1 G18 2.5 3.0 3.5 4.0 RSENSE = 0.015Ω RSENSE = 0.010Ω VOUT = 5V TEMPERATURE (°C) –50 –25 RUN/SS CURRENT (μA) 0.2 0.6 0.8 1.0 75 10050 1.8 3728L1 G25 0.4 0 25 125 1.2 1.4 1.6 3728L1 G19 VOUT 5V/DIV VRUN/SS 5V/DIV IL 2A/DIV 5ms/DIVVIN = 15V VOUT = 5V 3728L1 G20 VOUT 200mV/DIV IL 2A/DIV 20μs/DIVVIN = 15V VOUT = 5V VPLLFL TR = 50V LOAD STEP = 0A TO 3A Burst Mode OPERATION 3728L1 G21 VOUT 200mV/DIV IL 2A/DIV 20μs/DIVVIN = 15V VOUT = 5V VPLLFL TR = 50V LOAD STEP = 0A TO 3A CONTINUOUS MODE

TYPICAL PERFORMANCE CHARACTERISTICS Input Source/Capacitor Instantaneous Current (Figure 13) Burst Mode Operation (Figure 13) Constant Frequency (Burst Inhibit) Operation (Figure 13) Current Sense Pin Input Current vs Temperature EXTVCC Switch Resistance vs Temperature Oscillator Frequency vs Temperature Undervoltage Lockout vs Temperature 3728L1 G22 VIN 200mV/DIV VSW1 10V/DIV VSW2 10V/DIV IIN 2A/DIV 1μs/DIVVIN = 15V VOUT1 = 5V , VOUT2 = 3.3V VPLLFL TR = 0V IOUT5 = IOUT3.3 = 2A 3728L1 G23 VOUT 20mV/DIV IL 0.5A/DIV 10μs/DIVVIN = 15V VOUT = 5V VPLLFL TR = 0V VFCB = 5V IOUT = 20mA 3728L1 G24 VOUT 20mV/DIV IL 0.5A/DIV 2μs/DIVVIN = 15V VOUT = 5V VPLLFL TR = 0V VFCB = 5V IOUT = 20mA TEMPERATURE (°C) –50 –25 CURRENT SENSE INPUT CURRENT (μA) 0 50 75 3728L1 G26 25 100 125 VOUT = 5V TEMPERATURE (°C) –50 –25 EXTVCC SWITCH RESISTANCE (Ω) 0 50 75 3728L1 G27 25 100 125 TEMPERATURE (°C) –50 400 500 700 25 75 3728L1 G28 300 200 –25 0 50 100 125 100 600FREQUENCY (kHz) VPLLFLTR = 2.4V VPLLFLTR = 1.2V VPLLFLTR = 0V TEMPERATURE (°C) –50 UNDERVOLTAGE LOCKOUT (V) 3.40 3.45 3.50 25 75 3728L1 G29 3.35 3.30 –25 0 50 100 125 3.25 3.20

VOSENSE1, V OSENSE2: Error Amplifi er Feedback Input. Receives the remotely-sensed feedback voltage for each controller from an external resistive divider across the output. PLLFL TR: Filter Connection for Phase-Locked Loop. Alter- natively, this pin can be driven with an AC or DC voltage source to vary the frequency of the internal oscillator . PLLIN: External Synchronization Input to Phase Detector . This pin is internally terminated to SGND with 50kΩ. The phase-locked loop will force the rising top gate signal of controller 1 to be synchronized with the rising edge of the PLLIN signal. FCB: Forced Continuous Control Input. This input acts on both controllers and is normally used to regulate a secondary winding. Pulling this pin below 0.8V will force continuous synchronous operation. ITH1, ITH2: Error Amplifi er Output and Switching Regulator Compensation Point. Each associated channels’ current comparator trip point increases with this control voltage. SGND: Small Signal Ground. Common to both controllers, this pin must be routed separately from high current grounds to the common (–) terminals of the C OUT capacitors. 3.3VOUT: Linear Regulator Output. Capable of supplying 10mA DC with peak currents as high as 50mA. NC: No Connect. SENSE2–, SENSE1–: The (–) Input to the Differential Cur- rent Comparators. SENSE2+, SENSE1+: The (+) Input to the Differential Current Comparators. The ITH pin voltage and controlled offsets between the SENSE– and SENSE+ pins in conjunction with RSENSE set the current trip threshold. RUN/SS2, RUN/SS1: Combination of soft-start and run control inputs. A capacitor to ground at each of these pins sets the ramp time to full output current. Forcing either of these pins back below 1.0V causes the IC to shut down the circuitry required for that particular controller . TG2, TG1: High Current Gate Drives for Top N-Channel MOSFETs. These are the outputs of fl oating drivers with a voltage swing equal to INTV CC – 0.5V superimposed on the switch node voltage SW . SW2, SW1: Switch Node Connections to Inductors. Voltage swing at these pins is from a Schottky diode (external) voltage drop below ground to V IN. BOOST2, BOOST1: Bootstrapped Supplies to the Top Side Floating Drivers. Capacitors are connected between the boost and switch pins and Schottky diodes are tied between the boost and INTV CC pins. Voltage swing at the boost pins is from INTVCC to (VIN + INTVCC). BG2, BG1: High Current Gate Drives for Bottom (Synchro- nous) N-Channel MOSFETs. Voltage swing at these pins is from ground to INTV CC. PGND: Driver Power Ground. Connects to the sources of bottom (synchronous) N-channel MOSFETs, anodes of the Schottky rectifi ers and the (–) terminal(s) of C IN. INTVCC: Output of the Internal 5V Linear Low Dropout Regulator and the EXTVCC Switch. The driver and control circuits are powered from this voltage source. Must be decoupled to power ground with a minimum of 4.7μF tantalum or other low ESR capacitor . EXTV CC: External Power Input to an Internal Switch Con- nected to INTV CC. This switch closes and supplies V CC power , bypassing the internal low dropout regulator , when- ever EXTVCC is higher than 4.7V . See EXTVCC connection in Applications section. Do not exceed 7V on this pin. VIN: Main Supply Pin. A bypass capacitor should be tied between this pin and the signal ground pin. PGOOD: Open-Drain Logic Output. PGOOD is pulled to ground when the voltage on either V OSENSE pin is not within ±7.5% of its set point. Exposed Pad (UH Package Only): Signal Ground. Must be soldered to the PCB, providing a local ground for the control components of the IC, and be tied to the PGND pin under the IC.

0.8V 4.8V VIN VIN 4.5V BINH CLK2 CLK1 0.18μA FCB + VREF INTERNAL SUPPLY 3.3VOUT INTVCC RLP CLP FCB INTVCC SGND (UH PACKAGE PAD) LDO REG SW SHDN 0.55V TOP BOOST TG CB CIND1 DB PGND BOT BG INTVCC INTVCC VIN COUT VOUT 3728L1 F02 RSENSE VOSENSE DROP OUT DET RUN SOFT START BOT TOP ONS R Q Q OSCILLATOR PHASE DET PLLFLTR PLLIN FCB EA 0.86V 0.80V OV VFB 1.2μA RC 4(VFB) RST SHDN RUN/SS ITH CC CC2 CSS 4(VFB) 0.86V SLOPE COMP 3mV SENSE– SENSE+ INTVCC 30k 45k 2.4V 45k 30k I1 I2 B DUPLICATE FOR SECOND CONTROLLER CHANNEL +– –+ 50k FIN PGOOD VOSENSE1 VOSENSE2 0.86V 0.74V 0.86V 0.74V EXTVCC Figure 2

The L TC3728L-1 is a constant frequency, current mode step-down controller with two channels operating 180 degrees out of phase. During normal operation, each top MOSFET is turned on when the clock for that channel sets the RS latch, and turned off when the main current com- parator , I 1, resets the RS latch. The peak inductor current at which I1 resets the RS latch is controlled by the voltage on the ITH pin, which is the output of each error amplifi er EA. The VOSENSE pin receives the voltage feedback signal, which is compared to the internal reference voltage by the EA. When the load current increases, it causes a slight decrease in V OSENSE relative to the 0.8V reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. After the top MOSFET has turned off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by current comparator I 2, or the beginning of the next cycle. The top MOSFET drivers are biased from fl oating bootstrap capacitor CB, which normally is recharged during each off cycle through an external diode when the top MOSFET turns off. As V IN decreases to a voltage close to VOUT, the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector detects this and forces the top MOSFET off for about 400ns every tenth cycle to allow C B to recharge. The main control loop is shut down by pulling the RUN/SS pin low. Releasing RUN/SS allows an internal 1.2μA cur- rent source to charge soft-start capacitor C SS. When CSS reaches 1.5V , the main control loop is enabled with the ITH voltage clamped at approximately 30% of its maximum value. As C SS continues to charge, the I TH pin voltage is gradually released allowing normal, full-current operation. When both RUN/SS1 and RUN/SS2 are low, all controller functions are shut down, including the 5V regulator . Low Current Operation The FCB pin is a multifunction pin providing two func- tions: 1) to provide regulation for a secondary winding by temporarily forcing continuous PWM operation on both controllers; and 2) to select between two modes of low current operation. When the FCB pin voltage is below 0.8V , the controller forces continuous PWM cur- rent mode operation. In this mode, the top and bottom MOSFETs are alternately turned on to maintain the output voltage independent of direction of inductor current. When the FCB pin is below V INTVCC – 2V but greater than 0.8V , the controller enters Burst Mode operation. Burst Mode operation sets a minimum output current level before inhibiting the top switch and turns off the synchronous MOSFET(s) when the inductor current goes negative. This combination of requirements will, at low currents, force the I TH pin below a voltage threshold that will temporarily inhibit turn-on of both output MOSFETs until the output voltage drops. There is 60mV of hyster- esis in the burst comparator B tied to the I TH pin. This hysteresis produces output signals to the MOSFETs that turn them on for several cycles, followed by a variable “sleep” interval depending upon the load current. The resultant output voltage ripple is held to a very small value by having the hysteretic comparator after the error amplifi er gain block. Frequency Synchronization The phase-locked loop allows the internal oscillator to be synchronized to an external source via the PLLIN pin. The output of the phase detector at the PLLFL TR pin is also the DC frequency control input of the oscillator that operates over a 260kHz to 550kHz range corresponding to a DC voltage input from 0V to 2.4V . When locked, the PLL aligns the turn on of the top MOSFET to the rising edge of the synchronizing signal. When PLLIN is left open, the PLLFL TR pin goes low, forcing the oscillator to minimum frequency. Constant Frequency Operation When the FCB pin is tied to INTV CC, Burst Mode opera- tion is disabled and the forced minimum output current requirement is removed. This provides constant frequency, discontinuous current (preventing reverse inductor cur- rent) operation over the widest possible output current range. This constant frequency operation is not as effi cient (Refer to Functional Diagram)

OPERATION (Refer to Functional Diagram) as Burst Mode operation, but does provide a lower noise, constant frequency operating mode down to approximately 1% of the designed maximum output current. Continuous Current (PWM) Operation Tying the FCB pin to ground will force continuous current operation. This is the least effi cient operating mode, but may be desirable in certain applications. The output can source or sink current in this mode. When sinking current while in forced continuous operation, the controller will cause current to fl ow back into the input fi lter capacitor . If large enough, this element will prevent the input sup- ply from boosting to unacceptably high levels; see C OUT Selection in the Applications Information Section. INTVCC/EXTVCC Power Power for the top and bottom MOSFET drivers and most other internal circuitry is derived from the INTVCC pin. When the EXTVCC pin is left open, an internal 5V low dropout linear regulator supplies INTVCC power . If EXTVCC is taken above 4.7V , the 5V regulator is turned off and an internal switch is turned on connecting EXTV CC to INTVCC. This al- lows the INTVCC power to be derived from a high effi ciency external source such as the output of the regulator itself or a secondary winding, as described in the Applications Information section. Output Overvoltage Protection An overvoltage comparator , OV , guards against transient overshoots (>7.5%) as well as other more serious condi- tions that may overvoltage the output. In this case, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. Power Good (PGOOD) Pin The PGOOD pin is connected to an open drain of an internal MOSFET . The MOSFET turns on and pulls the pin low when either output is not within ± 7.5% of the nominal output level as determined by the resistive feedback divider . When both outputs meet the ±7.5% requirement, the MOSFET is turned off within 10μs and the pin is allowed to be pulled up by an external resistor to a source of up to 7V . Foldback Current The RUN/SS capacitors are used initially to limit the inrush current of each switching regulator . Foldback current limit- ing is activated when the output voltage falls below 70% of its nominal level. If a short is present, a safe, low output current is provided due to the internal current foldback and actual power wasted is low due to the effi cient nature of the current mode switching regulator . THEORY AND BENEFITS OF 2-PHASE OPERATION The L TC1628 and the L TC3728L-1 family of dual high ef- fi ciency DC/DC controllers brings the considerable benefi ts of 2-phase operation to portable applications for the fi rst time. Notebook computers, PDAs, handheld terminals and automotive electronics will all benefi t from the lower input fi ltering requirement, reduced electromagnetic interference (EMI) and increased effi ciency associated with 2-phase operation. Why the need for 2-phase operation? Up until the 2-phase family, constant-frequency dual switching regulators operated both channels in phase (i.e., single-phase operation). This means that both switches turned on at the same time, causing current pulses of up to twice the amplitude of those for one regulator to be drawn from the input capacitor and battery. These large amplitude current pulses increased the total RMS current fl owing from the input capacitor , requiring the use of more expensive input capacitors and increasing both EMI and losses in the input capacitor and battery. With 2-phase operation, the two channels of the dual- switching regulator are operated 180 degrees out of phase. This effectively interleaves the current pulses drawn by the switches, greatly reducing the overlap time where they add together . The result is a signifi cant reduction in total RMS input current, which in turn allows less expen sive input capacitors to be used, reduces shielding requirements for EMI and improves real world operating effi ciency.

25% of the current limit determined by R SENSE. Lower inductor values (higher ΔI L) will cause this to occur at lower load currents, which can cause a dip in effi ciency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to decrease. Inductor Core Selection Usually, high inductance is preferred for small current ripple and low core loss. Unfortunately, increased induc- tance requires more turns of wire or a smaller air gap in the inductor core, resulting in high copper loss or low saturation current. Once the value of L is known, the actual inductor must be selected. There are two popular types of core material of commercial available inductors. Ferrite core inductors usually have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing satura- tion. However , ferrite core saturates “hard”, which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. One advantage of the L TC3728L-1 is its current mode control that detects and limits cycle-by-cycle peak inductor current. Therefore, accurate and fast protection is achieved if the inductor is saturated in steady state or during transient mode. Powdered iron core inductors usually saturate “soft”, which means the inductance drops in a linear fashion when the current increases. However , the core loss of the powder iron inductor is usually higher than the ferrite inductor . So designs with high switching frequency should also address inductor core loss. Inductor manufacturers usually provide inductance, DCR, (peak) saturation current and (DC) heating current ratings in the inductor data sheet. A good supply design should not exceed the saturation and heating current rating of the inductor . Power MOSFET and D1 Selection T wo external power MOSFETs must be selected for each controller in the L TC3728L-1: One N-channel MOSFET for the top (main) switch, and one N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak drive levels are set by the INTV CC voltage. This voltage is typically 5V during start-up (see EXTV CC Pin Connection). Consequently, logic-level threshold MOSFETs must be used in most applications. The only exception is if low input voltage is expected (V IN < 5V); then, sub-logic level threshold MOSFETs (VGS(TH) < 3V) should be used. Pay close attention to the BV DSS specifi cation for the MOSFETs as well; most of the logic level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the “ON” resistance R DS(ON), Miller capacitance C MILLER, input voltage and maximum output current. Miller capacitance, C MILLER, can be approximated from the gate charge curve usually provided on the MOSFET manufacturers’ data sheet. C MILLER is equal to the increase in gate charge along the horizontal axis while the curve is approximately fl at divided by the specifi ed change in V DS. This result is then multiplied by the ratio of the application applied VDS to the Gate charge curve specifi ed VDS. When the IC is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle= VOUT VIN Synchronous Switch Duty Cycle= VIN –V OUT VIN The MOSFET power dissipations at maximum output current are given by: PMAIN = VOUT VIN IMAX() 2 1+ () RDS(ON) + VIN()

2 IMAX

RDR() CMILLER()  VINTVCC –V THMIN + 1 VTHMIN f() PSYNC = VIN –V OUT VIN IMAX() 2 1+ () RDS(ON)

where δ is the temperature dependency of R DS(ON) and RDR (approximately 4Ω) is the effective driver resistance at the MOSFET’s Miller threshold voltage. V THMIN is the typical MOSFET minimum threshold voltage. Both MOSFETs have I2R losses while the topside N-channel equation includes an additional term for transition losses, which are highest at high input voltages. For V IN < 20V the high current effi ciency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CMILLER actually provides higher effi ciency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. The term (1+ δ) is generally given for a MOSFET in the form of a normalized R DS(ON) vs Temperature curve, but δ = 0.005/°C can be used as an approximation for low voltage MOSFETs. The Schottky diode D1 shown in Figure 1 conducts dur- ing the dead-time between the conduction of the two power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on, storing charge during the dead-time and requiring a reverse recovery period that could cost as much as 3% in effi ciency at high V IN. A 1A to 3A Schottky is generally a good compromise for both regions of operation due to the relatively small aver- age current. Larger diodes result in additional transition losses due to their larger junction capacitance. Schottky diodes should be placed in parallel with the synchronous MOSFETs when operating in pulse-skip mode or in Burst Mode operation. C IN and COUT Selection The selection of C IN is simplifi ed by the multiphase ar- chitecture and its impact on the worst-case RMS current drawn through the input network (battery/fuse/capacitor). It can be shown that the worst case RMS current occurs when only one controller is operating. The controller with the highest (V OUT)(IOUT) product needs to be used in the formula below to determine the maximum RMS current requirement. Increasing the output current, drawn from the other out-of-phase controller , will actually decrease the input RMS ripple current from this maximum value (see Figure 4). The out-of-phase technique typically reduces the input capacitor’s RMS ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. The type of input capacitor , value and ESR rating have effi ciency effects that need to be considered in the selec- tion process. The capacitance value chosen should be suffi cient to store adequate charge to keep high peak battery currents down. 20μF to 40μF is usually suffi cient for a 25W output supply operating at 200kHz. The ESR of the capacitor is important for capacitor power dissipation as well as overall battery effi ciency. All of the power (RMS ripple current • ESR) not only heats up the capacitor but wastes power from the battery. Medium voltage (20V to 35V) ceramic, tantalum, OS-CON and switcher-rated electrolytic capacitors can be used as input capacitors, but each has drawbacks: ceramics have very high voltage coeffi cients and may have audible piezoelectric effects; tantalums need to be surge-rated; OS-CONs suffer from higher inductance, larger case size and limited surface-mount applicability; electrolytics’ higher ESR and dryout possibility require several to be used. Multiphase systems allow the lowest amount of capacitance overall. As little as one 22μF or two to three 10μF ceramic capacitors are an ideal choice in a 20W to 35W power supply due to their extremely low ESR. Even though the capacitance at 20V is substantially below their rating at zero-bias, very low ESR loss makes ceramics an ideal candidate for highest effi ciency battery operated systems. Also consider parallel ceramic and high quality electrolytic capacitors as an effective means of achieving ESR and bulk capacitance goals. In continuous mode, the source current of the top N-channel MOSFET is a square wave of duty cycle V OUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current of one channel must be used. The maximum RMS capacitor current is given by: CINRequiredIRMS IMAX VOUT VIN VOUT() VIN

This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst case condition is commonly used for design because even signifi cant deviations do not offer much relief. Note that capacitor manufacturer’s ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor , or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there is any question. The benefi t of the L TC3728L-1 multiphase clocking can be calculated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. The total RMS power lost is lower when both controllers are operating due to the interleaving of current pulses through the input capacitor’s ESR. This is why the input capacitor’s requirement calculated above for the worst-case controller is adequate for the dual controller design. Remember that input protection fuse resistance, battery resistance and PC board trace resistance losses are also reduced due to the reduced peak currents in a multi- phase system. The overall benefi t of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the effi ciency test- ing. The drains of the two top MOSFETS should be placed within 1cm of each other and share a common C IN(s). Separating the drains and C IN may produce undesirable voltage and current resonances at VIN. The selection of COUT is driven by the required effective series resistance (ESR). Typically once the ESR require- ment is satisfi ed the capacitance is adequate for fi ltering. The output ripple (ΔV OUT) is determined by: VOUT IL ESR+ 1 8fCOUT Where f = operating frequency, COUT = output capacitance, and ΔIL= ripple current in the inductor . The output ripple is highest at maximum input voltage since ΔIL increases with input voltage. With ΔI L = 0.3I OUT(MAX) the output ripple will typically be less than 50mV at the maximum VIN assuming: C OUT Recommended ESR < 2 RSENSE and C OUT > 1/(8fRSENSE) The fi rst condition relates to the ripple current into the ESR of the output capacitance while the second term guarantees that the output capacitance does not signifi cantly discharge during the operating frequency period due to ripple current. The choice of using smaller output capacitance increases the ripple voltage due to the discharging term but can be compensated for by using capacitors of very low ESR to maintain the ripple voltage at or below 50mV . The I TH pin OPTI-LOOP compensation components can be optimized to provide stable, high performance transient response regardless of the output capacitors selected. Manufacturers such as Nichicon, Nippon Chemi-Con and Sanyo can be considered for high performance through- hole capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest (ESR)(size) product of any aluminum electrolytic at a somewhat higher price. An additional ceramic capacitor in parallel with OS-CON capacitors is recommended to reduce the inductance effects. In surface mount applications multiple capacitors may need to be used in parallel to meet ESR, RMS cur- rent handling and load step requirements. Aluminum electrolytic, dry tantalum and special polymer capaci- tors are available in surface mount packages. Special polymer surface mount capacitors offer very low ESR but have lower storage capacity per unit volume than other capacitor types. These capacitors offer a very cost-effective output capacitor solution and are an ideal choice when combined with a controller having high loop bandwidth. Tantalum capacitors offer the highest capacitance density and are often used as output capaci- tors for switching regulators having controlled soft-start. Several excellent surge-tested choices are the AVX TPS, AVX TPSV or the KEMET T510 series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. Aluminum electrolytic capacitors can be used

in cost-driven applications providing that consideration is given to ripple current ratings, temperature and long term reliability. A typical application will require several to many aluminum electrolytic capacitors in parallel. A combination of the above mentioned capacitors will often result in maximizing performance and minimizing overall cost. Other capacitor types include Nichicon PL series, Panasonic SP, NEC Neocap, Cornell Dubilier ESRE and Sprague 595D series. Consult manufacturers for other specifi c recommendations. INTVCC Regulator An internal P-channel low dropout regulator produces 5V at the INTV CC pin from the V IN supply pin. INTV CC powers the drivers and internal circuitry within the IC. The INTV CC pin regulator can supply a peak current of 50mA and must be bypassed to ground with a minimum of 4.7μF tantalum, 10μF special polymer , or low ESR type electrolytic capacitor . A 1μF ceramic capacitor placed di- rectly adjacent to the INTV CC and PGND IC pins is highly recommended. Good bypassing is necessary to supply the high transient currents required by the MOSFET gate drivers and to prevent interaction between channels. Higher input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maxi- mum junction temperature rating for the IC to be exceeded. The system supply current is normally dominated by the gate charge current. Additional external loading of the INTV CC and 3.3V linear regulators also needs to be taken into account for the power dissipation calculations. The total INTV CC current can be supplied by either the 5V in- ternal linear regulator or by the EXTVCC input pin. When the voltage applied to the EXTVCC pin is less than 4.7V , all of the INTVCC current is supplied by the internal 5V linear regulator . Power dissipation for the IC in this case is high- est: (V IN)(IINTVCC), and overall effi ciency is lowered. The gate charge current is dependent on operating frequency as discussed in the Effi ciency Considerations section. The junction temperature can be estimated by using the equations given in Note 2 of the Electrical Characteristics. For example, the IC V IN current is thermally limited to less than 67mA from a 24V supply when not using the EXTVCC pin as follows: Use of the EXTV CC input pin reduces the junction tem- perature to: The absolute maximum rating for the INTVCC Pin is 40mA. Dissipation should be calculated to also include any added current drawn from the internal 3.3V linear regulator . To prevent maximum junction temperature from being exceeded, the input supply current must be checked operating in continuous mode at maximum V IN. EXTVCC Connection The IC contains an internal P-channel MOSFET switch connected between the EXTV CC and INTVCC pins. When the voltage applied to EXTVCC rises above 4.7V , the internal regulator is turned off and the switch closes, connecting the EXTV CC pin to the INTVCC pin thereby supplying internal power . The switch remains closed as long as the voltage applied to EXTV CC remains above 4.5V . This allows the MOSFET driver and control power to be derived from the output during normal operation (4.7V < V OUT < 7V) and from the internal regulator when the output is out of regu- lation (start-up, short-circuit). If more current is required through the EXTV CC switch than is specifi ed, an external Schottky diode can be added between the EXTV CC and INTVCC pins. Do not apply greater than 7V to the EXTVCC pin and ensure that EXTVCC < VIN. Signifi cant effi ciency gains can be realized by powering INTV CC from the output, since the V IN current resulting from the driver and control currents will be scaled by a factor of (Duty Cycle)/(Effi ciency). For 5V regulators this supply means connecting the EXTV CC pin directly to VOUT. However , for 3.3V and other lower voltage regulators, additional circuitry is required to derive INTV CC power from the output. The following list summarizes the four possible connec- tions for EXTVCC: 1. EXTVCC Left Open (or Grounded). This will cause INTVCC to be powered from the internal 5V regulator resulting in an effi ciency penalty of up to 10% at high input voltages.

1. EXTVCC Connected directly to VOUT. This is the normal connection for a 5V regulator and provides the highest effi ciency. 3. EXTV CC Connected to an External supply. If an external supply is available in the 5V to 7V range, it may be used to power EXTV CC providing it is compatible with the MOSFET gate drive requirements. 4. EXTVCC Connected to an Output-Derived Boost Network. For 3.3V and other low voltage regulators, effi ciency gains can still be realized by connecting EXTV CC to an output- derived voltage that has been boosted to greater than 4.7V . This can be done with either the inductive boost winding as shown in Figure 6a or the capacitive charge pump shown in Figure 6b. The charge pump has the advantage of simple magnetics. Topside MOSFET Driver Supply (C B, DB) External bootstrap capacitors CB connected to the BOOST pins supply the gate drive voltages for the topside MOSFETs. Capacitor C B in the functional diagram is charged through external diode DB from INTVCC when the SW pin is low. When one of the topside MOSFETs is to be turned on, the driver places the C B voltage across the gate-source of the desired MOSFET . This enhances the MOSFET and turns on the topside switch. The switch node voltage, SW , rises to V IN and the BOOST pin follows. With the topside MOSFET on, the boost voltage is above the input supply: VBOOST = VIN + VINTVCC. The value of the boost capacitor CB needs to be 100 times that of the total input capacitance of the topside MOSFET(s). The reverse breakdown of the external Schottky diode must be greater than V IN(MAX). When adjusting the gate drive level, the fi nal arbiter is the total input current for the regulator . If a change is made and the input current decreases, then the effi ciency has improved. If there is no change in input current, then there is no change in effi ciency. Output Voltage The output voltages are each set by an external feedback resistive divider carefully placed across the output capacitor . The resultant feedback signal is compared with the internal precision 0.800V voltage reference by the error amplifi er . The output voltage is given by the equation: VOUT = 0.8V 1 + R2 where R1 and R2 are defi ned in Figure 2. SENSE+/SENSE– Pins The common mode input range of the current comparator sense pins is from 0V to (1.1)INTVCC. Continuous linear operation is guaranteed throughout this range allowing output voltage setting from 0.8V to 7.7V , depending upon the voltage applied to EXTV CC. A differential NPN input Figure 6a. Secondary Output Loop & EXTVCC Connection Figure 6b. Capacitive Charge Pump for EXTV CC EXTVCC FCB SGND VIN TG1 SW BG1 PGND L TC3728L-1 RSENSE VOUT VSEC COUT 1μF 3728L1 F06a N-CH N-CH CIN VIN 1:N OPTIONAL EXTVCC CONNECTION 5V < V SEC < 7V BAT 85 EXTVCC VIN TG1 SW BG1 PGND L TC3728L-1 RSENSE VOUT VN2222LL COUT 3728L1 F06b N-CH N-CH CIN 1μF VIN BAT85 BAT85 BAT85 0.22μF

used for power supply sequencing. ing surge current required from the input power supply. can be driven directly from logic as shown in Figure 7. SS to ramp up slowly providing the soft-start function. Figure 7. RUN/SS Pin Interfacing

ent temperature, conditions that cause the highest power dissipation in the top MOSFET . Each controller includes current foldback to help further limit load current when the output is shorted to ground. The foldback circuit is active even when the overload shutdown latch described above is overridden. If the output falls below 70% of its nominal output level, then the maximum sense voltage is progressively lowered from 75mV to 17mV . Under short-circuit conditions with very low duty cycles, the controller will begin cycle skipping in order to limit the short-circuit current. In this situation the bottom MOSFET will be dissipating most of the power but less than in normal operation. The short-circuit ripple current is determined by the minimum on-time t ON(MIN) of each controller (typically 100ns), the input voltage and inductor value: ΔI L(SC) = tON(MIN) (VIN/L) The resulting short-circuit current is: ISC = 25mV RSENSE – 1

2 IL(SC)

Fault Conditions: Overvoltage Protection (Crowbar) The overvoltage crowbar is designed to blow a system input fuse when the output voltage of the regulator rises much higher than nominal levels. The crowbar causes huge currents to fl ow, that blow the fuse to protect against a shorted top MOSFET if the short occurs while the controller is operating. A comparator monitors the output for overvoltage con- ditions. The comparator (OV) detects overvoltage faults greater than 7.5% above the nominal output voltage. When this condition is sensed, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. The output of this comparator is only latched by the overvoltage condition itself and will therefore allow a switching regulator system having a poor PC layout to function while the design is being debugged. The bottom MOSFET remains on continuously for as long as the OV condition persists; if V OUT returns to a safe level, normal operation automatically resumes. A shorted top MOSFET will result in a high current condition which will open the system fuse. The switching regulator will regulate properly with a leaky top MOSFET by altering the duty cycle to accommodate the leakage. Phase-Locked Loop and Frequency Synchronization The IC has a phase-locked loop comprised of an internal voltage controlled oscillator and phase detector . This al- lows the top MOSFET turn-on to be locked to the rising edge of an external source. The frequency range of the voltage controlled oscillator is ± 50% around the center frequency f O. A voltage of 1.2V applied to the PLLFL TR pin corresponds to a frequency of approximately 400kHz. The nominal operating frequency range of the IC is 260kHz to 550kHz. The phase detector used is an edge sensitive digital type which provides zero degrees phase shift between the ex- ternal and internal oscillators. This type of phase detector will not lock up on input frequencies close to the harmonics of the VCO center frequency. The PLL hold-in range, Δf is equal to the capture range, ΔfC: ΔfH = ΔfC = ±0.5 fO (260kHz-550kHz) The output of the phase detector is a complementary pair of current sources charging or discharging the external fi lter network on the PLLFL TR pin. If the external frequency (f PLLIN) is greater than the os- cillator frequency f0SC, current is sourced continuously,

pulling up the PLLFL TR pin. When the external frequency is less than f0SC, current is sunk continuously, pulling down the PLLFL TR pin. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. Thus the voltage on the PLLFL TR pin is adjusted until the phase and frequency of the external and internal oscillators are identical. At this stable operat- ing point the phase comparator output is open and the fi lter capacitor C LP holds the voltage. The IC’s PLLIN pin must be driven from a low impedance source such as a logic gate located close to the pin. When using multiple ICs for a phase-locked system, the PLLFL TR pin of the master oscillator should be biased at a voltage that will guarantee the slave oscillator(s) ability to lock onto the master’s frequency. A DC voltage of 0.7V to 1.7V applied to the master oscillator’s PLLFL TR pin is recommended in order to meet this requirement. The resultant operating frequency can range from 300kHz to 500kHz. The loop fi lter components (C LP, RLP) smooth out the cur- rent pulses from the phase detector and provide a stable input to the voltage controlled oscillator . The fi lter compo- nents C LP and RLP determine how fast the loop acquires lock. Typically RLP =10kΩ and CLP is 0.01μF to 0.1μF . Minimum On-Time Considerations Minimum on-time tON(MIN) is the smallest time duration that each controller is capable of turning on the top MOSFET . It is determined by internal timing delays and the gate charge required to turn on the top MOSFET . Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that tON(MIN)< VOUT VIN(f) If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the ripple voltage and current will increase. The minimum on-time for each controller is approximately 100ns. However , as the peak sense voltage decreases the minimum on-time gradually increases up to about 150ns. This is of particular concern in forced continuous applica- tions with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a signifi cant amount of cycle skipping can occur with cor- respondingly larger current and voltage ripple. FCB Pin Operation The FCB pin can be used to regulate a secondary winding or as a logic level input. Continuous operation is forced on both controllers when the FCB pin drops below 0.8V . During continuous mode, current fl ows continuously in the transformer primary. The secondary winding(s) draw current only when the bottom, synchronous switch is on. When primary load currents are low and/or the V IN/VOUT ratio is low, the synchronous switch may not be on for a suffi cient amount of time to transfer power from the output capacitor to the secondary load. Forced continuous opera- tion will support secondary windings providing there is suffi cient synchronous switch duty factor . Thus, the FCB input pin removes the requirement that power must be drawn from the inductor primary in order to extract power from the auxiliary windings. With the loop in continuous mode, the auxiliary outputs may nominally be loaded without regard to the primary output load. The secondary output voltage V SEC is normally set as shown in Figure 6a by the turns ratio N of the transformer: V SEC ≅ (N + 1) VOUT However , if the controller goes into Burst Mode operation and halts switching due to a light primary load current, then V SEC will droop. An external resistive divider from VSEC to the FCB pin sets a minimum voltage VSEC(MIN): VSEC(MIN)0.8V 1 + R6 where R5 and R6 are shown in Figure 2.

current when choosing resistor values R5 and R6. the error amplifi er , or 1.2V (see Figure 8). taining the linear control range of the error amplifi er . complete explanation is included in Design Solutions 10. the output power divided by the input power times 100%.

1. The VIN current has two components: the fi rst is the DC

Figure 8. Active Voltage Positioning

1. INTVCC current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from INTV CC to ground. The resulting dQ/dt is a current out of INTVCC that is typically much larger than the control circuit cur- rent. In continuous mode, I GATECHG =f(QT+QB), where QT and QB are the gate charges of the topside and bottom side MOSFETs. Supplying INTVCC power through the EXTVCC switch input from an output-derived source will scale the V IN current required for the driver and control circuits by a factor of (Duty Cycle)/(Effi ciency). For example, in a 20V to 5V ap- plication, 10mA of INTV CC current results in approximately 2.5mA of VIN current. This reduces the mid-current loss from 10% or more (if the driver was powered directly from V IN) to only a few percent. 3. I2R losses are predicted from the DC resistances of the fuse (if used), MOSFET , inductor , current sense resis- tor , and input and output capacitor ESR. In continuous mode the average output current fl ows through L and R SENSE, but is “chopped” between the topside MOSFET and the synchronous MOSFET . If the two MOSFETs have approximately the same R DS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L, R SENSE and ESR to obtain I2R losses. For example, if each RDS(ON) = 30mΩ, RL = 50mΩ, RSENSE = 10mΩ and RESR = 40mΩ (sum of both input and output capacitance losses), then the total resistance is 130mΩ. This results in losses ranging from 3% to 13% as the output current increases from 1A to 5A for a 5V output, or a 4% to 20% loss for a 3.3V output. Effi ciency varies as the inverse square of V OUT for the same external components and output power level. The combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. T ransition losses apply only to the topside MOSFET(s), and become signifi cant only when operating at high input voltages (typically 15V or greater). T ransition losses can be estimated from: Transition Loss = V IN() 2  IMAX RDR()  CMILLER() f() 1 5V – VTH + 1 VTH Other “hidden” losses such as copper trace and internal battery resistances can account for an additional 5% to 10% effi ciency degradation in portable systems. It is very important to include these “system” level losses during the design phase. The internal battery and fuse resistance losses can be minimized by making sure that C IN has ad- equate charge storage and very low ESR at the switching frequency. A 25W supply will typically require a minimum of 20μF to 40μF of capacitance having a maximum of 20mΩ to 50mΩ of ESR. The L TC3728L-1 2-phase architecture typically halves this input capacitance requirement over competing solutions. Other losses including Schottky con- duction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. Checking T ransient Response The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, V OUT shifts by an amount equal to ΔI LOAD (ESR), where ESR is the ef- fective series resistance of C OUT. ΔILOAD also begins to charge or discharge COUT generating the feedback error signal that forces the regulator to adapt to the current change and return V OUT to its steady-state value. During this recovery time V OUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The availability of the ITH pin not only allows optimization of control loop behavior but also provides a DC coupled and AC fi ltered closed loop response test point. The DC step, rise time and settling

at this test point truly refl ects the closed loop response. the actual overall supply performance. cold engines faster than 12V . clamp the input voltage below breakdown of the converter . Figure 9. Automotive Application Protection

As a design example for one channel, assume V IN = 12V(nominal), VIN = 22V(max), V OUT = 1.8V , IMAX = 5A, and f = 300kHz. The inductance value is chosen fi rst based on a 30% ripple current assumption. The highest value of ripple current occurs at the maximum input voltage. Tie the PLLFL TR pin to a resistive divider from the INTV CC pin, generating 0.7V for 300kHz operation. The minimum inductance for 30% ripple current is: L VIN –V OUT (f)(IRIPPLE)  VOUT VIN or 3.7μH. Using standard inductor values: IL = VOUT (f)(L) 1– VOUT VIN A 4.7μH inductor will produce 23% ripple current and a 3.3μH will result in 33%. The peak inductor current will be the maximum DC value plus one half the ripple current, or 5.84A, for the 3.3μH value. Increasing the ripple current will also help ensure that the minimum on-time of 100ns is not violated. The minimum on-time occurs at maximum V IN: tON(MIN)= VOUT VIN(MAX)f = 1.8V 22V(300kHz) = 273ns The RSENSE resistor value can be calculated by using the maximum current sense voltage specifi cation with some accommodation for tolerances: RSENSE 60mV 5.84A 0.01 Since the output voltage is below 2.4V the output resistive divider will need to be sized to not only set the output voltage but also to absorb the SENSE pin’s specifi ed input current. R1(MAX) = 24k 0.8V 2.4V – VOUT = 24k 0.8V 2.4V – 1.8V = 32k Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields an output voltage of 1.816V . The power dissipation on the top side MOSFET can be easily estimated. Choosing a Fairchild FDS6982S dual MOSFET results in: R DS(ON) = 0.035Ω/0.022Ω, CMILLER = 215pF . At maximum input voltage with T(estimated) = 50°C: PMAIN = 1.8V 4() 215pF()  5– 2.3 + 1 2.3 300kHz() = 332mW A short-circuit to ground will result in a folded back current of: ISC = 25mV 0.01 – 1 120ns(22V) 3.3μH = 2.1A with a typical value of RDS(ON) and δ = (0.005/°C)(20) = 0.1. The resulting power dissipated in the bottom MOSFET is: PSYNC = 22V – 1.8V = 100mW which is less than under full-load conditions. CIN is chosen for an RMS current rating of at least 3A at temperature assuming only this channel is on. C OUT is chosen with an ESR of 0.02Ω for low output ripple. The output ripple in continuous mode will be highest at the

1. Are the top N-channel MOSFETs M1 and M3 located

the two channels as it can cause a large resonant loop.

1. Are the signal and power grounds kept separate? The

INTVCC must return to the combined COUT (–) terminals. Figure 10. L TC3728L-1 Recommended Printed Circuit Layout Diagram

the high current input feeds from the input capacitor(s). nections at the SENSE resistor . This capacitor carries the MOSFET drivers current peaks.

1. Keep the switching nodes (SW1, SW2), top gate nodes

of the L TC3728L-1 and occupy minimum PC trace area. Figure 11. Branch Current Waveforms

1. Use a modifi ed “star ground” technique: a low imped- ance, large copper area central grounding point on the same side of the PC board as the input and output capacitors with tie-ins for the bottom of the INTV CC decoupling capacitor , the bottom of the voltage feedback resistive divider and the SGND pin of the IC. PC Board Layout Debugging Start with one controller on at a time. It is helpful to use a DC-50MHz current probe to monitor the current in the inductor while testing the circuit. Monitor the output switching node (SW pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. Check for proper performance over the operating voltage and current range expected in the application. The frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold—typically 10% to 20% of the maximum designed current level in Burst Mode operation. The duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise PCB implementation. Variation in the duty cycle at a subharmonic rate can sug- gest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. Overcompensation of the loop can be used to tame a poor PC layout if regula- tor bandwidth optimization is not required. Only after each controller is checked for its individual performance should both controllers be turned on at the same time. A particularly diffi cult region of operation is when one controller channel is nearing its current comparator trip point when the other channel is turning on its top MOSFET . This occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter . Reduce V IN from its nominal level to verify operation of the regulator in dropout. Check the operation of the undervoltage lockout circuit by further lowering V IN while monitoring the outputs to verify operation. Investigate whether any problems exist only at higher out- put currents or only at higher input voltages. If problems coincide with high input voltages and low output currents, look for capacitive coupling between the BOOST , SW , TG, and possibly BG connections and the sensitive voltage and current pins. The capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the IC. This capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. If problems are encountered with high current output loading at lower input voltages, look for inductive coupling between C IN, Schottky and the top MOSFET components to the sensitive current and voltage sensing traces. In addition, investigate common ground path voltage pickup between these components and the SGND pin of the IC. An embarrassing problem, which can be missed in an otherwise properly working switching regulator , results when the current sensing leads are hooked up backwards. The output voltage under this improper hookup will still be maintained but the advantages of current mode control will not be realized. Compensation of the voltage loop will be much more sensitive to component selection. This behavior can be investigated by temporarily shorting out the current sensing resistor—don’t worry, the regulator will still maintain control of the output voltage.

Figure 12. L TC3728L-1 High Effi ciency Low Noise 5V/3A, 3.3V/5A, 12V/120mA Regulator

Figure 13. L TC3728L-1 5V/4A, 3.3V/5A Regulator with External Frequency Synchronization

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION .386 – .393* (9.804 – 9.982) GN28 (SSOP) 0204 12 3 4 5 6 7 8 9 10 11 12 .229 – .244 (5.817 – 6.198) .150 – .157** (3.810 – 3.988) 202122232425262728 19 18 17 13 14 1615 .016 – .050 (0.406 – 1.270) .015 ± .004 0° – 8° TYP.0075 – .0098 (0.19 – 0.25) .0532 – .0688 (1.35 – 1.75) .008 – .012 (0.203 – 0.305) TYP .004 – .0098 (0.102 – 0.249) .0250 (0.635) BSC .033 (0.838) REF .254 MIN RECOMMENDED SOLDER PAD LAYOUT .150 – .165 .0250 BSC.0165 ±.0015 .045 ±.005 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE INCHES (MILLIMETERS) NOTE: 1. CONTROLLING DIMENSION: INCHES 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE 5.00 ± 0.10 (4 SIDES) NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (NOTE 6) 0.40 ± 0.10 BOTTOM VIEW—EXPOSED PAD

3.50 REF

(4-SIDES) 3.45 ± 0.10 3.45 ± 0.10 0.75 ± 0.05 R = 0.115 TYP 0.25 ± 0.05 (UH32) QFN 0406 REV D

0.50 BSC

0.200 REF

0.00 – 0.05 0.70 ±0.05 (4 SIDES) 4.10 ±0.05 5.50 ±0.05 0.25 ± 0.05 PACKAGE OUTLINE RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER R = 0.05 TYP 3.45 ± 0.05 3.45 ± 0.05 32-Lead Plastic QFN (5mm × 5mm) (Reference L TC DWG # 05-08-1693 Rev D) 28-Lead Plastic SSOP (Narrow .150 Inch) (Reference L TC DWG # 05-08-1641)

Figure 14. Multioutput PolyPhase Application No RSENSE and PolyPhase are trademarks of Linear Technology Corporation.