LT1630CN8

LT1630 LINER | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 16

Technical content

30MHz, 10V/µs, Dual/Quad Rail-to-Rail Input and Output Precision Op Amps

FEATURES

n Gain-Bandwidth Product: 30MHz n Slew Rate: 10V/µs n Low Supply Current per Amplifier: 3.5mA n Input Common Mode Range Includes Both Rails n Output Swings Rail-to-Rail n Input Offset Voltage, Rail-to-Rail: 525µV Max n Input Offset Current: 150nA Max n Input Bias Current: 1000nA Max n Open-Loop Gain: 1000V/mV Min n Low Input Noise Voltage: 6nV/√Hz Typ n Low Distortion: – 91dBc at 100kHz n Wide Supply Range: 2.7V to ±15V n Large Output Drive Current: 35mA Min n Dual in 8-Pin PDIP and SO Packages n Quad in Narrow 14-Pin SO Package The LT 1630/LT1631 are dual/quad, rail-to-rail input and output op amps with a 30MHz gain-bandwidth product and a 10V/µs slew rate. The LT1630/LT1631 have excellent DC precision over the full range of operation. Input offset voltage is typically less than 150 µV and the minimum open-loop gain of one million into a 10k load virtually eliminates all gain error. To maximize common mode rejection, the LT1630/LT1631 employ a patented trim technique for both input stages, one at the negative supply and the other at the positive supply, that gives a typical CMRR of 106dB over the full input range. The LT1630/LT1631 maintain their performance for sup- plies from 2.7V to 36V and are specified at 3V, 5V and ±15V supplies. The inputs can be driven beyond the supplies without damage or phase reversal of the output. The output delivers load currents in excess of 35mA. The LT1630 is available in 8-pin PDIP and SO packages with the standard dual op amp pinout. The LT1631 features the standard quad op amp configuration and is available in a 14-pin plastic SO package. These devices can be used as plug-in replacements for many standard op amps to improve input/output range and performance. DESCRIPTIONU , LTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATIONU 1/2 LT1630 2.32k VIN VS/2 VOUT 1630/31 TA01 220pF 2.32k 6.65k 1/2 LT1630 2.74k 22pF 470pF 5.62k2.74k 47pF FREQUENCY (Hz) 0.1k GAIN (dB) 1k 10k 100k 1M 10M 1630/31 TA02 –10 –20 –30 –40 –50 –60 –70 –80 –90 VS = 3V, 0V VIN = 2.5VP-P Frequency Response Single Supply, 400kHz, 4th Order Butterworth Filter APPLICATIONSU n Active Filters n Rail-to-Rail Buffer Amplifiers n Driving A/D Converters n Low Voltage Signal Processing n Battery-Powered Systems

ABSOLUTE MAXIMUM RATINGSW WW U Specified Temperature Range (Note 4) ... – 40°C to 85°C

ELECTRICAL CHARACTERISTICS

Consult factory for Military and Industrial grade parts. PACKAGE/ORDER INFORMATIONW UU ORDER PART NUMBER LT1630CN8 LT1630CS8 ORDER PART NUMBER TJMAX = 150°C, θJA = 150°C/ W TJMAX = 150°C, θJA = 130°C/ W (N8) TJMAX = 150°C, θJA = 190°C/ W (S8) LT1631CS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VOS Input Offset Voltage V CM = V+ 150 525 µV VCM = V– 150 525 µV ΔVOS Input Offset Shift V CM = V– to V+ 150 525 µV Input Offset Voltage Match (Channel-to-Channel) V CM = V–, V+ (Note 5) 200 950 µV IB Input Bias Current V CM = V+ 0 540 1000 nA VCM = V– –1000 – 540 0 nA ΔIB Input Bias Current Shift V CM = V– to V+ 1080 2000 nA Input Bias Current Match (Channel-to-Channel) V CM = V+ (Note 5) 25 300 nA VCM = V– (Note 5) 25 300 nA IOS Input Offset Current V CM = V+ 20 150 nA VCM = V– 20 150 nA ΔIOS Input Offset Current Shift V CM = V– to V+ 40 300 nA Input Noise Voltage 0.1Hz to 10Hz 300 nV P-P en Input Noise Voltage Density f = 1kHz 6 nV/ √Hz in Input Noise Current Density f = 1kHz 0.9 pA/ √Hz CIN Input Capacitance 5p F AVOL Large-Signal Voltage Gain V S = 5V, VO = 300mV to 4.7V, RL = 10k 500 3500 V/mV VS = 3V, VO = 300mV to 2.7V, RL = 10k 400 2000 V/mV S8 PART MARKING TOP VIEW OUT A –IN A +IN A V OUT B –IN B +IN B S8 PACKAGE 8-LEAD PLASTIC SO N8 PACKAGE 8-LEAD PDIP A B 1630 TOP VIEW S PACKAGE 14-LEAD PLASTIC SO OUTA –IN A +IN A V +IN B –IN B OUT B OUT D –IN D +IN D V +IN C –IN C OUT C A D B C TA = 25°C, VS = 5V, 0V; VS = 3V, 0V; VCM = VOUT = half supply, unless otherwise noted. (Note 1)

TA = 25°C, VS = 5V, 0V; VS = 3V, 0V; VCM = VOUT = half supply, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CMRR Common Mode Rejection Ratio V S = 5V, VCM = V– to V+ 79 90 dB VS = 3V, VCM = V– to V+ 75 86 dB CMRR Match (Channel-to-Channel) (Note 5) V S = 5V, VCM = V– to V+ 72 96 dB VS = 3V, VCM = V– to V+ 67 88 dB PSRR Power Supply Rejection Ratio V S = 2.7V to 12V, VCM = VO = 0.5V 87 105 dB PSRR Match (Channel-to-Channel) (Note 5) V S = 2.7V to 12V, VCM = VO = 0.5V 80 107 dB Minimum Supply Voltage (Note 9) V CM = VO = 0.5V 2.6 2.7 V VOL Output Voltage Swing Low (Note 6) No Load 14 30 mV ISINK = 0.5mA 31 60 mV ISINK = 25mA, VS = 5V 600 1200 mV ISINK = 20mA, VS = 3V 500 1000 mV VOH Output Voltage Swing High (Note 6) No Load 15 40 mV ISOURCE = 0.5mA 42 80 mV ISOURCE = 20mA, VS = 5V 900 1800 mV ISOURCE = 15mA, VS = 3V 680 1400 mV ISC Short-Circuit Current V S = 5V ± 20 ± 41 mA VS = 3V ± 15 ± 30 mA IS Supply Current per Amplifier 3.5 4.4 mA GBW Gain-Bandwidth Product (Note 7) f = 100kHz 15 30 MHz SR Slew Rate (Note 8) V S = 5V, AV = –1, R L = Open, VO = 4V 4.6 9.2 V/ µs VS = 3V, AV = – 1, RL = Open 4.2 8.5 V/ µs tS Settling Time V S = 5V, AV = 1, RL = 1k, 520 ns 0.01%, VSTEP = 2V SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VOS Input Offset Voltage V CM = V+ – 0.1V l 175 700 µV VCM = V– + 0.2V l 175 700 µV VOS TC Input Offset Voltage Drift (Note 3) l 2.5 5.5 µV/°C VCM = V+ – 0.1V l 1 3.5 µV/°C ΔVOS Input Offset Voltage Shift V CM = V– + 0.2V to V+ – 0.1V l 175 750 µV Input Offset Voltage Match (Channel-to-Channel) V CM = V – + 0.2V, V+ – 0.1V (Note 5) l 200 1200 µV IB Input Bias Current V CM = V+ – 0.1V l 0 585 1100 nA VCM = V– + 0.2V l –1100 –585 0 nA ΔIB Input Bias Current Shift V CM = V– + 0.2V to V+ – 0.1V l 1170 2200 nA Input Bias Current Match (Channel-to-Channel) V CM = V+ – 0.1V (Note 5) l 25 340 nA VCM = V– + 0.2V (Note 5) l 25 340 nA IOS Input Offset Current V CM = V+ – 0.1V l 20 170 nA VCM = V– + 0.2V l 20 170 nA ΔIOS Input Offset Current Shift V CM = V– + 0.2V to V+ – 0.1V l 40 340 nA AVOL Large-Signal Voltage Gain V S = 5V, VO = 300mV to 4.7V, RL = 10k l 450 3500 V/mV VS = 3V, VO = 300mV to 2.7V, RL = 10k l 350 2000 V/mV CMRR Common Mode Rejection Ratio V S = 5V, VCM = V– + 0.2V to V+ – 0.1V l 75 89 dB VS = 3V, VCM = V– + 0.2V to V+ – 0.1V l 71 83 dB CMRR Match (Channel-to-Channel) (Note 5) V S = 5V, VCM = V– + 0.2V to V+ – 0.1V l 70 90 dB VS = 3V, VCM = V– + 0.2V to V+ – 0.1V l 65 85 dB 0°C < TA < 70°C, VS = 5V, 0V; VS = 3V, 0V; VCM = VOUT = half supply, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS PSRR Power Supply Rejection Ratio V S = 3V to 12V, VCM = VO = 0.5V l 82 101 dB PSRR Match (Channel-to-Channel) (Note 5) V S = 3V to 12V, VCM = VO = 0.5V l 78 102 dB Minimum Supply Voltage (Note 9) V CM = VO = 0.5V l 2.6 2.7 V VOL Output Voltage Swing Low (Note 6) No Load l 17 40 mV ISINK = 0.5mA l 36 80 mV ISINK = 25mA, VS = 5V l 700 1400 mV ISINK = 20mA, VS = 3V l 560 1200 mV VOH Output Voltage Swing High (Note 6) No Load l 16 40 mV ISOURCE = 0.5mA l 50 100 mV ISOURCE = 15mA, VS = 5V l 820 1600 mV ISOURCE = 10mA, VS = 3V l 550 1100 mV ISC Short-Circuit Current V S = 5V l ± 18 ± 36 mA VS = 3V l ± 13 ± 25 mA IS Supply Current per Amplifier l 4.0 5.1 mA GBW Gain-Bandwidth Product (Note 7) f = 100kHz l 14 28 MHz SR Slew Rate (Note 8) V S = 5V, AV = –1, R L = Open, VO = 4V l 4.2 8.3 V/ µs VS = 3V, AV = – 1, RL = Open l 3.9 7.7 V/ µs 0°C < TA < 70°C, VS = 5V, 0V; VS = 3V, 0V; VCM = VOUT = half supply, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VOS Input Offset Voltage V CM = V+ – 0.1V l 250 775 µV VCM = V– + 0.2V l 250 775 µV VOS TC Input Offset Voltage Drift (Note 3) l 2.5 5.5 µV/°C VCM = V+ – 0.1V l 1 3.5 µV/°C ΔVOS Input Offset Voltage Shift V CM = V– + 0.2V to V+ – 0.1V l 200 750 µV Input Offset Voltage Match (Channel-to-Channel) V CM = V– + 0.2V, V+ (Note 5) l 210 1500 µV IB Input Bias Current V CM = V+ – 0.1V l 0 650 1300 nA VCM = V– + 0.2V l –1300 –650 0 nA ΔIB Input Bias Current Shift V CM = V– + 0.2V to V+ – 0.1V l 1300 2600 nA Input Bias Current Match (Channel-to-Channel) V CM = V+ – 0.1V (Note 5) l 25 390 nA VCM = V– + 0.2V (Note 5) l 25 390 nA IOS Input Offset Current V CM = V+ – 0.1V l 25 195 nA VCM = V– + 0.2V l 25 195 nA ΔIOS Input Offset Current Shift V CM = V– + 0.2V to V+ – 0.1V l 50 390 nA AVOL Large-Signal Voltage Gain V S = 5V, VO = 300mV to 4.7V, RL = 10k l 400 3500 V/mV VS = 3V, VO = 300mV to 2.7V, RL = 10k l 300 1800 V/mV CMRR Common Mode Rejection Ratio V S = 5V, VCM = V– + 0.2V to V+ – 0.1V l 75 87 dB VS = 3V, VCM = V– + 0.2V to V+ – 0.1V l 71 83 dB CMRR Match (Channel-to-Channel) (Note 5) V S = 5V, VCM = V– + 0.2V to V+ – 0.1V l 69 89 dB VS = 3V, VCM = V– + 0.2V to V+ – 0.1V l 65 85 dB PSRR Power Supply Rejection Ratio V S = 3V to 12V, VCM = VO = 0.5V l 82 98 dB PSRR Match (Channel-to-Channel) (Note 5) V S = 3V to 12V, VCM = VO = 0.5V l 78 102 dB Minimum Supply Voltage (Note 9) V CM = VO = 0.5V l 2.6 2.7 V VOL Output Voltage Swing Low (Note 6) No Load l 18 40 mV ISINK = 0.5mA l 38 80 mV ISINK = 25mA, VS = 5V l 730 1500 mV ISINK = 20mA, VS = 3V l 580 1200 mV –4 0°C < TA < 85°C, VS = 5V, 0V; VS = 3V, 0V; VCM = VOUT = half supply, unless otherwise noted. (Note 4)

–4 0°C < TA < 85°C, VS = 5V, 0V; VS = 3V, 0V; VCM = VOUT = half supply, unless otherwise noted. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VOH Output Voltage Swing High (Note 6) No Load l 15 40 mV ISOURCE = 0.5mA l 55 110 mV ISOURCE = 15mA, VS = 5V l 860 1700 mV ISOURCE = 10mA, VS = 3V l 580 1200 mV ISC Short-Circuit Current V S = 5V l ± 17 ± 34 mA VS = 3V l ± 12 ± 24 mA IS Supply Current per Amplifier l 4.1 5.2 mA GBW Gain-Bandwidth Product (Note 7) f = 100kHz l 14 28 MHz SR Slew Rate (Note 8) V S = 5V, AV = –1, RL = Open, VO = 4V l 3.5 7 V/ µs VS = 3V, AV = –1, RL = Open l 3.3 6.5 V/ µs SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VOS Input Offset Voltage V CM = V+ 220 1000 µV VCM = V– 220 1000 µV ΔVOS Input Offset Voltage Shift V CM = V– to V+ 150 1000 µV Input Offset Voltage Match (Channel-to-Channel) V CM = V–, V+ (Note 5) 200 1500 µV IB Input Bias Current V CM = V+ 0 550 1100 nA VCM = V– –1100 –550 0 nA ΔIB Input Bias Current Shift V CM = V– to V+ 1100 2200 nA Input Bias Current Match (Channel-to-Channel) V CM = V+ (Note 5) 20 300 nA VCM = V– (Note 5) 20 300 nA IOS Input Offset Current V CM = V+ 20 150 nA VCM = V– 20 150 nA ΔIOS Input Offset Current Shift V CM = V– to V+ 40 300 nA Input Noise Voltage 0.1Hz to 10Hz 300 nV P-P en Input Noise Voltage Density f = 1kHz 6 nV/ √Hz in Input Noise Current Density f = 1kHz 0.9 pA/ √Hz CIN Input Capacitance f = 100kHz 3 pF AVOL Large-Signal Voltage Gain V O = –14.5V to 14.5V, R L = 10k 1000 5000 V/mV VO = – 10V to 10V, RL = 2k 650 3500 V/mV Channel Separation V O = – 10V to 10V, RL = 2k 112 134 dB CMRR Common Mode Rejection Ratio V CM = V– to V+ 89 106 dB CMRR Match (Channel-to-Channel) (Note 5) V CM = V– to V+ 86 110 dB PSRR Power Supply Rejection Ratio V S = ±5V to ±15V 87 105 dB PSRR Match (Channel-to-Channel) (Note 5) V S = ±5V to ±15V 82 107 dB VOL Output Voltage Swing Low (Note 6) No Load 16 35 mV ISINK = 5mA 150 300 mV ISINK = 25mA 600 1200 mV VOH Output Voltage Swing High (Note 6) No Load 15 40 mV ISOURCE = 5mA 250 500 mV ISOURCE = 25mA 1200 2400 mV TA = 25°C, VS = ±15V, VCM = 0V, VOUT = 0V, unless otherwise noted.

TA = 25°C, VS = ±15V, VCM = 0V, VOUT = 0V, unless otherwise noted. 0°C < TA < 70°C, VS = ±15V, VCM = 0V, VOUT = 0V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ISC Short-Circuit Current ± 35 ± 70 mA IS Supply Current per Amplifier 4.1 5.0 mA GBW Gain-Bandwidth Product (Note 7) f = 100kHz 15 30 MHz SR Slew Rate A V = –1, R L = Open, VO = ±10V, 5 10 V/ µs Measure at VO = ±5V tS Settling Time 0.01%, V STEP = 10V, AV = 1, RL = 1k 1.2 µs SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VOS Input Offset Voltage V CM = V+ – 0.1V l 300 1250 µV VCM = V– + 0.2V l 300 1250 µV VOS TC Input Offset Voltage Drift (Note 3) l 4.5 7 µV/°C VCM = V+ – 0.1V l 1.5 4 µV/°C ΔVOS Input Offset Voltage Shift V CM = V– + 0.2V to V+ – 0.1V l 180 1100 µV Input Offset Voltage Match (Channel-to-Channel) V CM = V– + 0.2V, V+ – 0.1V (Note 5) l 300 2000 µV IB Input Bias Current V CM = V+ – 0.1V l 0 600 1200 nA VCM = V– + 0.2V l –1200 –600 0 nA ΔIB Input Bias Current Shift V CM = V– + 0.2V to V+ – 0.1V l 1200 2400 nA Input Bias Current Match (Channel-to-Channel) V CM = V+ – 0.1V (Note 5) l 30 350 nA VCM = V– + 0.2V (Note 5) l 30 350 nA IOS Input Offset Current V CM = V+ – 0.1V l 25 175 nA VCM = V– + 0.2V l 25 175 nA ΔIOS Input Offset Current Shift V CM = V– + 0.2V to V+ – 0.1V l 50 350 nA AVOL Large-Signal Voltage Gain V O = –14.5V to 14.5V, R L = 10k l 900 6000 V/mV VO = – 10V to 10V, RL = 2k l 600 4000 V/mV Channel Separation V O = – 10V to 10V, RL = 2k l 112 132 dB CMRR Common Mode Rejection Ratio V CM = V– + 0.2V to V+ – 0.1V l 88 104 dB CMRR Match (Channel-to-Channel) (Note 5) V CM = V– + 0.2V to V+ – 0.1V l 84 104 dB PSRR Power Supply Rejection Ratio V S = ±5V to ±15V l 86 100 dB PSRR Match (Channel-to-Channel) (Note 5) V S = ±5V to ±15V l 80 104 dB VOL Output Voltage Swing Low (Note 6) No Load l 19 45 mV ISINK = 5mA l 175 350 mV ISINK = 25mA l 670 1400 mV VOH Output Voltage Swing High (Note 6) No Load l 15 40 mV ISOURCE = 5mA l 300 600 mV ISOURCE = 25mA l 1400 2800 mV ISC Short-Circuit Current l ± 28 ± 57 mA IS Supply Current per Amplifier l 4.6 5.6 mA GBW Gain-Bandwidth Product (Note 7) f = 100kHz l 14 28 MHz SR Slew Rate A V = –1, R L = Open, VO = ±10V, l 4.5 9 V/ µs Measured at VO = ±5V

–40 °C < TA < 85°C, VS = ±15V, VCM = 0V, VOUT = 0V, unless otherwise noted. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VOS Input Offset Voltage V CM = V+ – 0.1V l 350 1400 µV VCM = V– + 0.2V l 350 1400 µV VOS TC Input Offset Voltage Drift (Note 3) l 4.5 7 µV/°C VCM = V+ – 0.1V l 1.5 4 µV/°C ΔVOS Input Offset Voltage Shift V CM = V– + 0.2V to V+ – 0.1V l 180 1200 µV Input Offset Voltage Match (Channel-to-Channel) V CM = V– + 0.2V, V+ – 0.1V (Note 5) l 350 2200 µV IB Input Bias Current V CM = V+ – 0.1V l 0 690 1400 nA VCM = V– + 0.2V l –1400 –690 0 nA ΔIB Input Bias Current Shift V CM = V– + 0.2V to V+ – 0.1V l 1380 2800 nA Input Bias Current Match (Channel-to-Channel) V CM = V+ – 0.1V (Note 5) l 30 420 nA VCM = V– + 0.2V (Note 5) l 30 420 nA IOS Input Offset Current V CM = V+ – 0.1V l 30 210 nA VCM = V– + 0.2V l 30 210 nA ΔIOS Input Offset Current Shift V CM = V– + 0.2V to V+ – 0.1V l 60 420 nA AVOL Large-Signal Voltage Gain V O = –14.5V to 14.5V, R L = 10k l 700 6000 V/mV VO = – 10V to 10V, RL = 2k l 400 4000 V/mV Channel Separation V O = – 10V to 10V, RL = 2k l 112 132 dB CMRR Common Mode Rejection Ratio V CM = V– + 0.2V to V+ – 0.1V l 87 104 dB CMRR Match (Channel-to-Channel) (Note 5) V CM = V– + 0.2V to V+ – 0.1V l 84 104 dB PSRR Power Supply Rejection Ratio V S = ±5V to ±15V l 84 100 dB PSRR Match (Channel-to-Channel) (Note 5) V S = ±5V to ±15V l 80 100 dB VOL Output Voltage Swing Low (Note 6) No Load l 22 50 mV ISINK = 5mA l 180 350 mV ISINK = 25mA l 700 1400 mV VOH Output Voltage Swing High (Note 6) No Load l 15 40 mV ISOURCE = 5mA l 300 600 mV ISOURCE = 25mA l 1500 3000 mV ISC Short-Circuit Current l ± 27 ± 54 mA IS Supply Current per Amplifier l 4.8 5.9 mA GBW Gain-Bandwidth Product (Note 7) f = 100kHz l 14 27 MHz SR Slew Rate A V = –1, R L = Open, VO = ±10V, l 4.2 8.5 V/ µs Measure at VO = ±5V Note 5: Matching parameters are the difference between amplifiers A and D and between B and C on the LT1631; between the two amplifiers on the LT1630. Note 6: Output voltage swings are measured between the output and power supply rails. Note 7: VS = 3V, VS = ±15V GBW limit guaranteed by correlation to 5V tests. Note 8: VS = 3V, VS = 5V slew rate limit guaranteed by correlation to ±15V tests. Note 9: Minimum supply voltage is guaranteed by testing the change of VOS to be less than 250µV when the supply voltage is varied from 3V to 2.7V. The l denotes specifications that apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: A heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted indefinitely. Note 3: This parameter is not 100% tested. Note 4: The LT1630C/LT1631C are guaranteed to meet specified performance from 0°C to 70°C and are designed, characterized and expected to meet these extended temperature limits, but are not tested at –4 0°C and 85°C. Guaranteed I grade parts are available, consult factory.

TYPICAL PERFORMANCE CHARACTERISTICS UW Input Bias Current vs Common Mode Voltage INPUT OFFSET VOLTAGE (µV) –500 PERCENT OF UNITS (%) 300 1630/31 G34 –300 –100 100 500 VS = 5V, 0V Supply Current vs Supply Voltage Input Bias Current vs Temperature VOS Distribution, VCM = 0V (PNP Stage) INPUT OFFSET VOLTAGE (µV) –500 PERCENT OF UNITS (%) 300 1630/31 G32 –300 –100 100 500 VS = 5V, 0V VCM = 0V INPUT OFFSET VOLTAGE (µV) –500 PERCENT OF UNITS (%) 300 1630/31 G33 –300 –100 100 500 VS = 5V, 0V VCM = 5V ΔVOS Shift for VCM = 0V to 5V VOS Distribution, VCM = 5V (NPN Stage) TOTAL SUPPLY VOTAGE (V) SUPPLY CURRENT PER AMPLIFIER (mA) 1630/31 G01 81 2 16 20 24 28 32 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 TA = 125°C TA = –55 °C TA = 25°C TEMPERATURE (°C) –75 SUPPLY CURRENT PER AMPLIFIER (mA) 1630/31 G02 –50 –25 25 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 50 75 125 100 VS = –15V VS = 5V, 0V Supply Current vs Temperature COMMON MODE VOLTAGE (V) INPUT BIAS CURRENT (nA) 23456 1630/31 G03 –1 0 1 600 400 200 –200 –400 –600 –800 –1000 TA = 125°C VS = 5V, 0V TA = 25°C TA = –55 °C TEMPERATURE (°C) –50 INPUT BIAS CURRENT (µA) 1.0 0.8 0.6 0.4 0.2 –0.2 –0.4 –0.6 –0.8 –1.0 1630/31 G04 –20 10 40–35 85 –5 25 55 100 VS = 5V, 0V VCM = 0V VS = –15V VCM = 15V VS = –15V VCM = –15V VS = 5V, 0V VCM = 5V Output Saturation Voltage vs Load Current (Output Low) LOAD CURRENT (mA) SATURATION VOLTAGE (V) 0.01 1 10 100 1630/31 G05 0.1 0.1 0.01 VS = 5V, 0V TA = –55°C TA = 125°C TA = 25°C LOAD CURRENT (mA) SATURATION VOLTAGE (V) 0.01 1 10 100 1630/31 G06 0.1 0.1 0.01 VS = 5V, 0V TA = –55°C TA = 125°C TA = 25°C Output Saturation Voltage vs Load Current (Output High)

TYPICAL PERFORMANCE CHARACTERISTICS UW TOTAL SUPPLY VOLTAGE (V) CHANGE IN OFFSET VOLTAGE (µV) 100 150 200 23 4 5 1630/31 G07 250 300 TA = 125°C TA = –55 °C TA = 25°C Minimum Supply Voltage Noise Voltage Spectrum FREQUENCY (Hz) NOISE VOLTAGE (nV/√Hz) 10 100 1000 11630/31 G09 VS = 5V, 0V VCM = 2.5V PNP ACTIVE VCM = 4.25V NPN ACTIVE FREQUENCY (Hz) CURRENT NOISE (pA/√Hz) 10 100 1000 1630/31 G10 VS = 5V, 0V VCM = 2.5V PNP ACTIVE VCM = 4.25V NPN ACTIVE Current Noise Spectrum 0.1Hz to 10Hz Output Voltage Noise TIME (1s/DIV) OUTPUT VOLTAGE (200nV/DIV) 1630/31 G25 VS =5V, 0V VCM = VS/2 TOTAL SUPPLY VOLTAGE (V) GAIN BANDWIDTH (MHz) PHASE MARGIN (DEG) 5 10 15 20 1630/31 G14 100 PHASE MARGIN GAIN BANDWIDTH VCM = VS/2 Gain Bandwidth and Phase Margin vs Supply VoltageGain and Phase vs Frequency FREQUENCY (MHz) VOLTAGE GAIN (dB) PHASE SHIFT (DEG) –10 –20 180 135 –45 –90 –135 –180 –225 –270 0.01 1 10 100 1630/31 G11 0.1 PHASE GAIN RL = 1k VS = 3V, 0V VS = –15V FREQUENCY (Hz) COMMON MODE REJECTION RATIO (dB) 100 120 110 1k 100k 1M 10M 1630/31 G12 10k VS = –15V VS = 5V, 0V CMRR vs Frequency PSRR vs Frequency FREQUENCY (Hz) POWER SUPPLY REJECTION RATIO (dB) 100 1k 100k 1M 10M 1630/31 G13 10k VS = –15V POSITIVE SUPPLY NEGATIVE SUPPLY FREQUENCY (Hz) CHANNEL SEPARATION (dB) 100 1k 10k 100k 1M 1630/31 G15 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 Channel Separation vs Frequency

TYPICAL PERFORMANCE CHARACTERISTICS UW OUTPUT VOLTAGE (V) INPUT VOLTAGE (µV) 3 5 1630/31 G20 12 4 VS = 5V, 0V RL = 1k RL = 10k Open-Loop Gain OUTPUT VOLTAGE (V) –20 –15 INPUT VOLTAGE (µV) 1630/31 G19 –10 –20 –10 –5 05 10 15 –15 VS = –15V RL = 1k RL = 10k Open-Loop Gain TIME AFTER POWER-UP (SEC) CHANGE IN OFFSET VOLTAGE (µV) –40 –80 –120 –160 –200 60 100 160 1630/31 G22 20 40 80 120 140 S8 PACKAGE VS = –15V LT1631CS VS = –15V N8 PACKAGE VS = 5V, 0V N8 PACKAGE VS = –15V S8 PACKAGE VS = 5V, 0V LT1631CS VS = 5V, 0V Warm-Up Drift vs Time OUTPUT VOLTAGE (V) INPUT VOLTAGE (µV) 200 150 100 –50 –100 –150 –200 1630/31 G21 10246 57 VS = – 15V RL = 100Ω Open-Loop Gain CAPACITIVE LOAD (pF) OVERSHOOT (%) 10 100 1000 1630/31 G16 VS = 5V, 0V AV = 1 RL = 1k Capacitive Load Handling TOTAL SUPPLY VOLTAGE (V) SLEW RATE (V/µs) 8 1 22 02 841 6 24 32 1630/31 G17 RISING EDGE FALLING EDGE VOUT = 80% OF VS AV = –1 Slew Rate vs Supply Voltage Output Step vs Settling Time to 0.01% Maximum Undistorted Output Signal vs Frequency FREQUENCY (kHz) OUTPUT VOLTAGE SWING (VP-P) 10 100 1000 1630/31 G24 VS = 5V, 0V AV = –1 VS = 5V, 0V AV = 1 FREQUENCY (kHz) THD + NOISE (%) 0.1 0.01 0.001 0.0001 0.1 10 100

163031 G23

VIN = 2VP-P RL = 10k VS = 3V, 0V AV = 1 VS = 5V, 0V AV = 1 VS = 5V, 0V AND 3V, 0V AV = –1 Total Harmonic Distortion + Noise vs Frequency SETTLING TIME (µs) 0 0.25 –10 OUTPUT STEP (V) 0.50 0.75 1.00 1630/31 G18 1.25 1.50 VS = –15V NONINVERTING INVERTING INVERTINGNONINVERTING

TYPICAL PERFORMANCE CHARACTERISTICS UW Harmonic Distortion vs Frequency FREQUENCY (kHz) 100 HARMONIC DISTORTION (dBc) –20 –40 –60 –80 –100 1000 1630/31 G301000 200 500 3RD 2ND 2ND 3RD VS = 5V, 0V AV = 1 VIN = 2VP-P RL = 150Ω RL = 1k Harmonic Distortion vs Frequency 5V Large-Signal Response 1630/31 G27VS = 5V, 0V AV = 1 RL = 1k 5V Small-Signal Response 1630/31 G26VS = 5V, 0V AV = 1 RL = 1k FREQUENCY (kHz) 100 HARMONIC DISTORTION (dBc) –20 –40 –60 –80 –100 1000 1630/31 G311000 200 500 3RD 2ND 3RD VS = 5V, 0V AV = –1 VIN = 2VP-P RL = 150Ω RL = 1k 2ND ±15V Small-Signal Response VS = ±15V AV = 1 RL = 1k ±15V Large-Signal Response 1630/31 G29VS = ±15V AV = 1 RL = 1k 1630/31 G28 APPLICATIONS INFORMATIONWU UU Rail-to-Rail Input and Output The LT1630/LT1631 are fully functional for an input and output signal range from the negative supply to the posi- tive supply. Figure 1 shows a simplified schematic of the amplifier. The input stage consists of two differential amplifiers, a PNP stage Q1/Q2 and an NPN stage Q3/Q4 that are active over different ranges of input common mode voltage. The PNP differential input pair is active for input common mode voltages V CM between the negative supply to approximately 1.4V below the positive supply. As V CM moves closer toward the positive supply, the transistor Q5 will steer the tail current I 1 to the current mirror Q6/Q7, activating the NPN differential pair and the PNP pair becomes inactive for the rest of the input com- mon mode range up to the positive supply. The output is configured with a pair of complementary common emitter stages Q14/Q15 that enables the output to swing from rail to rail. These devices are fabricated on Linear Technology’s proprietary complementary bipolar process to ensure similar DC and AC characteristics. Capacitors C1 and C2 form local feedback loops that lower the output impedance at high frequencies.

Figure 1. LT1630 Simplified Schematic Diagram voltage or use the DIP package part.

APPLICATIONS INFORMATIONWU UU Input Offset Voltage The offset voltage changes depending upon which input stage is active, and the maximum offset voltages are trimmed to less than 525 µV. To maintain the precision characteristics of the amplifier, the change of VOS over the entire input common mode range (CMRR) is guaranteed to be less than 525µV on a single 5V supply. Input Bias Current The input bias current polarity depends on the input common mode voltage. When the PNP differential pair is active, the input bias currents flow out of the input pins. They flow in the opposite direction when the NPN input stage is active. The offset voltage error due to input bias currents can be minimized by equalizing the noninverting and inverting input source impedance. Output The outputs of the LT1630/LT1631 can deliver large load currents; the short-circuit current limit is 70mA. Take care to keep the junction temperature of the IC below the absolute maximum rating of 150 °C (refer to the Power Dissipation section). The output of these amplifiers have reverse-biased diodes to each supply. If the output is forced beyond either supply, unlimited current will flow through these diodes. If the current is transient and limited to several hundred mA, no damage to the part will occur. Overdrive Protection To prevent the output from reversing polarity when the input voltage exceeds the power supplies, two pairs of crossing diodes D1 to D4 are employed. When the input voltage exceeds either power supply by approximately 700mV, D1/D2 or D3/D4 will turn on, forcing the output to the proper polarity. For this phase reversal protection to work properly, the input current must be limited to less than 5mA. If the amplifier is to be severely overdriven, an external resistor should be used to limit the overdrive current. The LT1630/LT1631’s input stages are protected against large differential input voltages by a pair of back-to-back diodes D5/D6. When a differential voltage of more than 0.7V is applied to the inputs, these diodes will turn on, preventing the emitter-base breakdown of the input transistors. The current in D5/D6 should be limited to less than 10mA. Internal 225Ω resistors R6 and R7 will limit the input current for differential input signals of 4.5V or less. For larger input levels, a resistor in series with either or both inputs should be used to limit the current. Worst-case differential input voltage usually occurs when the output is shorted to ground. In addition, the amplifier is protected against ESD strikes up to 3kV on all pins. Capacitive Load The LT1630/LT1631 are wideband amplifiers that can drive capacitive loads up to 200pF on ±15V supplies in a unity-gain configuration. On a 3V supply, the capacitive load should be kept to less than 100pF. When there is a need to drive larger capacitive loads, a resistor of 20Ω to 50Ω should be connected between the output and the capacitive load. The feedback should still be taken from the output so that the resistor isolates the capacitive load to ensure stability. Feedback Components The low input bias currents of the LT1630/LT1631 make it possible to use the high value feedback resistors to set the gain. However, care must be taken to ensure that the pole formed by the feedback resistors and the total capacitance at the inverting input does not degrade stability. For instance, the LT1630/LT1631 in a noninverting gain of 2, set with two 20k resistors, will probably oscillate with 10pF total input capacitance (5pF input capacitance and 5pF board capacitance). The amplifier has a 5MHz cross- ing frequency and a 52° phase margin at 6dB of gain. The feedback resistors and the total input capacitance form a pole at 1.6MHz that induces a phase shift of 72° at 5MHz! The solution is simple: either lower the value of the resistors or add a feedback capacitor of 10pF or more.

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. Dimensions in inches (millimeters) unless otherwise noted.PACKAGE DESCRIPTIONU 8-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 0.016 – 0.050 0.406 – 1.270 0.010 – 0.020 0° – 8° TYP 0.008 – 0.010 (0.203 – 0.254) S14 0695 1 2 3 4 0.150 – 0.157** (3.810 – 3.988) 14 13 0.337 – 0.344* (8.560 – 8.738) 0.228 – 0.244 (5.791 – 6.197) 12 11 10 9 5 6 7 80.053 – 0.069 (1.346 – 1.752) 0.014 – 0.019 (0.355 – 0.483) 0.004 – 0.010 (0.101 – 0.254) 0.050 (1.270) TYP DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE N8 1197 0.009 – 0.015 (0.229 – 0.381) 0.300 – 0.325 (7.620 – 8.255) 0.325 +0.035 –0.015 +0.889 –0.3818.255() 0.100 – 0.010 (2.540 – 0.254) 0.065 (1.651) TYP 0.045 – 0.065 (1.143 – 1.651) 0.130 – 0.005 (3.302 – 0.127) 0.020 (0.508) MIN0.018 – 0.003 (0.457 – 0.076) 0.125 (3.175) MIN 12 3 4 87 6 5 0.255 – 0.015* (6.477 – 0.381) 0.400* (10.160) MAX *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) S Package 14-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) SO8 0996 0.016 – 0.050 0.406 – 1.270 0.010 – 0.020 0°– 8° TYP 0.008 – 0.010 (0.203 – 0.254) 0.053 – 0.069 (1.346 – 1.752) 0.014 – 0.019 (0.355 – 0.483) 0.004 – 0.010 (0.101 – 0.254) 0.050 (1.270) TYP 1 2 3 4 0.150 – 0.157** (3.810 – 3.988) 8 7 6 5 0.189 – 0.197* (4.801 – 5.004) 0.228 – 0.244 (5.791 – 6.197) DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

amplifier A2 is used to restore the DC level at the output. Figure 6. RF Amplifier Control Biasing and DC Restoration C-Load is a trademark of Linear Technology Corporation.