LT1460

LTC2758 LINER | Alldatasheet

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Technical content

For more information www.linear .com/L TC2758 Typical applicaTion

FeaTures

applicaTions

DescripTion

The LT C®2758 is a dual 18-bit multiplying serial-input, current-output digital-to-analog converter . L TC2758A provides full 18-bit performance (INL and DNL of ±1LSB maximum) over temperature without any adjustments. 18-bit monotonicity is guaranteed in all performance grades. This SoftSpan™ DAC operates from a single 3V to 5V supply and offers six output ranges (up to ±10V) that can be programmed through the 3-wire SPI serial interface or pin-strapped for operation in a single range. Any on-chip register (including DAC output-range set - tings) can be read for verification in just one instruction cycle; and if you change register content, the altered register will be automatically read back during the next instruction cycle. Voltage-controlled offset and gain adjustments are also provided; and the power -on reset circuit and CLR pin both reset the DAC outputs to 0V regardless of output range. L, L T , L TC, L TM, Linear Technology and the Linear logo are registered trademarks and SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Dual 18-Bit VOUT DAC with Software-Selectable Ranges n Maximum 18-Bit INL Error: ±1 LSB Over Temperature n Program or Pin-Strap Six Output Ranges: 0V to 5V , 0V to 10V , –2.5V to 7.5V , ±2.5V , ±5V , ±10V n Guaranteed Monotonic Over Temperature n Glitch Impulse 0.4nV•s (3V), 2nV•s (5V) n 18-Bit Settling Time: 2.1µs n 2.7V to 5.5V Single Supply Operation n 1µA Maximum Supply Current n Voltage-Controlled Offset and Gain T rims n Serial Interface with Readback of All Registers n Clear and Power-On-Reset to 0V Regardless of Output Range n 48-Pin 7mm × 7mm LQFP Package n Instrumentation n Medical Devices n Automatic Test Equipment n Process Control and Industrial Automation L TC2758 Integral Nonlinearity CODE 0 65536 –1.0 INL (LSB) –0.8 –0.6 –0.4 –0.2 0.6 0.4 0.2 0.8 1.0 131072 196608 262143

2758 TA01b

R OFSAGEADJA GEADJB ROFSB RCOMB RCOMA RINB VOSADJA VOSADJB IOUT1A IOUT2A IOUT1B IOUT2B RFBA RFBB

2758 TA01a

0.1µF OFFSET A ADJUST OFFSET B ADJUST GAIN A ADJUST GAIN B ADJUST 27pF 27pF

For more information www.linear .com/L TC2758 http://www.linear .com/product/L TC2758#orderinfo absoluTe MaxiMuM raTings RINX, RCOMX, REFX, RFBX, ROFSX, VOSADJX , 0.3V to 7V 0.3V to VDD+0.3V (max 7V) Operating Temperature Range LT °C to 70°C L 40°C to 85°C 0°C 65°C to 150°C 00°C orDer inForMaTion LEAD FREE FINISH PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L TC2758BCLX#PBF L TC2758LX 48-Lead (7mm × 7mm) Plastic LQFP 0°C to 70°C L TC2758BILX#PBF L TC2758LX 48-Lead (7mm × 7mm) Plastic LQFP –40°C to 85°C L TC2758ACLX#PBF L TC2758LX 48-Lead (7mm × 7mm) Plastic LQFP 0°C to 70°C L TC2758AILX#PBF L TC2758LX 48-Lead (7mm × 7mm) Plastic LQFP –40°C to 85°C Consult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear .com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear .com/packaging/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. pin conFiguraTion (Notes 1, 2) REF A REF A R COMA GEADJA RINA RINA GND IOUT2AS IOUT2AF GND CS/LD SDI SCK SRO GND V DD GND GND CLR RFLAG DNC M-SPAN R OFSA ROFSA RFBA RFBA IOUT1A VOSADJA VOSADJB IOUT1B RFBB RFBB ROFSB ROFSB REF B REF B R COMB GEADJB RINB RINB GND I OUT2BS IOUT2BF GND LDAC TOP VIEW LX PACKAGE 48-LEAD (7mm × 7mm) PLASTIC LQFP TJMAX = 150°C, θJA = 53°C/W

For more information www.linear .com/L TC2758 elecTrical characTerisTics VDD = 5V , V(RINX) = 5V unless otherwise specified. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER CONDITIONS L TC2758B L TC2758A UNITSMIN TYP MAX MIN TYP MAX Static Performance Resolution l 18 18 Bits Monotonicity l 18 18 Bits DNL Differential Nonlinearity l ±1 ±0.2 ±1 LSB INL Integral Nonlinearity l ±2 ±0.5 ±1 LSB GE Gain Error All Output Ranges l ±48 ±6 ±32 LSB Gain Error Temperature Coefficient ∆Gain/∆Temp ±0.25 ±0.25 ppm/°C BZE Bipolar Zero Error All Bipolar Ranges l ±36 ±1 ±24 LSB Bipolar Zero Temperature Coefficient ±0.2 ±0.2 ppm/°C Unipolar Zero-Scale Error Unipolar Ranges (Note 3) l ±0.03 ±3.2 ±0.03 ±3.2 LSB PSR Power Supply Rejection VDD = 5V , ±10% VDD = 3V , ±10% l l ±1.6 ±0.1 ±0.3 ±0.8 LSB/V LSB/V I LKG IOUT1 Leakage Current TA = 25°C TMIN to TMAX l ±0.05 ±2 ±0.05 ±2 nA nA SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Analog Pins Reference Inverting Resistors (Note 4) l 16 20 kΩ RREF DAC Input Resistance (Notes 5, 6) l 8 10 kΩ RFB Feedback Resistors (Note 6) l 8 10 kΩ ROFS Bipolar Offset Resistors (Note 6) l 16 20 kΩ RVOSADJ Offset Adjust Resistors l 1024 1280 kΩ RGEADJ Gain Adjust Resistors l 2048 2560 kΩ CIOUT1 Output Capacitance Full-Scale Zero-Scale pF Dynamic Performance Output Settling Time Span Code = 0000, 10V Step. T o ±0.0004% FS (Note 7) 2.1 μs Glitch Impulse VDD = 5V (Note 8) VDD = 3V (Note 8) 0.4 nV•s nV •s Digital-to-Analog Glitch Impulse V DD = 5V (Note 9) VDD = 3V (Note 9) 2.6 0.6 nV•s nV Reference Multiplying BW 0V to 5V Range, Code = Full Scale, –3dB Bandwidth

1 MHz

Multiplying Feedthrough Error 0V to 5V Range, V REF = ±10V , 10kHz Sine Wave 0.4 mV Analog Crosstalk (Note 10) –109 dB THD Total Harmonic Distortion (Note 11) Multiplying –110 dB Output Noise V oltage Density (Note 12) at I OUT1 13 nV/√Hz VDD = 5V , V(RINX) = 5V unless otherwise specified. The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C.

For more information www.linear .com/L TC2758 TiMing characTerisTics The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. elecTrical characTerisTics VDD = 5V , V(RINX) = 5V unless otherwise specified. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Supply VDD Supply Voltage l 2.7 5.5 V IDD VDD Supply Current Digital Inputs = 0V or VDD l 0.5 2 μA Digital Inputs V IH Digital Input High Voltage 3.3V ≤ VDD ≤ 5.5V 2.7V ≤ VDD < 3.3V l l 2.4 V V VIL Digital Input Low Voltage 4.5V < VDD ≤ 5.5V 2.7V ≤ VDD ≤ 4.5V l l 0.8 0.6 V V Hysteresis Voltage 0.1 V I IN Digital Input Current VIN = GND to VDD l ±1 µA CIN Digital Input Capacitance VIN = 0V (Note 13) l 6 pF Digital Outputs VOH IOH = 200µA 2.7V ≤ VDD ≤ 5.5V l VDD – 0.4 V VOL IOL = 200µA 2.7V ≤ VDD ≤ 5.5V l 0.4 V SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD = 4.5V to 5.5V t1 SDI Valid to SCK Set-Up l 7 ns t2 SDI Valid to SCK Hold l 7 ns t3 SCK High Time l 11 ns t4 SCK Low Time l 11 ns t5 CS/LD Pulse Width l 9 ns t6 LSB SCK High to CS/LD High l 4 ns t7 CS/LD Low to SCK Positive Edge l 4 ns t8 CS/LD High to SCK Positive Edge l 4 ns t9 SRO Propagation Delay CLOAD = 10pF l 18 ns t10 CLR Pulse Width Low l 36 ns t11 LDAC Pulse Width Low l 15 ns t12 CLR Low to RFLAG Low CLOAD = 10pF (Note 13) l 50 ns t13 CS/LD High to RFLAG High CLOAD = 10pF (Note 13) l 40 ns SCK Frequency 50% Duty Cycle (Note 14) l 40 MHz VDD = 2.7V to 3.3V t1 SDI Valid to SCK Set-Up l 9 ns t2 SDI Valid to SCK Hold (Note 13) l 9 ns t3 SCK High Time CL = 10pF l 15 ns t4 SCK Low Time l 15 ns t5 CS/LD Pulse Width l 12 ns t6 LSB SCK High to CS/LD High l 5 ns

For more information www.linear .com/L TC2758 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 3: Calculation from feedback resistance and I OUT1 leakage current specifications; not production tested. In most applications, unipolar zero- scale error is dominated by contributions from the output amplifier . Note 4: Input resistors measured from RINX to RCOMX; feedback resistors measured from RCOMX to REFX. Note 5: DAC input resistance is independent of code. Note 6: Parallel combination of the resistances from the specified pin to I OUT1X and from the specified pin to IOUT2X. Note 7: Using L T1468 with CFEEDBACK = 27pF . A ±0.0004% settling time of 1.8µs can be achieved by optimizing the time constant on an individual basis. See Application Note 120, 1ppm Settling Time Measurement for a Monolithic 18-Bit DAC. TiMing characTerisTics The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Note 8: Measured at the major carry transition, 0V to 5V range. Output amplifier: L T1468; C FB = 50pF. Note 9: Full-scale transition; REF = 0V. Note 10: Analog Crosstalk is defined as the AC voltage ratio VOUTB/VREFA, expressed in dB. REFB is grounded, and DAC B is set to 0V-5V span and zero-, mid- or full- scale code. VREFA is a 3VRMS, 1kHz sine wave. Note 11: REF = 6VRMS at 1kHz. 0V to 5V range. DAC code = FS. Output amplifier = L T1468. Note 12: Calculation from V n = √4kTRB, where k = 1.38E-23 J/°K (Boltzmann constant), R = resistance (Ω), T = temperature (°K), and B = bandwidth (Hz). 0V to 5V Range; zero-, mid-, or full-scale. Note 13: Guaranteed by design; not production tested. Note 14: When using SRO, maximum SCK frequency f MAX is limited by SRO propagation delay t9 as follows: fMAX = 1 2 t 9 + tS( ) ⎠⎟ , where tS is the setup time of the receiving device. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS t7 CS/LD Low to SCK Positive Edge l 5 ns t8 CS/LD High to SCK Positive Edge l 5 ns t9 SRO Propagation Delay CLOAD = 10pF l 26 ns t10 CLR Pulse Width Low l 60 ns t11 LDAC Pulse Width Low l 20 ns t12 CLR Low to RFLAG Low CLOAD = 10pF (Note 13) l 70 ns t13 CS/LD High to RFLAG high CLOAD = 10pF (Note 13) l 60 ns SCK Frequency 50% Duty Cycle (Note 14) l 25 MHz

For more information www.linear .com/L TC2758 INL vs Temperature DNL vs Temperature Gain Error vs Temperature Bipolar Zero Error vs Temperature INL vs Reference Voltage DNL vs Reference Voltage Typical perForMance characTerisTics Integral Nonlinearity (INL) Differential Nonlinearity (DNL) V DD = 5V , V(RINX) = 5V , TA = 25°C, unless otherwise noted. INL vs Output Range CODE 0 65536 –1.0 INL (LSB) –0.8 –0.6 –0.4 –0.2 0.6 0.4 0.2 0.8 1.0 131072 196608 262143

2758 G01

–1.0 DNL (LSB) –0.8 –0.6 –0.4 –0.2 0.6 0.4 0.2 0.8 1.0 131072 196608 262143

2758 G02

–2.5V TO 2.5V –2.5V TO 7.5V –1.0 INL (LSB) –0.8 –0.6 –0.4 –0.2 0.4 0.2 0.6 0.8 1.0 TO –5V TO –10V TO 10V TO 10V

2758 G03

TEMPERATURE (°C) –40 –20 –1.0 INL (LSB) –0.8 –0.6 –0.4 –0.2 0.4 0.2 0.6 0.8 1.0 0 20 80 60 4085

2758 G04

+INL –INL 0V TO 10V RANGE TEMPERATURE (°C) –40 –20 –1.0 DNL (LSB) –0.8 –0.6 –0.4 –0.2 0.4 0.2 0.6 0.8 1.0 0 20 80 60 4085

2758 G05

+DNL –DNL 0V TO 10V RANGE TEMPERATURE (°C) –40 –20 GE (LSB) 0 20 80 60 4085

2758 G06

±0.25ppm/°C TYP ±2.5V ±5V ±10V 0V TO 5V 0V TO 10V –2.5V TO 7.5V TEMPERATURE (°C) –40 –20 –16 BZE (LSB) –12 0 20 80 60 4085

2758 G07

±5V ±10V ±2.5V –2.5V TO 7.5V ±0.15ppm/°C TYP V(RIN) (V) –10 –2 –6 –4 –1.0 INL (LSB) –0.8 –0.6 –0.2 –0.4 0.4 0.2 0.6 0.8 1.0 0 2 8 6 4 10

2758 G08

+INL –INL +INL –INL ±5V RANGE V(RIN) (V) –10 –2 –6 –4 –1.0 DNL (LSB) –0.8 –0.6 –0.2 –0.4 0.4 0.2 0.6 0.8 1.0 0 2 8 6 4 10

2758 G09

+DNL –DNL +DNL –DNL ±5V RANGE

For more information www.linear .com/L TC2758 Typical perForMance characTerisTics Settling Full-Scale Step INL vs V DD DNL vs V DD Logic Threshold vs Supply Voltage Supply Current vs Logic Input Voltage Supply Current vs Update Frequency Mid-Scale Glitch (V DD = 3V) VDD = 5V , V(RINX) = 5V , TA = 25°C, unless otherwise noted. Mid-Scale Glitch (V DD = 5V) Multiplying Frequency Response vs Digital Code VDD (V) 2.5 3.5 4 –1.0 INL (LSB) –0.8 –0.6 –0.2 –0.4 0.4 0.2 0.6 0.8 1.0 5 4.5 5.5

2758 G10

+INL –INL 0V TO 10V RANGE VDD (V) 2.5 3.5 4 –1.0 DNL (LSB) –0.8 –0.6 –0.2 –0.4 0.4 0.2 0.6 0.8 1.0 5 4.5 5.5

2758 G11

+DNL –DNL 0V TO 10V RANGE ALL BITS ON ALL BITS OFF FREQUENCY (Hz) 100 1k 10k –140 ATTENUATION (dB)–100 –120 –60 –80 –40 –20 1M100k 10M

2758 G12

C FEEDBACK = 15pF D17 D16 D15 D14 D13 D12 D11 D10 500ns/DIV CS/LD 5V/DIV GATED SETTLING WAVEFORM 100µV/DIV (AVERAGED)

2758 G13

LT1468 AMP; CFEEDBACK = 20pF 0V TO 10V STEP VREF = –10V; SPAN CODE = 0000 tSETTLE = 1.8µs to 0.0004% (18 BITS) DIGITAL INPUT VOL TAGE (V) SUPPL Y CURRENT (mA)

2758 G16

VDD = 5V CLR, LDAC, SDI, SCK, CS/LD TIED TOGETHER VDD = 3V VDD (V) 2.5 0.5 LOGIC THRESHOLD (V) 0.75 1.25 1.5 3 3.5 4 4.5 5 5.5 1.75

2758 G17

SCK FREQUENCY (Hz)

0.0001 SUPPL Y CURRENT (mA)

0.001 0.01 0.1 100 VDD = 5V 100 10k 1M 100M

2758 G18

VDD = 3V AL TERNATING ZERO-SCALE AND FULL-SCALE 500ns/DIV CS/LD 5V/DIV VOUT 5mV/DIV (AVERAGED)

2758 G14

C FEEDBACK = 50pF RISING MAJOR CARRY TRANSITION. FALLING TRANSITION IS SIMILAR OR BETTER. 0.4nV•s TYP 500ns/DIV CS/LD 5V/DIV VOUT 5mV/DIV (AVERAGED)

2758 G15

C FEEDBACK = 50pF RISING MAJOR CARRY TRANSITION. FALLING TRANSITION IS SIMILAR OR BETTER. 2nV•s TYP

For more information www.linear .com/L TC2758 pin FuncTions REFA (Pins 1, 2): Feedback Resistor for the DAC A Refer- ence Inverting Amplifier , and Reference Input for DAC A. The 20k feedback resistor is connected internally from REFA to R COMA. For normal operation tie this pin to the output of the DAC A reference inverting amplifier (see Typical Application). Typically –5V; accepts up to ±15V . Pins 1 and 2 are internally shorted together . R COMA (Pin 3): Virtual Ground Point for the DAC A Ref - erence Amplifier Inverting Resistors. The 20k reference inverting resistors are connected internally from R INA to RCOMA and from RCOMA to REFA, respectively (see Block Diagram). For normal operation tie RCOMA to the negative input of the external reference inverting amplifier (see Typical Application). GE ADJA (Pin 4): Gain Adjust Pin for DAC A. This control pin can be used to null gain error or to compensate for reference errors. The gain change expressed in LSB is the same for any output range. See System Offset and Gain Adjustments in the Operation section. Tie to ground if not used. R INA (Pins 5, 6): Input Resistor for the DAC A External Reference Inverting Amplifier . The 20k input resistor is connected internally from RINA to RCOMA. For normal op- eration tie RINA to the external positive reference voltage (see Typical Application). Either or both of these precision- matched resistor sets (each set comprising R INX, RCOMX and REFX) may be used to invert positive references to provide the negative voltages needed by the DACs. Typi- cally 5V; accepts up to ±15V . Pins 5 and 6 are internally shorted together . GND (Pins 7, 10, 15, 17, 18, 27, 30): Ground; tie to ground. IOUT2AS, I OUT2AF (Pins 8, 9): DAC A Current Output Complement Sense and Force Pins. Tie to ground via a clean, low-impedance path. These pins may be used with a precision ground buffer amp as a Kelvin sensing pair (see the Applications Information section). CS/LD (Pin 11): Synchronous Chip Select and Load Input Pin. SDI (Pin 12): Serial Data Input. Data is clocked in on the rising edge of the serial clock (SCK) when CS/LD is low. SCK (Pin 13): Serial Clock Input. SRO (Pin 14): Serial Readback Output. Data is clocked out on the falling edge of SCK. Readback data begins clocking out after the last address bit A0 is clocked in. SRO is an active output only when the chip is selected (i.e., when CS/LD is low). Otherwise SRO presents a high-impedance output in order to allow other parts to control the bus. V DD (Pin 16): Positive Supply Input; 2.7V ≤ VDD ≤ 5.5V . By- pass with a 0.1μF low-ESR ceramic capacitor to ground. CLR (Pin 19): Asynchronous Clear Input. When this pin is low, all DAC registers (both code and span) are cleared to zero. All DAC outputs are cleared to zero volts. RFLAG (Pin 20): Reset Flag Output. An active low output is asserted when there is a power-on reset or a clear event. Returns high when an Update command is executed. DNC (Pin 21): Do Not Connect. M-SPAN (Pin 22): Manual Span Control Pin. M-SPAN is used in conjunction with pins S2, S1 and S0 (Pins 25, 24 and 23) to configure all DACs for operation in a single, fixed output range. To configure the part for manual-span use, tie M-SPAN directly to V DD. The DAC output range is then set via hardware pin strapping of pins S2, S1 and S0 (rather than through the SPI port); and Write and Update commands have no effect on the active output span. To configure the part for SoftSpan use, tie M-SPAN directly to GND. The output ranges are then individually control- lable through the SPI port; and pins S2, S1 and S0 have no effect. See Ma nual Span Configuration in the Operation section. M- SPAN must be connected either directly to GND (SoftSpan configuration) or to VDD (manual-span configuration). S0 (Pin 23): Span Bit 0 Input. In Manual Span mode (M- SPAN tied to V DD), Pins S0, S1 and S2 are pin-strapped to select a single fixed output range for all DACs. These pins should be tied to either GND or V DD even if they are unused. S1 (Pin 24): Span Bit 1 Input. In Manual Span mode (M- SPAN tied to VDD), Pins S0, S1 and S2 are pin-strapped to select a single fixed output range for all DACs. These pins should be tied to either GND or V DD even if they are unused.

For more information www.linear .com/L TC2758 pin FuncTions S2 (Pin 25): Span Bit 2 Input. In Manual Span mode (M- SPAN tied to VDD), Pins S0, S1 and S2 are pin-strapped to select a single fixed output range for all DACs. These pins should be tied to either GND or V DD even if they are unused. LDAC (Pin 26): Asynchronous DAC Load Input. When LDAC is a logic low, all DACs are updated (CS/LD must be high). I OUT2BF, IOUT2BS (Pins 28, 29): DAC B Current Output Complement Force and Sense Pins. Tie to ground via a clean, low-impedance path. These pins may be used with a precision ground buffer amp as a Kelvin sensing pair (see the Applications Information section). R INB (Pins 31, 32): Input Resistor for the DAC B External Reference Inverting Amplifier . The 20k input resistor is connected internally from RINB to RCOMB. For normal op- eration tie RINB to the external positive reference voltage (see Typical Application). Either or both of these precision- matched resistor sets (each set comprising R INX, RCOMX and REFX) may be used to invert positive references to provide the negative voltages needed by the DACs. Typi- cally 5V; accepts up to ±15V . Pins 31 and 32 are internally shorted together . GE ADJB (Pin 33): Gain Adjust Pin for DAC B. This control pin can be used to null gain error or to compensate for reference errors. The gain change expressed in LSB is the same for any output range. See System Offset and Gain Adjustments in the Operation section. Tie to ground if not used. R COMB (Pin 34): Virtual Ground Point for the DAC B Ref- erence Amplifier Inverting Resistors. The 20k reference inverting resistors are connected internally from RINB to RCOMB and from RCOMB to REFB, respectively (see Block Diagram). For normal operation tie RCOMB to the negative input of the external reference inverting amplifier (see Typical Application). REFB (Pins 35, 36): Feedback Resistor for the DAC B Reference Inverting Amplifier , and Reference Input for DAC B. The 20k feedback resistor is connected internally from REFB to R COMB. For normal operation tie this pin to the output of the DAC B reference inverting amplifier (see Typical Application). Typically –5V; accepts up to ±15V . Pins 35 and 36 are internally shorted together . R OFSB (Pins 37, 38): Bipolar Offset Resistor for DAC B. These pins provide the translation of the output voltage range for bipolar spans. Accepts up to ±15V; for normal operation tie to the positive reference voltage at R INB (Pins 31, 32). Pins 37 and 38 are internally shorted together . RFBB (Pins 39, 40): DAC B Feedback Resistor . For normal operation tie to the output of the I/V converter amplifier for DAC B (see Typical Application). The DAC output current from I OUT1B flows through the feedback resistor to the RFBB pins. Pins 39 and 40 are internally shorted together . IOUT1B (Pin 41): DAC B Current Output. This pin is a virtual ground when the DAC is operating and should reside at 0V . For normal operation tie to the negative input of the I/V converter amplifier for DAC B (see Typical Application). V OSADJB (Pin 42): DAC B Offset Adjust Pin. This voltage- control pin can be used to null unipolar offset or bipolar zero error . The offset change expressed in LSB is the same for any output range. See System Offset and Gain Adjust- ments in the Operation section. Tie to ground if not used. V OSADJA (Pin 43): DAC A Offset Adjust Pin. This voltage- control pin can be used to null unipolar offset or bipolar zero error . The offset change expressed in LSB is the same for any output range. See System Offset and Gain Adjust- ments in the Operation section. Tie to ground if not used. I OUT1A (Pin 44): DAC A Current Output. This pin is a virtual ground when the DAC is operating and should reside at 0V . For normal operation tie to the negative input of the I/V converter amplifier for DAC A (see Typical Application). R FBA (Pins 45, 46): DAC A Feedback Resistor . For normal operation tie to the output of the I/V converter amplifier for DAC A (see Typical Application). The DAC output current from I OUT1A flows through the feedback resistor to the RFBA pins. Pins 45 and 46 are internally shorted together . ROFSA (Pins 47, 48): Bipolar Offset Resistor for DAC A. This pin provides the translation of the output voltage range for bipolar spans. Accepts up to ±15V; for normal operation tie to the positive reference voltage at R INA (Pins 5, 6). Pins 47 and 48 are internally shorted together .

For more information www.linear .com/L TC2758 block DiagraM TiMing DiagraM SDI SRO Hi-Z CS/LD SCK LSB 2758 TD LSB t5 t7 1 2 31 32 LDAC t3 t4 t11 CODE REGISTERS SPAN REGISTERS 31,32 35,36 37,38 39,40 ROFSB REFB RINB SROSCKSDIS2 S1 S0M-SPAN CS/LD LDACCLRRFLAG GEADJB RCOMB IOUT1B IOUT2BS IOUT2BF VOSADJB RFBB 26131211192025242322 CODE REGISTERS SPAN REGISTERS DAC REG DAC REG 5,6 1,2 47,48 45,46 ROFSA REFA RINA GEADJA RCOMA IOUT1A IOUT2AS IOUT2AF VOSADJA RFBA DAC A 18-BIT WITH SPAN SELECT GND 7, 10, 15, 17, 18, 27, 30 VDD INPUT REG INPUT REG INPUT REG INPUT REG DAC REG DAC REG DAC B 18-BIT WITH SPAN SELECT CONTROL AND READBACK LOGIC 2758 BD L TC2758 2.56M 2.56M 20k 20k 20k 20k POWER-ON RESET

four bipolar ranges (±2.5V, ±5V, ±10V and –2.5V to 7.5V).

2754 F01

Figure 1. Using M-SPAN to Configure the L TC2758 register and a DAC register. DAC output voltage or output range. previously been altered via a Write operation.

For more information www.linear .com/L TC2758 operaTion data occupies the first 18 bits of the 24-bit field; and the span bits are the last four bits of the second data byte when checking the output range. In both cases, all other bits in the 24-bit data field are filled by zeros. Figure 2 shows the input and readback sequences. The data outputted by SRO is always in the same position and sequence as the input data. Note, however , that this means that the SRO data shifts out one-half clock cycle earlier than the corresponding bit shifting in on SDI. For example, code bit D9, which is shifted in to SDI on the rising edge of SCK clock 17, is clocked out of SRO on the falling edge of clock 16. This allows D9 to be clocked to an external microprocessor on the rising edge of clock 17. For Read commands, the requested data is shifted out of SRO in the 3-byte (24-bit) data field immediately after the command/address byte. There is no instruction-cycle latency for Read commands; the data shifts out in the same instruction cycle in which it was requested. For non-read (i.e., Write and/or Update) commands, SRO automatically shifts out the contents of the buffer that was acted upon in the preceding command. This “rolling readback” default mode of operation can dramatically re- duce the number of instruction cycles needed, since most commands can be verified during subsequent commands with no additional overhead. A conceptual flow diagram is shown in Figure 3. Table 1 shows, for each anteced - ent command, which register (‘readback pointer’) will be copied into the Readback register and outputted from SRO during the following instruction cycle. Span Readback in Manual Span Configuration If a Span DAC register is chosen for readback, SRO re - sponds by outputting the actual output span; this is true whether the LTC2758 is configured for SoftSpan (M-SP AN tied to GND) or manual span (M-SPAN tied to VDD). In SoftSpan configuration, SRO outputs the span code from the Span DAC register (programmed through the SPI port). In manual span configuration, the active output range is controlled by pins S2, S1 and S0, so SRO outputs the logic values of these pins. The span code bits S2, S1 and S0 always appear in the same order and positions in the SRO output sequence; see Figure 2. Serial Interface When the CS/LD pin is taken low, the data on the SDI pin is loaded into the shift register on the rising edge of the clock (SCK pin). The loading sequence required for the L TC2758 is one byte consisting of a 4-bit command word (C3 C2 C1 C0) and a 4-bit address word (A3 A2 A1 A0), then three bytes (24 bits) of data. When writing a code, the code data is left (MSB) justified; so that the 24-bit data field consists of 18 code bits fol - lowed by 6 don’t-care bits. When writing an output range, the span data should oc - cupy the last 4 bits of the second data byte, ordered S3 through S0. Figure 2 shows the SDI input word syntax for writing. When CS/LD is low, the SRO pin (Serial Readback Output) is an active output. The readback data begins after the command (C3-C0) and address (A3-A0) words have been shifted in to SDI. SRO outputs a logic low from the falling edge of CS/LD until the Readback data begins. When CS/LD is high, the SRO pin presents a high imped- ance (three-state) output. LDAC is an asynchronous update pin. When LDAC is taken low, all DACs are updated with code and span data (data in the Input buffers is copied into the DAC buffers). CS/LD must be high during this operation; otherwise LDAC is locked out and will have no effect. The use of LDAC is functionally identical to the “Update All DACs” serial input command. The codes for the command (C3-C0) are defined in Table 1; Table 2 defines the codes for the address (A3-A0). Readback In addition to the Code and Span register sets, each DAC has one Readback register associated with it. Every instruc- tion cycle, the contents of one of the on-chip registers is copied into a Readback register and serially shifted out through the SRO pin. Readback data always appears in the 24-bit data field, starting on the falling SCK edge immediately after the last address bit is shifted in on SDI. When reading a code, code

Table 1. Command Codes Table 2. Address Codes Codes not shown are reserved–do not use. × = Don’t Care. Table 3. Span Codes Codes not shown are reserved–do not use. × = Don’t Care.

For more information www.linear .com/L TC2758 operaTion Examples 1. Load DAC A with 0V to 10V range, output at zero volts; and DAC B with ±10V range, output at zero volts. Note the DAC outputs should change at the same time. CS/LD ↓. Clock SDI: 00101111 00000000 00000011 00000000 b) CS/LD Span Input register- Range of DACs set to bipolar ±10V . c) CS/LD ↓. Clock SDI: 00100000 00000000 00000001 00000000 d) CS/LD Span Input register- Range of DAC A set to unipolar 0V to 10V. CS/LD ↓. Clock SDI: 00111111 10000000 00000000 00XXXXXX f) CS/LD Code Input register- Code of all DACs set to mid-scale. g) CS/LD ↓. Clock SDI: 00110000 00000000 00000000 00XXXXXX h) CS/LD Code Input register- Code of DAC A set to zero. i) CS/LD ↓. Clock SDI:

01001111 XXXXXXXX XXXXXXXX XXXXXXXX

j) CS/LD Update all DACs for both Code and Range. k) Alternatively steps i and j could be replaced with LDAC 2. Load DAC B with ±2.5V range with its output at zero volts. Use readback to check Input register contents before updating the DAC output (i.e., before copying Input register contents into DAC registers). Note that after power-on, the code in Input registers is zero. CS/LD ↓. Clock SDI: 00110010 10000000 00000000 00XXXXXX b) CS/LD Code Input register- DAC B set to mid-scale. c) CS/LD ↓. Clock SDI: 00100010 00000000 00000100 00000000 Data out on SRO: 10000000 00000000 00000000 Verifies Code Input register- DAC B set to mid-scale. CS/LD Span Input register- Range of DAC B set to Bipolar ±2.5V range. CS/LD ↓. Clock SDI:

10100010 XXXXXXXX XXXXXXXX XXXXXXXX

Data Out on SRO: 00000000 00000100 00000000 Verifies Span Input register- DAC B set to Bipolar ±2.5V Range. CS/LD↑ CS/LD ↓. Clock SDI:

01000010 XXXXXXXX XXXXXXXX XXXXXXXX

g) CS/LD Update DAC B for both Code and Range h) Alternatively steps f and g could be replaced with LDAC

For more information www.linear .com/L TC2758 System Offset and Reference Adjustments Many systems require compensation for overall system offset. This may be an order of magnitude or more greater than the offset of the L TC2758, which is so low as to be dominated by external output amplifier errors even when using the most precise op amps. The offset adjust pins V OSADJX can be used to null unipolar offset or bipolar zero error . The offset change expressed in LSB is the same for any output range: VREF A 5V control voltage applied to VOSADJX produces ∆VOS = –2048 LSB in any output range, assuming a 5V reference voltage at RINX. In voltage terms, the offset delta is attenuated by a factor of 32, 64 or 128, depending on the output range. (These functions hold regardless of reference voltage.) ∆VOS = –(1/128)VOSADJX [0V to 5V , ±2.5V spans] ∆VOS = –(1/64)VOSADJX [0V to 10V , ±5V , –2.5V to 7.5V spans] ∆VOS = –(1/32)VOSADJX [±10V span] The gain error adjust pins GE ADJX can be used to null gain error or to compensate for reference errors. The gain error change expressed in LSB is the same for any output range: ∆GE = V(GEADJX ) V(RINX ) •2048 The gain-error delta is non-inverting for positive reference voltages. Note that this pin compensates the gain by altering the inverted reference voltage V(REFX). In voltage terms, the V(REFX) delta is inverted and attenuated by a factor of 128. ∆V(REFX) = –(1/128)GEADJX The nominal input range of these pins is ±5V; other volt- ages of up to ±15V may be used if needed. However , do operaTion not use voltages divided down from power supplies; ref- erence-quality, low-noise inputs are required to maintain the best DAC performance. The VOSADJX pins have an input impedance of 1.28MΩ. These pins should be driven with a Thevenin-equivalent impedance of 10k or less to preserve the settling perfor- mance of the L TC2758. They should be shorted to GND if not used. The GE ADJX pins have an input impedance of 2.56MΩ, and are intended for use with fixed reference voltages only. They should be shorted to GND if not used. Power-On Reset and Clear When power is first applied to the L TC2758, all DACs power-up in unipolar 5V mode (S3 S2 S1 S0 = 0000). All internal DAC registers are reset to 0 and the DAC outputs initialize to zero volts. If the part is configured for manual span operation, all DACs will be set into the pin-strapped range at the first Update command. This allows the user to simultaneously update span and code for a smooth voltage transition into the chosen output range. When the CLR pin is taken low, a system clear results. The DAC buffers are reset to 0 and the DAC outputs are all reset to zero volts. The Input buffers are left intact, so that any subsequent Update command (including the use of LDAC) restores the addressed DACs to their respective previous states. If CLR is asserted during an instruction, i.e., when CS/LD is low, the instruction is aborted. Integrity of the relevant Input buffers is not guaranteed under these conditions, therefore the contents should be checked using readback or replaced. The RFLAG pin is used as a flag to notify the system of a loss of data integrity. The RFLAG output is asserted low at power-up, system clear , or if the supply V DD dips below approximately 2V; and stays asserted until any valid Update command is executed.

2758 F02

8 DON’T-CARE

Figure 2. Serial Input and Output Sequences

2758 F03

Figure 3. Rolling Readback

compared to previous generations of multiplying DACs. in a unipolar or bipolar output range. Table 5. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges (Circuit of Page 1). Subscript 1 Refers to Output Amp, Subscript 2 Refers to Reference Inverting Amp. Table 4. Coefficients for the Equations of Table 5 Table 6. Partial List of L TC Precision Amplifiers Recommended for Use with the L TC2758 with Relevant Specifications

For more information www.linear .com/L TC2758 applicaTions inForMaTion Op amp offset contributes mostly to DAC output offset and gain error , and has minimal effect on INL and DNL. For example, consider the L TC2758 in unipolar 5V output range. (Note that for this example, the LSB size is 19µV .) An op amp offset of 35µV will cause 1.8LSB of output offset, and 1.8LSB of gain error; but 0.4LSB of INL, and just 0.1LSB of DNL. While not directly addressed by the simple equations in Tables 4 and 5, temperature effects can be handled just as easily for unipolar and bipolar applications. First, consult an op amp’s data sheet to find the worst-case V OS and IB over temperature. Then, plug these numbers in the V OS and IB equations from Table 5 and calculate the tempera- ture-induced effects. For applications where fast settling time is important, Ap- plication Note 120, 1ppm Settling Time Measurement for a Monolithic 18-Bit DAC, offers a thorough discussion of 18-bit DAC settling time and op amp selection. Recommendations For DC or low-frequency applications, the L TC1150 is the simplest 18-bit accurate output amplifier . An auto-zero amp, its exceptionally low offset (10µV max) and offset drift (0.01µV/°C) make nulling unnecessary. For swings above 8V , use an L T1010 buffer to boost the load current capability. The settling of auto-zero amps is a special case; see Application Note 120, 1ppm Settling Time Measurement for a Monolithic 18-Bit DAC, Appendix E, for details. The L T1012 and L T1001 are good intermediate output-amp solutions that achieve moderate speed and good accuracy. They are also excellent choices for the reference inverting amplifier in fixed-reference applications. For high speed applications, the L TC1468 settles in 2.1µs. Note that the 75µV max offset will degrade the INL at the DAC output by up to 0.9LSB. For high-speed applications demanding higher precision, the amplifier offset can be nulled with a digital potentiometer . The Typical Application on the last page shows a composite output amplifier that achieves fast settling (8µs) and very low offset (3µV max) without offset nulling. This circuit offers high open-loop gain (1000V/mV min), low input bias current (0.15nA max), fast slew rate (25V/µs min), and a high gain-bandwidth product (30MHz typ). The high speed path consists of an L TC6240HV , which is an 18MHz ultralow bias current amplifier , followed by an L T1360, a 50MHz fast-slewing amplifier which provides additional gain and the ability to swing to ±10V at the output. Com- pensation is taken from the output of the L TC6240HV , allowing the use of a much larger compensation capacitor than if taken after the gain-of-five stage. An L TC2054HV auto-zero amplifier senses the voltage at I OUT1 and drives the non-inverting input of the L TC6240HV to eliminate the offset of the high speed path. The 100:1 attenuator and input filter reduce the low frequency noise in this stage while maintaining low DC offset. Precision Voltage Reference Considerations Much in the same way selecting an operational amplifier for use with the L TC2758 is critical to the performance of the system, selecting a precision voltage reference also requires due diligence. The output voltage of the L TC2758 is directly affected by the voltage reference; thus, any voltage reference error will appear as a DAC output volt- age error . There are three primar y error sour ces to consider when selecting a precision voltage reference for 18-bit applications: output voltage initial tolerance, output voltage temperature coefficient and output voltage noise. Initial reference output voltage tolerance, if uncorrected, generates a full-scale error term. Choosing a reference with low output voltage initial tolerance, like the L T1236 (±0.05%), minimizes the gain error caused by the reference; however , a calibration sequence that corrects for system zero- and full-scale error is always recommended. A reference’s output voltage temperature coefficient affects not only the full-scale error, but can also affect the circuit’s INL and DNL performance. If a reference is chosen with a loose output voltage temperature coefficient, then the DAC output voltage along its transfer characteristic will be very dependent on ambient conditions. Minimizing the error due to reference temperature coefficient can be achieved by choosing a precision reference with a low output voltage temperature coefficient and/or tightly con- trolling the ambient temperature of the circuit to minimize temperature gradients.

Table 7. Partial List of L TC Precision References Recommended degrade system dynamic range and signal-to-noise ratio. may be required to minimize output noise. pins if voltage drops to ground are allowed to develop. plane by multiple vias located directly underneath the part. than 30 squares of 1oz copper .

Figure 4. Optional Circuits for Driving IOUT2 from GND with a Force/Sense Amplifier

2758 F05

For more information www.linear .com/L TC2758 Please refer to http://www.linear .com/product/L TC2758#packaging for the most recent package drawings. package DescripTion LX48 LQFP 0113 REV A 0° – 7° 11° – 13° 0.45 – 0.75

1.00 REF

11° – 13°

9.00 BSC

7.00 BSC

1.60 MAX1.35 – 1.45 BSC 0.17 – 0.27 GAUGE PLANE 0.25 NOTE: 1. PACKAGE DIMENSIONS CONFORM TO JEDEC #MS-026 PACKAGE OUTLINE 2. DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT 4. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER 5. DRAWING IS NOT TO SCALE SEE NOTE: 4 C0.30 – 0.50 R0.08 – 0.20 7.15 – 7.25

5.50 REF

7.15 – 7.25 PACKAGE OUTLINE RECOMMENDED SOLDER PAD LAYOUT APPL Y SOLDER MASK TO AREAS THAT ARE NOT SOLDERED SECTION A – A

0.50 BSC

0.20 – 0.30

1.30 MIN

48-Lead Plastic LQFP (7mm × 7mm) (Reference LTC DWG # 05-08-1760 Rev A) L TCXXXX LX-ES XXYY TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1”

For more information www.linear .com/L TC2758 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER A 09/13 Fixed R COMA (Pin 3) description Updated Typical Application B 11/16 Updated amplifier part numbers 19

For more information www.linear .com/L TC2758  LINEAR TECHNOLOGY CORPORATION 2011 LT 1116 REV B • PRINTED IN USA Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com/L TC2758 relaTeD parTs Typical applicaTion PART NUMBER DESCRIPTION COMMENTS L TC2757 Single Parallel 18-Bit IOUT SoftSpan DAC ±1LSB INL/DNL, Software-Selectable Ranges, 7mm × 7mm LQFP-48 Package L TC1592 Single Serial 16-/14-/12-Bit IOUT SoftSpan DACs ±1LSB INL, DNL, Software-Selectable Ranges, 16-Lead SSOP Package L TC2752 Dual Serial 16-Bit IOUT SoftSpan DAC ±1LSB INL/DNL, Software-Selectable Ranges, 7mm × 7mm LQFP-48 Package L TC2754-12 Quad Serial 16-/12-Bit IOUT SoftSpan DACs ±1LSB INL/DNL, Software-Selectable Ranges, 7mm × 8mm QFN-52 Package L TC2704-12 Quad Serial 16-/14-/12-Bit VOUT SoftSpan DACs ±1LSB INL/DNL, Software-Selectable Ranges, Integrated Amplifiers References L TC6655 Low Drift Precision Buffered Reference 0.025% Max Tolerance, 2ppm/°C Max, 0.25ppmP-P 0.1Hz to 10Hz Noise L T1236 Precision Reference 0.05% Max Tolerance, 5ppm/°C Max, 3µVP-P 0.1Hz to 10Hz Noise L T1460 Micropower Precision Series Reference 0.075% Max Tolerance, 10ppm/°C Max, 20µVP-P 0.1Hz to 10Hz Noise L T1790 Micropower Low Dropout Reference 0.05% Max Tolerance, 10ppm/°C Max, 12µVP-P 0.1Hz to 10Hz Noise L TC6652 Precision Low Drift Low Noise Buffered Reference 0.05% Max Tolerance, 5ppm/°C Max, 2.1ppm P-P 0.1Hz to 10Hz Noise Amplifiers L TC1150 Zero-Drift Op Amp with Internal Capacitors 10µV Max Offset, ±16V High Voltage Operation, 1.8µV P-P Noise L T1012 Precision Op Amp 25µV Max Offset, 100pA Max Input Current, 0.5µVP-P Noise, 380µA Supply Current L T1001 Precision Op Amp 25µV Max Offset, 0.3µVP-P Noise, High Output Drive L T1468 Single 16-Bit Accurate Op Amp 900ns Settling, 90MHz GBW , 22V/μs Slew Rate, 75µV Max Offset Composite Amplifier Circuit Achieves Both Fast Settling and 18-Bit Precision with No Adjustments 10k L TC2758 GND VDD LDAC CLR RINA ROFSB RCOMB RINB REFA, REFB SDI SPI BUS SCKCS/LD SRO ROFSA GEADJA GEADJB RCOMA VOSADJA VOSADJB M-SPAN IOUT1A IOUT2A IOUT1B IOUT2B RFBA RFBB

2758 TA02

–5V 10k 8, 9 45, 46 OUTIN 1, 2, 35, 363 28, 29 7, 10, 15, 17, 18, 27, 30 11 12 13 14 39, 40 1µF 10k 1µF 10k 10k + L TC6240HV –5V –15V 15V100pF 10Ω 5pF 4.02k L TC2054HV –5V 10k 1µF 1µF L TC6240HV –5V –15V 15V100pF 10Ω 5pF 4.02k L T1360 VOUTA VOUTB L T1360 –15V 15V12V L T1012 100pF L TC6655-5 10µF0.1µF 5, 6 37, 38 34 31, 3247, 48