LT1310 LINER | Alldatasheet
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tolerance NP0 dielectric capacitors. , LTC and LT are registered trademarks of Linear Technology Corporation.
1310 F01a
1310 F01b
Figure 1. 5V to 12V Converter Synchronized at 1.6MHz
PARAMETER CONDITIONS MIN TYP MAX UNITS Undervoltage Lockout 2.8 V Maximum Input Voltage 18 V Feedback Voltage 1.242 1.255 1.268 V l 1.236 1.268 V FB Pin Bias Current 60 150 nA Reference Line Regulation V IN = 2.9V to 18V 0.01 0.05 %/V Error Amplifier Transconductance DI = 5mA 350 mA/V Error Amplifier Voltage Gain 200 V/V SW Current Limit 1.5 2.1 2.8 A SW Saturation Voltage I SW = 1A 0.240 0.320 V SW Maximum Duty Cycle C T = 220pF 80 84 % CT = 47pF 78 83 % SW Minimum On Time I SW = 150mA, VC = 0.25V 70 ns VCO Frequency C T = 220pF, PLL-LPF = High 0.950 1.10 1.25 MHz CT = 220pF, PLL-LPF = High l 0.800 1.30 MHz CT = 220pF, PLL-LPF = Low 500 630 kHz CT = 47pF, PLL-LPF = High 3.3 MHz Frequency Foldback C T = 220pF, PLL-LPF = High, FB = 0V 200 kHz PLL Lock Range C T = 220pF, Maximum 0.950 1.10 1.25 MHz CT = 220pF, Minimum (Percent Change from Max) –40 –50 % Supply Current SHDN = High 11.5 15 mA SHDN = Low 1 mA SW Leakage Current Switch Off, SW = 3.3V 0.1 5 mA SHDN Pin Bias Current V SHDN = 2.4V 35 65 mA SHDN Pin High Active Mode 2.4 V SHDN Pin Low Shutdown Mode 0.4 V (Note 1) C Operating Temperature Range (Note 2) .. – 40°C to 85°C ORDER PART NUMBER LT1310EMSE TJMAX = 125°C, qJA = 40°C/W EXPOSED PAD IS GROUND (MUST BE SOLDERED TO PCB) The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V, VSHDN = 3.3V, unless otherwise noted. (Note 2) FB SHDN PLL-LPF SYNC GND V C CT VIN SW SW TOP VIEW MSE EXPOSED PAD PACKAGE 10-LEAD PLASTIC MSOP MSE PART MARKING LTRZ Consult LTC Marketing for parts specified with wider operating temperature ranges. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT1310E is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the –40 °C to 85°C operating temperature range are assured by design, chacterization and correlation with statistical process controls. ABSOLUTE AXI U RATI GSW WW U PACKAGE/ORDER I FOR ATIOUU W
ELECTRICAL CHARACTERISTICS
TEMPERATURE (°C) –50
1.22 FB VOLTAGE (V)
1.23 1.24 1.25 1.26 1.27 –25 02 5 5 0
1310 G01
TEMPERATURE (°C) –50 140 120 100 25 75
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–25 0 50 100 FEEDBACK CURRENT (nA) TEMPERATURE (°C) –50 2.50 UNDERVOLTAGE LOCKOUT (V)2.55 2.60 2.65 2.70 2.80 –25 02 5 5 0
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2.75 Feedback Pin Current Undervoltage Lockout Oscillator Frequency vs CT Capacitor CAPACITOR (pF)
1000 FREQUENCY (kHz)
LT1372 • G10 2000 5000 4000 80 100 PLL-LPF = HIGH Oscillator Frequency vs CT Capacitor CAPACITOR (pF) 100 FREQUENCY (kHz) 1200 1600 2000 900
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PLL-LPF = HIGH Oscillator Frequency vs Feedback Voltage FEEDBACK (V) 800 1000 1400 0.6 1.0
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1200FREQUENCY (kHz) 220pF CT CAPACITOR Oscillator Frequency 220pF Capacitor on CT Pin Maximum Duty Cycle vs Oscillator Frequency TEMPERATURE (°C) –50 1600 1400 1200 1000 800 600 400 200 25 75
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–25 0 50 100 FREQUENCY (kHz) PLL-LPF = HIGH Oscillator Frequency 47pF Capacitor on CT Pin TEMPERATURE (°C) –50
2000 FREQUENCY (kHz)
–25 02 5 5 0
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PLL-LPF = HIGH OSCILLATOR FREQENCY (kHz) 500 1000 MAX DUTY CYCLE (%) 100 1500 2500 3000
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100°C 25°C –50°C TYPICAL PERFOR A CE CHARACTERISTICS UW
Supply Current Switch V CESAT TEMPERATURE (°C) –50 MINIMUM ON TIME (ns) 100 –25 02 5 5 0
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TEMPERATURE (°C) –50 200 FREQUENCY (kHz) 400 600 800 1000 1400 –25 02 5 5 0
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TEMPERATURE (°C) –50 500 FREQUENCY (kHz) 1000 1500 2000 2500 3500 –25 02 5 5 0
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TEMPERATURE (°C) –50 SUPPLY CURRENT (mA) –25 02 5 5 0
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SWITCH CURRENT (A) VCESAT (mV) 100 200 300 400 0.5 1.0
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1.5 Transient Response PLL Response Start-Up Response VOUT 100mV/DIV IL 500mA/DIV 200mA 100mAILOAD fSYNC = 1.5MHz 50 ms/DIV LT1310 G16 VOUT 50mV/DIV IL 200mA/DIV 1.9MHz 1.2MHzfSYNC 50ms/DIV LT1310 G17 VOUT 5V/DIV IL 1A/DIV VSHDN NO SYNC SIGNAL 20 ms/DIV LT1310 G18 f = 1.2MHz TYPICAL PERFOR A CE CHARACTERISTICS UW
FB (Pin 1): Feedback Pin for Error Amplifier. Connect the resistor divider here to set output voltage according to the formula: VOUT = 1.255(1 + R1/R2) FB VOUT Minimize trace area at this pin. SHDN (Pin 2): Shutdown Pin. For active mode, tie this pin to a voltage between 2.4V and 18V. To disable the part and go into low current mode, pull this pin below 0.4V. PLL-LPF (Pin 3): Phase Locked-Loop Filter Pin. This is the output of the phase detector and also the input to the voltage controlled oscillator (VCO). Connect an RC filter here. Typically, R = 3k and C = 1500pF. The voltage range at the PLL-LPF pin is approximately 0V to 1.5V with 1.5V corresponding to the maximum switching frequency. For applications not requiring synchronization, use a pull-up resistor at this pin; the pull-up voltage must be above 2.4V. Set the pull-up resistor value according to: R VV APULLUP PULLUP= () m ±.15 300 For a pull-up voltage of 5V: R VV A kPULLUP = () m »51 5 300 11 6±. . SYNC (Pin 4): Frequency Synchronization Pin. Inject the external synchronizing signal here. The phase detector is edge triggered and when locked the rising edge of the sync signal will be aligned with the turn-on of the power transistor. The SYNC signal must have a minimum HIGH amplitude of 1.2V and a maximum LOW amplitude of 0.2V with the signal staying low for at least 100ns. 1.2V (MIN) 0.2V (MAX) 100ns (MIN) GND (Pin 5, Exposed Pad): Ground. Tie both Pin 5 and the exposed pad directly to local ground plane . The ground metal to the exposed pad should be wide for better heat dissipation. Multiple vias (local ground plane « ground backplane) placed close to the exposed pad can further aid in reducing thermal resistance. The exposed pad must be soldered to ground for the LT1310 to function properly. SW (Pins 6, 7): Switch Pin. Connect inductor/diode here. Minimize trace area at this pin to keep EMI down. V IN (Pin 8): Supply Pin. Must be bypassed as close as possible to the pin. CT (Pin 9): Timing Capacitor Pin for VCO. Place the timing capacitor from this pin to ground to set the frequency range for the oscillator. Minimize trace at this pin to reduce stray capacitance. V C (Pin 10): Compensation Pin for Error Amplifier. Tie an RC network here to compensate the voltage feedback loop. UUUPI FU CTIO S
S FB SHDN SHUTDOWN GND VC 1.255V REF RAMP GEN. EXPOSED PAD PHASE DETECTORVCO R S Q Q CT PLL-LPF SYNC SW 0.024Ω 1310 BD 6, 7 To understand operation, refer to the Block Diagram. The LT1310 contains a boost switching regulator that can be phase locked to an external synchronizing signal. The boost regulator uses current mode control and contains a 1.5A NPN power transistor. This type of control uses two feedback loops. The main control loop sets output voltage and operates as follows: a load step causes V OUT and the FB voltage to be slightly perturbed. The error amplifier A1 responds to this change in FB by driving the VC pin either higher or lower. Because switch current is proportional to the V C pin voltage, this change causes the switch current to be adjusted until V OUT is once again satisfied. Loop compensation is taken care of by an RC network from the V C pin to ground. Inside this main loop is another that sets current limit on a cycle-by-cycle basis. This loop utilizes current comparator A2 to control peak current. The oscil- lator issues a set pulse to the flip-flop at the beginning of each cycle, turning the switch on. With the switch now in the ON state, the SW pin is effectively connected to ground. Current ramps up in the inductor linearly at a rate of V IN/L. Switch current is set by the V C pin voltage and when the voltage across R SENSE trips the current com- parator, a reset pulse will be generated and the switch will be turned off. Since the inductor is now loaded up with current, the SW pin will fly high until it is clamped by the catch diode, D1. Current will flow through the diode decreasing at a rate of (V OUT – VIN)/L until the oscillator issues a new set pulse, causing the cycle to repeat. The LT1310 is phase lockable up to 4.5MHz, giving the user precise control over switching frequency. The phase detector compares the incoming sync signal to the internal oscillator signal. If the switching frequency is lower than the sync signal, or if the phase lags the sync signal, then the phase detector output will source current into the PLL-LPF pin, driving it higher. The PLL-LPF pin is also the input to the voltage controlled oscillator. If the sync signal is slower than the switching frequency, the PLL-LPF pin will sink current until the PLL-LPF pin voltage drops. When locked, the PLL-LPF pin rests at a voltage between 0V and 1.5V. The PLL-LPF pin is capable of sinking or sourcing approximately 140mA. BLOCK DIAGRA W OPERATIOU
frequency corresponds to an 100pF timing capacitor. Table 1. Recommended Component Values for Various Switching
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inductor only carries one-half of the total switch current. The inductors shown in Table 2 were chosen for small size. Table 2. Recommended Inductors be used at the output to minimize the output ripple voltage. with a sufficient voltage rating. Table 3. Ceramic Capacitor Manufacturers
Table 4. Bode Plot Parameters zero to achieve adequate phase margin.
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Figure 4. Boost Converter Equivalent Model A Schottky diode is recommended for use with the LT1310. ON Semiconductor MBR0520 diode can be used. A good range for R2 is from 5k to 30k.
1310 F05a
1946 F05b
Figure 5. Bode Plot of Figure 1’s Circuit
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
- DIMENSIONS IN MILLIMETER/(INCH)
- DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
- DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
- LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
Figure 6. Recommended Component Placement for Boost Converter. Note Direct High Current Paths Using Wide PC Traces. Minimize
ª LINEAR TECHNOLOGY CORPORATION 2001 LT/TP 0103 2K • PRINTED IN USA RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1613 550mA (I SW), 1.4MHz High Efficiency Step-Up DC/DC Converter 90% Efficiency, V IN: 0.9V to 10V, VOUT(MAX): 34V, IQ: 3mA, ISD: <1mA, ThinSOT TM Package LT1618 1.5A (I SW), 1.25MHz, High Efficiency Step-Up DC/DC Converter 90% Efficiency, V IN: 1.6V to 18V, VOUT(MAX): 35V, IQ: 1.8mA, ISD: <1mA, 10-Lead MS Package LT1961 1.5A (I SW), 1.25MHz, High Efficiency Step-Up DC/DC Converter 90% Efficiency, V IN: 3V to 25V, VOUT(MAX): 35V, IQ: 0.9mA, ISD: 6mA, MS8E Package LTC 3400/LTC3400B 600mA (I SW), 1.2MHz, Synchronous Step-Up DC/DC Converters 92% Efficiency, V IN: 0.85V to 5V, VOUT(MAX): 5V, IQ: 19mA/300mA, ISD: <1mA, ThinSOT Package LTC3401 1A (I SW), 3MHz, Synchronous Step-Up DC/DC Converter 97% Efficiency, V IN: 0.5V to 5V, VOUT(MAX): 6V, IQ: 38mA, ISD: <1mA, 10-Lead MS Package LTC3402 2A (I SW), 3MHz, Synchronous Step-Up DC/DC Converter 97% Efficiency, V IN: 0.5V to 5V, VOUT(MAX): 6V, IQ: 38mA, ISD: <1mA, 10-Lead MS Package ThinSOT is a trademark of Linear Technology Corporation. VIN SHDNSHUTDOWN SYNC IN 3MHz SYNC PLL-LPF RLP 3.01k VIN RC 10k 178k 20.5k C T 33pF NP0
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2.2µF V OUT 12V 400mA CLP 1000pF CC 680pF C1, C2: TAIYO YUDEN LMK212BJ225MG D1: MOTOROLA MBRM120 L1: PANASONIC ELL6RH2R7M *EXPOSED PAD MUST ALSO BE GROUNDED 2.2µF FB C T VC SW LT1310 3.3µH GND* 3MHz 5V to 12V Converter LOAD CURRENT (mA) EFFICIENCY (%) 100 200
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3.3VIN 5VIN Efficiency TYPICAL APPLICATIO U Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 l FAX: (408) 434-0507 l www.linear.com